WO2024134241A1 - Procédé d'évaluation de la stabilité d'un système gdphil et procédé et dispositifs associés - Google Patents

Procédé d'évaluation de la stabilité d'un système gdphil et procédé et dispositifs associés Download PDF

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WO2024134241A1
WO2024134241A1 PCT/IB2022/000737 IB2022000737W WO2024134241A1 WO 2024134241 A1 WO2024134241 A1 WO 2024134241A1 IB 2022000737 W IB2022000737 W IB 2022000737W WO 2024134241 A1 WO2024134241 A1 WO 2024134241A1
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block
transfer function
evaluating
path
under test
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PCT/IB2022/000737
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English (en)
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Tran-The HOANG
Quoc-Tuan TRAN
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Commissariat A L'energie Atomique Et Aux Energies Alternatives
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Publication of WO2024134241A1 publication Critical patent/WO2024134241A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B17/00—Systems involving the use of models or simulators of said systems
    • G05B17/02—Systems involving the use of models or simulators of said systems electric
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B5/00—Anti-hunting arrangements
    • G05B5/01—Anti-hunting arrangements electric

Definitions

  • the present invention concerns a method for evaluating the stability of a geographically distributed power hardware-in-the-loop system.
  • the present invention also deals with a method for designing a geographically distributed hardware-in-the-loop system.
  • the present invention also concerns a computer program product and a computer-readable medium.
  • GDPHIL The basic concept of GDPHIL lies in splitting the system under test into two or more subsystems that can be located in geographically distributed laboratories. These subsystems then are interconnected over the internet, facilitated by advanced low-latency communication technologies and well-developed HIL interfacing tools.
  • the GDPHIL technologies obviously, allows for complementary expertise, additional equipment, domains and computational resources to be harnessed across multiple laboratories that are geographically dispersed.
  • GDPHIL system provides with a comprehensive characterization: Where the real-time simulation capability is limited due to computational constraints of the digital real time simulator, the simulators across multiple laboratories can be utilized to realize more detailed large scale models for high fidelity simulations. It also enables to obtain representative systems: with the transition of the power system towards an integrated energy system with decarbonization of heat and transport, the concept of GDPHIL allows for domain specific laboratories (such as heat and electrical power) to be interconnected to evaluate next generation concepts to facilitate the transition. Even within a domain, the equipment at each laboratory is unique and therefore the concept of GDS allows for utilization of hardware equipment of different laboratories within an experiment enabling the realization of broader range and more representative testing scenarios.
  • GDPHIL system provides with an acceleration of validation in two different ways.
  • the system enables integration of specialist skills and services, where the communications emulation capability of one laboratory was utilized for an experiment by another laboratory, both geographically dispersed. This saves time and effort in realizing services that might be readily available for utilization.
  • the system facilitates the cooperation between industrial partners as sensitive models are no longer required to be shared, can be run at independent organization facilities with only a data link to other cooperating organizations. This adds an additional level of intellectual property protection and helps accelerate the validation.
  • the GDPHIL system further enables the testing of prototype controllers without having to be delivered to a laboratory, making it logistically more convenient.
  • the specification describes a computer- implemented method for evaluating the stability of a geographically distributed power hardware-in-the-loop system, the system comprising several units among which:
  • a communication network enabling communication of data between the digital real time simulation unit and the hardware under test along a first path from the digital real time simulation unit to the hardware under test named the feed forward path and a second path from the hardware under test to the digital real time simulation unit, the second path being named the feedback path,
  • each unit comprising at least one component
  • the system being modelled by a predetermined block circuitry in the s-domain
  • the predetermined block circuitry representing each component of the system by blocks having function depending from at least one respective parameters, the set of parameters enabling to set a feed forward transfer function and a feedback transfer function, the transfer function of the system being the product of the feed forward transfer function and the feedback transfer function, one block of the predetermined block circuitry being a phase-locked loop block, the phase-locked loop block having a transfer function
  • the method comprising the steps of:
  • the method for evaluating might incorporate one or several of the following features, taken in any technically admissible combination: - the predetermined block circuitry comprises two phase-locked loop blocks, one phase-locked loop block being taken into account into the feed forward transfer function and the other phase-locked loop block being taken into account into feedback transfer function.
  • - at least one component is chosen among:
  • the power amplifier having a gain, one value obtained at the step of obtaining being the gain of the power amplifier, and
  • a low-pass filter having a filter function depending from at least one filter parameter, the values obtained at the step of obtaining comprising the at least one filter parameter.
  • an equivalence impedance is defined for the digital real time simulation unit and an equivalence admittance is defined for the hardware under test, one value obtained at the step of obtaining being the equivalence impedance of the digital real time simulation unit and another value being the equivalence admittance of the hardware under test.
  • one block is a time-delay block introducing a time-delay, the value of the time-delay depending from measurements of the time-delays of the communication network.
  • the transfer function of the phase-locked loop block is of the form where k p and k i are two constants.
  • At least one block is a conversion block adapted to apply a transform function, the transform function being chosen among a Park transform, a Clarke transform and a Clarke-Park transform.
  • the predetermined block circuitry comprises a first conversion block adapted to convert the signal from abc representation to alpha beta representation, a second conversion block adapted to convert the signal from alpha beta representation to dqO representation, the first conversion block being followed by the second conversion block.
  • At least one block is a conversion subunit adapted to transform a signal from abc representation to a representation in root mean square voltage and frequency.
  • the stability criterion is the Nyquist stability criterion .
  • the specification also relates to the method for designing a geographically distributed power hardware-in-the-loop system, the system comprising several units among which:
  • a communication network enabling communication of data between the digital real time simulation unit and the hardware under test along a first path from the digital real time simulation unit to the hardware under test named the feed forward path and a second path from the hardware under test to the digital real time simulation unit, the second path being named the feedback path,
  • each unit comprising at least one component having values, the arrangement of the units and the set of the values of all components defining a design of the system, the method for evaluating comprising the steps of:
  • the method for designing might incorporate one or several of the following features, taken in any technically admissible combination:
  • the method further comprises a step of fabricating the system corresponding to the validated design.
  • the specification also relates to a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the steps of a method as previously described.
  • the specification further describes a computer- readable medium comprising instructions which, when executed by a computer, cause the computer to carry out the steps of a method as previously described.
  • FIG. 1 is a schematic view of a geographically distributed power hardware-in-the- loop system
  • figure 2 is a block diagram of an example of block circuitry in the s-domain modelling the system of figure 1 .
  • FIG. 3 is a schematic view of a specific geographically distributed power hardware-in-the-loop system
  • figures 4 to 9 corresponds to the results obtained from theoretical stability analysis and simulation in MATLAB/Simulink® for the geographically distributed power hardware-in-the-loop system of figure 3.
  • the present specification describes a method for evaluating the stability of a geographically distributed power hardware-in-the-loop (GDPHIL) system 10.
  • GDPHIL hardware-in-the-loop
  • This method for evaluating the stability is a computer-implemented method. This means that the method for evaluating is carried out by a computing device.
  • FIG. 1 An example of a general architecture of the units of GDPHIL system 10 is represented in figure 1 .
  • This system 10 at least comprises a digital real time simulation unit 12, a hardware under test 14 and a communication network 16.
  • DRTS unit 12 DRTS standing for digital real time simulation
  • HUT 14 hardware under test
  • the DRTS unit 12 is the master unit, which is adapted to generate testing signals to be sent to the HUT 14.
  • testing signals are signals representative of the conditions of use of the HUT 14, so that the DRTS unit 12 is adapted to create a test simulation environment of the HUT 14.
  • the HUT 14 is a physical element, which needs to be tested.
  • HUT 14 Before being inserted in the grid, such HUT 14 has to be tested so as to check whether or not it operates property.
  • the GDPHiL system 10 serves to carry out such tests in a virtual environment to avoid disturbing the real grid, at a much lower cost and time.
  • the communication network 16 is adapted to enable communication of data between the DRTS unit 12 and the HUT 14.
  • Such communication is a two-path communication.
  • the first path is from the DRTS unit 12 to the HUT 14. This first path is the feed forward path.
  • the second path is from the HUT 14 to the DRTS unit 12.
  • the second path is named the feedback path.
  • the system 10 also comprises four interfaces for signal processing, two on each path.
  • the system 10 comprises a first feed forward interface 18 coupling the DRTS unit 12 and the communication network 16, a second feed forward interface 20 coupling the communication network 16 and the HUT 14, a first feedback interface 22 coupling the HUT 14 and the communication network 16, and a second feedback interface 24 coupling the communication network 16 and the DRTS unit 12.
  • the first feed forward interface 18, the second feedback interface 24 and the DRTS unit 12 forms a first subsystem 26 while the second feed forward interface 20, the first feedback interface 22 and the HUT 14 forms a second subsystem 28.
  • the GDPHIL system 10 may comprise more than two subsystems according to the element to be tested.
  • the same DRTS unit 12 may be used to test the behaviour of two HUTs situated at two different locations.
  • This GDPHIL system 10 is modelled by a predetermined block circuitry 30 in the s- domain.
  • the predetermined block circuitry 30 represents each component of the system 10 by blocks having function depending from at least one respective parameter.
  • the set of parameters enables to set a feed forward transfer function and a feedback transfer function.
  • the transfer function of the GDPHIL system 10 is the product of the feed forward transfer function and the feedback transfer function.
  • the transfer function of the GDPHIL system 10 is the open-loop transfer function of the GDPHIL system 10 and that this function can be expressed in s- domain as a function of the set of parameters.
  • GOL(S) Such transfer function of the GDPHIL system 10 is denoted as GOL(S) in what follows.
  • An example of such predetermined block circuitry 30 will be described later in reference to figure 2,
  • a resistance can be replaced by a resistance bridge.
  • the predetermined block circuitry 30 has the specificity that at least one block of the predetermined block circuitry 30 is a phase-locked loop block, named PLL block, that have a transfer function denoted by GpLi(s).
  • the transfer function GOL(S) of the GDPHIL system 10 depends on the transfer function GPLL(S) of the PLL block.
  • the predetermined block circuitry 30 described here comprises two PLL blocks: a first PLL block 31 and a second PLL block 32,This PLL blocks 31 and 32 shares the same transfer function GPLL(S) and differs only by their position.
  • the method for evaluating the stability comprises three steps including a step of obtaining, a step of calculating and a step of determining.
  • the computing device obtains values representative of the physical values of the set of parameters in the system 10.
  • Such values may be obtained by measurement.
  • a typical example is the measurement of time delays that will be introduced hereinafter.
  • this value may be obtained by knowing the specifications, operating parameters, operation modes, and control algorithms of the HUT 14. This enables to obtain an acceptable approximate value, which is representative of the real value without having measuring effectively such value.
  • the method for evaluating the stability is taking as input measurement values and obtains as output the stability of the system 10.
  • Such method is therefore a tool measuring the stability of a GDPHIL system 10.
  • the computing device calculates the transfer function of the GDPHIL system 10. For this, the computing device will use the values obtained at the step of obtaining.
  • the computing device will also use the transfer function of the PLL block (here PLL blocks 31 and 32). During the third step, the computing device determines whether the transfer function fulfils a stability criterion or not.
  • the Nyquist stability criterion is selected thanks to its ease of use and high accuracy.
  • the Nyquist plot mapped through the function 1 + G 0L (s) yields a plot of 1 + G 0L (s) in the complex plane.
  • the number of clockwise encirclements of the -1 point must be the number of zeros of 1 + G 0L (s) in the right-half complex plane minus the number of poles of 1 + G 0L (s) in the right-half complex plane.
  • the computing device considers that the system 10 is stable when the transfer function fulfils the stability criteria; otherwise it is considered unstable.
  • Such method for evaluating can advantageously be used to design a GDPHIL system 10.
  • the computing device is provided with a design of a GPHIL system 10 to be evaluated, the computing device is able to determine whether this system 10 is stable or not.
  • GPHIL system By design, it is meant here the characteristics of the GPHIL system 10, namely which are the units, the arrangement of these units and the set of the values of all components of the units.
  • the design comprises all the elements enabling to fabricate the GPHIL system 10.
  • the method for designing is an iterative method in which, a design is proposed, the stability is evaluated and either the design is validated (because stable) or the design is modified, and the modified design is again evaluated and so on until reaching a stable GPHIL system 10 design.
  • the modification of the design can be achieved by carried out a modification of at least one value of a component, adding a component and suppressing a component.
  • Other example of modifying/changing the communication network 16, concerning the system or topology used can be consider for obtaining lower delays, but potentially at higher cost.
  • a validated design is obtained and the method may comprise fabricating the GDPHIL system 10 corresponding to the validated design.
  • the stability of such a GDPHIL system 10 can be guaranteed, notably because the method provides with a representative experiment.
  • This example of method for evaluating is associated to the transfer function resulting from the representation of the GDPHIL system 10 in the s-domain as the block circuitry schematically represented on figure 2.
  • the wording “unit” will preferably be used when referring to the GDPHIL system 10 while the wording “block” will be used when referring to the predetermined block circuitry 30.
  • model block and the corresponding real unit are in reality nearly identical.
  • the DRTS unit 12 corresponds to a block 32 with a multiplier 34 linked to a voltage source V s and an impedance block 38 named Z s .
  • the DRTS unit 12 can be represented by an impedance connected in series with a voltage source. This representation is the one chosen for figure 1.
  • PCC point of common coupling
  • the HUT 14 corresponds to an admittance block 38 of 1/Z H where Z H is the impedance of the HUT 14.
  • the communication network 16 introduces time delays in both paths.
  • the estimated/measured/approximated average time delay of the feed forward path is denoted by and that of the feedback path is by .
  • time delays of the feed forward path and feedback path are approximately equal and commonly denoted by T d .
  • the communication network 16 corresponds in figure 2 to a delay block 40 and a delay compensation block 42.
  • the delay block 40 introduces a delay, which should, for example, correspond to the measured delay.
  • the first PLL block 31 is a control system whose main function is to generate the phase angle of the input signal.
  • the delay compensation block 40 is used to compensate for the introduced delay.
  • ⁇ the first feed forward interface 18 comprises a first signal processing unit 44;
  • the second feed forward interface 20 comprises a first signal reconstruction unit 46, a digital to analog converter 48 and a power amplifier 50;
  • the first feedback interface 22 comprises a filter 52, a sensor 54, an analog to digital converter 56, and a second signal processing unit 58, and
  • the second feedback interface 24 comprises a second signal reconstruction unit 60.
  • the first feed forward interface 18 corresponds to a first signal processing block 62
  • the second feed forward interface 20 corresponds to a first signal reconstruction block 64 and a power amplifier block 66
  • the first feedback interface 22 corresponds to a second signal processing block 68
  • the second feedback interface 24 corresponds to a second reconstruction block 70.
  • the first signal processing block 62 is configured to convert three-phase instantaneous voltage signals V Sabc from the DRTS unit 12 into dqO component voltage signals 7 Sdq0 and their phase angle for time delay compensation.
  • dqO stands for “direct-quadrature-zero” and designates a specific representation of three-phase electrical signals.
  • the first signal processing block 62 comprises two successive conversion blocks 72 and 74.
  • the first conversion block 72 is configured to act as a first conversion function for converting the three-phase voltage signals 7 Sa6c (represented in the abc representation or domain) into a0y quantities V Sa ⁇ Y (a/3y representation or domain).
  • the first conversion function is, for instance, a Clarke transform.
  • the second conversion block 74 is configured to act as a second conversion function for converting the ⁇ y quantities V S ⁇ Y into dq0 quantities V Sdq0 .
  • the second conversion function is, for instance, a Park transform.
  • the second conversion block 74 is also configured to receive from the PLL block 32 an additional signal of voltage phase angle ⁇ S .
  • the transfer function of the first signal processing block 62 can be expressed as:
  • the first signal reconstruction block 64 is configured to reconstruct the three phase voltage signals based on the dq0 quantities and the compensated phase quantity 0/ provided by the delay compensation block.
  • the first signal reconstruction block 64 comprises a third conversion block 76 and a fourth conversion block 78.
  • the third conversion block 76 is configured to apply a third conversion function consisting in converting dqO quantities V Sdq0 into a[Jy quantities V/ ajgy .
  • the third conversion function is, for instance, an inverse Park transform.
  • the third conversion block 76 is also configured to receive the compensated phase quantity and to add it to the dqO quantities
  • the fourth conversion block 78 is configured to apply a fourth conversion function consisting in converting a ⁇ y quantities into three-phase instantaneous voltage signal
  • the fourth conversion function is, for instance, an inverse Clark transform.
  • the transfer function of the first signal reconstruction unit 64 can be expressed as:
  • the digital to analog converter 48 enables to convert the digital output signal of the first signal reconstruction unit into an analog signal.
  • the power amplifier 66 is configured to amplify the analog signal of the digital to analog converter 48 by applying an amplification function.
  • the output signal of the power amplifier 66 is sent to the HUT 14.
  • the sensor 54 is adapted to measure the output of the HUT 14, both the output voltage and the output current.
  • the analog to digital converter 56 converts the measured signal which is analogic into a digital signal.
  • the second PLL block 32 takes as input the output voltage V Habc of the HUT 14 to calculate the voltage phase angle 9 H .
  • the filter 52 is configured to filter the high-harmonic components of the HUT 14’s output current
  • the filter 52 is here a low-pass filter.
  • the output current of the adopted low-pass filter 52 is the filtered three-phase current
  • the second signal processing block 68 is configured to convert the filtered three- phase currents of the HUT 14 into dqO quantities
  • the second signal processing block 68 comprises a fifth conversion block 82 and a sixth conversion block 84.
  • the fifth conversion block 82 is configured to apply a fifth conversion function consisting in converting the three-phase currents I H ' abc (represented in abc domain) into ⁇ y quantities
  • the fifth conversion function is, for instance, a Clarke transform.
  • the sixth conversion block 84 is adapted to apply a sixth conversion function consisting in converting the ⁇ y quantities I H ! a p Y into dqo quantities I H ' d(]0 .
  • the sixth conversion function is, for instance, a Park transform.
  • the sixth conversion block 84 is also configured to receives from the second PLL block 32 the signal of voltage phase angle to perform a Park transform.
  • the transfer function of the second signal processing block 68 can be expressed as: / 1/3 /
  • the second delay block 40 introduces a time delay in the input signal delivered at the second signal reconstruction block 68.
  • the second signal reconstruction block 70 is then configured to convert the delayed current signal expressed in dq0 quantities into a three-phase instantaneous signal current I Habc .
  • the first signal reconstruction block 70 comprises a seventh conversion block 86 and an eightieth conversion block 88.
  • the seventh conversion block 86 is configured to a seventh conversion function consisting in converting dqO quantities of the current I Hdq0 into afty quantities I Ha p y .
  • the seventh conversion block 86 is, for instance, an inverse Park transform.
  • the seventh conversion block 86 is also configured to receive the compensated phase angle of the voltage signal & s to perform the Park transform.
  • the eightieth conversion block 86 is configured to apply a eightieth conversion function consisting in converting ⁇ y quantities of the current I Ha p Y into three-phase instantaneous currents
  • the eightieth conversion function is, for instance, an inverse Clark transform.
  • the transfer function of the second signal processing block 70 can be expressed as:
  • ⁇ Z s (s) and Z w (s) are the equivalent impedance of the network simulated in DRTS unit 12 and the estimated impedance of the HUT 14, correspondingly,
  • ⁇ G PA(S) is the transfer function of power amplifier, this transfer function may, for instance, be reduced to a gain, and
  • the parameters include the gain of the power amplifier, the cut-off frequency of the low-pass filter, the respective impedances of the DRTS unit 12 and the HUT 14.
  • These parameters are the parameters that will be obtained during the step of obtaining.
  • the GDPHIL system 10 is the specific one represented on figure 3, wherein the CRTS unit 12 emulates an environment consisting of several 0.4 kV conductors connected to an external grid via a 20/0.4 kV 1000 kVA step-down secondary distribution transformer.
  • the HUT 14 is here a hardware variable load bank. In this case, the HUT 14 is chosen to simulate physically many household loads and roof-top solar inverters.
  • the HUT 14 is coupled with the CRTS via a power amplifier on one path and with a low-pass filter in the other path.
  • system 10 can be considered as the combination of a grid and a load, the grid being connected to the load by a line.
  • Each of these components are characterized by specific values, which are given in the following table:
  • the method for evaluating the stability according to the first example is carried out.
  • the present method is a MIMO method while the conventional method is a SISO method.
  • MIMO stands for multiple input multiple output
  • SISO stands for single input single output.
  • the present MIMO method provides with 3x3 values, i.e., three- phase voltage signals V a , V b , V c x three-phase current signals l a , l b , l c after being multiplied by Z H (s)).
  • the results derived from the adoption of proposed stability evaluation method for the first example are in consistence with the simulation results, confirming its accuracy.
  • the results derived from the proposed method of are in consistence with the simulation results, confirming its accuracy.
  • both stability assessment methods accurately determine the stability of the considered GDPHIL system, which is indeed stable as confirmed by the simulation results shown in figure 9.
  • the conventional SISO stability assessment method is able to provide accurate result for a limited range of impedance ratio For higher value of impedance ratio, this method fails to guarantee accurate prediction.
  • Clarke-Park transformation which is composed of Clarke and Park transformations, can be defined by:
  • T c is the coefficient matrix of Clarke transformation.
  • the inverse Clarke Park transform can be expressed as:
  • ® (equation 16) is the transfer function of the PLL block
  • k p and k L are the proportional and integral coefficients of the PI controller of the PLL block.
  • Equation 17 The s-domain representation of equation 17 can be obtained by application of Euler’s formulas and Laplace transform and its resulted form is as:
  • ⁇ is the magnitude of the voltage signal and can be considered to be equal to which is the magnitude of of the d-axis voltage.
  • Equation 11 1 The s-domain representation of equation 11 1 can be obtained by application of Euler’s formulas and Laplace transform and its resulted form is as:
  • the compensated voltage phase angle can be obtained from ) determined as:
  • ® T d is the time delay of the feed forward loop to be compensated.
  • Equation 116 can be rewritten as:
  • the next step is to eliminate the presence of the q-component voltage.
  • the active power measured at the HUT side can be determined through the three-phase currents and voltages as: (equation 118)
  • ® is the magnitude of the three-phase voltage measured at HUT's terminal
  • HUT active power can also be defined by dqO components as:
  • ® are the magnitudes of the d-axis and q-axis currents of the HUT 14, respectively
  • ⁇ are the transfer function of power amplifier and low pass filter, respectively that are defined as: where with f c is the cut-off frequency of the LPF.

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Abstract

La présente invention concerne un procédé d'évaluation de la stabilité d'un système GDPHIL (10), le système (10) étant modélisé par un ensemble de circuits de blocs prédéterminé dans le domaine s, représentant chaque composant du système (10) par des blocs ayant une fonction dépendant d'au moins un paramètre respectif, un bloc de l'ensemble de circuits de blocs prédéterminé étant un bloc PLL, le procédé comprenant les étapes consistant à : - obtenir des valeurs représentatives des valeurs physiques des paramètres dans le système (10), - calculer la fonction de transfert du système (10) en fonction de la fonction de transfert du bloc PLL et des valeurs obtenues et - déterminer si la fonction de transfert remplit ou non un critère de stabilité, le système (10) étant considéré stable lorsque la fonction de transfert remplit le critère de stabilité, instable dans le cas contraire.
PCT/IB2022/000737 2022-12-22 2022-12-22 Procédé d'évaluation de la stabilité d'un système gdphil et procédé et dispositifs associés WO2024134241A1 (fr)

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Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
FENG ZHIWANG ET AL: "Current-Type Power Hardware-in-the-Loop Interface for Black-Start Testing of Grid-Forming Converter", IECON 2022 - 48TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, IEEE, 17 October 2022 (2022-10-17), pages 1 - 7, XP034243533, DOI: 10.1109/IECON49645.2022.9968517 *
SYED MAZHERUDDIN H ET AL: "Real-Time Coupling of Geographically Distributed Research Infrastructures: Taxonomy, Overview, and Real-World Smart Grid Applications", IEEE TRANSACTIONS ON SMART GRID, IEEE, USA, vol. 12, no. 2, 22 October 2020 (2020-10-22), pages 1747 - 1760, XP011840699, ISSN: 1949-3053, [retrieved on 20210225], DOI: 10.1109/TSG.2020.3033070 *

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