WO2024129626A1

WO2024129626A1 - Switched capacitor interleaved multilevel inverters

Info

Publication number: WO2024129626A1
Application number: PCT/US2023/083462
Authority: WO
Inventors: Rafael OLIVEIRA
Original assignee: Worksport Ltd.
Priority date: 2022-12-16
Filing date: 2023-12-11
Publication date: 2024-06-20

Abstract

A switched capacitor interleaved multilevel inverter (100) includes a plurality of switched capacitor submodules (200) arranged in series with first and second input voltages (110) and connected to a common ground (120), and a full bridge (400). Each submodule includes a respective first half bridge (210) comprising a respective first capacitor association (300a) and connected to the common ground, and a respective second half bridge (220) comprising a respective second capacitor association (300b) and connected to the common ground. The first half bridge and the second half bridge interleaved such that the first half bridge can be selectively configured to charge the first capacitor association in parallel with the first input voltage while the second half bridge is selectively configured to discharge the second capacitor association in series with the second input voltage to generate an output voltage of the submodule that is greater than the second input voltage.

Description

Switched Capacitor Interleaved Multilevel Inverters

TECHNICAL FIELD [0001] This disclosure relates to multilevel inverters.

BACKGROUND

[0002] A step-up converter may be used to, for example, raise a direct current (DC) voltage (e.g., received from a battery) to the peak voltage of an alternating current (AC) power source. In some examples, an inverter generates, based on outputs of the step-up converter, a sinusoidal waveform that complies with desired characteristics of the AC power source.

SUMMARY

[0003] One aspect of the disclosure provides a switched capacitor interleaved multilevel inverter including a plurality of switched capacitor submodules arranged in series with first and second input voltages and connected to a common ground, and a full bridge. Each submodule of the plurality of submodules includes a respective first half bridge including a respective first capacitor association and connected to the common ground; and a respective second half bridge including a respective second capacitor association and connected to the common ground. The first half bridge and the second half bridge are interleaved such that the first half bridge can be selectively configured to charge the first capacitor association in parallel with the first input voltage while the second half bridge is selectively configured to discharge the second capacitor association in series with the second input voltage to generate an output voltage of the submodule that is greater than the input voltage. The full bridge selectively configurable to generate an output voltage that is selectively a positive version of an output voltage of plurality of submodules or a negative version of the output voltage of the plurality of submodules. [0004] Implementations of the disclosure may include one or more of the following optional features. In some implementations, the first input voltage is the second input voltage. In some examples, each submodule of the plurality of submodules also includes a respective third half bridge including a respective third capacitor association and connected to the common ground. In some implementations, the first half bridge of each submodule includes a first power transistor having a drain, a source, and a gate; and a second power transistor having a drain, a source, and a gate. The drain of the second power transistor connected to the source of the first power transistor, the source of the second power transistor connected to the common ground, and the first capacitor association connected between the drain of the first power transistor and the source of the second power transistor. Each submodule may further include a first gate driver configured to provide a first gate control signal at the gate of the first power transistor based on a first digital control input provided by a controller; a second gate driver configured to provide a second gate control signal at the gate of the second power transistor based on a second digital control input provided by the controller; and a bootstrap capacitor connected between the drain of the second power transistor and a drive supply voltage for the submodule. The bootstrap capacitor may float the first gate driver such that an isolated voltage source is not needed by the first gate driver to drive the first gate control signal. In some examples, the second half bridge of each submodule includes: a third power transistor having a drain, a source, and a gate; and a fourth power transistor having a drain, a source, and a gate. The drain of the fourth power transistor connected to the source of the third power transistor; the source of the fourth power transistor connected to the common ground; and the second capacitor association connected between the drain of the third power transistor and the source of the fourth power transistor. The source of the second power transistor may be connected to the source of the fourth power transistor and to the common ground.

[0005] In some examples, the first capacitor association includes a first plurality of capacitors. The first plurality of capacitors may include a first plurality of surface mount ceramic multilayer capacitors. The first plurality of capacitors may include a plurality of series capacitor associations connected in parallel, each series capacitor association including two or more capacitors connected in series.

[0006] In some implementations, a first submodule of the plurality of submodules can be isolated while other submodules are selectively configured to generate the output voltage of the plurality of submodules. In some examples, one or more of the plurality of submodules are hot swappable during operation of the switched capacitor interleaved multilevel inverter. In some implementations, one or more of the plurality of submodules are redundant submodules.

[0007] Another aspect of the disclosure provides a method of up-converting an input voltage using a plurality of switched capacitor submodules arranged in series, each submodule of the plurality of submodules comprising a respective first half bridge including a respective first capacitor association and a respective second half bridge comprising a respective second capacitor association. The method including, during a first time interval, configuring the respective first half bridges and the respective second half bridges of one or more of the plurality of submodules to charge their respective capacitor associations. During a second time interval, the method includes configuring the respective first half bridge of a first submodule of the plurality of submodules to charge its respective first capacitor association; and configuring the respective second half bridge of the first submodule to discharge its respective second capacitor association in series with the input voltage.

[0008] Implementations of the disclosure may include one or more of the following optional features. In some implementations, during a third time interval, the method includes configuring the respective second half bridge of the first submodule to charge its second capacitor association; and configuring the respective first half bridge of the first submodule to discharge its first capacitor association in series with the input voltage. In some examples, the method, during a third interval, includes configuring the respective second half bridge of a second submodule of the plurality of submodules to charge its respective second capacitor association; and configuring the respective first half bridge of the second submodule to discharge its first capacitor association in series with the input voltage. The method may further include selecting the second submodule to be different from the first submodule to allow the first submodule to thermally cool during the third time interval.

[0009] In some examples, the method includes, during a third time interval, configuring the respective first half bridges of a first pair of the plurality of submodules to charge their respective first capacitor associations; and configuring the respective second half bridges of the first pair of the plurality of submodules to discharge their respective second capacitor associations in series with the input voltage. In some implementations, during a fourth time interval, the method includes configuring the respective second half bridges of the first pair of the plurality of submodules to charge their respective second capacitor associations; and configuring the respective first half bridges of the first pair of the plurality of submodules to discharge their respective first capacitor associations in series with the input voltage. Alternatively, during a fourth time interval, the method includes configuring the respective first half bridges of a second pair of the plurality of submodules to charge their respective first capacitor associations; and configuring the respective second half bridges of the second pair of the plurality of submodules to discharge their respective second capacitor associations in series with the input voltage. The second pair of the plurality of submodules may be selected to be different from the first pair of the plurality of submodules to allow one or more submodules of the first pair of the plurality of submodules to thermally cool during the fourth time interval. In another alternative, during a fourth time interval, the method includes configuring the respective first half bridges of three submodules of the plurality of submodules to charge their respective first capacitor associations; and configuring the respective second half bridges of the three submodules to discharge their respective second capacitor associations in series with the input voltage. During a fifth time interval, the method includes configuring the respective second half bridges of the three submodules to charge their respective first capacitor associations; and configuring the respective first half bridges of the three submodules to discharge their respective second capacitor associations in series with the input voltage.

[0010] The details of one or more implementations of the disclosure are set forth in the accompanying drawings and the description below. Other aspects, features, and advantages will be apparent from the description and drawings, and from the claims. DESCRIPTION OF DRAWINGS

[0011] FIG. lA is a schematic diagram of an example switched capacitor interleaved multilevel inverter (SCI-MI).

[0012] FIG. IB is a schematic diagram of another example switched capacitor interleaved multilevel inverter (SCI-MI).

[0013] FIG. 1C is a schematic diagram of yet another example switched capacitor interleaved multilevel inverter (SCI-MI).

[0014] FIG. 2 is a schematic diagram of an example switched capacitor submodule.

[0015] FIG. 3 is a schematic diagram of an example capacitor association.

[0016] FIG. 4 is a schematic diagram of an example full bridge.

[0017] FIG. 5 is a flowchart of an example arrangement of operations for a method of operating an SCI-MI.

[0018] FIG. 6 is a schematic view of an example controller that may be used to implement the systems and methods described herein.

[0019] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0020] For safety purposes, current batteries provide a maximum direct current (DC) voltage of 48 volts (V). Most of the portable batteries found in the market obey this voltage limitation, to comply with safety standards. The electric grid, however, provides an alternating current (AC) voltage with a peak of 170V to 180V for power levels up to 2400W, or 240V for higher power levels. In order to generate such AC voltages, one needs to at least generate the peak voltage. In some examples, an inverter generates a cycling stepped sequence of voltages that includes the peak voltage and approximates a sinusoidal voltage waveform. The inverter may include a step-up converter to increase the 48 V DC voltage to create the stepped sequence of voltages, including the peak voltage. An inverter may be used in any number of applications. For example, an inverter may be electrically connected to an array of photovoltaic cells to harvest energy from the sun and provide for efficient conversion to AC voltages. [0021] Some conventional step-up converters generate a higher voltage from a lower voltage by passing current through an inductor, where the inductor generates the higher voltage when the current is turned OFF. Typically, the inductor is turned on and off quickly, and the generated voltage is stored in a capacitor. However, opening and closing the circuit creates heat and electromagnetic radiation. Additionally, inductors are very large and bulky.

[0022] Another conventional step-up converter is a switched capacitor converter that includes multiple capacitors in series with an input voltage to multiply the input voltage. Such converters rely on low-frequency capacitor switching using electrolytic capacitors. However, electrolytic capacitors are bulky, large, and prone to degradation over time, which may result in converters that are large, heavy, and unreliable. Moreover, conventional switch-capacitor converters rely on multiple floating power switches that each require a dedicate voltage source, which further increases design complexity, size, and cost. Furthermore, the exchange of charge between capacitors in conventional switch-capacitor converters introduces intrinsic losses.

[0023] Disclosed implementations overcome at least these disadvantages using a plurality of selectively controllable switched capacitor submodules that each include two or more half bridges, where the half bridges are interleaved and each half bridge has a respective capacitor association. Here, a capacitor association refers to a collection of capacitors connected in series and/or in parallel. For example, by interleaving two half bridges within a submodule, one half bridge can be selectively configured so that its respective capacitor association is parallel to, and is charged by an input voltage, while the other half bridge of the submodule is selectively configured so that its respective capacitor association is in series with the input voltage and, thus, increases an output voltage by up to the input voltage. That is, the capacitor associations may be charged and discharged with 180 degrees of phase shift, which reduces harmonic distortion in the input and output of the submodule, or a converter including the submodule. Disclosed implementations do not depend on charge transfer between the capacitor associations, nor do they rely on inductors. [0024] By selectively controlling which and how many submodules across one or more switched capacitor submodules are discharging at the same time, an output voltage may be selectively controlled and used to generate a sequence of stepped output voltages. That is, by sequentially increasing and decreasing the number of capacitor associations that are discharging during a particular time interval, the output voltage may be sequentially increased and decreased according to a sinusoidal voltage waveform.

[0025] In disclosed implementations, the submodules can be operated independently such the number and selection of submodules used to generate a particular voltage can be dynamically and selectively changed over time. For example, first and second capacitor associations may be discharged during a first time interval, while third and fourth capacitor associations are discharged during a second time interval. During any given time interval, particular capacitor associations may be neither charging nor discharging, which allows those capacitor associations to thermally cool to improve system efficiency and reduce the need for heat sinks or other cooling mechanisms. Disclosed implementations allow for redundancy between submodules and/or capacitor associations such that not all half bridges have to be activated (e.g., charging or discharging) each switching cycle. In some implementations, additional redundant submodules may be provided such that a redundant submodule may be used when/if a submodule malfunctions. In some implementations, submodules are hot swappable during operation, such that a malfunctioning submodule may be isolated (e.g., not used), physically replaced, and then used for subsequent conversions. In some implementations, additional submodules are included to provide additional opportunities for capacitor associations to thermally cool and, thus, to improve system efficiency. In some examples, submodules and/or capacitor associations are implemented as pluggable modules that can be selectively installed by plugging them into a socket on a circuit board and/or can be selectively removed by unplugging them from the circuit board.

[0026] Disclosed implementations enable a higher switching frequency (e.g., between 50kHz and 100kHz) such that capacitor associations of smaller and more thermally stable surface mount multilayer capacitors may be used instead of conventional bulky electrolytic capacitors. Due to the higher switching frequency, disclosed capacitor associations do not need to hold their output voltage as long, which reduces the amount of capacitance disclosed capacitor associations need to provide.

[0027] FIG. 1 A is a schematic diagram of an example switched capacitor interleaved multilevel inverter (SCI-MI) 100a. The SCI-MI 100a includes a plurality of switched capacitor submodules 200, 200a-n that are arranged in series with an input voltage Vi 110 and connected to a common ground 120. The submodules 200 are selectively configurable by a controller 600 to generate output voltages Vo 140 that are multiples of the input voltage Vi 110. Here, each submodule 200 may be selectively configured to provide a gain of two (2). For example, the controller 600 may selective configure various numbers and combinations of the submodules 200 to generate different output voltages Vo 140. Example output voltages Vo 140 include, but are not limited to, 0V, Vi, 2* Vi, and 3* Vi. Notably, the controller 600 may sequentially configure increasing and decreasing numbers of the submodules 200 to discharge during sequential time intervals to cause the output voltage Vo 140 to be an increasing and decreasing sequence of stepped voltages approximating a step-wise sinusoidal waveform.

[0028] The SCI-MI 100a also includes a full bridge circuit 400 selectively configurable by the controller 600 to generate positive or negative voltages Vt 150 from the output voltages Vo 140, and a filter 160 configured to smooth the voltages Vt 150 to provide output AC voltages Vac 170. In some implementations, because the submodules 200 can be selectively configured by the controller 600 to generate a step-wise sinusoidal waveform, a filter 160 implements a second order low pass filter. However, in some implementations, the filter 160 is omitted, or more complex.

[0029] FIG. IB is a schematic diagram of another example SCI-MI 100b. The SCI- MI 100b is similar to the SCI-MI 100a of FIG. 1 A, except that the submodules 200 of FIG. IB are powered by multiple input voltages Vi 110a, 110b. The input voltages Vi 110a and 110b may be of the same voltage (as shown) or different voltages. By using N input voltages Vi 110, each input voltage Via 110 needs to only provide 1/Nth the power of the input voltage Vi 110 of FIG. 1 A.

[0030] FIG. 1C is a schematic diagram of yet another example SCI-MI 100c. The SCI-MI 100c is similar to the SCI-MI 100b of FIG. IB, except that the submodules 200 of FIG. 1C include more than two half bridges that are powered by respective input voltages Vi HOa-n. The input voltages Vi HOa-n may be of the same voltage or different voltages. By using multiple input voltages Vi 1 lOa-n, each input voltages Vi HOa-n needs to only a portion of the power of the input voltage Vi 110 of FIG. 1A. [0031] FIG. 2 is a schematic diagram of an example switched capacitor submodule 200. In the example shown, the submodule 200 includes a first half bridge 210 and a second half bridge 220. However, one of ordinary skill in the art will recognize that a switched capacitor submodule may be expanded to implement more than two half bridges, as shown in FIG. 1C. Moreover, not all switched capacitor submodules of an SCI-MI 100 need to implement the same number of half bridges. The first half bridge 210 includes a first power transistor Tin 211 with an associated bypass capacitor (not shown for clarity of illustration), a second power transistor T2n 212 with an associated bypass capacitor (not shown for clarity of illustration), and a first capacitor association Cln 300, 300a. As shown, the drain 21 Id of the first power transistor Tin 211 is connected to a first input terminal 230 of the submodule 200, the source 21 Is of the first power transistor Tin 211 is connected to the drain 212d of the second power transistor T2n 212, the source 212s of the first power transistor T2n 212 is connected to a ground 240 of the submodule 200, and the first capacitor association Cln 300a is connected between the drain 21 Id and the source 212s.

[0032] The first half bridge 210 includes a first gate driver 213 for providing a first gate voltage 214 to control (i.e., turn ON and turn OFF) the first power transistor Tin 211 responsive to a respective first digital control input Sin 215 provided by the controller 600. Notably, a first bootstrap capacitor 216 is connected between the drain 212d of the second power transistor T2n 212 and a drive supply voltage 245 to float the first gate driver 213 rather than using a separate isolated drive voltage supply to generate a separate drive voltage for the first gate driver 213. The first half bridge 210 also includes a second gate driver 217 for providing a second gate voltage 218 to control (i.e., turn ON and turn OFF) the second power transistor T2n 212 responsive to a respective second digital control input S2n 219 provided by the controller 600. [0033] When the first power transistor Tin 211 is turned OFF (i.e., the first digital control input Sin 215 is low) and the second power transistor T2n 212 is turned ON (i.e., the second digital control input S2n 219 is high), the first capacitor association Cln 300a is charged to, and in parallel with an input voltage on the first input terminal 230. When the first power transistor Tin 211 is turned ON (i.e., the first digital control input Sin 215 is high) and the second power transistor T2n 212 is turned OFF (i.e., the second digital control input S2n 219 is low), the first capacitor association Cln 300a is discharged onto a first output terminal 250 in series with an input voltage on the first input terminal 230, thus creating an output voltage that is twice the input voltage.

[0034] Similarly, the second half bridge 220 includes a third power transistor T3n 221 with an associated bypass capacitor (not shown for clarity of illustration), a fourth power transistor T4n 222 with an associated bypass capacitor (not shown for clarity of illustration), and a second capacitor association C2n 300, 300b. As shown, the drain 221d of the third power transistor T3n 221 is connected to a second input terminal 260 of the submodule 200, the source 221s of the third power transistor T3n 221 is connected to the drain 222d of the fourth power transistor T4n 222, the source 222s of the fourth power transistor T4n 222 is connected to the ground 240 of the submodule 200, and the second capacitor association C2n 300b is connected between the drain 22 Id and the source 222s.

[0035] The second half bridge 220 includes a third gate driver 223 for providing a third gate voltage 224 to control (i.e., turn ON and turn OFF) the third power transistor T3n 221 responsive to a respective third digital control input S3n 225 provided by the controller 600. Notably, a second bootstrap capacitor 226 is connected between the drain 222d of the fourth power transistor T4n 222 and the drive supply voltage 245 to float the third gate driver 223 rather than using a separate isolated drive voltage supply to generate a separate drive voltage for the third gate driver 223. The second half bridge 220 also includes a fourth gate driver 227 for providing a fourth gate voltage 228 to control (i.e., turn ON and turn OFF) the fourth power transistor T4n 222 responsive to a respective fourth digital control input S4n 229 provided by the controller 600. [0036] When the third power transistor T3n 221 is turned OFF (i.e., the third digital control input S3n 225 is low) and the fourth power transistor T4n 222 is turned ON (i.e., the fourth digital control input S4n 229 is high), the second capacitor association C2n 300b is charged to, and in parallel with an input voltage on the second input terminal 260. When the third power transistor T3n 221 is turned ON (i.e., the third digital control input S3n 225 is high) and the fourth power transistor T4n 222 is turned OFF (i.e., the fourth digital control input S4n 229 is low), the second capacitor association C2n 300b is discharged onto a second output terminal 270 in series with an input voltage on the second input terminal 260, thus creating an output voltage that is twice the input voltage. [0037] As shown, the first half bridge 210 and the second half bridge 220 are interleaved such that one of the capacitor associations 300 (e.g., the first capacitor association 300a) may be charged while the other capacitor association 300 (e.g., the second capacitor association 300b) is discharged. That is, the capacitor associations 300 may be charged and discharged with 180 degrees of phase shift, which reduces harmonic distortion. Additionally, both capacitor associations 300 may be charged at the same time, or may both be discharged at the same time. Moreover, both capacitor associations 300 may be isolated at the same time (i.e., neither charging nor discharging). In some implementations, the capacitor associations 300 are positioned adjacent to one another on a circuit board. Any resulting variation in output voltage may be the same as not using multiple capacitor associations 300, or may be reduced compared to conventional switched capacitor step-up converters. Ultimately, because of the interleaving, disclosed implementations require a smaller amount of capacitance compared to conventional switched capacitor step-up converters. Disclosed implementations do not depend on charge transfer between the capacitor associations 300, nor do they rely on inductors. [0038] Because of how the plurality of submodules 200 are connected (see FIGS.

1 A-C), whether the capacitor associations 300 of a particular submodule 200 are charging and/or discharging is independent of, and doesn’t depend on whether the capacitor associations 300 of other submodules 200 are charging or discharging.

[0039] FIG. 3 is a schematic diagram of an example capacitor association 300. The capacitor association 300 includes a plurality of capacitors 310, 3 lOa-n. In some examples, the capacitors 310 are surface mount ceramic multiplayer capacitors. In the example shown, the capacitors 310 are arranged in a plurality of series associations 320, 320a-n that are connected in parallel, with each series association 320 including two or more capacitors 310 arranged in series.

[0040] FIG. 4 is a schematic diagram of an example full bridge 400. The full bridge 400 includes a first switch 410, a second switch 420, a third switch 430, and a fourth switch 440 arranged in a full bridge configuration. When the controller 600 configures the full bridge 400 by turning ON the first switch 410 and the fourth switch 440, and turning OFF the second switch 420 and the third switch 430, the full bridge 400 outputs positive voltages Vt 150 based on voltages Vo 140. That is, generate positive versions of the voltages Vo 140. When the controller 600 configures the full bridge 400 by turning OFF the first switch 410 and the fourth switch 440, and turning ON the second switch 420 and the third switch 430, the full bridge 400 outputs negative voltages Vt 150 based on voltages Vo 140. That is, generate negative versions of the voltages Vo 140.

[0041] FIG. 5 is a flowchart of an example arrangement of operations for a computer- implemented method 500 of operating an SCI-MI 100 including switched capacitor submodules 200 having two half bridges. However, one of ordinary skill in the art will recognize that the method 500 may be modified to accommodate more than two half bridges per submodule 200 and/or to accommodate different numbers of half bridges per submodule 200. Operations of the method 500 are repeated for each cycle period of a desired AC waveform.

[0042] At operation 502, the method 500 includes configuring the full bridge 400 to generate positive voltages. That is, by turning ON the first switch 410 and the fourth switch 440, and turning OFF the second switch 420 and the third switch 430.

[0043] At operation 504, the method 500 includes for a first time interval corresponding to the desired duration of an output voltage Vo 140 corresponding to an input voltage Vi 110, charging the capacitor associations 300 of one or more submodules 200. For example, by setting their digital control inputs Sin and S3n to low, and setting their digital control inputs S2n and S4n to high. In some implementations, which submodules 200 are charging is varied over time to allow thus isolated capacitor associations 300 to thermally cool.

[0044] The method 500 includes, for a second time interval corresponding to the desired duration of an output voltage Vo 140 corresponding to twice the input voltage Vi 110, at operation 506 configuring a first single submodule 200 to, during a sub interval, charge its first capacitor association 300a while discharging its second capacitor association 300b. For example, by setting its digital control inputs Sin and S4n to high, and setting its digital control inputs S2n and S3n to low. Then, at operation 508, the method 500 includes configuring the first submodule 200 to, during a subsequent sub interval, discharge its first capacitor association 300a while charging its second capacitor association 300b. For example, by setting its digital control inputs S2n and S3n to high, and setting its digital control inputs Sin and S4n to low. Operations 506 and 508 may be repeated using the first submodule 200, or using one or more other single submodules 200 for a remaining portion of the second time interval. For example, using the submodule 200a, then using the submodule 200b, then using the submodule 200c, etc. [0045] The method 500 includes, for a third time interval corresponding to the desired duration of an output voltage Vo 140 corresponding to three times the input voltage Vi 110, at operation 510 configuring a first pair of submodules 200 to, during a sub interval, charge their first capacitor 300a while discharging their second capacitor association 300b. For example, by setting their digital control inputs Sin and S4n to high, and setting their digital control inputs S2n and S3n to low. Then, at operation 512, the method 500 includes configuring the first pair of submodules 200 to, during a subsequent sub interval, discharge their first capacitor associations 300a while charging their second capacitor associations 300b. For example, by setting their digital control inputs S2n and S3n to high, and setting their digital control inputs Sin and S4n to low. Operations 510 and 512 may be repeated using the first pair of submodules 200, or using one or more other pairs of the submodules 200 for a remaining portion of the desired duration of an output voltage corresponding to three times the input voltage. For example, using the submodules 200a and 200b, then using the submodules 200b and 200c, then using the submodules 200c and 200d, etc. [0046] The method 500 may continue using increasing numbers of submodules 200 until either a desired peak output voltage Vo 140 is being generated, or all functioning submodule 200 are being used at the same time.

[0047] The method 500 continues at operation 514 with performing operations 512 to 504 in reverse order to sequentially step down the output voltage Vo 140.

[0048] At operation 516, the method 500 includes configuring the full bridge 400 to generate negative voltages. That is by turning OFF the first switch 410 and the fourth switch 440, and turning ON the second switch 420 and the third switch 430.

[0049] The method 500 continues at operation 518 with performing operations 504 to 514 to generate step-wise negative voltages.

[0050] FIG. 6 is schematic view of an example controller 600 that may be used to implement the systems and methods described in this document. The controller 600 is intended to represent various forms of controllers, and other appropriate computing platforms. The controller 600 may be, for example, an embedded controller of a device including or implementing an SCI-MI 100. The components shown here, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed in this document.

[0051] The controller 600 includes a processor 610 (i.e., data processing hardware), memory 620 (i.e., memory hardware), a storage device 630 (i.e., memory hardware), a high-speed interface/controller 640 connecting to the memory 620 and high-speed expansion ports 650, and a low speed interface/controller 660 connecting to a low speed bus 670 and a storage device 630. Each of the components 610, 620, 630, 640, 650, and 660, are interconnected using various busses, and may be mounted on a common motherboard or in other manners as appropriate. The processor 610 can process instructions for execution within the controller 600, including instructions stored in the memory 620 or on the storage device 630 to display graphical information for a graphical user interface (GUI) on an external input/output device, such as display 680 coupled to high speed interface 640. In other implementations, multiple processors and/or multiple buses may be used, as appropriate, along with multiple memories and types of memory. [0052] The memory 620 stores information non-transitorily within the controller 600. The memory 620 may be a computer-readable medium, a volatile memory unit(s), or non-volatile memory unit(s). The non-transitory memory 620 may be physical devices used to store programs (e.g., sequences of instructions) or data (e.g., program state information) on a temporary or permanent basis for use by the controller 600. Examples of non-volatile memory include, but are not limited to, flash memory and read-only memory (ROM) / programmable read-only memory (PROM) / erasable programmable read-only memory (EPROM) / electronically erasable programmable read-only memory (EEPROM) (e.g., typically used for firmware, such as boot programs). Examples of volatile memory include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), phase change memory (PCM) as well as disks or tapes.

[0053] The storage device 630 is capable of providing mass storage for the controller 600. In some implementations, the storage device 630 is a computer-readable medium. In various different implementations, the storage device 630 may be a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid state memory device, or an array of devices, including devices in a storage area network or other configurations. In additional implementations, a computer program product is tangibly embodied in an information carrier. The computer program product contains instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer- or machine-readable medium, such as the memory 620, the storage device 630, or memory on processor 610.

[0054] The high speed controller 640 manages bandwidth-intensive operations for the controller 600, while the low speed controller 660 manages lower bandwidth-intensive operations. Such allocation of duties is exemplary only. In some implementations, the high-speed controller 640 is coupled to the memory 620, the display 680 (e.g., through a graphics processor or accelerator), and to the high-speed expansion ports 650, which may accept various expansion cards (not shown). In some implementations, the low-speed controller 660 is coupled to the storage device 630 and a low-speed expansion port 690. The low-speed expansion port 690, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), may be coupled to one or more input/output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or router, e.g., through a network adapter.

[0055] Various implementations of the systems and techniques described herein can be realized in digital electronic and/or optical circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0056] These computer programs (also known as programs, software, software applications or code) include machine instructions for a programmable processor, and can be implemented in a high-level procedural and/or object-oriented programming language, and/or in assembly/machine language. As used herein, the terms “machine-readable medium” and “computer-readable medium” refer to any computer program product, non- transitory computer readable medium, apparatus and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term “machine-readable signal” refers to any signal used to provide machine instructions and/or data to a programmable processor.

[0057] The processes and logic flows described in this specification can be performed by one or more programmable processors, also referred to as data processing hardware, executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0058] To provide for interaction with a user, one or more aspects of the disclosure can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube), LCD (liquid crystal display) monitor, or touch screen for displaying information to the user and optionally a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user's client device in response to requests received from the web browser.

[0059] The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The claimed invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

[0060] In the foregoing specification, specific examples/implementations have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present disclosure. Additionally, the described examples/implementations should not be interpreted as mutually exclusive, and should instead be understood as potentially combinable if such combinations are permissive in any way. In other words, any feature disclosed in any of the aforementioned examples/implementations may be included in any of the other aforementioned examples/implementations.

[0061] Relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0062] The terms “comprises,” “comprising,” “has”, “having,” “includes”, “including,” “contains”, “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises .. . a”, “has .. . a”, “includes . . . a”, “contains ... a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element.

[0063] The terms “a” or “an” are employed to describe elements and components of the embodiments herein. This is done merely for convenience and to give a general sense of the description. The terms “a” and “an” are defined as one or more unless explicitly stated otherwise herein. This description, and the claims that follow, should be read to include one or at least one, and the singular also includes the plural unless it is obvious that it is meant otherwise.

[0064] A device or structure that is “configured” in a certain way is configured in at least that way, but may also be configured in ways that are not listed. As used herein, the expressions “in communication,” “coupled” and “connected,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct mechanical or physical (e g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events. Disclosed examples/implementations are not limited in this context.

[0065] Unless expressly stated to the contrary, the phrase “at least one of A, B, or C” is intended to refer to any combination or subset of A, B, C such as: (1) at least one A alone; (2) at least one B alone; (3) at least one C alone; (4) at least one A with at least one B; (5) at least one A with at least one C; (6) at least one B with at least C; and (7) at least one A with at least one B and at least one C. Moreover, unless expressly stated to the contrary, the phrase “at least one of A, B, and C” is intended to refer to any combination or subset of A, B, C such as: (1) at least one A alone; (2) at least one B alone; (3) at least one C alone; (4) at least one A with at least one B; (5) at least one A with at least one C; (6) at least one B with at least one C; and (7) at least one A with at least one B and at least one C. Furthermore, unless expressly stated to the contrary, “A or B” is intended to refer to any combination of A and B, such as: (1) A alone; (2) B alone; and (3) A and B. [0066] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various implementations/ examples for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples/implementations require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter may lie in less than all features of a single disclosed example/implementation.

Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

[0067] A number of examples/implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other examples/implementations may be within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:

1. A switched capacitor interleaved multilevel inverter (100) comprising: a plurality of switched capacitor submodules (200) arranged in series with first and second input voltages (110) and connected to a common ground (120), each submodule (200) of the plurality of submodules (200) comprising: a respective first half bridge (210) comprising a respective first capacitor association (300a) and connected to the common ground (120); and a respective second half bridge (220) comprising a respective second capacitor association (300b) and connected to the common ground (120), the first half bridge (210) and the second half bridge (220) interleaved such that the first half bridge (210) can be selectively configured to charge the first capacitor association (300a) in parallel with the first input voltage (110) while the second half bridge (220) is selectively configured to discharge the second capacitor association (300b) in series with the second input voltage (110) to generate an output voltage of the submodule that is greater than the second input voltage (110); and a full bridge (400) selectively configurable to generate an output voltage (150) that is selectively a positive version of an output voltage (140) of plurality of submodules (200) or a negative version of the output voltage (140) of the plurality of submodules (200).

2. The switched capacitor interleaved multilevel inverter (100) of claim 1, wherein the first input voltage (110) comprises the second input voltage (110).

3. The switched capacitor interleaved multilevel inverter (100) of any of claims 1-2, wherein each submodule (200) of the plurality of submodules (200) further comprises a respective third half bridge comprising a respective third capacitor association and connected to the common ground (120).

4. The switched capacitor interleaved multilevel inverter (100) of any of claims 1-3, wherein: the first half bridge (210) of each submodule (200) comprises: a first power transistor (211) comprising a drain (21 Id), a source (211s), and a gate (211g); and a second power transistor (212) comprising a drain (212d), a source (212s), and a gate (212g); the drain (212d) of the second power transistor (212) is connected to the source (211s) of the first power transistor (211); the source (212s) of the second power transistor (212) is connected to the common ground (120); and the first capacitor association (300a) is connected between the drain (21 Id) of the first power transistor (211) and the source (212s) of the second power transistor (212).

5. The switched capacitor interleaved multilevel inverter (100) of claim 4, wherein each submodule (200) further comprises: a first gate driver (213) configured to provide a first gate control signal (214) at the gate (211g) of the first power transistor (211) based on a first digital control input (215) provided by a controller (600); a second gate driver (217) configured to provide a second gate control signal (218) at the gate (212g) of the second power transistor (212) based on a second digital control input (219) provided by the controller (600); and a bootstrap capacitor (216) connected between the drain (212d) of the second power transistor (212) and a drive supply voltage (240) for the submodule (200).

6. The switched capacitor interleaved multilevel inverter (100) of claim 5, wherein the bootstrap capacitor (216) floats the first gate driver (213) such that an isolated voltage source is not needed by the first gate driver (213) to drive the first gate control signal (214).

7. The switched capacitor interleaved multilevel inverter (100) of claim 4, wherein: the second half bridge (220) of each submodule (200) comprises: a third power transistor (221) comprising a drain (221d), a source (221s), and a gate (221g); and a fourth power transistor (222) comprising a drain (222d), a source (222s), and a gate (222g); the drain (222d) of the fourth power transistor (222) is connected to the source (221s) of the third power transistor (221); the source (222s) of the fourth power transistor (222) is connected to the common ground (120); and the second capacitor association (300b) is connected between the drain (22 Id) of the third power transistor (221) and the source (222s) of the fourth power transistor (222).

8. The switched capacitor interleaved multilevel inverter (100) of claim 7, wherein the source (212s) of the second power transistor (212) is connected to the source (222s) of the fourth power transistor (222) and to the common ground (120).

9. The switched capacitor interleaved multilevel inverter (100) of claim 1, wherein the first capacitor association (300a) comprises a first plurality of capacitors (310).

10. The switched capacitor interleaved multilevel inverter (100) of claim 9, wherein the first plurality of capacitors (310) comprises a first plurality of surface mount ceramic multilayer capacitors.

11. The switched capacitor interleaved multilevel inverter (100) of claim 9, wherein the first plurality of capacitors (310) comprises a plurality of series capacitor associations (320) connected in parallel, each series capacitor association (320) comprising two or more capacitors (310) connected in series.

12. The switched capacitor interleaved multilevel inverter (100) of any of claims 1-

11, wherein a first submodule (200) of the plurality of submodules (200) can be isolated while other submodules (200) are selectively configured to generate the output voltage (140) of the plurality of submodules (200).

13. The switched capacitor interleaved multilevel inverter (100) of any of claims 1-

12, wherein one or more of the plurality of submodules (200) are hot swappable during operation of the switched capacitor interleaved multilevel inverter (100).

14. The switched capacitor interleaved multilevel inverter (100) of any of claims 1-

13, wherein one or more of the plurality of submodules (200) are redundant submodules (200).

15. A method (500) of up-converting an input voltage (110) using a plurality of switched capacitor submodules (200) arranged in series, each submodule (200) of the plurality of submodules (200) comprising a respective first half bridge (210) including a respective first capacitor association (300a), and a respective second half bridge (220) comprising a respective second capacitor association (300b), the method (500) comprising: during a first time interval, configuring the respective first half bridges (210) and the respective second half bridges (220) of one or more of the plurality of submodules (200) to charge their respective capacitor associations (300a, 300b); and during a second time interval: configuring the respective first half bridge (210) of a first submodule (200) of the plurality of submodules (200) to charge its respective first capacitor association (300a); and configuring the respective second half bridge (220) of the first submodule (200) to discharge its respective second capacitor association (300b) in series with the input voltage (110).

16. The method (500) of claim 15, further comprising, during a third time interval: configuring the respective second half bridge (220) of the first submodule (200) to charge its second capacitor association (300b); and configuring the respective first half bridge (210) of the first submodule (200) to discharge its first capacitor association (300a) in series with the input voltage (110).

17. The method (500) of claim 15, further comprising, during a third time interval: configuring the respective second half bridge (220) of a second submodule (200) of the plurality of submodules (200) to charge its respective second capacitor association (300b); and configuring the respective first half bridge (210) of the second submodule (200) to discharge its first capacitor association (300a) in series with the input voltage (110).

18. The method (500) of claim 17, further comprising selecting the second submodule (200) to be different from the first submodule (200) to allow the first submodule (200) to thermally cool during the third time interval.

19. The method (500) of claim 15, further comprising, during a third time interval: configuring the respective first half bridges (210) of a first pair of the plurality of submodules (200) to charge their respective first capacitor associations (300a); and configuring the respective second half bridges (220) of the first pair of the plurality of submodules (200) to discharge their respective second capacitor associations (300b) in series with the input voltage (110).

20. The method (500) of any of claims 16-19, further comprising, during a fourth time interval: configuring the respective second half bridges (220) of the first pair of the plurality of submodules (200) to charge their respective second capacitor associations (300b); and configuring the respective first half bridges (210) of the first pair of the plurality of submodules (200) to discharge their respective first capacitor associations (300a) in series with the input voltage (110).

21. The method (500) of any of claims 16-19, further comprising, during a fourth time interval: configuring the respective first half bridges (210) of a second pair of the plurality of submodules (200) to charge their respective first capacitor associations (300a); and configuring the respective second half bridges (220) of the second pair of the plurality of submodules (200) to discharge their respective second capacitor associations (300b) in series with the input voltage (110).

22. The method (500) of claim 21, further comprising selecting the second pair of the plurality of submodules (200) to be different from the first pair of the plurality of submodules (200) to allow one or more submodules (200) of the first pair of the plurality of submodules (200) to thermally cool during the fourth time interval.

23. The method (500) of any of claims 16-19, further comprising, during a fourth time interval: configuring the respective first half bridges (210) of three submodules (200) of the plurality of submodules (200) to charge their respective first capacitor associations (300a); and configuring the respective second half bridges (220) of the three submodules (200) to discharge their respective second capacitor associations (300b) in series with the input voltage (110).

24. The method (500) of any of claims 20-23, further comprising, during a fifth time interval: configuring the respective second half bridges (220) of the three submodules (200) to charge their respective first capacitor associations (300a); and configuring the respective first half bridges (210) of the three submodules (200) to discharge their respective second capacitor associations (300b) in series with the input voltage (110).