WO2024129546A1

WO2024129546A1 - Using voltage comparators at different threshold values and at different states using firmware

Info

Publication number: WO2024129546A1
Application number: PCT/US2023/083238
Authority: WO
Inventors: Ramesh Arvapalli; Kai-Yen WANG; Hanil Lee; Chulmin Jung; Shao-Hsuan Chang; Kaustav ROYCHOWDHURY
Original assignee: Qualcomm Incorporated
Priority date: 2022-12-13
Filing date: 2023-12-08
Publication date: 2024-06-20

Abstract

A method for using a voltage comparator circuit at different thresholds and at different sates using firmware includes detecting, via the voltage comparator circuit, a transition of a processor from a first mode to a second mode. A voltage reference threshold of the voltage comparator circuit is dynamically adapted from a first threshold to a second threshold. The processor operates in the second mode responsive to the voltage comparator circuit detecting that a voltage of the processor is greater than or equal to the second threshold.

Description

USING VOLTAGE COMPARATORS AT DIFFERENT THRESHOLD VALUES AND AT DIFFERENT STATES USING FIRMWARE

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims the benefit of India Application No. 202241072001, filed on December 13, 2022, and titled “USING VOLTAGE COMPARATORS AT DIFFERENT THRESHOLD VALUES AND AT DIFFERENT STATES USING FIRMWARE,” the disclosure of which is expressly incorporated by reference in its entirety.

BACKGROUND

Field

[0002] Aspects of the present disclosure relate to integrated circuits and more particularly to using voltage comparator circuits at different threshold values at different states using firmware.

Background

[0003] State-of-the-art mobile application devices demand a small form factor, low cost, a tight power budget, and high electrical performance. To increase performance (e.g., processor speed) and reduce power consumption, some conventional approaches utilize various low voltage processor operating modes. In doing so, certain settings may be implemented in hardware to control changing the system clock when transitioning between the different modes. Unfortunately, failing to appropriately change the system clock for the different modes may result in critical errors that may be challenging and costly to remedy.

SUMMARY

[0004] The present disclosure is set forth in the independent claims, respectively. Some aspects of the disclosure are described in the dependent claims.

[0005] In aspects of the present disclosure, a method includes detecting, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode. The method further includes dynamically adapting a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold. The method still further includes operating the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold.

[0006] Other aspects of the present disclosure are directed to an apparatus including means for detecting, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode. The apparatus further includes means for dynamically adapting a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold. The apparatus still further includes means for operating the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold.

[0007] In other aspects of the present disclosure, a non-transitory computer-readable medium with non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes program code to detect, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode. The program code further includes program code to dynamically adapt a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold. The program code still further includes program code to operate the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold.

[0008] Other aspects of the present disclosure are directed to an apparatus having memory and one or more processors coupled to the memory. The processor(s) is configured to detect, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode. The processor(s) is further configured to dynamically adapt a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold. The processor(s) is still further configured to operate the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold.

[0009] This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure will be described below. It should be appreciated by those skilled in the art that this present disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0011] FIGURE 1 illustrates an example implementation of a host system-on-a-chip (SOC), including a voltage comparator circuit, in accordance with certain aspects of the present disclosure.

[0012] FIGURE 2 shows a cross-sectional view of a stacked integrated circuit (IC) package, including the host system-on-a-chip (SOC) of FIGURE 1.

[0013] FIGURE 3 shows a cross-sectional view illustrating the stacked integrated circuit (IC) package of FIGURE 2, incorporated into a mobile device, according to one aspect of the present disclosure.

[0014] FIGURE 4 is a diagram illustrating example logic using a voltage comparator circuit at different thresholds at different states using firmware, according to various aspects of the present disclosure.

[0015] FIGURE 5 is a diagram illustrating an example sequence for adapting a reference voltage using control and status register (CSR) programming, in accordance with various aspects of the present disclosure. [0016] FIGURE 6 is a process flow diagram illustrating a method for operating a voltage comparator circuit at different thresholds at different modes using firmware, according to various aspects of the present disclosure.

[0017] FIGURE 7 is a block diagram showing an exemplary wireless communications system in which a configuration of the present disclosure may be advantageously employed.

[0018] FIGURE 8 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component according to one configuration.

DETAILED DESCRIPTION

[0019] The detailed description set forth in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent, however, to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0020] As described, the use of the term “and/or” is intended to represent an “inclusive OR,” and the use of the term “or” is intended to represent an “exclusive OR.” As described, the term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described, the term “coupled” used throughout this description means “connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described, the term “proximate” used throughout this description means “adjacent, very near, next to, or close to.” As described, the term “on” used throughout this description means “directly on” in some configurations, and “indirectly on” in other configurations. [0021] State-of-the-art mobile application devices demand a small form factor, low cost, a tight power budget, and high electrical performance. To increase performance (e.g., processor speed) and reduce power consumption, some conventional approaches utilize various low voltage processor operating modes. In doing so, certain settings may be implemented in hardware to control changing the system clock when transitioning between the different modes. Unfortunately, failing to appropriately change the system clock for the different modes may result in critical errors that may be challenging and costly to remedy.

[0022] Aspects of the present disclosure are directed to using a voltage comparator circuit at different thresholds at different states using firmware. In accordance with aspects of the preset disclosure, the voltage compactor may monitor an operating mode of a processor (e.g., central processing unit (CPU)). In response to detecting a transition from a first mode (e.g., low power mode ) to a second mode, a voltage threshold of the voltage comparator circuit may dynamically adapt from a first threshold to a second threshold. The voltage threshold may adapt via firmware or control and status register (CSR) programming, for example. Additionally, the firmware may also be employed to set or clear fused register bits, which may manage the CPU operating frequency, for instance.

[0023] Accordingly, aspects of the present disclosure may beneficially be employed to reliably change an operating mode of the processor at different points in the development cycle. Additionally, aspects of the present disclosure may beneficially enable correction of issues resulting from a mismatch of the CPU frequency and operating mode, such as when the CPU frequency is too high for a lower voltage mode, for example. Such issues may otherwise be challenging and costly to address.

[0024] FIGURE 1 illustrates an example implementation of a host system-on-a-chip (SOC) 100, which includes a voltage comparator circuit, in accordance with aspects of the present disclosure. The host SOC 100 includes processing blocks tailored to specific functions, such as a connectivity block 100. The connectivity block 110 may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth® connectivity, Secure Digital (SD) connectivity, and the like. [0025] In this configuration, the host SOC 100 includes various processing units that support multi -threaded operation. For the configuration shown in FIGURE 1, the host SOC 100 includes a multi-core central processing unit (CPU) 102, a graphics processor unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processor unit (NPU) 108. The host SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, a navigation module 120, which may include a global positioning system (GPS), and a memory 118. The multi-core CPU 102, the GPU 104, the DSP 106, the NPU 108, and the multi-media engine 112 support various functions such as video, audio, graphics, gaming, artificial networks, and the like. Each processor core of the multi-core CPU 102 may be a reduced instruction set computing (RISC) machine, an advanced RISC machine (ARM), a microprocessor, a RISC-V (RISC five) machine or some other type of processor. The NPU 108 may be based on an ARM or RISC-V instruction set.

[0026] FIGURE 2 shows a cross-sectional view illustrating a stacked integrated circuit (IC) package 200 of the host system-on-a-chip (SOC) 100 of FIGURE 1. Representatively, the stacked IC package 200 includes a printed circuit board (PCB) 202 connected to a package substrate 210 with interconnects 212. In this configuration, the package substrate 210 includes conductive layers 214 and 216. Above the package substrate 210 is a 3D chip stack 220, including stacked dies 222, 224, and 230, encapsulated by mold compound 211. In one aspect of the present disclosure, the die 230 is the host SOC 100 of FIGURE 1.

[0027] FIGURE 3 shows a cross-sectional view illustrating the stacked integrated circuit (IC) package 200 of FIGURE 2, incorporated into a wireless device 300, according to one aspect of the present disclosure. As described, the wireless device 300 may include, but is not limited to, a smartphone, tablet, handheld device, or other limited form factor device configured for 5G communications. Representatively, the stacked IC package 200 is within a phone case 304, including a display 306. In this configuration, a voltage comparator circuit is integrated into the stacked IC package 200, for example.

[0028] FIGURE 4 is a logic diagram 400 illustrating an example use of a voltage comparator circuit 402 at different thresholds at different states using firmware, according to various aspects of the present disclosure. As shown in FIGURE 4, the voltage comparator circuit 402 is coupled to a pair of AND gates 404a, 404b, the outputs of which may be used to respectively set and clear register bits (e.g., accelerator (ACC)[9:8]). The voltage comparator circuit 402 compares an input voltage with a known reference voltage. For example, the voltage comparator circuit 402 may compare a voltage of a processor (e.g., a power rail of a processor) with a reference voltage value. The voltage comparator circuit may indicate a mode of operation based on whether the detected voltage of the processor is above or below the reference voltage. In accordance with aspects of the present disclosure, the reference voltage may adapt or change using firmware or control and status register (CSR) programming, for example. In an example, the firmware may be employed to change a reference voltage of the voltage comparator circuit 402, for instance, from a first voltage VI (e.g., 1 V) to a second voltage V2 (e.g., 0.5 V). In some aspects, the reference voltage may change upon the occurrence of certain conditions. For example, the reference voltage may be conditioned on the transition of the processor from a low voltage mode to an intermediate or higher voltage mode. Of course, this is merely an example and not limiting and other criteria may control the adapting of the reference voltage.

[0029] The output of the comparator may be supplied to the AND gate 404a and an inverted input of the AND gate 404b. Because the second inputs of the AND gate 404a and gate 404b, respectively are the same (e.g., active processor chip (APC) (e.g., processor) rail_mem_svs), only one AND gate 404a and gate 404b may supply an output to change a register bit. In other words, only register ACC 9 may be set or only register ACC 8 may be cleared. The register bits may indicate a mode of operation of a processor, for instance. Additionally, the status of the register bits may control an operating frequency of the processor. For instance, when the ACC 9 bit is set, the operating frequency of the processor may decrease (e.g., for low voltage modes) and when the ACC 8 bit clears, the operating frequency may increase (e.g., for higher voltage modes). Timer elements 406a and 406b may be included to provide a delay to allow for compensation time following a change in frequency or voltage mode. The delay period for each of the timer elements 406a and 406 may be the same or different according to design preference.

[0030] FIGURE 5 is a diagram illustrating an example sequence 500 for adapting a reference voltage using control and status register (CSR) programming, in accordance with various aspects of the present disclosure. Referring to FIGURE 5, the example sequence 500 may be added in firmware when an advanced microprocessor rail ramps out of a lower voltage mode. The example sequence 500 may include accessing the CSR of the voltage comparator circuit on an advanced high-performance bus (AHB). The AHB is a high-performance bus protocol for connecting high-speed peripherals and memory in an SoC (e.g., 100).

[0031] As shown in FIGURE 5, a timeline 502 includes events related to processor voltages. A timeline 504 may include events related to the firmware (FW). At a start time 506, an adaptive clock distribution (ACD) status flag (e.g., ACD Active) may be set high to initiate an interrupt service routine to monitor for power change events, for example.

[0032] At time 508, the APC voltage may begin to ramp up. At time 510, the voltage reference Vref may dynamically adapt to a lower voltage value VI, such as 0.5 V, for example. Of course, the signals adapted and the value are merely examples and not limiting. Other signals may be adapted using CSR bits via the AHB. The change in Vref to VI (e.g., 0.5 V) may trigger a back end (BE) of the interrupt service routine (BE ISR).

[0033] In some aspects, the example sequence 500 may include a delay element that delays a predefined time period for voltage comparator behavior to change. For instance, a delay period (e.g., 300 nanoseconds (ns)) may following the change in Vref. After the delay period, at time 512, the power management system may switch to a lower voltage mode (Mem_SVS).

[0034] At time 514, the frequency of the phase locked loop (PLL) may ramp up to increase the processor operating frequency. In response to the frequency increase, a dynamic clock and voltage status (DC VS) flag may be set to high, which may trigger an interrupt service routine at time 516. When the frequency exceeds a threshold and/or the APC rail voltage exceed a threshold, CSR bits (e.g., AC[9:8]) may be cleared and at time 518, the voltage reference Vref may reset back to a default level V2 (e.g., 1 V) or another level according to design preference, for example. [0035] Accordingly, various aspects of the present disclosure beneficially enable dynamically changing the behavior of analog integrated circuitry at different DC VS modes by accessing and modifying CSR bits on an AHB using the CPU firmware.

[0036] FIGURE 6 is a process flow diagram illustrating a method 600 for operating a voltage comparator circuit at different thresholds at different modes using firmware, according to various aspects of the present disclosure. The method 600 may be performed by a processor such as CPU 102, for example.

[0037] At block 602, the method 600 detects, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode. In one example, the first mode may be a low voltage VI (e.g., 0.5 V) mode and the second mode may be a high voltage V2 (e.g., 1 V) mode.

[0038] At block 604, the method 600 dynamically adapts a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold. In one example, the first threshold may be 0.75 V and the second threshold may be 0.5 V. However, it will be understood that values for the first threshold and the second threshold are merely examples for ease of understanding, and any other values may also be used.

[0039] At block 606, the method 600 operates the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold. In some aspects, the operation of the processor may be delayed for a predefined period (e.g., 300 ns). In various aspects, the predefined delay period may be configured to provide time to accommodate completing the process of adapting the reference voltage.

[0040] At block 608, the method 600 may optionally set a first register bit to zero when the voltage of the processor exceeds the second threshold. For instance, a fuse register bit may be cleared (e.g., set to 0) when the processor voltage rail exceeds the second threshold (e.g., 0.5 V). Clearing the fuse register bit may indicate that the mode of operation is a higher voltage mode. In some aspects, the fuse register bit may control the operating frequency of the processor. [0041] FIGURE 7 is a block diagram showing an exemplary wireless communications system 700, in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration, FIGURE 7 shows three remote units 720, 730, and 750, and two base stations 740. It will be recognized that wireless communications systems may have many more remote units and base stations. Remote units 720, 730, and 750 include integrated circuit (IC) devices 725A, 725B, and 725C that include the voltage comparator circuit. It will be recognized that other devices may also include the voltage comparator circuit, such as the base stations, switching devices, and network equipment. FIGURE 7 shows forward link signals 780 from the base stations 740 to the remote units 720, 730, and 750, and reverse link signals 790 from the remote units 720, 730, and 750 to the base stations 740.

[0042] In FIGURE 7, remote unit 720 is shown as a mobile telephone, remote unit 730 is shown as a portable computer, and remote unit 750 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as meter reading equipment, or other device that stores or retrieves data or computer instructions, or combinations thereof. Although FIGURE 7 illustrates remote units according to the aspects of the present disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, which include the disclosed voltage comparator circuit.

[0043] FIGURE 8 is a block diagram illustrating a design workstation 800 used for circuit, layout, and logic design of a semiconductor component, such as the voltage comparator circuit disclosed above. The design workstation 800 includes a hard disk 801 containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 800 also includes a display 802 to facilitate design of a circuit 810 (e.g., voltage comparator) or a semiconductor component 812, such as a processor. A storage medium 804 is provided for tangibly storing the design of the circuit 810 or the semiconductor component 812 (e.g., a processor). The design of the circuit 810 or the semiconductor component 812 may be stored on the storage medium 804 in a file format such as GDSII or GERBER. The storage medium 804 may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation 800 includes a drive apparatus 803 for accepting input from or writing output to the storage medium 804.

[0044] Data recorded on the storage medium 804 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium 804 facilitates the design of the circuit 810 or the semiconductor component 812 by decreasing the number of processes for designing semiconductor wafers.

[0045] Implementation examples are described in the following numbered clauses:

1. An apparatus comprising: a processor including a register; a voltage comparator circuit to detect a transition of a processor from a first mode to a second mode; and a threshold adapter circuit coupled to the processor and the voltage comparator circuit to adapt a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold.

2. The apparatus of clause 1, in which the threshold adapter circuit is configured to set a first bit of the register to zero and a second bit of the register to one when the voltage of the processor exceeds the second threshold.

3. The apparatus of clause 1 or 2, in which the threshold adapter circuit is configured to dynamically adapt the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

4. The apparatus of any of clauses 1-3, in which the first threshold is greater than the second threshold. 5. The apparatus of any of clauses 1-4, further comprising at least one delay circuit to delay operation of the processor in the second mode for a predefined delay period after the voltage of the processor exceeds the second threshold.

6. A method comprising: detecting, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode; dynamically adapting a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold; and operating the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold.

7. The method of clause 6, further comprising setting a first register bit to zero when the voltage of the processor exceeds the second threshold.

8. The method of clause 6 or 7, further comprising: detecting the processor is operating in the second mode; and dynamically adapting the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

9. The method of any of clauses 6-8, in which the first threshold is greater than the second threshold.

10. The method of any of clauses 6-9, in which the processor operation in the second mode is delayed for a predefined delay period after the voltage of the processor exceeds the second threshold.

11. A non-transitory computer-readable medium having program code recorded thereon, the program code executed by a processor and comprising: program code to detect, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode; program code to dynamically adapt a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold; and program code to operate the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold.

12. The non-transitory computer-readable medium of clause 11, in which the program code further comprises program code to set a first register bit to zero when the voltage of the processor exceeds the second threshold.

13. The non-transitory computer-readable medium of clause 11 or 12, in which the program code further comprises: program code to detect the processor is operating in the second mode; and program code to dynamically adapt the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

14. The non-transitory computer-readable medium of any of clauses 11-13, in which the first threshold is greater than the second threshold.

15. The non-transitory computer-readable medium of any of clauses 11-14, in which the processor operation in the second mode is delayed for a predefined delay period after the voltage of the processor exceeds the second threshold.

16. An apparatus comprising: means for detecting, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode; means for dynamically adapting a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold; and means for operating the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold. 17. The apparatus of clause 16, further comprising means for setting a first register bit to zero when the voltage of the processor exceeds the second threshold.

18. The apparatus of clause 16 or 17, further comprising: means for detecting the processor is operating in the second mode; and means for dynamically adapting the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

19. The apparatus of any of clauses 16-18, in which the first threshold is greater than the second threshold.

20. The apparatus of any of clauses 16-19, in which the processor operation in the second mode is delayed for a predefined delay period after the voltage of the processor exceeds the second threshold.

[0046] For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used, the term “memory” refers to types of long term, short term, volatile, nonvolatile, or other memory and is not limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

[0047] If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer- readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0048] In addition to storage on computer-readable medium, instructions and/or data may be provided as signals on transmission media included in a communications apparatus. For example, a communications apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0049] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the technology of the disclosure as defined by the appended claims. For example, relational terms, such as “above” and “below” are used with respect to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if oriented sideways, above and below may refer to sides of a substrate or electronic device. Moreover, the scope of the present disclosure is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding configurations described may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0050] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the present disclosure may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0051] The various illustrative logical blocks, modules, and circuits described in connection with the disclosure may be implemented or performed with a general- purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described. A general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0052] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, erasable programmable read-only memory (EPROM), EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

[0053] The previous description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs described, but is to be accorded the widest scope consistent with the principles and novel features disclosed.

Claims

CLAIMS WHAT IS CLAIMED IS:

2. The apparatus of claim 1, in which the threshold adapter circuit is configured to set a first bit of the register to zero and a second bit of the register to one when the voltage of the processor exceeds the second threshold.

3. The apparatus of claim 1, in which the threshold adapter circuit is configured to dynamically adapt the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

4. The apparatus of claim 1, in which the first threshold is greater than the second threshold.

5. The apparatus of claim 1, further comprising at least one delay circuit to delay operation of the processor in the second mode for a predefined delay period after the voltage of the processor exceeds the second threshold.

7. The method of claim 6, further comprising setting a first register bit to zero when the voltage of the processor exceeds the second threshold.

8. The method of claim 6, further comprising: detecting the processor is operating in the second mode; and dynamically adapting the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

9. The method of claim 6, in which the first threshold is greater than the second threshold.

10. The method of claim 6, in which the processor operation in the second mode is delayed for a predefined delay period after the voltage of the processor exceeds the second threshold.

12. The non-transitory computer-readable medium of claim 11, in which the program code further comprises program code to set a first register bit to zero when the voltage of the processor exceeds the second threshold.

13. The non-transitory computer-readable medium of claim 11, in which the program code further comprises: program code to detect the processor is operating in the second mode; and program code to dynamically adapt the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

14. The non-transitory computer-readable medium of claim 11, in which the first threshold is greater than the second threshold.

15. The non-transitory computer-readable medium of claim 11, in which the processor operation in the second mode is delayed for a predefined delay period after the voltage of the processor exceeds the second threshold.

16. An apparatus comprising: means for detecting, via a voltage comparator circuit, a transition of a processor from a first mode to a second mode; means for dynamically adapting a voltage reference threshold of the voltage comparator circuit from a first threshold to a second threshold; and means for operating the processor in the second mode responsive to detecting, via the voltage comparator circuit, that a voltage of the processor is greater than or equal to the second threshold.

17. The apparatus of claim 16, further comprising means for setting a first register bit to zero when the voltage of the processor exceeds the second threshold.

18. The apparatus of claim 16, further comprising: means for detecting the processor is operating in the second mode; and means for dynamically adapting the voltage reference threshold of the voltage comparator circuit from the second threshold to the first threshold responsive to detecting the processor is operating in the second mode.

19. The apparatus of claim 16, in which the first threshold is greater than the second threshold.

20. The apparatus of claim 16, in which the processor operation in the second mode is delayed for a predefined delay period after the voltage of the processor exceeds the second threshold.