WO2024127853A1 - Light detection device and electronic apparatus - Google Patents

Light detection device and electronic apparatus Download PDF

Info

Publication number
WO2024127853A1
WO2024127853A1 PCT/JP2023/040092 JP2023040092W WO2024127853A1 WO 2024127853 A1 WO2024127853 A1 WO 2024127853A1 JP 2023040092 W JP2023040092 W JP 2023040092W WO 2024127853 A1 WO2024127853 A1 WO 2024127853A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
view
plan
bonding pad
shielding structure
Prior art date
Application number
PCT/JP2023/040092
Other languages
French (fr)
Japanese (ja)
Inventor
肇 山岸
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニーセミコンダクタソリューションズ株式会社 filed Critical ソニーセミコンダクタソリューションズ株式会社
Publication of WO2024127853A1 publication Critical patent/WO2024127853A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • This technology (the technology disclosed herein) relates to photodetection devices and electronic devices, and in particular to technology that is effective when applied to photodetection devices in which semiconductor layers are stacked in multiple stages and electronic devices equipped with such devices.
  • Patent Document 1 discloses a solid-state imaging device with a two-stage stacked structure in which two semiconductor layers are stacked. Patent Document 1 also discloses a technology in which a light-shielding member is provided to block the light emitted from the active element when the active element is operating from entering the photoelectric conversion unit.
  • Patent Document 2 also discloses a solid-state imaging device with a three-layer stack structure including three semiconductor layers, an upper layer, a middle layer, and a lower layer.
  • the upper semiconductor layer is provided with a photoelectric conversion section.
  • Each of the middle and lower semiconductor layers is provided with transistors that constitute a pixel circuit (readout circuit) that outputs a pixel signal based on the signal charge photoelectrically converted by the photoelectric conversion section, and a logic circuit that processes the pixel signal output from the pixel circuit.
  • pixel circuit readout circuit
  • transistors that construct logic circuits are provided in the middle and lower semiconductor layers. For this reason, there is a concern that noise generated during operation of one transistor between the transistor in the lower semiconductor layer and the transistor in the middle semiconductor layer may propagate to the other transistor, resulting in crosstalk that may affect the operation of the other transistor.
  • This technology was developed in consideration of these circumstances, and aims to provide a photodetector and electronic device that can suppress crosstalk.
  • a photodetector a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side; a second semiconductor layer having a transistor and provided on the first surface side of the first semiconductor layer; a third semiconductor layer having a transistor and provided on the second semiconductor layer on a side opposite to the first semiconductor layer; a shield provided between the second semiconductor layer and the third semiconductor layer; It is equipped with:
  • An electronic device includes: The photodetector; an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device; a signal processing circuit for processing a signal output from the photodetector; It is equipped with:
  • FIG. 1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology.
  • 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology.
  • 2 is an equivalent circuit diagram showing a configuration example of a sensor pixel and a pixel circuit in a solid-state imaging device according to a first embodiment of the present technology.
  • FIG. 1 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a solid-state imaging device according to a first embodiment of the present technology.
  • FIG. 5 is an enlarged longitudinal sectional view of a portion of FIG. 4 .
  • FIG. 5 is an enlarged longitudinal sectional view of a portion of FIG. 4 .
  • FIG. 1 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding solid film mounted on a solid-state imaging device according to a first embodiment of the present technology.
  • 6B is a plan view showing a schematic planar pattern of the solid shielding film of FIG. 6A.
  • 1 is a diagram showing an example of a circuit block in a solid-state imaging device according to a first embodiment of the present technology;
  • FIG. 11 is a vertical cross-sectional view that illustrates a vertical cross-sectional structure of a modified example of the first embodiment.
  • FIG. 11 is a plan view illustrating a plane pattern of a modified example of the first embodiment.
  • FIG. 11 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a solid-state imaging device according to a second embodiment of the present technology.
  • FIG. 10 is an enlarged longitudinal sectional view of a portion of FIG. 9 .
  • 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a second embodiment of the present technology.
  • FIG. 11B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 11A.
  • 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a third embodiment of the present technology.
  • FIG. 10 is an enlarged longitudinal sectional view of a portion of FIG. 9 .
  • 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a second embodiment of the present technology.
  • FIG. 11B
  • FIG. 11B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 11A.
  • FIG. 13 is a plan view illustrating a plane pattern of a modified example of the third embodiment. 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a fourth embodiment of the present technology.
  • FIG. 14B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 14A.
  • FIG. 16B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 16A.
  • FIG. 13 is a plan view diagrammatically showing a plane pattern of a modified example of the fifth embodiment.
  • 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a sixth embodiment of the present technology.
  • FIG. 18B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 18A.
  • 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a seventh embodiment of the present technology.
  • FIG. 19B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 19A.
  • FIG. 23 is a plan view illustrating a plane pattern of a modified example of the seventh embodiment.
  • 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to an eighth embodiment of the present technology.
  • FIG. 21B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 21A.
  • FIG. 23 is a plan view illustrating a plane pattern of a modified example of the eighth embodiment.
  • 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a ninth embodiment of the present technology.
  • FIG. 23B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 23A.
  • FIG. 13 is a plan view illustrating a plane pattern of a modified example of the ninth embodiment.
  • FIG. 23 is a diagram showing a schematic configuration of an electronic device according to a tenth embodiment of the present technology.
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit;
  • FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system.
  • 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU.
  • up and down and other directions in the following explanation are merely for the convenience of explanation and do not limit the technical ideas of this technology. For example, if an object is rotated 90 degrees and observed, up and down are converted into left and right and read, and of course, if it is rotated 180 degrees and observed, up and down are read inverted.
  • a first direction and a second direction mutually orthogonal in the same plane are defined as an X direction and a Y direction, respectively, and a third direction perpendicular to each of the first direction and the second direction is defined as a Z direction.
  • the thickness direction of a semiconductor layer described later is described as the Z direction.
  • the Z direction will be described as "one direction" of the present technology.
  • the thickness of the semiconductor layer is the distance between a first surface portion and a second surface portion located opposite each other in the Z direction, and the thickness direction of the semiconductor layer is the direction representing the thickness of the semiconductor layer.
  • a plan view refers to a semiconductor layer viewed from the Z direction (one direction)
  • a cross-sectional view refers to a cross section along the Z direction (one direction) viewed from a direction perpendicular to the cross section (Z direction).
  • CMOS complementary metal oxide semiconductor
  • a solid shielding film will be described as a shielding body that blocks an electromagnetic field.
  • the solid shielding film corresponds to a specific example of a "shielding body" of the present technology.
  • the solid-state imaging device 1A is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plane. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As shown in Fig. 1, the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plane. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As shown in Fig.
  • this solid-state imaging device 1A (101) takes in image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.
  • the semiconductor chip 2 on which the solid-state imaging device 1A is mounted has, in a two-dimensional plane including mutually orthogonal X and Y directions, a square sensor pixel array section 2A provided in the center, and a peripheral section 2B provided on the outside of the sensor pixel array section 2A so as to surround the sensor pixel array section 2A.
  • the semiconductor chip 2 is formed by dicing a semiconductor wafer including first to third semiconductor layers 20, 50, and 80 described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, this technology can be applied in the state of a semiconductor chip and in the state of a semiconductor wafer.
  • the sensor pixel array section 2A is a light receiving surface that receives light focused by, for example, an optical lens (optical system) 102 shown in FIG. 25.
  • a plurality of sensor pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction.
  • the sensor pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are mutually orthogonal within the two-dimensional plane.
  • a plurality of bonding pads 14 are arranged in the peripheral portion 2B.
  • Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides of the semiconductor chip 2 in a two-dimensional plane.
  • Each of the plurality of bonding pads 14 functions as an input/output terminal that electrically connects the semiconductor chip 2 to an external device.
  • the semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2.
  • the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.
  • the logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, an n-channel conductivity type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a p-channel conductivity type MOSFET.
  • CMOS Complementary MOS
  • the vertical drive circuit 4 is composed of, for example, a shift register.
  • the vertical drive circuit 4 sequentially selects the desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the sensor pixels 3, and drives each sensor pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each sensor pixel 3 in the sensor pixel array section 2A vertically row by row, and supplies pixel signals from the sensor pixels 3 based on signal charges generated by the photoelectric conversion section (photoelectric conversion element) of each sensor pixel 3 according to the amount of light received to the column signal processing circuit 5 via the vertical signal line 11.
  • the column signal processing circuit 5 is arranged, for example, for each column of sensor pixels 3, and performs signal processing such as noise removal for each pixel column on the signals output from one row of sensor pixels 3.
  • the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-to-Digital) conversion to remove pixel-specific fixed pattern noise.
  • the horizontal drive circuit 6 is composed of, for example, a shift register.
  • the horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn, and causing each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to the horizontal signal line 12.
  • the output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12.
  • the signal processing may include buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.
  • the control circuit 8 generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.
  • each of the sensor pixels 3 includes a photoelectric conversion region 21 and a pixel circuit (readout circuit) 15.
  • the photoelectric conversion region 21 includes a photoelectric conversion unit 24, a transfer transistor TR as a pixel transistor, and a floating diffusion region FD as a charge holding unit.
  • the pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 21.
  • a circuit configuration is used in which one pixel circuit 15 is assigned to one sensor pixel 3, but the present invention is not limited to this first embodiment.
  • a circuit configuration may be used in which one pixel circuit 15 is shared by multiple sensor pixels 3.
  • a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which four sensor pixels 3 are arranged in a 2 ⁇ 2 arrangement, two in each of the X and Y directions, as one unit.
  • a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which two sensor pixels 3 are arranged as one unit.
  • a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which four or more sensor pixels 3 are arranged as one unit.
  • the photoelectric conversion unit 24 shown in FIG. 3 is composed of, for example, a pn junction type photodiode (PD) and generates a signal charge according to the amount of light received.
  • the cathode side of the photoelectric conversion unit 24 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).
  • the transfer transistor TR shown in FIG. 3 transfers the signal charge photoelectrically converted by the photoelectric conversion unit 24 to the floating diffusion region FD.
  • the source region of the transfer transistor RT is electrically connected to the cathode side of the photoelectric conversion unit 24, and the drain region of the transfer transistor TR is electrically connected to the floating diffusion region FD.
  • the gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line of the pixel drive line 10 (see FIG. 2).
  • the floating diffusion region FD shown in FIG. 3 temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 24 via the transfer transistor TR.
  • the pixel circuit 15 shown in FIG. 3 reads out the signal charge held in the floating diffusion region FD and outputs a pixel signal based on the read-out signal charge.
  • the pixel circuit 15 includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors.
  • Each of these pixel transistors (AMP, SEL, RST) and the above-mentioned transfer transistor TR is configured as a field effect transistor, for example, a MOSFET having a gate insulating film made of a silicon oxide (SiO 2 ) film, a gate electrode, and a pair of main electrode regions functioning as a source region and a drain region.
  • these transistors may be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of a silicon nitride (Si 3 N 4 ) film or a laminated film such as a silicon nitride film and a silicon oxide film.
  • MISFETs Metal Insulator Semiconductor FETs
  • the source region of the amplification transistor AMP is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST.
  • the gate electrode of the amplification transistor AMP is electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.
  • the source of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP.
  • the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive line 10 shown in FIG. 2.
  • the source region of the reset transistor RST is electrically connected to the floating diffusion region FD and the gate electrode of the amplifier transistor AMP, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP.
  • the gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG. 2.
  • the transfer transistor TR transfers the signal charge generated in the photoelectric conversion unit 24 to the floating diffusion region FD.
  • the selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 15.
  • the amplification transistor AMP shown in FIG. 3 generates a pixel signal whose voltage corresponds to the level of the signal charge held in the floating diffusion region FD.
  • the amplification transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 24.
  • the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD, and outputs a voltage corresponding to that potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).
  • the signal charge generated in the photoelectric conversion unit 24 of the sensor pixel 3 is held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the sensor pixel 3.
  • the signal charge held in the floating diffusion region FD is read out by the pixel circuit 15 and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 15.
  • a horizontal line selection control signal is provided to the gate electrode of the selection transistor SEL of the pixel circuit 15 from the vertical shift register.
  • the selection transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP flows in the vertical signal line 11. Also, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 to a high (H) level, the reset transistor RST becomes conductive, and the signal charge accumulated in the floating diffusion region FD is reset.
  • the selection transistor SEL may be omitted if necessary.
  • the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).
  • a switching transistor may also be provided between the reset transistor RST and the gate electrode of the floating diffusion region FD and the amplifier transistor AMP.
  • the switching transistor controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP.
  • the switching transistor is also used to switch the conversion efficiency.
  • the FD capacitance C of the charge holding section needs to be large so that the voltage V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small).
  • the switching transistor when the switching transistor is turned on, the gate capacitance of the switching transistor increases, so the overall FD capacitance C becomes large.
  • the switching transistor when the switching transistor is turned off, the overall FD capacitance C becomes small. In this way, by switching the switching transistor on/off, the FD capacitance C can be made variable and the conversion efficiency can be switched.
  • the solid-state imaging device 1A (semiconductor chip 2) has a laminated structure in which a light collecting layer 90, a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 40, a second semiconductor layer 50, a third wiring layer 60, a fourth wiring layer 70, and a third semiconductor layer 80 are laminated in this order.
  • the first semiconductor layer 20, the second semiconductor layer 50, and the third semiconductor layer 80 correspond to specific examples of the "first semiconductor layer”, the "second semiconductor layer”, and the "third semiconductor layer” of the present technology.
  • the third wiring layer 60 and the fourth wiring layer 70 correspond to specific examples of the "first wiring layer” and the "second wiring layer” of the present technology.
  • the first semiconductor layer 20 "as a first semiconductor layer” of the present technology has a first surface S1 and a second surface S2 located opposite to each other in a thickness direction (Z direction) of the first semiconductor layer 20 (see FIG. 5A ).
  • the first semiconductor layer 20 has a photoelectric conversion region 21 (see FIG. 5A ) described later.
  • the light collecting layer 90 is provided on the second surface S2 side of the first semiconductor layer 20.
  • the light collecting layer 90 has a laminated structure in which, for example, but not limited to, a color filter 91 and an on-chip lens 92 are laminated in this order from the second surface S2 side of the first semiconductor layer 20.
  • the first wiring layer 30 is provided on the first surface S ⁇ b>1 side of the first semiconductor layer 20 and overlaps the first surface S ⁇ b>1 of the first semiconductor layer 20 .
  • the second wiring layer 40 is provided on the side of the first wiring layer 30 opposite to the first semiconductor layer 20 side, and is superimposed on the surface of the first wiring layer 30 on the first semiconductor layer 20 side.
  • the second semiconductor layer 50 "as the second semiconductor layer” of the present technology has a third surface S3 and a fourth surface S4 located opposite to each other in the thickness direction (Z direction) of the second semiconductor layer 50 (see FIG. 5B ).
  • the second semiconductor layer 50 is provided on the side of the second wiring layer 40 opposite to the first wiring layer 30 side, and is superimposed on the surface of the second wiring layer 40 opposite to the first wiring layer 30 side.
  • the third wiring layer 60 “as a first wiring layer” in the present technology is provided on the side of the second semiconductor layer 50 opposite the second wiring layer 40 side, and is superimposed on the fourth surface S ⁇ b>4 of the second semiconductor layer 50 .
  • the fourth wiring layer 70 “as the second wiring layer” in the present technology is provided on the side opposite the second semiconductor layer 50 side of the third wiring layer 60, and is superimposed on the surface of the third wiring layer 60 opposite the second semiconductor layer 50 side.
  • the third semiconductor layer 80 "as the third semiconductor layer" of the present technology has a fifth surface S5 and a sixth surface S6 located on opposite sides to each other in the thickness direction of the third semiconductor layer 80.
  • the third semiconductor layer 80 is provided on the side of the fourth wiring layer 70 opposite to the third wiring layer 60 side, and is superimposed on the surface of the fourth wiring layer 70 opposite to the third wiring layer 60 side.
  • the first surface S1 of the first semiconductor layer 20 is sometimes called the element formation surface or main surface
  • the second surface S2 of the first semiconductor layer 20 is sometimes called the light incidence surface or back surface
  • the third surface S3 of the second semiconductor layer 50 is sometimes called the element formation surface or main surface
  • the fourth surface S4 of the second semiconductor layer 50 is sometimes called the back surface
  • the fifth surface S5 of the third semiconductor layer 80 is sometimes called the element formation surface or main surface, and the surface opposite the fifth surface S5 is sometimes called the back surface.
  • the first semiconductor layer 20 and the second semiconductor layer 50 are bonded together by the F2F (Face to Face) method, i.e., with their element formation surfaces facing each other, via the first wiring layer 30 and the second wiring layer 40.
  • the second semiconductor layer 50 and the third semiconductor layer 80 are bonded together by the B2F (Back to Face) method, i.e., with their back surfaces facing each other, via the third wiring layer 60 and the fourth wiring layer 70.
  • the first semiconductor layer 20 is made of a semiconductor substrate.
  • the first semiconductor layer 20 is made of, for example, a p-type single crystal silicon substrate as the first conductivity type.
  • a photoelectric conversion region 21 is provided for each sensor pixel 3.
  • the photoelectric conversion region 21 is partitioned by a separation region provided in the first semiconductor layer 20. Note that the number of sensor pixels 3 is not limited to that shown in FIG. 4.
  • the photoelectric conversion region 21, although not shown, has, for example, a p-type well region and an n-type semiconductor region (photoelectric conversion section) as the second conductivity type buried inside this well region.
  • the photoelectric conversion element PD shown in FIG. 3 is configured in the photoelectric conversion region 21 including the well region and photoelectric conversion section of the first semiconductor layer 20.
  • the photoelectric conversion region 21 is provided with, for example, a charge holding section (charge accumulation section) made of an n-type semiconductor region, and a transfer transistor TR, although this is not limited thereto.
  • the first wiring layer 30 includes an insulating film 31, a wiring 32, a bonding pad (bonding metal pad) 33, and a contact electrode (via).
  • the wiring 32 and the bonding pad 33 are laminated with the insulating film 31 interposed therebetween as shown in the figure.
  • the bonding pad 33 faces the surface of the first wiring layer 30 opposite the first semiconductor layer 20 side.
  • the bonding pad 33 is provided in the top layer of the first wiring layer 30 opposite the first semiconductor layer 20 side, and is electrically connected to the wiring 32 in the lower layer via a contact electrode.
  • the wiring 32 and the bonding pad 33 are made of, but are not limited to, copper, and may be formed by a damascene method, for example.
  • the second wiring layer 40 includes an insulating film 41, a wiring 42, a bonding pad (bonding metal pad) 43, and a contact electrode (via).
  • the wiring 42 and the bonding pad 43 are laminated with the insulating film 41 interposed therebetween as shown in the figure.
  • the bonding pad 43 faces the surface of the second wiring layer 40 opposite to the second semiconductor layer 50 side.
  • the bonding pad 43 is provided in the uppermost layer of the second wiring layer 40 opposite to the second semiconductor layer 50 side, and is electrically connected to the wiring 42 in the lower layer via a contact electrode.
  • the bonding pad 43 is bonded to the bonding pad 33 of the first wiring layer 30.
  • the wiring 42 and the bonding pad 43 are not limited to this, but may be made of copper, for example, and may be formed by a damascene method.
  • the second semiconductor layer 50 is made of, for example, a p-type single crystal silicon substrate, but is not limited thereto.
  • a plurality of transistors T1 are provided in the second semiconductor layer 50.
  • the transistors T1 are, for example, pixel transistors constituting the pixel circuit (readout circuit) 15 shown in FIG. 3 or transistors constituting the logic circuit 13 shown in FIG. 2.
  • the third wiring layer 60 includes an insulating film 61, a wiring 62, and a bonding pad (bonding metal pad) 63.
  • the wiring 62 and the bonding pad 63 are laminated via the insulating film 61 as shown in the figure.
  • the bonding pad 63 faces the surface of the third wiring layer 60 opposite to the second semiconductor layer 50 side.
  • the wiring 62 and the bonding pad 63 are made of, but are not limited to, copper, and may be formed by a damascene method, for example.
  • the bonding pad 63 corresponds to a specific example of the "first bonding pad" of the present technology
  • the third wiring layer 60 corresponds to a specific example of the "first wiring layer” of the present technology.
  • the fourth wiring layer 70 includes an insulating film 71, wirings 72 and 72a, a bonding pad (bonding metal pad) 73, and a contact electrode.
  • the wirings 72 and the bonding pads 73 are laminated with the insulating film 71 interposed therebetween as shown in the figure.
  • the bonding pads 73 face the surface of the fourth wiring layer 70 opposite to the third semiconductor layer 80 side.
  • the bonding pads 73 are provided in the uppermost layer of the fourth wiring layer 70 on the second semiconductor layer 50 side, and are electrically connected to the lower wiring 72a via the contact electrode.
  • the wirings 72 and the bonding pads 73 may be made of, for example, copper and formed by a damascene method, although they are not limited thereto.
  • the wirings 72a are different from the wirings 72 below the wirings 72a, and are made of, for example, an aluminum film.
  • the third semiconductor layer 80 is made of, for example, a p-type single crystal silicon substrate.
  • a plurality of transistors T2 are provided in the third semiconductor layer 80.
  • the transistors T2 are, for example, transistors that constitute the logic circuit 13 shown in FIG.
  • the wiring 42 of the second wiring layer 40 and the bonding pad 63 of the third wiring layer 60 are electrically connected via a through contact electrode 51 that penetrates the second semiconductor layer 50 in its thickness direction (Z direction).
  • the through contact electrode 51 penetrates a through hole of the second semiconductor layer 50, and is electrically insulated and separated from the second semiconductor layer 50 through an insulating film inside the through hole.
  • the through contact electrode 51 it is preferable to use a material with a linear expansion coefficient close to that of the second semiconductor layer 50 in order to penetrate the second semiconductor layer 50.
  • the through contact electrode 51 is made of polycrystalline silicon into which an impurity that reduces the resistance value is introduced.
  • a shielding solid film 66 is provided as a shield on the fourth surface S4 side of the second semiconductor layer 50. That is, the solid-state imaging device 1A according to the first embodiment includes the shielding solid film 66 as a shield between the second semiconductor layer 50 and the third semiconductor layer 80. The shielding solid film 66 is fixed to the fourth surface S4 of the second semiconductor layer 50 via a fixed charge film 65. The shielding solid film 66 suppresses an electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the fixed charge film 65 includes, for example, a dielectric film that generates negative fixed charges.
  • this dielectric film for example, hafnium oxide (HfO 2 ) having a high dielectric constant can be used.
  • This fixed charge film 65 induces holes (h + ) in the surface layer portion on the fourth surface S4 side of the second semiconductor layer 50, and pinning at this interface portion can be ensured.
  • zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), etc. can also be used.
  • the shielding solid film 66 is electrically connected to the wiring to which a potential is applied.
  • the potential of the shielding solid film 66 is fixed to the potential applied to the wiring.
  • the potential is a power supply potential supplied from a power generation circuit.
  • the power supply potential can be, for example, a first reference potential of 0V, a second reference potential that is a positive potential higher than the first reference potential, or a third reference potential that is a negative potential lower than the first reference potential.
  • the first reference potential of, for example, 0V is supplied to the shielding solid film 66.
  • the application of the potential to the shielding solid film 66 is maintained during operation of the solid-state imaging device 1A.
  • the solid shielding film 66 is preferably made of a material suitable for shielding electromagnetic fields such as band noise and hot carrier light.
  • a material suitable for shielding electromagnetic fields such as band noise and hot carrier light.
  • high melting point metals such as tantalum (Ta), titanium (Ti), and tungsten (W), or nitrides of these metals, or metals such as copper (Cu) and aluminum (Al) can be used.
  • the shielding solid film 66 is provided on the fourth surface S4 side of the second semiconductor layer 50 across the sensor pixel array section 2A and the peripheral section 2B in a plan view, and has a plate shape that spreads two-dimensionally.
  • the shielding solid film 66 has an opening 66a through which the through contact electrode 51 penetrates. That is, the through contact electrode 51 penetrates the through hole of the second semiconductor layer 50 and the opening 66a of the shielding solid film 66, and electrically connects the wiring 42 of the second wiring layer 40 provided on the third surface S3 side of the second semiconductor layer 50 to the bonding pad 63 of the third wiring layer 60 provided on the fourth surface S4 side of the second semiconductor layer 50.
  • the opening 66a can be formed by patterning the solid shielding film 66 using well-known photolithography or dry etching techniques.
  • the solid shielding film 66 can also be selectively provided by patterning it to match the area to be shielded. Therefore, in this embodiment, as shown in FIG. 5B, the solid shielding film 66 is provided on the fourth surface S4 side of the second semiconductor layer 50 across the sensor pixel array portion 2A and the peripheral portion 2B, but the solid shielding film 66 can be selectively provided in the area to be shielded, for example, the peripheral portion 2B.
  • the second semiconductor layer 50 is provided with a transistor T1 constituting the pixel circuit 15 and the logic circuit 13.
  • the third semiconductor layer 80 is also provided with a transistor T2 constituting the logic circuit 13.
  • a solid shielding film 66 is provided between the lower third semiconductor layer 80 and the middle second semiconductor layer 50.
  • the solid shielding film 66 is provided between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50. For this reason, the solid shielding film 66 can block the propagation of band noise generated during the operation of the transistor T2 to the transistor T1.
  • the solid shielding film 66 can block the propagation of band noise generated during the operation of the transistor T1 to the transistor T2. That is, between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, the band noise generated during the operation of one transistor is propagated to the other transistor, and the occurrence of crosstalk affecting the operation of the other transistor can be suppressed.
  • the pixel transistors included in the pixel circuit 15 are provided in the second semiconductor layer 50 different from the first semiconductor layer 20 in which the photoelectric conversion unit 24, the transfer transistor TR, and the charge holding unit (FD) are provided, the degree of freedom in arranging the pixel transistors (AMP, SEL, RST) included in the pixel circuit 15 can be increased, and higher integration and improved noise resistance can be achieved compared to a case in which the photoelectric conversion unit 24, the transfer transistor TR, the charge holding unit (FD), and the pixel transistors are provided in the same semiconductor layer.
  • FIG. 7 is a diagram illustrating an example of a circuit block.
  • the solid-state imaging device 1A of the first embodiment includes, for example, the circuit blocks shown in Fig. 7.
  • a logic operation circuit is provided in a circuit block 18a
  • a load MOS transistor circuit is provided in a circuit block 18b
  • a comparator circuit is provided in a circuit block 18c
  • a counter circuit is provided in a circuit block 18d.
  • a scanner circuit is provided in a circuit block 18e
  • a D/C converter is provided in a circuit block 18f
  • a mobile processor interface circuit is provided in a circuit block 18G.
  • circuit blocks 18a, 18b, 18c, 18f, and 18G each operate at high speed and are therefore likely to become noise sources. Therefore, by selectively providing a solid shielding film 66 so that it overlaps in a planar view with the circuit blocks that are likely to become noise sources, crosstalk between the third semiconductor layer 80 in the lower stage and the second semiconductor layer 50 in the middle stage can be suppressed. In this case, the solid shielding film 66 selectively overlaps in a planar view with the circuit blocks to be shielded.
  • the logic circuit 13 shown in FIG. 2 is composed of a CMOS circuit.
  • CMOS circuit measures against latch-up are necessary.
  • transistors emit hot carrier light during operation. This hot carrier light can be a cause of latch-up. Therefore, by providing a solid shielding film 66 between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, the hot carrier light emitted by the transistors T2 and T1 can be blocked by the solid shielding film 66, thereby suppressing the occurrence of latch-up caused by hot carrier light.
  • the shielding solid film 66 may be provided directly on the fourth surface S4 of the second semiconductor layer 50. In this case, since the second semiconductor layer 50 is usually supplied with a reference potential, the shielding solid film 66 is also fixed to the reference potential of the second semiconductor layer 50. All of the pixel transistors included in the pixel circuit 15 in FIG. Furthermore, pixel transistors included in the pixel circuit 15, including pixel transistors not shown in FIG. 3, may be appropriately divided and disposed in the first semiconductor layer 20 and the second semiconductor layer 50. Furthermore, a signal processing circuit, a driving circuit, a memory circuit, and the like may be arbitrarily disposed in at least one of the first semiconductor layer 20, the second semiconductor layer 50, and the third semiconductor layer 80.
  • a gap is formed between the shielding solid film 66 and the through contact electrode 51 due to the separation between the shielding solid film 66 and the through contact electrode 51, so that electromagnetic fields such as band noise and hot carrier light may pass through.
  • at least one of the bonding pads 63 and 73 is configured to have a planar size that overlaps with the entire opening 66a of the shielding solid film 66 in a planar view, thereby preventing the electromagnetic field from passing through.
  • both the bonding pads 63 and 73 are configured to have a planar size that overlaps with the entire opening 66a of the shielding solid film 66 in a planar view.
  • FIG. 9 is a longitudinal sectional view that typically illustrates a longitudinal sectional structure of a solid-state imaging device 1B according to the second embodiment of the present technology.
  • FIG. 10 is an enlarged longitudinal sectional view of a portion of FIG.
  • FIG. 11A is a vertical cross-sectional view showing, in a simplified form, the vertical cross-sectional structure of the shielding structure shown in FIG.
  • FIG. 11B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG.
  • the solid-state imaging device 1B according to the second embodiment has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, but differs in the following respects.
  • the solid-state imaging device 1B according to the second embodiment includes a shielding structure 55B instead of the solid shielding film 66 shown in Fig. 5B of the first embodiment described above.
  • the other configurations are generally similar to those of the first embodiment described above.
  • the shielding structure 55B corresponds to a specific example of a "shield" of the present technology.
  • the solid-state imaging device 1B has a shielding structure 55B between the second semiconductor layer 50 and the third semiconductor layer 80 as a shield.
  • the shielding structure 55B includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 and extends linearly in the X direction (first direction) in a planar view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and bonded to the bonding pad 63, and extends linearly in the X direction (first direction) in a planar view.
  • the shielding structure 55B has the bonding pads 63 and 73 repeatedly arranged with their positions relatively shifted in the Y direction (second direction) intersecting the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. That is, the shielding structure 55B combines the bonding pads 63 and 73 to construct a shielding plate that spreads two-dimensionally in a plan view.
  • the shielding structure 55B of the second embodiment is also electrically connected to the wiring to which a potential is applied, like the above-mentioned shielding solid film 66, and the potential is fixed to the potential applied to the wiring.
  • the shielding structure 55B also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the shielding structure 55B of the second embodiment is constructed by combining the bonding pads 63 and 73 to form a shielding plate that extends two-dimensionally in a plan view, so that between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, noise generated during operation of one transistor is propagated to the other transistor, and crosstalk that affects the operation of the other transistor can be suppressed.
  • the solid-state imaging device 1B according to the second embodiment which is equipped with this shielding structure 55B, also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.
  • a shielding structure including a first bonding pad, a second bonding pad, and a conductor penetrating the second semiconductor layer as a shield for shielding an electromagnetic field will be described.
  • FIG. 12A is a simplified vertical cross-sectional view showing the vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to a third embodiment of the present technology.
  • FIG. 12B is a simplified plan view showing the planar pattern of the shielding structure of FIG. 12A.
  • the solid-state imaging device 1C according to the third embodiment has a shielding structure 55C instead of the shielding structure 55B shown in FIG. 9 of the second embodiment described above.
  • the other configurations are generally similar to those of the first embodiment described above.
  • the solid-state imaging device 1C according to the third embodiment has a shielding structure 55C between the second semiconductor layer 50 and the third semiconductor layer 80 as a shielding body instead of the shielding structure 55B, as in the second embodiment described above.
  • the shielding structure 55C of the third embodiment corresponds to a specific example of the "shield" of the present technology.
  • the shielding structure 55C includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extends linearly in the X direction (first direction) in a plan view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63 and extends linearly in the X direction (first direction) in a plan view.
  • the shielding structure 55C further includes a conductor 52 that penetrates the second semiconductor layer 50 in the thickness direction (Z direction), overlaps with the bonding pad 63 in a plan view, and extends linearly in the X direction.
  • the conductor 52 can be formed in the same process as the through contact electrode 51.
  • the conductor 52 corresponds to a specific example of a "conductor" of the present technology.
  • the bonding pads 63 and the bonding pads 73 are repeatedly arranged with their positions relatively shifted in the Y direction (second direction) that intersects with the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. That is, in the shielding structure 55C, the bonding pads 63 and the bonding pads 73 are combined to construct a shielding plate that spreads two-dimensionally in a plan view.
  • the shielding structure 55C of the third embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to the wiring. And, in the second semiconductor layer 50 and the third semiconductor layer 80, this shielding structure 55C also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer.
  • the conductor 52 is electrically connected to the bonding pad 63 via a contact electrode.
  • the conductor 52 is arranged in a position overlapping in plan view with the bonding pad 63 arranged in the first row of the multiple bonding pads 63 arranged repeatedly in the Y direction, and is also arranged in a position overlapping in plan view with the bonding pad 63 arranged in the final row.
  • the shielding structure 55C of the third embodiment combines the bonding pads 63 and 73 to construct a shielding plate that extends two-dimensionally in a plan view, so that between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, noise generated during operation of one transistor is propagated to the other transistor, and crosstalk that affects the operation of the other transistor can be suppressed.
  • the shielding structure 55C of this embodiment has a conductor 52 that penetrates the second semiconductor layer 50, so the shielding efficiency can be improved compared to the shielding structure 55B of the second embodiment described above.
  • the solid-state imaging device 1C according to this embodiment can further suppress crosstalk.
  • the shielding structure 55C including the conductor 52 extending in the X direction has been described.
  • the present technology is not limited to the conductor 52 extending in the X direction.
  • the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap the bonding pads 63 in a plan view, and are dot-like in the X direction.
  • the planar shape of the conductors 53 may be circular or rectangular.
  • the shielding efficiency in the planar direction can be further improved by arranging the conductors 53 in a staggered manner rather than arranging them in a linear row.
  • the conductors 53 can be formed in the same process as the through contact electrodes 51.
  • the conductors 53 correspond to a specific example of a "conductor" in the present technology.
  • FIG. 14A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a fourth embodiment of the present technology.
  • FIG. 14B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 14A.
  • the solid-state imaging device 1D according to the fourth embodiment has a shielding structure 55D instead of the shielding structure 55B shown in FIGS. 11A and 11B of the second embodiment described above.
  • the other configurations are generally similar to those of the first embodiment described above.
  • the solid-state imaging device 1D according to the fourth embodiment includes a shielding structure 55D between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B, as in the second embodiment described above.
  • the shielding structure 55D of the fourth embodiment corresponds to a specific example of the "shield" of the present technology.
  • the shielding structure 55D includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extends in the X direction (first direction) in a plan view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63 and extends linearly in the X direction (first direction) in a plan view.
  • the shielding structure 55D further includes conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction), overlap the bonding pad 63 in a plan view, and are dot-like in the X direction.
  • the bonding pads 63 and the bonding pads 73 are repeatedly arranged with their positions relatively shifted in the Y direction (second direction) that intersects with the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. That is, in the shielding structure 55D, the bonding pads 63 and the bonding pads 73 are combined to construct a shielding plate that spreads two-dimensionally in a plan view.
  • the shielding structure 55D of the fourth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to the wiring. The shielding structure 55D also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the conductors 53 are electrically connected to the bonding pads 63 via contact electrodes. Although not limited to this, the conductors 53 are dot-like in the X direction for each of the bonding pads 63 that are repeatedly arranged in the Y direction.
  • the solid-state imaging device 1D according to the fourth embodiment also provides the same effects as the solid-state imaging device 1C according to the third embodiment described above.
  • the conductors 53 that are scattered in the X direction have been described as the conductors included in the shielding structure.
  • the present technology is not limited to the conductors 53 that are scattered in the X direction.
  • a conductor 52 extending linearly in the X direction may be combined with multiple conductors 53 scattered in a dot pattern in the X direction.
  • the conductor 52 corresponds to a specific example of the "first conductor” of the present technology
  • the conductor 53 corresponds to a specific example of the "second conductor" of the present technology.
  • FIG. 16A is a longitudinal sectional view showing, in a simplified form, a configuration example of a shielding structure mounted on a solid-state imaging device according to a fifth embodiment of the present technology.
  • FIG. FIG. 16B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 16A.
  • the solid-state imaging device 1E according to the fifth embodiment includes a shielding structure 55E instead of the shielding structure 55B shown in FIG. 10 of the second embodiment described above.
  • the other configurations are generally similar to those of the first embodiment described above.
  • the solid-state imaging device 1E has a shielding structure 55E between the second semiconductor layer 50 and the third semiconductor layer 80 instead of the shielding structure 55B as a shield, as in the second embodiment described above.
  • the shielding structure 55E corresponds to a specific example of a "shield" of the present technology.
  • the shielding structure 55E includes a conductor 52 that penetrates the second semiconductor layer 50 in the thickness direction (Z direction) and extends linearly in the X direction in a planar view, a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see Figure 10) and extends linearly in the X direction (first direction) in a planar view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63, and extends linearly in the X direction (first direction) in a planar view.
  • the conductor 52, the bonding pad 63, and the bonding pad 73 are repeatedly arranged with their positions relatively shifted in the Y direction intersecting the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. In a plan view, the bonding pad 63 and the bonding pad 73 are arranged between the bonding pad 63 and the bonding pad 73, overlapping with each part of the bonding pads 63 and 73. In other words, the shielding structure 55E combines the conductor 52, the bonding pad 63, and the bonding pad 73 to construct a shielding plate that spreads two-dimensionally in a plan view.
  • the conductor 52 is spaced from each of the bonding pads 63 and 73.
  • the shielding structure 55E of the fifth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to this wiring. This shielding structure 55E also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the solid-state imaging device 1E according to the fifth embodiment also provides the same effects as the solid-state imaging device 1C according to the third embodiment described above.
  • the shielding structure 55E including the conductor 52 extending in the X direction has been described.
  • the present technology is not limited to the conductor 52 extending in the X direction.
  • the shielding structure may include a plurality of conductors 53 scattered in a dot pattern in the X direction, instead of the conductors 52 extending in the X direction.
  • FIG. 18A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a sixth embodiment of the present technology.
  • FIG. 18B is a plan view showing, in a simplified form, the planar pattern of the shielding structure of FIG. 18A.
  • a solid-state imaging device 1F according to the sixth embodiment includes a shielding structure 55F instead of the shielding structure 55B of the second embodiment shown in Fig. 10.
  • the other configurations are generally similar to those of the first embodiment.
  • a solid-state imaging device 1F according to the sixth embodiment includes, similarly to the above-described second embodiment, a shielding structure 55F instead of the shielding structure 55B between the second semiconductor layer 50 and the third semiconductor layer 80.
  • the shielding structure 55F corresponds to a specific example of a “shield” of the present technology.
  • the shielding structure 55F includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extends linearly in the X direction (first direction) in a plan view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63 and extends linearly in the X direction in a plan view.
  • the shielding structure 55F also includes a wiring 72a that is provided on the third semiconductor layer 80 side of the bonding pad 73 and extends linearly in the X direction in a plan view.
  • the wiring 72a is provided in the fourth wiring layer 70 and is provided closer to the third semiconductor layer 80 than the bonding pad 73.
  • the bonding pads 63 and 73 and the wiring 72a are repeatedly arranged with their positions relatively shifted in the Y direction (second direction) intersecting the X direction in a plan view.
  • the bonding pads 63 and 73 are joined in an overlapping manner in a plan view.
  • the wiring 72a is arranged between the bonding pads 63 and 63 in a plan view, overlapping with a part of each. That is, the shielding structure 55F combines the bonding pads 63 and 73 with the wiring 72a to construct a shielding plate that spreads two-dimensionally in a plan view.
  • the shielding structure 55F of the sixth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to the wiring.
  • the shielding structure 55F also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the solid-state imaging device 1F according to the sixth embodiment also provides the same effects as the solid-state imaging device 1B according to the second embodiment described above.
  • FIG. 19A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a seventh embodiment of the present technology.
  • FIG. FIG. 19B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 19A.
  • a solid-state imaging device 1G according to the seventh embodiment includes a shielding structure 55G instead of the shielding structure 55B of the second embodiment shown in Fig. 10.
  • the other configurations are generally similar to those of the first embodiment.
  • the solid-state imaging device 1G according to the seventh embodiment includes a shielding structure 55G between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B, as in the second embodiment described above.
  • the shielding structure 55G of the seventh embodiment corresponds to a specific example of the "shield" of the present technology.
  • the shielding structure 55G is configured by incorporating a conductor 52 into the shielding structure 55F of the sixth embodiment described above.
  • the conductor 52 is electrically connected to the bonding pad 63 via a contact electrode.
  • the conductor 52 is arranged, but is not limited to, at a position overlapping the bonding pad 63 arranged in the first row of the multiple bonding pads 63 repeatedly arranged in the Y direction in a planar view, and is also arranged at a position overlapping the bonding pad 63 arranged in the last row in a planar view.
  • the bonding pad 73 is electrically connected to the wiring 72a in the lower layer via a contact electrode.
  • the shielding structure 55G of the seventh embodiment is also electrically connected to the wiring to which a potential is applied, like the shielding solid film 66 described above, and the potential is fixed to the potential applied to the wiring.
  • the shielding structure 55G also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the solid-state imaging device 1G according to the seventh embodiment also provides the same effects as the solid-state imaging device 1C according to the third embodiment described above.
  • the shielding structure 55G including the conductor 52 extending in the X direction has been described.
  • the present technology is not limited to the conductor 52 extending in the X direction.
  • the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap with the bonding pads 63 in a planar view, and are dot-like in the X direction.
  • the planar shape of the conductors 53 may be circular or square. In this case, by arranging the conductors 53 in a staggered pattern rather than arranging them in a straight line, the shielding efficiency in the planar direction can be further improved.
  • FIG. 21A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to an eighth embodiment of the present technology.
  • FIG. 21B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 21A.
  • the solid-state imaging device 1H according to the eighth embodiment includes a shielding structure 55H instead of the shielding structure 55B shown in FIG. 10 of the second embodiment described above.
  • the other configurations are generally similar to those of the first embodiment described above.
  • the solid-state imaging device 55H according to the eighth embodiment includes a shielding structure 55H between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B, as in the second embodiment described above.
  • the shielding structure 55H of the eighth embodiment corresponds to a specific example of the "shield" of the present technology.
  • the shielding structure 55H is basically configured in the same manner as the shielding structure 55G of the seventh embodiment described above.
  • the difference between the shielding structures 1H and 1G is that a conductor 52 is provided for each bonding pad 63.
  • the shielding structure 55H of the eighth embodiment is also electrically connected to a wiring to which a potential is applied, and the potential is fixed to the potential applied to this wiring.
  • the shielding structure 55H also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the solid-state imaging device 1H according to the eighth embodiment also provides the same effects as the solid-state imaging device 1D according to the fourth embodiment described above.
  • the shielding structure 55H including the conductor 52 extending in the X direction has been described.
  • the present technology is not limited to the conductor 52 extending in the X direction.
  • the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap the bonding pads 63 in a plan view, and are dot-like in the X direction.
  • the planar shape of the conductors 53 may be circular or square.
  • the conductors 53 are arranged in a linear row in this modified example, they may also be arranged in a staggered pattern.
  • FIG. 23A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a ninth embodiment of the present technology.
  • FIG. 23B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 23A.
  • the solid-state imaging device 1I according to the ninth embodiment includes a shielding structure 55I instead of the shielding structure 55B shown in FIG. 10 of the second embodiment described above.
  • the other configurations are generally similar to those of the first embodiment described above.
  • the solid-state imaging device 1I includes a shielding structure 55I between the second semiconductor layer 50 and the third semiconductor layer 80 instead of the shielding structure 55B, as in the second embodiment described above.
  • the shielding structure 55I of the ninth embodiment corresponds to a specific example of the "shield" of the present technology.
  • the shielding structure 55I includes a conductor 52 penetrating the second semiconductor layer 50 in the thickness direction, a bonding pad 63 provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extending linearly in the X direction in a plan view, a bonding pad 73 provided on the third semiconductor layer 80 side of the bonding pad 63 and bonded to the bonding pad 63, and extending linearly in the X direction in a plan view, and a wiring 72a provided on the third semiconductor layer 80 side of the bonding pad 73 and extending linearly in the X direction in a plan view.
  • the conductor 52, the bonding pad 63, the bonding pad 73, and the wiring 72a are repeatedly arranged with their positions relatively shifted in the Y direction that intersects with the X direction in a plan view.
  • the bonding pads 63 and 73 are joined together with parts of each overlapping in a plan view.
  • the wiring 72a is arranged between the bonding pads 63 and 73 adjacent to each other in a plan view, overlapping with parts of each of the bonding pads 63 and 73.
  • the conductor 52 is arranged between the bonding pads 63 and 73 adjacent to each other in a plan view, overlapping with parts of each of the bonding pads 63 and 73.
  • the wiring 72a and the conductor 52 are arranged alternately in the Y direction in a plan view. In this shielding structure 55I, the conductor 52, the bonding pad 63, and the bonding pad 73 are combined to construct a shielding plate that spreads two-dimensionally in a plan view.
  • the shielding structure 55I of the ninth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to this wiring.
  • This shielding structure 55I also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
  • the conductor 52 and the wiring 72a are spaced apart from the bonding pads 63 and 73, respectively, and are not electrically connected to the bonding pads 63 and 73 via contact electrodes.
  • the solid-state imaging device 1I according to the ninth embodiment also provides the same effects as the solid-state imaging device 1D according to the fourth embodiment described above.
  • the shielding structure 55I including the conductor 52 extending in the X direction has been described.
  • the present technology is not limited to the conductor 52 extending in the X direction.
  • the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap the bonding pads 63 in a plan view, and are dot-like in the X direction.
  • the planar shape of the conductors 53 may be circular or square.
  • the conductors 53 are arranged in a linear row in this modification, they may also be arranged in a staggered pattern.
  • the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a driving circuit 104, and a signal processing circuit 105.
  • the electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto.
  • the electronic device 100 also includes the above-mentioned solid-state imaging device 1A as the solid-state imaging device 101.
  • the optical lens (optical system) 102 focuses image light (incident light 106) from the subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time.
  • the shutter device 103 controls the light irradiation period and light blocking period for the solid-state imaging device 101.
  • the drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103.
  • the drive signal (timing signal) supplied from the drive circuit 104 transfers signals from the solid-state imaging device 101.
  • the signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101.
  • the video signals that have undergone signal processing are stored in a storage medium such as a memory, or output to a monitor.
  • the electronic device 100 is not limited to a camera, but may be other electronic devices.
  • it may be an imaging device such as a camera module for a mobile device such as a mobile phone.
  • the electronic device 100 may also include, as the solid-state imaging device 101, a photodetector 1 according to either the first embodiment or its modified examples, or a photodetector 1 according to a combination of at least two of the first embodiment and its modified examples.
  • the technology disclosed herein can be applied to a variety of products.
  • the technology disclosed herein may be realized as a device mounted on any type of moving object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.
  • FIG. 26 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 27 is a diagram showing an example of the installation position of the imaging unit 12031.
  • a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 27 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology disclosed herein can be applied to, for example, the multiple electronic control units and imaging unit 12031 described above.
  • the shields (solid shielding films and shielding structures) of the first to ninth embodiments described above can be applied to the multiple electronic control units and imaging unit 12031 described above.
  • the technology according to the present disclosure (the present technology) can be applied to various products.
  • the technology according to the present disclosure may be applied to an endoscopic surgery system.
  • FIG. 28 is a diagram showing an example of the general configuration of an endoscopic surgery system to which the technology disclosed herein (the present technology) can be applied.
  • an operator (doctor) 11131 is shown using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a patient bed 11133.
  • the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.
  • the endoscope 11100 is composed of a lens barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 at a predetermined length, and a camera head 11102 connected to the base end of the lens barrel 11101.
  • the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.
  • the tip of the tube 11101 has an opening into which an objective lens is fitted.
  • a light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the tube by a light guide extending inside the tube 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132.
  • the endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.
  • An optical system and an image sensor are provided inside the camera head 11102, and the reflected light (observation light) from the object of observation is focused on the image sensor by the optical system.
  • the observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image.
  • the image signal is sent to the camera control unit (CCU: Camera Control Unit) 11201 as RAW data.
  • CCU Camera Control Unit
  • the CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the overall operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), in order to display an image based on the image signal.
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the display device 11202 under the control of the CCU 11201, displays an image based on the image signal that has been subjected to image processing by the CCU 11201.
  • the light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.
  • a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.
  • the input device 11204 is an input interface for the endoscopic surgery system 11000.
  • a user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204.
  • the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.
  • the treatment tool control device 11205 controls the operation of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc.
  • the insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity in order to ensure a clear field of view for the endoscope 11100 and to ensure a working space for the surgeon.
  • the recorder 11207 is a device capable of recording various types of information related to the surgery.
  • the printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.
  • the light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203.
  • the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals.
  • the image sensor of the camera head 11102 may be controlled to acquire images in a time-division manner in synchronization with the timing of the change in the light intensity, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.
  • the light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to special light observation.
  • special light observation for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band of light is irradiated compared to the light irradiated during normal observation (i.e., white light), and a predetermined tissue such as blood vessels on the surface of the mucosa is photographed with high contrast, so-called narrow band imaging is performed.
  • fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light.
  • excitation light is irradiated to the body tissue and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescent wavelength of the reagent is irradiated to the body tissue to obtain a fluorescent image.
  • the light source device 11203 may be configured to supply narrow band light and/or excitation light corresponding to such special light observation.
  • FIG. 29 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in FIG. 28.
  • the camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405.
  • the CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413.
  • the camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.
  • the lens unit 11401 is an optical system provided at the connection with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401.
  • the lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.
  • the imaging unit 11402 is composed of an imaging element.
  • the imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type).
  • each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these.
  • the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site.
  • 3D dimensional
  • the imaging unit 11402 does not necessarily have to be provided in the camera head 11102.
  • the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.
  • the driving unit 11403 is composed of an actuator, and moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.
  • the communication unit 11404 is configured with a communication device for transmitting and receiving various information to and from the CCU 11201.
  • the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.
  • the communication unit 11404 also receives control signals for controlling the operation of the camera head 11102 from the CCU 11201, and supplies them to the camera head control unit 11405.
  • the control signals include information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and/or information specifying the magnification and focus of the captured image.
  • the above-mentioned frame rate, exposure value, magnification, focus, and other imaging conditions may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal.
  • the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.
  • the camera head control unit 11405 controls the operation of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.
  • the communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102.
  • the communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.
  • the communication unit 11411 also transmits to the camera head 11102 a control signal for controlling the operation of the camera head 11102.
  • the image signal and the control signal can be transmitted by electrical communication, optical communication, etc.
  • the image processing unit 11412 performs various image processing operations on the image signal, which is the RAW data transmitted from the camera head 11102.
  • the control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100, and the display of the captured images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.
  • the control unit 11413 also causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific body parts, bleeding, mist generated when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.
  • various image recognition techniques such as forceps, specific body parts, bleeding, mist generated when the energy treatment tool 11112 is used, etc.
  • the transmission cable 11400 that connects the camera head 11102 and the CCU 11201 is an electrical signal cable that supports electrical signal communication, an optical fiber that supports optical communication, or a composite cable of these.
  • communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.
  • the technology disclosed herein can be applied to, for example, the CCU11201 and the imaging unit 11402 of the camera head 11102.
  • the shields (solid shielding films and shielding structures) of the first to ninth embodiments described above can be applied to the CCU11201 and the imaging unit 10402.
  • this technology can be applied to light detection devices in general, including solid-state imaging devices as image sensors described above, as well as distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors.
  • a distance measurement sensor emits light toward an object, detects the light that is reflected back from the surface of the object, and calculates the distance to the object based on the flight time from when the light is emitted to when the reflected light is received.
  • the structure of the first conductor and second conductor described above can be adopted as the structure of this distance measurement sensor.
  • this technology can be applied to semiconductor devices other than light detection devices.
  • the present technology may be configured as follows. (1) a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side; a second semiconductor layer having a transistor and provided on the first surface side of the first semiconductor layer; a third semiconductor layer having a transistor and provided on the second semiconductor layer on a side opposite to the first semiconductor layer; a shield provided between the second semiconductor layer and the third semiconductor layer;
  • the optical detection device comprises: (2) The photodetector according to claim 1, wherein the shield blocks an electromagnetic field propagating from one of the second and third semiconductor layers to the other.
  • the light detection device further comprising: (9)
  • the shielding body is a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view; a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
  • a shielding structure comprising: The optical detection device described in (1) above, wherein the shielding structure is such that the first bond pad and the second bond pad are repeatedly arranged with a relative offset position in a second direction intersecting the first direction.
  • the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a planar view, and extends in the first direction.
  • the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a planar view, and is scattered in multiple locations in the first direction.
  • the shielding structure includes: a first conductor penetrating the second semiconductor layer in a thickness direction, overlapping the first bonding pad in a plan view, and extending in the first direction; a second conductor penetrating the second semiconductor layer in a thickness direction, overlapping the first bonding pad in a plan view, and being scattered in the first direction;
  • the shielding body is A conductor penetrating the second semiconductor layer in a thickness direction; a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view; a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
  • a shielding structure comprising: The optical detection device described in (1) above, wherein the shielding structure is arranged such that the conductor, the first bonding pad, and the second bonding pad are repeatedly arranged with their positions relatively shifted in
  • the photodetector according to claim 13 wherein the conductor has a stripe shape extending in the first direction in a plan view.
  • the conductors are arranged in a plurality of locations in the first direction in a plan view.
  • the shielding body is a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view; a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view; a wiring provided on the third semiconductor layer side of the second bonding pad and extending in the first direction in a plan view;
  • a shielding structure comprising:
  • the shielding structure is a photodetector device described in (1) above, in which the first and second bonding pads and the wiring are repeatedly arranged with their positions relatively shifted in a second direction that intersects the first direction in a planar view.
  • the shielding structure further comprises a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a planar view, and extends in the first direction in a planar view.
  • the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps with the first metal pad in a planar view, and is scattered in multiple locations in the first direction in a planar view.
  • the shielding body is A conductor penetrating the second semiconductor layer in a thickness direction; a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view; a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view; a wiring provided on the third semiconductor layer side of the second bonding pad and extending in the first direction in a plan view;
  • a shielding structure comprising: The optical detection device described in (1) above, wherein the shielding structure is arranged such that the conductor, the first bonding pad, the second bonding pad, and the wiring are repeatedly arranged with relative positional shifts in a second direction that intersects the first direction in a planar view.
  • An electronic device comprising:

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The present invention minimizes the occurrence of crosstalk. This light detection device comprises: a first semiconductor layer that has first and second surfaces located on opposite sides from one another, and is provided with a photoelectric conversion unit performing photoelectric conversion of light that has entered from the second surface side; a second semiconductor layer that has a transistor and is provided on the first surface side of the first semiconductor layer; a third semiconductor layer that has a transistor and is provided overlapping with the second semiconductor layer, on the opposite side of the second semiconductor layer from the first semiconductor layer side; and a shielding body that is provided between the second semiconductor layer and the third semiconductor layer.

Description

光検出装置及び電子機器Photodetection device and electronic device
　本技術（本開示に係る技術）は、光検出装置及び電子機器に関し、特に、半導体層が複数段に積層された光検出装置及びそれを備えた電子機器に適用して有効な技術に関するものである。 This technology (the technology disclosed herein) relates to photodetection devices and electronic devices, and in particular to technology that is effective when applied to photodetection devices in which semiconductor layers are stacked in multiple stages and electronic devices equipped with such devices.
　固体撮像装置や測距装置などの光検出装置では、素子が形成される半導体層を複数段に積層した積層型が知られている。この積層型の光検出装置は、信号を高速で転送することが可能となる。特許文献１には、２つの半導体層を積層した２段積層構造の固体撮像装置が開示されている。そして、特許文献１には、能動素子の動作時に能動素子から放射される光の光電変換部への入射を遮る遮光部材を設けた技術も開示されている。 In photodetection devices such as solid-state imaging devices and distance measuring devices, a stacked type is known in which semiconductor layers in which elements are formed are stacked in multiple stages. This stacked type photodetection device is capable of transferring signals at high speed. Patent Document 1 discloses a solid-state imaging device with a two-stage stacked structure in which two semiconductor layers are stacked. Patent Document 1 also discloses a technology in which a light-shielding member is provided to block the light emitted from the active element when the active element is operating from entering the photoelectric conversion unit.
　また、特許文献２には、上段、中段、下段の３つの半導体層を含む３段積層構造の固体撮像装置が開示されている。上段の半導体層には光電変換部が設けられている。中段及び下段の各々の半導体層には、光電変換部で光電変換された信号電荷に基づく画素信号を出力する画素回路（読出し回路）や、画素回路から出力された画素信号を処理するロジック回路などを構成するトランジスタが設けられている。 Patent Document 2 also discloses a solid-state imaging device with a three-layer stack structure including three semiconductor layers, an upper layer, a middle layer, and a lower layer. The upper semiconductor layer is provided with a photoelectric conversion section. Each of the middle and lower semiconductor layers is provided with transistors that constitute a pixel circuit (readout circuit) that outputs a pixel signal based on the signal charge photoelectrically converted by the photoelectric conversion section, and a logic circuit that processes the pixel signal output from the pixel circuit.
特開２０１２－６４７０９号公報JP 2012-64709 A 特開２０２１－７１７６号公報JP 2021-7176 A
　ところで、３段積層構造の光検出装置は、中段及び下段の各々の半導体層に、ロジック回路を構築するトランジスタが設けられている。このため、下段の半導体層のトランジスタと中段の半導体層のトランジスタとの間において、一方のトランジスタの動作時のノイズが他方のトランジスタに伝播し、他方のトランジスタの動作に影響するクロストークの発生が懸念される。 In a photodetector with a three-layer stack structure, transistors that construct logic circuits are provided in the middle and lower semiconductor layers. For this reason, there is a concern that noise generated during operation of one transistor between the transistor in the lower semiconductor layer and the transistor in the middle semiconductor layer may propagate to the other transistor, resulting in crosstalk that may affect the operation of the other transistor.
　本技術は、このような事情に鑑みてなされたもので、クロストークを抑制することが可能な光検出装置及び電子機器を提供することにある。 This technology was developed in consideration of these circumstances, and aims to provide a photodetector and electronic device that can suppress crosstalk.
　（１）本技術の一態様に係る光検出装置は、
　互いに反対側に位置する第１及び第２の面を有し、かつ前記第２の面側から入射した光を光電変換する光電変換部が設けられた第１半導体層と、
　トランジスタを有し、かつ前記第１半導体層の前記第１の面側に設けられた第２半導体層と、
　トランジスタを有し、かつ前記第２半導体層の前記第１半導体層側とは反対側に前記第２半導体層と重畳して設けられた第３半導体層と、
　前記第２半導体層と前記第３半導体層との間に設けられた遮蔽体と、
　を備えている。 (1) A photodetector according to an aspect of the present disclosure,
a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side;
a second semiconductor layer having a transistor and provided on the first surface side of the first semiconductor layer;
a third semiconductor layer having a transistor and provided on the second semiconductor layer on a side opposite to the first semiconductor layer;
a shield provided between the second semiconductor layer and the third semiconductor layer;
It is equipped with:
　（２）本技術の他態様に係る電子機器は、
　上記光検出装置と、
　被写体からの像光を上記光検出装置の撮像面上に結像される光学レンズと、
　上記光検出装置から出力される信号に信号処理を行う信号処理回路と、
　を備えている。 (2) An electronic device according to another aspect of the present technology includes:
The photodetector;
an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device;
a signal processing circuit for processing a signal output from the photodetector;
It is equipped with:
本技術の第１実施形態に係る固体撮像装置の一構成例を示すチップレイアウト図である。1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. 本技術の第１実施形態に係る固体撮像装置の一構成例を示すブロック図である。1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. 本技術の第１実施形態に係る固体撮像装置において、センサ画素及び画素回路の一構成例を示す等価回路図である。2 is an equivalent circuit diagram showing a configuration example of a sensor pixel and a pixel circuit in a solid-state imaging device according to a first embodiment of the present technology. FIG. 本技術の第１実施形態に係る固体撮像装置の縦断面構造を模式的に示す縦断面図である。1 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a solid-state imaging device according to a first embodiment of the present technology. 図４の一部を拡大した縦断面図である。FIG. 5 is an enlarged longitudinal sectional view of a portion of FIG. 4 . 図４の一部を拡大した縦断面図である。FIG. 5 is an enlarged longitudinal sectional view of a portion of FIG. 4 . 本技術の第１実施形態に係る固体撮像装置に搭載された遮蔽ベタ膜の縦断面構造を模式的に示す縦断面図である。1 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding solid film mounted on a solid-state imaging device according to a first embodiment of the present technology. 図６Ａの遮蔽ベタ膜の平面パターンを模式的に示す平面図である。6B is a plan view showing a schematic planar pattern of the solid shielding film of FIG. 6A. 本技術の第１実施形態に係る固体撮像装置において、回路ブロックの一例を示す図である。1 is a diagram showing an example of a circuit block in a solid-state imaging device according to a first embodiment of the present technology; 第１実施形態の変形例の縦断面構造を模式的に示す縦断面図である。FIG. 11 is a vertical cross-sectional view that illustrates a vertical cross-sectional structure of a modified example of the first embodiment. 第１実施形態の変形例の平面パターンを模式的に示す平面図である。FIG. 11 is a plan view illustrating a plane pattern of a modified example of the first embodiment. 本技術の第２実施形態に係る固体撮像装置の縦断面構造を模式的に示す縦断面図である。11 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a solid-state imaging device according to a second embodiment of the present technology. FIG. 図９の一部を拡大した縦断面図である。FIG. 10 is an enlarged longitudinal sectional view of a portion of FIG. 9 . 本技術の第２実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a second embodiment of the present technology. FIG. 図１１Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。11B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 11A. 本技術の第３実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a third embodiment of the present technology. FIG. 図１１Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。11B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 11A. 第３実施形態の変形例の平面パターンを模式的に示す平面図である。FIG. 13 is a plan view illustrating a plane pattern of a modified example of the third embodiment. 本技術の第４実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 図１４Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。14B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 14A. 第４実施形態の変形例の平面パターンを模式的に示す平面図である。FIG. 13 is a plan view illustrating a plane pattern of a modified example of the fourth embodiment. 本技術の第５実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 図１６Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。16B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 16A. 第５実施形態の変形例の平面パターンを模式的に示す平面図である。FIG. 13 is a plan view diagrammatically showing a plane pattern of a modified example of the fifth embodiment. 本技術の第６実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a sixth embodiment of the present technology. FIG. 図１８Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。18B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 18A. 本技術の第７実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a seventh embodiment of the present technology. FIG. 図１９Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。19B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 19A. 第７実施形態の変形例の平面パターンを模式的に示す平面図である。FIG. 23 is a plan view illustrating a plane pattern of a modified example of the seventh embodiment. 本技術の第８実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to an eighth embodiment of the present technology. FIG. 図２１Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。21B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 21A. 第８実施形態の変形例の平面パターンを模式的に示す平面図である。FIG. 23 is a plan view illustrating a plane pattern of a modified example of the eighth embodiment. 本技術の第９実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を模式的に示す縦断面図である。13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a ninth embodiment of the present technology. FIG. 図２３Ａの遮蔽構造体の平面パターンを模式的に示す平面図である。23B is a plan view showing a schematic planar pattern of the shielding structure of FIG. 23A. 第９実施形態の変形例の平面パターンを模式的に示す平面図である。FIG. 13 is a plan view illustrating a plane pattern of a modified example of the ninth embodiment. 本技術の第１０実施形態に係る電子機器の概略構成を示す図である。FIG. 23 is a diagram showing a schematic configuration of an electronic device according to a tenth embodiment of the present technology. 車両制御システムの概略的な構成の一例を示すブロック図である。1 is a block diagram showing an example of a schematic configuration of a vehicle control system; 車外情報検出部及び撮像部の設置位置の一例を示す説明図である。4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. 内視鏡手術システムの概略的な構成の一例を示す図である。1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. カメラヘッド及びＣＣＵの機能構成の一例を示すブロック図である。2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. FIG.
　以下、図面を参照して本技術の実施形態を詳細に説明する。
　なお、以下の説明で参照する図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。 Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings.
In the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description.
　また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。また、本明細書中に記載された効果はあくまで例示であって限定されるものでは無く、また他の効果があってもよい。 Of course, there are parts in which the dimensional relationships and ratios differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also exist.
　また、以下の実施形態は、本技術の技術的思想を具体化するための装置や方法を例示するものであり、構成を下記のものに特定するものではない。即ち、本技術の技術的思想は、特許請求の範囲に記載された技術的範囲内において、種々の変更を加えることができる。 Furthermore, the following embodiments are merely examples of devices and methods for embodying the technical ideas of the present technology, and are not intended to limit the configuration to those described below. In other words, the technical ideas of the present technology can be modified in various ways within the technical scope described in the claims.
　また、以下の説明における上下等の方向の定義は、単に説明の便宜上の定義であって、本技術の技術的思想を限定するものではない。例えば、対象を９０°回転して観察すれば上下は左右に変換して読まれ、１８０°回転して観察すれば上下は反転して読まれることは勿論である。 Furthermore, the definitions of up and down and other directions in the following explanation are merely for the convenience of explanation and do not limit the technical ideas of this technology. For example, if an object is rotated 90 degrees and observed, up and down are converted into left and right and read, and of course, if it is rotated 180 degrees and observed, up and down are read inverted.
　また、以下の実施形態では、空間内で互に直交する三方向において、同一平面内で互に直交する第１の方向及び第２の方向をそれぞれＸ方向、Ｙ方向とし、第１の方向及び第２の方向のそれぞれと直交する第３の方向をＺ方向とする。そして、以下の実施形態では、後述する半導体層の厚さ方向をＺ方向として説明する。
　また、以下の実施形態では、Ｚ方向を本技術の「一方向」として説明する。
　また、以下の実施形態において、半導体層の厚さとは、Ｚ方向において互いに反対側に位置する第１の面部と第２の面部との離間距離であり、半導体層の厚さ方向とは、半導体層の厚さを表す方向である。
　また、以下の実施形態において、平面視とは、Ｚ方向（一方向）から半導体層を視た場合を指す。断面視とは、Ｚ方向（一方向）に沿う断面をこの断面と直交する方向（Ｚ方向）方向から視た場合を指す。 In the following embodiments, among the three mutually orthogonal directions in space, a first direction and a second direction mutually orthogonal in the same plane are defined as an X direction and a Y direction, respectively, and a third direction perpendicular to each of the first direction and the second direction is defined as a Z direction. In the following embodiments, the thickness direction of a semiconductor layer described later is described as the Z direction.
In the following embodiments, the Z direction will be described as "one direction" of the present technology.
In addition, in the following embodiments, the thickness of the semiconductor layer is the distance between a first surface portion and a second surface portion located opposite each other in the Z direction, and the thickness direction of the semiconductor layer is the direction representing the thickness of the semiconductor layer.
In the following embodiments, a plan view refers to a semiconductor layer viewed from the Z direction (one direction), and a cross-sectional view refers to a cross section along the Z direction (one direction) viewed from a direction perpendicular to the cross section (Z direction).
　〔第１実施形態〕
　この第１実施形態では、光検出装置として、裏面照射型のＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサである固体撮像装置に本技術を適用した一例について説明する。
　また、この第１実施形態では、電磁場を遮蔽する遮蔽体としての遮蔽ベタ膜について説明する。遮蔽ベタ膜は、本技術の「遮蔽体」の一具体例に相当する。 First Embodiment
In the first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor as a photodetector will be described.
In addition, in the first embodiment, a solid shielding film will be described as a shielding body that blocks an electromagnetic field. The solid shielding film corresponds to a specific example of a "shielding body" of the present technology.
　≪固体撮像装置の全体構成≫
　まず、固体撮像装置１Ａの全体構成について説明する。
　図１に示すように、本技術の第１実施形態に係る固体撮像装置１Ａは、平面視したときの二次元平面形状が方形状の半導体チップ２を主体に構成されている。即ち、固体撮像装置１Ａは半導体チップ２に搭載されており、半導体チップ２を固体撮像装置１Ａとみなすことができる。この固体撮像装置１Ａ（１０１）は、図２５に示すように、光学レンズ１０２を介して被写体からの像光（入射光１０６）を取り込み、撮像面上に結像された入射光１０６の光量を画素単位で電気信号に変換して画素信号として出力する。 <Overall configuration of solid-state imaging device>
First, the overall configuration of the solid-state imaging device 1A will be described.
As shown in Fig. 1, the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plane. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. As shown in Fig. 25, this solid-state imaging device 1A (101) takes in image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.
　図１に示すように、固体撮像装置１Ａが搭載された半導体チップ２は、互いに直交するＸ方向及びＹ方向を含む二次元平面において、中央部に設けられた方形状のセンサ画素アレイ部２Ａと、このセンサ画素アレイ部２Ａの外側にセンサ画素アレイ部２Ａを囲むようにして設けられた周辺部２Ｂとを備えている。半導体チップ２は、製造プロセスにおいて、後述の第１～第３半導体層２０，５０，８０を含む半導体ウエハをチップ形成領域毎に小片化することによって形成される。したがって、以下に説明する固体撮像装置１Ａの構成は、半導体ウエハを小片化する前のウエハ状態においても概ね同様である。即ち、本技術は、半導体チップの状態及び半導体ウエハの状態において適用が可能である。 As shown in FIG. 1, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted has, in a two-dimensional plane including mutually orthogonal X and Y directions, a square sensor pixel array section 2A provided in the center, and a peripheral section 2B provided on the outside of the sensor pixel array section 2A so as to surround the sensor pixel array section 2A. In the manufacturing process, the semiconductor chip 2 is formed by dicing a semiconductor wafer including first to third semiconductor layers 20, 50, and 80 described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, this technology can be applied in the state of a semiconductor chip and in the state of a semiconductor wafer.
　センサ画素アレイ部２Ａは、例えば図２５に示す光学レンズ（光学系）１０２により集光される光を受光する受光面である。そして、センサ画素アレイ部２Ａには、Ｘ方向及びＹ方向を含む二次元平面において複数のセンサ画素３が行列状に配置されている。換言すれば、センサ画素３は、二次元平面内で互いに直交するＸ方向及びＹ方向のそれぞれの方向に繰り返し配置されている。 The sensor pixel array section 2A is a light receiving surface that receives light focused by, for example, an optical lens (optical system) 102 shown in FIG. 25. In the sensor pixel array section 2A, a plurality of sensor pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the sensor pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are mutually orthogonal within the two-dimensional plane.
　図１に示すように、周辺部２Ｂには、複数のボンディングパッド１４が配置されている。複数のボンディングパッド１４の各々は、例えば、半導体チップ２の二次元平面における４つの辺の各々の辺に沿って配列されている。複数のボンディングパッド１４の各々は、半導体チップ２と外部装置とを電気的に接続する入出力端子として機能する。 As shown in FIG. 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides of the semiconductor chip 2 in a two-dimensional plane. Each of the plurality of bonding pads 14 functions as an input/output terminal that electrically connects the semiconductor chip 2 to an external device.
　＜ロジック回路＞
　半導体チップ２は、図２に示すロジック回路１３を備えている。ロジック回路１３は、図２に示すように、垂直駆動回路４、カラム信号処理回路５、水平駆動回路６、出力回路７及び制御回路８などを含む。ロジック回路１３は、電界効果トランジスタとして、例えば、ｎチャネル導電型のＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）及びｐチャネル導電型のＭＯＳＦＥＴを有するＣＭＯＳ（Complementary MOS）回路で構成されている。 <Logic circuit>
The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, an n-channel conductivity type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a p-channel conductivity type MOSFET.
　垂直駆動回路４は、例えばシフトレジスタによって構成されている。垂直駆動回路４は、所望の画素駆動線１０を順次選択し、選択した画素駆動線１０にセンサ画素３を駆動するためのパルスを供給し、各センサ画素３を行単位で駆動する。即ち、垂直駆動回路４は、センサ画素アレイ部２Ａの各センサ画素３を行単位で順次垂直方向に選択走査し、各センサ画素３の光電変換部（光電変換素子）が受光量に応じて生成した信号電荷に基づくセンサ画素３からの画素信号を、垂直信号線１１を通してカラム信号処理回路５に供給する。 The vertical drive circuit 4 is composed of, for example, a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the sensor pixels 3, and drives each sensor pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each sensor pixel 3 in the sensor pixel array section 2A vertically row by row, and supplies pixel signals from the sensor pixels 3 based on signal charges generated by the photoelectric conversion section (photoelectric conversion element) of each sensor pixel 3 according to the amount of light received to the column signal processing circuit 5 via the vertical signal line 11.
　カラム信号処理回路５は、例えばセンサ画素３の列毎に配置されており、１行分のセンサ画素３から出力される信号に対して画素列毎にノイズ除去等の信号処理を行う。例えばカラム信号処理回路５は、画素固有の固定パターンノイズを除去するためのＣＤＳ（Correlated Double Sampling：相関２重サンプリング）及びＡＤ（Analog Digital）変換等の信号処理を行う。 The column signal processing circuit 5 is arranged, for example, for each column of sensor pixels 3, and performs signal processing such as noise removal for each pixel column on the signals output from one row of sensor pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-to-Digital) conversion to remove pixel-specific fixed pattern noise.
　水平駆動回路６は、例えばシフトレジスタによって構成されている。水平駆動回路６は、水平走査パルスをカラム信号処理回路５に順次出力することによって、カラム信号処理回路５の各々を順番に選択し、カラム信号処理回路５の各々から信号処理が行われた画素信号を水平信号線１２に出力させる。 The horizontal drive circuit 6 is composed of, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn, and causing each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to the horizontal signal line 12.
　出力回路７は、カラム信号処理回路５の各々から水平信号線１２を通して順次に供給される画素信号に対し、信号処理を行って出力する。信号処理としては、例えば、バッファリング、黒レベル調整、列ばらつき補正、各種デジタル信号処理等を用いることができる。 The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. For example, the signal processing may include buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.
　制御回路８は、垂直同期信号、水平同期信号、及びマスタクロック信号に基づいて、垂直駆動回路４、カラム信号処理回路５、及び水平駆動回路６等の動作の基準となるクロック信号や制御信号を生成する。そして、制御回路８は、生成したクロック信号や制御信号を、垂直駆動回路４、カラム信号処理回路５、及び水平駆動回路６等に出力する。 The control circuit 8 generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.
　＜センサ画素の回路構成＞
　図３に示すように、複数のセンサ画素３の各々のセンサ画素３は、光電変換領域２１及び画素回路（読出し回路）１５を備えている。光電変換領域２１は、光電変換部２４と、画素トランジスタとしての転送トランジスタＴＲと、電荷保持部としてのフローティングディフュージョン（Floating Diffusion）領域ＦＤとを備えている。画素回路１５は、光電変換領域２１のフローティングディフュージョン領域ＦＤと電気的に接続されている。 <Circuit configuration of sensor pixel>
3, each of the sensor pixels 3 includes a photoelectric conversion region 21 and a pixel circuit (readout circuit) 15. The photoelectric conversion region 21 includes a photoelectric conversion unit 24, a transfer transistor TR as a pixel transistor, and a floating diffusion region FD as a charge holding unit. The pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 21.
　この第１実施形態では、一例として１つのセンサ画素３に１つの画素回路１５を割り与えた回路構成としているが、この第１実施形態に限定されるものではない。例えば、１つの画素回路１５を複数のセンサ画素３で共有する回路構成としてもよい。具体的には、Ｘ方向及びＹ方向の各々の方向に２つずつ配置された２×２配置の４つのセンサ画素３を一単位とする１つのセンサ画素群（光電変換群）で１つの画素回路１５を共有する回路構成としてもよい。また、２つのセンサ画素３を一単位とする１つのセンサ画素群（光電変換群）で１つの画素回路１５を共有する回路構成としてもよい。また、４つ以上のセンサ画素３を一単位とする１つのセンサ画素群（光電変換群）で１つの画素回路１５を共有する回路構成としてもよい。 In the first embodiment, as an example, a circuit configuration is used in which one pixel circuit 15 is assigned to one sensor pixel 3, but the present invention is not limited to this first embodiment. For example, a circuit configuration may be used in which one pixel circuit 15 is shared by multiple sensor pixels 3. Specifically, a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which four sensor pixels 3 are arranged in a 2×2 arrangement, two in each of the X and Y directions, as one unit. Also, a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which two sensor pixels 3 are arranged as one unit. Also, a circuit configuration may be used in which one pixel circuit 15 is shared by one sensor pixel group (photoelectric conversion group) in which four or more sensor pixels 3 are arranged as one unit.
　図３に示す光電変換部２４は、例えばｐｎ接合型のフォトダイオード（ＰＤ）で構成され、受光量に応じた信号電荷を生成する。光電変換部２４は、カソード側が転送トランジスタＴＲのソース領域と電気的に接続され、アノード側が基準電位線（例えばグランド）と電気的に接続されている。 The photoelectric conversion unit 24 shown in FIG. 3 is composed of, for example, a pn junction type photodiode (PD) and generates a signal charge according to the amount of light received. The cathode side of the photoelectric conversion unit 24 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).
　図３に示す転送トランジスタＴＲは、光電変換部２４で光電変換された信号電荷をフローティングディフュージョン領域ＦＤに転送する。転送トランジスタＲＴのソース領域は光電変換部２４のカソード側と電気的に接続され、転送トランジスタＴＲのドレイン領域はフローティングディフュージョン領域ＦＤと電気的に接続されている。そして、転送トランジスタＴＲのゲート電極は、画素駆動線１０（図２参照）のうちの転送トランジスタ駆動線と電気的に接続されている。 The transfer transistor TR shown in FIG. 3 transfers the signal charge photoelectrically converted by the photoelectric conversion unit 24 to the floating diffusion region FD. The source region of the transfer transistor RT is electrically connected to the cathode side of the photoelectric conversion unit 24, and the drain region of the transfer transistor TR is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line of the pixel drive line 10 (see FIG. 2).
　図３に示すフローティングディフュージョン領域ＦＤは、光電変換部２４から転送トランジスタＴＲを介して転送された信号電荷を一時的に保持（蓄積）する。 The floating diffusion region FD shown in FIG. 3 temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 24 via the transfer transistor TR.
　光電変換部２４、転送トランジスタＴＲ及びフローティングディフュージョン領域ＦＤを含む光電変換領域２１は、図５に示す第１半導体層２０にセンサ画素３毎に搭載されている。 The photoelectric conversion region 21, which includes the photoelectric conversion unit 24, the transfer transistor TR, and the floating diffusion region FD, is mounted for each sensor pixel 3 on the first semiconductor layer 20 shown in FIG. 5.
　図３に示す画素回路１５は、フローティングディフュージョン領域ＦＤに保持された信号電荷を読み出し、読み出した信号電荷に基づく画素信号を出力する。画素回路１５は、これに限定されないが、画素トランジスタとして、例えば、増幅トランジスタＡＭＰと、選択トランジスタＳＥＬと、リセットトランジスタＲＳＴと、を備えている。これらの画素トランジスタ（ＡＭＰ，ＳＥＬ，ＲＳＴ）、及び上述の転送トランジスタＴＲの各々は、電界効果トランジスタとして、例えば、酸化シリコン（ＳｉＯ２）膜からなるゲート絶縁膜と、ゲート電極と、ソース領域及びドレイン領域として機能する一対の主電極領域と、を有するＭＯＳＦＥＴで構成されている。また、これらのトランジスタとしては、ゲート絶縁膜が窒化シリコン（Ｓｉ３Ｎ４）膜、或いは窒化シリコン膜及び酸化シリコン膜などの積層膜からなるＭＩＳＦＥＴ（Metal Insulator Semiconductor FET）でも構わない。 The pixel circuit 15 shown in FIG. 3 reads out the signal charge held in the floating diffusion region FD and outputs a pixel signal based on the read-out signal charge. The pixel circuit 15 includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors. Each of these pixel transistors (AMP, SEL, RST) and the above-mentioned transfer transistor TR is configured as a field effect transistor, for example, a MOSFET having a gate insulating film made of a silicon oxide (SiO 2 ) film, a gate electrode, and a pair of main electrode regions functioning as a source region and a drain region. In addition, these transistors may be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of a silicon nitride (Si 3 N 4 ) film or a laminated film such as a silicon nitride film and a silicon oxide film.
　図３に示すように、増幅トランジスタＡＭＰは、ソース領域が選択トランジスタＳＥＬのドレイン領域と電気的に接続され、ドレイン領域が電源線Ｖｄｄ及びリセットトランジスタＲＳＴのドレイン領域と電気的に接続されている。そして、増幅トランジスタＡＭＰのゲート電極は、フローティングディフュージョン領域ＦＤ及びリセットトランジスタＲＳＴのソース領域と電気的に接続されている。 As shown in FIG. 3, the source region of the amplification transistor AMP is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplification transistor AMP is electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.
　図３に示すように、選択トランジスタＳＥＬは、ソースが垂直信号線１１（ＶＳＬ）と電気的に接続され、ドレイン領域が増幅トランジスタＡＭＰのソース領域と電気的に接続されている。そして、選択トランジスタＳＥＬのゲート電極は、図２に示す画素駆動線１０のうちの選択トランジスタ駆動線と電気的に接続されている。 As shown in FIG. 3, the source of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive line 10 shown in FIG. 2.
　図３に示すように、リセットトランジスタＲＳＴは、ソース領域がフローティングディフュージョン領域ＦＤ及び増幅トランジスタＡＭＰのゲート電極と電気的に接続され、ドレイン領域が電源線Ｖｄｄ及び増幅トランジスタＡＭＰのドレイン領域と電気的に接続されている。そして、リセットトランジスタＲＳＴのゲート電極は、図２に示す画素駆動線１０のうちのリセットトランジスタ駆動線と電気的に接続されている。 As shown in FIG. 3, the source region of the reset transistor RST is electrically connected to the floating diffusion region FD and the gate electrode of the amplifier transistor AMP, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG. 2.
　図３に示す転送トランジスタＴＲは、転送トランジスタＴＲＧがオン状態となると、光電変換部２４で生成された信号電荷をフローティングディフュージョン領域ＦＤに転送する。 When the transfer transistor TRG shown in FIG. 3 is turned on, the transfer transistor TR transfers the signal charge generated in the photoelectric conversion unit 24 to the floating diffusion region FD.
　図３に示すリセットトランジスタＲＳＴは、リセットトランジスタＲＳＴがオン状態となると、フローティングディフュージョン領域ＦＤの電位（信号電荷）を電源線Ｖｄｄの電位にリセットする。選択トランジスタＳＥＬは、画素回路１５からの画素信号の出力タイミングを制御する。 When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 15.
　図３に示す増幅トランジスタＡＭＰは、画素信号として、フローティングディフュージョン領域ＦＤに保持された信号電荷のレベルに応じた電圧の信号を生成する。増幅トランジスタＡＭＰは、ソースフォロア型のアンプを構成しており、光電変換部２４で生成された信号電荷のレベルに応じた電圧の画素信号を出力するものである。増幅トランジスタＡＭＰは、選択トランジスタＳＥＬがオン状態となると、フローティングディフュージョン領域ＦＤの電位を増幅して、その電位に応じた電圧を、垂直信号線１１（ＶＳＬ）を介してカラム信号処理回路５に出力する。 The amplification transistor AMP shown in FIG. 3 generates a pixel signal whose voltage corresponds to the level of the signal charge held in the floating diffusion region FD. The amplification transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 24. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD, and outputs a voltage corresponding to that potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).
　ここで、図３を参照して説明すれば、この第１実施形態に係る固体撮像装置１Ａの動作時には、センサ画素３の光電変換部２４で生成された信号電荷がセンサ画素３の転送トランジスタＴＲを介してフローティングディフュージョン領域ＦＤに保持（蓄積）される。そして、フローティングディフュージョン領域ＦＤに保持された信号電荷が画素回路１５により読み出されて、画素回路１５の増幅トランジスタＡＭＰのゲート電極に印加される。画素回路１５の選択トランジスタＳＥＬのゲート電極には水平ラインの選択用制御信号が垂直シフトレジスタから与えられる。そして、選択用制御信号をハイ（Ｈ）レベルにすることにより、選択トランジスタＳＥＬが導通し、増幅トランジスタＡＭＰで増幅された、フローティングディフュージョン領域ＦＤの電位に対応する電流が垂直信号線１１に流れる。また、画素回路１５のリセットトランジスタＲＳＴのゲート電極に印加するリセット用制御信号をハイ（Ｈ）レベルにすることにより、リセットトランジスタＲＳＴが導通し、フローティングディフュージョン領域ＦＤに蓄積された信号電荷をリセットする。 Now, referring to FIG. 3, during operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated in the photoelectric conversion unit 24 of the sensor pixel 3 is held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the sensor pixel 3. The signal charge held in the floating diffusion region FD is read out by the pixel circuit 15 and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 15. A horizontal line selection control signal is provided to the gate electrode of the selection transistor SEL of the pixel circuit 15 from the vertical shift register. Then, by setting the selection control signal to a high (H) level, the selection transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP flows in the vertical signal line 11. Also, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 to a high (H) level, the reset transistor RST becomes conductive, and the signal charge accumulated in the floating diffusion region FD is reset.
　＜他の画素回路＞
　なお、選択トランジスタＳＥＬは、必要に応じて省略してもよい。選択トランジスタＳＥＬを省略する場合は、増幅トランジスタＡＭＰのソース領域が垂直信号線１１（ＶＳＬ）と電気的に接続される。 <Other pixel circuits>
The selection transistor SEL may be omitted if necessary. In the case where the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).
　また、リセットトランジスタＲＳＴと、フローティングディフュージョン領域ＦＤ及び増幅トランジスタＡＭＰのゲート電極との間に切替トランジスタを設けてもよい。切替トランジスタは、フローティングディフュージョン領域ＦＤによる電荷保持を制御すると共に、増幅トランジスタＡＭＰで増幅される電位に応じた電圧の増倍率を調整する。 A switching transistor may also be provided between the reset transistor RST and the gate electrode of the floating diffusion region FD and the amplifier transistor AMP. The switching transistor controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP.
　また、切替トランジスタは、変換効率を切り替える際に用いられる。一般に、暗い場所での撮影時には画素信号が小さい。Ｑ＝ＣＶに基づき、電荷電圧変換を行う際に、電荷保持部（フローティングディフュージョン領域ＦＤ）のＦＤ容量Ｃ（フローティングディフュージョン容量Ｃ）が大きければ、増幅トランジスタＡＭＰで電圧に変換した際の電圧Ｖが小さくなってしまう。一方、明るい場所では、画素信号が大きくなるので、電荷保持部のＦＤ容量Ｃが大きくなければ、電荷保持部で、光電変換部２４（フォトダイオードＰＤ）の電荷を受けきれない。さらに、増幅トランジスタＡＭＰで電圧に変換した際の電圧Ｖが大きくなりすぎないように（言い換えると、小さくなるように）、電荷保持部のＦＤ容量Ｃが大きくなっている必要がある。これらを踏まえると、切替トランジスタをオンにしたときには、切替トランジスタ分のゲート容量が増えるので、全体のＦＤ容量Ｃが大きくなる。一方、切替トランジスタをオフにしたときには、全体のＦＤ容量Ｃが小さくなる。このように、切替トランジスタのオン／オフを切り替えることで、ＦＤ容量Ｃを可変にし、変換効率を切り替えることができる。 The switching transistor is also used to switch the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, if the FD capacitance C (floating diffusion capacitance C) of the charge holding section (floating diffusion region FD) is large when performing charge-voltage conversion, the voltage V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal is large, so if the FD capacitance C of the charge holding section is not large, the charge holding section cannot receive the charge of the photoelectric conversion section 24 (photodiode PD). Furthermore, the FD capacitance C of the charge holding section needs to be large so that the voltage V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In light of this, when the switching transistor is turned on, the gate capacitance of the switching transistor increases, so the overall FD capacitance C becomes large. On the other hand, when the switching transistor is turned off, the overall FD capacitance C becomes small. In this way, by switching the switching transistor on/off, the FD capacitance C can be made variable and the conversion efficiency can be switched.
　≪固体撮像装置の具体的な構成≫
　次に、固体撮像装置１Ａの具体的な構成について、図４、図５Ａ及び図５Ｂを用いて説明する。 <<Specific configuration of solid-state imaging device>>
Next, a specific configuration of the solid-state imaging device 1A will be described with reference to FIGS. 4, 5A, and 5B.
　＜固体撮像装置の積層構造＞
　図４、図５Ａ及び図５Ｂに示すように、固体撮像装置１Ａ（半導体チップ２）は、集光層９０と、第１半導体層２０と、第１配線層３０と、第２配線層４０と、第２半導体層５０と、第３配線層６０と、第４配線層７０と、第３半導体層８０と、をこの順で積層した積層構造を有する。ここで、第１半導体層２０、第２半導体層５０、第３半導体層８０は、本技術の「第１半導体層」、「第２半導体層」、「第３半導体層」の一具体例に相当する。また、第３配線層６０、第４配線層７０は、本技術の「第１配線層」、「第２配線層」の一具体例に相当する。 <Stacked structure of solid-state imaging device>
As shown in Figures 4, 5A, and 5B, the solid-state imaging device 1A (semiconductor chip 2) has a laminated structure in which a light collecting layer 90, a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 40, a second semiconductor layer 50, a third wiring layer 60, a fourth wiring layer 70, and a third semiconductor layer 80 are laminated in this order. Here, the first semiconductor layer 20, the second semiconductor layer 50, and the third semiconductor layer 80 correspond to specific examples of the "first semiconductor layer", the "second semiconductor layer", and the "third semiconductor layer" of the present technology. Also, the third wiring layer 60 and the fourth wiring layer 70 correspond to specific examples of the "first wiring layer" and the "second wiring layer" of the present technology.
　本技術の「第１半導体層として」の第１半導体層２０は、第１半導体層２０の厚さ方向（Ｚ方向）において互いに反対側に位置する第１の面Ｓ１及び第２の面Ｓ２を有する（図５Ａ参照）。そして、第１半導体層２０は、後述の光電変換領域２１（図５Ａ参照）を有する。
　集光層９０は、第１半導体層２０の第２の面Ｓ２側に設けられている。そして、集光層９０は、第１半導体層２０の第２の面Ｓ２側から、これに限定されないが、例えば、カラーフィルタ９１と、オンチップレンズ９２とがこの順で積層された積層構造を有する。
　第１配線層３０は、第１半導体層２０の第１の面Ｓ１側に設けられ、第１半導体層２０の第１の面Ｓ１に重ね合わされている。
　第２配線層４０は、第１配線層３０の第１半導体層２０側とは反対側に設けられ、第１配線層３０の第１半導体層２０側の面に重ね合わされている。 The first semiconductor layer 20 "as a first semiconductor layer" of the present technology has a first surface S1 and a second surface S2 located opposite to each other in a thickness direction (Z direction) of the first semiconductor layer 20 (see FIG. 5A ). The first semiconductor layer 20 has a photoelectric conversion region 21 (see FIG. 5A ) described later.
The light collecting layer 90 is provided on the second surface S2 side of the first semiconductor layer 20. The light collecting layer 90 has a laminated structure in which, for example, but not limited to, a color filter 91 and an on-chip lens 92 are laminated in this order from the second surface S2 side of the first semiconductor layer 20.
The first wiring layer 30 is provided on the first surface S<b>1 side of the first semiconductor layer 20 and overlaps the first surface S<b>1 of the first semiconductor layer 20 .
The second wiring layer 40 is provided on the side of the first wiring layer 30 opposite to the first semiconductor layer 20 side, and is superimposed on the surface of the first wiring layer 30 on the first semiconductor layer 20 side.
　本技術の「第２半導体層として」の第２半導体層５０は、第２半導体層５０の厚さ方向（Ｚ方向）において互いに反対側に位置する第３の面Ｓ３及び第４の面Ｓ４を有する（図５Ｂ参照）。そして、第２半導体層５０は、第２配線層４０の第１配線層３０側とは反対側に設けられ、第２配線層４０の第１配線層３０側とは反対側の面に重ね合わされている。
　本技術の「第１配線層として」の第３配線層６０は、第２半導体層５０の第２配線層４０側とは反対側に設けられ、第２半導体層５０の第４の面Ｓ４に重ね合わされている。
　本技術の「第２配線層として」の第４配線層７０は、第３配線層６０の第２半導体層５０側とは反対側に設けられ、第３配線層６０の第２半導体層５０側とは反対側の面に重ね合わされている。 The second semiconductor layer 50 "as the second semiconductor layer" of the present technology has a third surface S3 and a fourth surface S4 located opposite to each other in the thickness direction (Z direction) of the second semiconductor layer 50 (see FIG. 5B ). The second semiconductor layer 50 is provided on the side of the second wiring layer 40 opposite to the first wiring layer 30 side, and is superimposed on the surface of the second wiring layer 40 opposite to the first wiring layer 30 side.
The third wiring layer 60 “as a first wiring layer” in the present technology is provided on the side of the second semiconductor layer 50 opposite the second wiring layer 40 side, and is superimposed on the fourth surface S<b>4 of the second semiconductor layer 50 .
The fourth wiring layer 70 “as the second wiring layer” in the present technology is provided on the side opposite the second semiconductor layer 50 side of the third wiring layer 60, and is superimposed on the surface of the third wiring layer 60 opposite the second semiconductor layer 50 side.
　本技術の「第３半導体層として」の第３半導体層８０は、第３半導体層８０の厚さ方向において互いに反対側に位置する第５の面Ｓ５及び第６の面Ｓ６を有する。そして、第３半導体層８０は、第４配線層７０の第３配線層６０側とは反対側に設けられ、第４配線層７０の第３配線層６０側とは反対側の面に重ね合わされている。 The third semiconductor layer 80 "as the third semiconductor layer" of the present technology has a fifth surface S5 and a sixth surface S6 located on opposite sides to each other in the thickness direction of the third semiconductor layer 80. The third semiconductor layer 80 is provided on the side of the fourth wiring layer 70 opposite to the third wiring layer 60 side, and is superimposed on the surface of the fourth wiring layer 70 opposite to the third wiring layer 60 side.
　ここで、第１半導体層２０の第１の面Ｓ１を素子形成面又は主面と呼び、第１半導体層２０の第２の面Ｓ２を光入射面又は裏面と呼ぶこともある。また、第２半導体層５０の第３の面Ｓ３を素子形成面又は主面と呼び、第２半導体層５０の第４の面Ｓ４を裏面と呼ぶこともある。さらに、第３半導体層８０の第５の面Ｓ５を素子形成面又は主面と呼び、第５の面Ｓ５とは反対側の面を裏面と呼ぶこともある。 Here, the first surface S1 of the first semiconductor layer 20 is sometimes called the element formation surface or main surface, and the second surface S2 of the first semiconductor layer 20 is sometimes called the light incidence surface or back surface. The third surface S3 of the second semiconductor layer 50 is sometimes called the element formation surface or main surface, and the fourth surface S4 of the second semiconductor layer 50 is sometimes called the back surface. Furthermore, the fifth surface S5 of the third semiconductor layer 80 is sometimes called the element formation surface or main surface, and the surface opposite the fifth surface S5 is sometimes called the back surface.
　また、第１半導体層２０と第２半導体層５０とは、第１配線層３０及び第２配線層４０を介して、Ｆ２Ｆ（Face to Face）法で、すなわち素子形成面同士が向かい合うように、接合されている。さらに、第２半導体層５０と第３半導体層８０とは、第３配線層６０及び第４配線層７０を介して、Ｂ２Ｆ（Back to Face）法で、すなわち裏面と素子形成面とが向かい合うように、接合されている。 The first semiconductor layer 20 and the second semiconductor layer 50 are bonded together by the F2F (Face to Face) method, i.e., with their element formation surfaces facing each other, via the first wiring layer 30 and the second wiring layer 40. The second semiconductor layer 50 and the third semiconductor layer 80 are bonded together by the B2F (Back to Face) method, i.e., with their back surfaces facing each other, via the third wiring layer 60 and the fourth wiring layer 70.
　＜第１半導体層＞
　第１半導体層２０は、半導体基板で構成されている。第１半導体層２０は、例えば第１導電型としてのｐ型の単結晶シリコン基板で構成されている。第１半導体層２０のうち、平面視でセンサ画素アレイ部２Ａと重なる領域には、光電変換領域２１がセンサ画素３毎に設けられている。光電変換領域２１は、図示していないが、第１半導体層２０に設けられた分離領域によって区画されている。なお、センサ画素３の数は、図４に限定されるものではない。 <First Semiconductor Layer>
The first semiconductor layer 20 is made of a semiconductor substrate. The first semiconductor layer 20 is made of, for example, a p-type single crystal silicon substrate as the first conductivity type. In the region of the first semiconductor layer 20 that overlaps with the sensor pixel array section 2A in a planar view, a photoelectric conversion region 21 is provided for each sensor pixel 3. Although not shown, the photoelectric conversion region 21 is partitioned by a separation region provided in the first semiconductor layer 20. Note that the number of sensor pixels 3 is not limited to that shown in FIG. 4.
　光電変換領域２１は、図示していないが、例えばｐ型のウエル領域と、このウエル領域の内部に埋設された第２導電型としてのｎ型の半導体領域（光電変換部）と、を有する。図３に示した光電変換素子ＰＤは、第１半導体層２０のウエル領域と光電変換部とを含む光電変換領域２１に構成されている。また、光電変換領域２１には、これに限定されないが、例えばｎ型の半導体領域からなる電荷保持部（電荷蓄積部）と、転送トランジスタＴＲとが設けられている。 The photoelectric conversion region 21, although not shown, has, for example, a p-type well region and an n-type semiconductor region (photoelectric conversion section) as the second conductivity type buried inside this well region. The photoelectric conversion element PD shown in FIG. 3 is configured in the photoelectric conversion region 21 including the well region and photoelectric conversion section of the first semiconductor layer 20. In addition, the photoelectric conversion region 21 is provided with, for example, a charge holding section (charge accumulation section) made of an n-type semiconductor region, and a transfer transistor TR, although this is not limited thereto.
　＜第１配線層＞
　第１配線層３０は、絶縁膜３１と、配線３２と、接合パッド（接合メタルパッド）３３と、コンタクト電極（ビア）と、を含む。配線３２及び接合パッド３３は、図示のように絶縁膜３１を介して積層されている。接合パッド３３は、第１配線層３０の第１半導体層２０側とは反対側の面に臨んでいる。接合パッド３３は、第１配線層３０の第１半導体層２０側とは反対側の最上層に設けられ、コンタクト電極を介して下層の配線３２と電気的に接続されている。配線３２及び接合パッド３３は、これに限定されないが、例えば、銅製であり、ダマシン法により形成されていても良い。 <First Wiring Layer>
The first wiring layer 30 includes an insulating film 31, a wiring 32, a bonding pad (bonding metal pad) 33, and a contact electrode (via). The wiring 32 and the bonding pad 33 are laminated with the insulating film 31 interposed therebetween as shown in the figure. The bonding pad 33 faces the surface of the first wiring layer 30 opposite the first semiconductor layer 20 side. The bonding pad 33 is provided in the top layer of the first wiring layer 30 opposite the first semiconductor layer 20 side, and is electrically connected to the wiring 32 in the lower layer via a contact electrode. The wiring 32 and the bonding pad 33 are made of, but are not limited to, copper, and may be formed by a damascene method, for example.
　＜第２配線層＞
　第２配線層４０は、絶縁膜４１と、配線４２と、接合パッド（接合メタルパッド）４３と、コンタクト電極（ビア）とを含む。配線４２及び接合パッド４３は、図示のように絶縁膜４１を介して積層されている。接合パッド４３は、第２配線層４０の第２半導体層５０側とは反対側の面に臨んでいる。接合パッド４３は、第２配線層４０の第２半導体層５０側とは反対側の最上層に設けられ、コンタクト電極を介して下層の配線４２と電気的に接続されている。そして、接合パッド４３は、第１配線層３０の接合パッド３３と接合されている。配線４２及び接合パッド４３は、これに限定されないが、例えば、銅製であり、ダマシン法により形成されていても良い。 <Second Wiring Layer>
The second wiring layer 40 includes an insulating film 41, a wiring 42, a bonding pad (bonding metal pad) 43, and a contact electrode (via). The wiring 42 and the bonding pad 43 are laminated with the insulating film 41 interposed therebetween as shown in the figure. The bonding pad 43 faces the surface of the second wiring layer 40 opposite to the second semiconductor layer 50 side. The bonding pad 43 is provided in the uppermost layer of the second wiring layer 40 opposite to the second semiconductor layer 50 side, and is electrically connected to the wiring 42 in the lower layer via a contact electrode. The bonding pad 43 is bonded to the bonding pad 33 of the first wiring layer 30. The wiring 42 and the bonding pad 43 are not limited to this, but may be made of copper, for example, and may be formed by a damascene method.
　＜第２半導体層＞
　第２半導体層５０は、これに限定されないが、例えばｐ型の単結晶シリコン基板で構成されている。第２半導体層５０には、トランジスタＴ１が複数設けられている。トランジスタＴ１は、例えば、図３に示す画素回路（読出し回路）１５を構成する画素トランジスタや、図２に示すロジック回路１３を構成するトランジスタである。 <Second Semiconductor Layer>
The second semiconductor layer 50 is made of, for example, a p-type single crystal silicon substrate, but is not limited thereto. A plurality of transistors T1 are provided in the second semiconductor layer 50. The transistors T1 are, for example, pixel transistors constituting the pixel circuit (readout circuit) 15 shown in FIG. 3 or transistors constituting the logic circuit 13 shown in FIG. 2.
　＜第３配線層＞
　図５Ｂに示すように、第３配線層６０は、絶縁膜６１と、配線６２と、接合パッド（接合メタルパッド）６３と、とを含む。配線６２及び接合パッド６３は、図示のように絶縁膜６１を介して積層されている。接合パッド６３は、第３配線層６０の第２半導体層５０側とは反対側の面に臨んでいる。配線６２及び接合パッド６３は、これに限定されないが、例えば、銅製であり、ダマシン法により形成されていても良い。 <Third Wiring Layer>
5B, the third wiring layer 60 includes an insulating film 61, a wiring 62, and a bonding pad (bonding metal pad) 63. The wiring 62 and the bonding pad 63 are laminated via the insulating film 61 as shown in the figure. The bonding pad 63 faces the surface of the third wiring layer 60 opposite to the second semiconductor layer 50 side. The wiring 62 and the bonding pad 63 are made of, but are not limited to, copper, and may be formed by a damascene method, for example.
　ここで、この第１実施形態では、接合パッド６３が本技術の「第１接合パッド」の一具体例に相当し、第３配線層６０が本技術の「第１配線層」の一具体例に相当する。 In this first embodiment, the bonding pad 63 corresponds to a specific example of the "first bonding pad" of the present technology, and the third wiring layer 60 corresponds to a specific example of the "first wiring layer" of the present technology.
　＜第４配線層＞
　図５Ｂに示すように、第４配線層７０は、絶縁膜７１と、配線７２及び７２ａと、接合パッド（接合メタルパッド）７３と、コンタクト電極とを含む。配線７２及び接合パッド７３は、図示のように絶縁膜７１を介して積層されている。接合パッド７３は、第４配線層７０の第３半導体層８０側とは反対側の面に臨んでいる。接合パッド７３は、第４配線層７０の第２半導体層５０側の最上層に設けられ、コンタクト電極を介して下層の配線７２ａと電気的に接続されている。配線７２及び接合パッド７３は、これに限定されないが、例えば、銅製であり、ダマシン法により形成されていても良い。また、配線７２ａは、この配線７２ａよりも下層の配線７２とは異なり、例えばアルミニウム膜で構成されている。 <Fourth Wiring Layer>
As shown in FIG. 5B, the fourth wiring layer 70 includes an insulating film 71, wirings 72 and 72a, a bonding pad (bonding metal pad) 73, and a contact electrode. The wirings 72 and the bonding pads 73 are laminated with the insulating film 71 interposed therebetween as shown in the figure. The bonding pads 73 face the surface of the fourth wiring layer 70 opposite to the third semiconductor layer 80 side. The bonding pads 73 are provided in the uppermost layer of the fourth wiring layer 70 on the second semiconductor layer 50 side, and are electrically connected to the lower wiring 72a via the contact electrode. The wirings 72 and the bonding pads 73 may be made of, for example, copper and formed by a damascene method, although they are not limited thereto. The wirings 72a are different from the wirings 72 below the wirings 72a, and are made of, for example, an aluminum film.
　＜第３半導体層＞
　第３半導体層８０は、例えばｐ型の単結晶シリコン基板で構成されている。第３半導体層８０には、トランジスタＴ２が複数設けられている。トランジスタＴ２は、例えば、図２に示すロジック回路１３を構成するトランジスタである。 <Third Semiconductor Layer>
The third semiconductor layer 80 is made of, for example, a p-type single crystal silicon substrate. A plurality of transistors T2 are provided in the third semiconductor layer 80. The transistors T2 are, for example, transistors that constitute the logic circuit 13 shown in FIG.
　＜貫通コンタクト電極＞
　図５Ｂに示すように、第２配線層４０の配線４２と第３配線層６０の接合パッド６３とは、第２半導体層５０をその厚さ方向（Ｚ方向）に貫通する貫通コンタクト電極５１を介して電気的に接続されている。貫通コンタクト電極５１は、図示していないが、第２半導体層５０の貫通孔を貫通し、この貫通孔の内部において絶縁膜を介して第２半導体層５０と電気的に絶縁分離されている。貫通コンタクト電極５１としては、第２半導体層５０を貫通するため、第２半導体層５０の線膨張係数に近い材料を用いることが好ましい。この実施形態では、第２半導体層５０は単結晶シリコンで構成されているため、貫通コンタクト電極５１としては、抵抗値を低減する不純物が導入された多結晶シリコンを用いている。 <Through contact electrode>
As shown in FIG. 5B, the wiring 42 of the second wiring layer 40 and the bonding pad 63 of the third wiring layer 60 are electrically connected via a through contact electrode 51 that penetrates the second semiconductor layer 50 in its thickness direction (Z direction). Although not shown, the through contact electrode 51 penetrates a through hole of the second semiconductor layer 50, and is electrically insulated and separated from the second semiconductor layer 50 through an insulating film inside the through hole. As the through contact electrode 51, it is preferable to use a material with a linear expansion coefficient close to that of the second semiconductor layer 50 in order to penetrate the second semiconductor layer 50. In this embodiment, since the second semiconductor layer 50 is made of single crystal silicon, the through contact electrode 51 is made of polycrystalline silicon into which an impurity that reduces the resistance value is introduced.
　＜遮蔽ベタ膜＞
　図５Ｂに示すように、第２半導体層５０の第４の面Ｓ４側には、遮蔽体としての遮蔽ベタ膜６６が設けられている。即ち、この第１実施形態に係る固体撮像装置１Ａは、第２半導体層５０と第３半導体層８０との間に遮蔽体としての遮蔽ベタ膜６６を備えている。遮蔽ベタ膜６６は、第２半導体層５０の第４の面Ｓ４に固定電荷膜６５を介して固定されている。そして、遮蔽ベタ膜６６は、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 <Shielding solid film>
5B, a shielding solid film 66 is provided as a shield on the fourth surface S4 side of the second semiconductor layer 50. That is, the solid-state imaging device 1A according to the first embodiment includes the shielding solid film 66 as a shield between the second semiconductor layer 50 and the third semiconductor layer 80. The shielding solid film 66 is fixed to the fourth surface S4 of the second semiconductor layer 50 via a fixed charge film 65. The shielding solid film 66 suppresses an electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　固定電荷膜６５は、例えば負の固定電荷を発生させる誘電体膜を含んでいる。この誘電体膜としては、誘電率が高い例えは酸化ハフニウム（ＨｆＯ２）を用いることができる。この固定電荷膜６５により、第２半導体層５０の第４の面Ｓ４側の表層部に正孔（ｈ＋）が誘起され、この界面部分でのピニングを確保することができる。この誘電体膜としては、他に酸化ジルコニウム（ＺｒＯ２）や酸化タンタル（Ｔａ２Ｏ５）などを用いることができる。 The fixed charge film 65 includes, for example, a dielectric film that generates negative fixed charges. As this dielectric film, for example, hafnium oxide (HfO 2 ) having a high dielectric constant can be used. This fixed charge film 65 induces holes (h + ) in the surface layer portion on the fourth surface S4 side of the second semiconductor layer 50, and pinning at this interface portion can be ensured. As this dielectric film, zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), etc. can also be used.
　遮蔽ベタ膜６６は、電位が印加される配線と電気的に接続されている。そして、遮蔽ベタ膜６６は、配線に印加される電位に電位固定される。電位としては、電源生成回路から供給される電源電位がある。電源電位としては、例えば０Ｖの第１基準電位や、この第１基準電位よりも高い正電位の第２基準電位や、この第１基準電位よりも低い負電位の第３基準電位などがある。この実施形態では、遮蔽ベタ膜６６に例えば０Ｖの第１基準電位が供給される。遮蔽ベタ膜６６への電位の印加は、固体撮像装置１Ａの動作中において保持される。 The shielding solid film 66 is electrically connected to the wiring to which a potential is applied. The potential of the shielding solid film 66 is fixed to the potential applied to the wiring. The potential is a power supply potential supplied from a power generation circuit. The power supply potential can be, for example, a first reference potential of 0V, a second reference potential that is a positive potential higher than the first reference potential, or a third reference potential that is a negative potential lower than the first reference potential. In this embodiment, the first reference potential of, for example, 0V is supplied to the shielding solid film 66. The application of the potential to the shielding solid film 66 is maintained during operation of the solid-state imaging device 1A.
　遮蔽ベタ膜６６としては、バンドノイズやホットキャリア光などの電磁場の遮蔽に好適な材料を用いることが好ましい。例えばタンタル（Ｔａ）、チタン（Ｔｉ）、タングステン（Ｗ）などの高融点金属、若しくはこれらの窒化物、或いは銅（Ｃｕ）、アルミニウム（Ａｌ）などの金属を用いることができる。 The solid shielding film 66 is preferably made of a material suitable for shielding electromagnetic fields such as band noise and hot carrier light. For example, high melting point metals such as tantalum (Ta), titanium (Ti), and tungsten (W), or nitrides of these metals, or metals such as copper (Cu) and aluminum (Al) can be used.
　図５Ｂに示すように、遮蔽ベタ膜６６は、第２半導体層５０の第４の面Ｓ４側において、平面視でセンサ画素アレイ部２Ａ及び周辺部２Ｂに亘って設けられ、二次元状に広がるプレート形状になっている。そして、遮蔽ベタ膜６６は、図６Ａ及び図６Ｂに示すように、貫通コンタクト電極５１が貫通する開口部６６ａを有する。即ち、貫通コンタクト電極５１は、第２半導体層５０の貫通孔及び遮蔽ベタ膜６６の開口部６６ａを貫通し、第２半導体層５０の第３の面Ｓ３側に設けられた第２配線層４０の配線４２と、第２半導体層５０の第４の面Ｓ４側に設けられた第３配線層６０の接合パッド６３とを電気的に接続している。 As shown in FIG. 5B, the shielding solid film 66 is provided on the fourth surface S4 side of the second semiconductor layer 50 across the sensor pixel array section 2A and the peripheral section 2B in a plan view, and has a plate shape that spreads two-dimensionally. As shown in FIG. 6A and FIG. 6B, the shielding solid film 66 has an opening 66a through which the through contact electrode 51 penetrates. That is, the through contact electrode 51 penetrates the through hole of the second semiconductor layer 50 and the opening 66a of the shielding solid film 66, and electrically connects the wiring 42 of the second wiring layer 40 provided on the third surface S3 side of the second semiconductor layer 50 to the bonding pad 63 of the third wiring layer 60 provided on the fourth surface S4 side of the second semiconductor layer 50.
　開口部６６ａは、遮蔽ベタ膜６６を周知のフォトリソグラフィ技術やドライエッチング技術を用いてパターンニングすることにより形成することができる。そして、遮蔽ベタ膜６６は、遮蔽したい領域に合わせてパターンニングすることにより、選択的に設けることもできる。したがって、この実施形態では、図５Ｂに示すように、第２半導体層５０の第４の面Ｓ４側にセンサ画素アレイ部２Ａ及び周辺部２Ｂに亘って遮蔽ベタ膜６６を設けているが、遮蔽したい領域、例えば周辺部２Ｂに選択的に遮蔽ベタ膜６６を設けることができる。 The opening 66a can be formed by patterning the solid shielding film 66 using well-known photolithography or dry etching techniques. The solid shielding film 66 can also be selectively provided by patterning it to match the area to be shielded. Therefore, in this embodiment, as shown in FIG. 5B, the solid shielding film 66 is provided on the fourth surface S4 side of the second semiconductor layer 50 across the sensor pixel array portion 2A and the peripheral portion 2B, but the solid shielding film 66 can be selectively provided in the area to be shielded, for example, the peripheral portion 2B.
　≪実施形態の主な効果≫
　次に、この第１実施形態の主な効果について説明する。
　第２半導体層５０には、画素回路１５やロジック回路１３を構成するトランジスタＴ１が設けられている。一方、第３半導体層８０にもロジック回路１３を構成するトランジスタＴ２が設けられている。そして、この実施形態では、下段の第３半導体層８０と中段の第２半導体層５０との間に遮蔽ベタ膜６６が設けられさている。そして、遮蔽ベタ膜６６は、下段の第３半導体層８０のトランジスタＴ２と、中段の第２半導体層５０のトランジスタＴ１との間に設けられている。このため、トランジスタＴ２の動作時に生じるバンドノイズのトランジスタＴ１への伝播を遮蔽ベタ膜６６で遮蔽することができる。また、その逆で、トランジスタＴ１の動作時に生じるバンドノイズのトランジスタＴ２への伝播を遮蔽ベタ膜６６で遮蔽することができる。即ち、下段の第３半導体層８０のトランジスタＴ２と中段の第２半導体層５０のトランジスタＴ１との間において、一方のトランジスタの動作時のバンドノイズが他方のトランジスタに伝播し、他方のトランジスタの動作に影響するクロストークの発生を抑制することができる。
　また、画素回路１５に含まれる画素トランジスタは、光電変換部２４、転送トランジスタＴＲ及び電荷保持部（ＦＤ）が設けられた第１半導体層２０とは異なる第２半導体層５０に設けられているので、画素回路１５に含まれる画素トランジスタ（ＡＭＰ，ＳＥＬ，ＲＳＴ）の配置自由度を高めることができると共に、同一の半導体層に光電変換部２４、転送トランジスタＴＲ及び電荷保持部（ＦＤ）や画素トランジスタを設けた場合と比較して、より高集積化及びノイズ耐性の向上を図ることが可能である。 <<Main Effects of the Embodiment>>
Next, the main effects of the first embodiment will be described.
The second semiconductor layer 50 is provided with a transistor T1 constituting the pixel circuit 15 and the logic circuit 13. Meanwhile, the third semiconductor layer 80 is also provided with a transistor T2 constituting the logic circuit 13. In this embodiment, a solid shielding film 66 is provided between the lower third semiconductor layer 80 and the middle second semiconductor layer 50. The solid shielding film 66 is provided between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50. For this reason, the solid shielding film 66 can block the propagation of band noise generated during the operation of the transistor T2 to the transistor T1. Conversely, the solid shielding film 66 can block the propagation of band noise generated during the operation of the transistor T1 to the transistor T2. That is, between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, the band noise generated during the operation of one transistor is propagated to the other transistor, and the occurrence of crosstalk affecting the operation of the other transistor can be suppressed.
Furthermore, since the pixel transistors included in the pixel circuit 15 are provided in the second semiconductor layer 50 different from the first semiconductor layer 20 in which the photoelectric conversion unit 24, the transfer transistor TR, and the charge holding unit (FD) are provided, the degree of freedom in arranging the pixel transistors (AMP, SEL, RST) included in the pixel circuit 15 can be increased, and higher integration and improved noise resistance can be achieved compared to a case in which the photoelectric conversion unit 24, the transfer transistor TR, the charge holding unit (FD), and the pixel transistors are provided in the same semiconductor layer.
　図７は、回路ブロックの一例を示す図である。
　この第１実施形態の固体撮像装置１Ａは、例えば図７に示す回路ブロックを含んでいる。図７において、回路ブロック１８ａには論理演算回路が設けられ、回路ブロック１８ｂにはロードＭＯＳトランジスタ回路が設けられ、回路ブロック１８ｃにはコンパレータ回路が設けられ、回路ブロック１８ｄにはカウンタ回路が設けられている。また、回路ブロック１８ｅにはスキャナ回路が設けられ、回路ブロック１８ｆにはＤ／Ｃコンバータが設けられ、回路ブロック１８Ｇにはモバイル・プロセッサ・インターフェイス回路が設けられている。 FIG. 7 is a diagram illustrating an example of a circuit block.
The solid-state imaging device 1A of the first embodiment includes, for example, the circuit blocks shown in Fig. 7. In Fig. 7, a logic operation circuit is provided in a circuit block 18a, a load MOS transistor circuit is provided in a circuit block 18b, a comparator circuit is provided in a circuit block 18c, and a counter circuit is provided in a circuit block 18d. In addition, a scanner circuit is provided in a circuit block 18e, a D/C converter is provided in a circuit block 18f, and a mobile processor interface circuit is provided in a circuit block 18G.
　これらの回路ブロックは、第２半導体層５０のトランジスタＴ１や第３半導体層８０トランジスタＴ２で構成される。そして、これらの回路ブロックのうち、回路ブロック１８ａ、１８ｂ、１８ｃ、１８ｆ及び１８Ｇの各々は高速に動作するため、ノイズ源になり易い。したがって、ノイズ源となり易い回路ブロックと平面視で重畳するように遮蔽ベタ膜６６を選択的に設けることにより、下段の第３半導体層８０と中段の第２半導体層５０との間でのクロストークを抑制することができる。この場合、遮蔽ベタ膜６６は、遮蔽したい回路ブロックと平面視で選択的に重畳している。 These circuit blocks are composed of transistor T1 of the second semiconductor layer 50 and transistor T2 of the third semiconductor layer 80. Of these circuit blocks, circuit blocks 18a, 18b, 18c, 18f, and 18G each operate at high speed and are therefore likely to become noise sources. Therefore, by selectively providing a solid shielding film 66 so that it overlaps in a planar view with the circuit blocks that are likely to become noise sources, crosstalk between the third semiconductor layer 80 in the lower stage and the second semiconductor layer 50 in the middle stage can be suppressed. In this case, the solid shielding film 66 selectively overlaps in a planar view with the circuit blocks to be shielded.
　上述したように、図２に示すロジック回路１３はＣＭＯＳ回路で構成されている。ＣＭＯＳ回路の場合、ラッチアップの対策が必要である。一方、トランジスタは動作時にホットキャリア光を発する。このホットキャリア光はラッチアップの発生の要因となることがある。したがって、下段の第３半導体層８０のトランジスタＴ２と、中段の第２半導体層５０のトランジスタＴ１との間に遮蔽ベタ膜６６を設けることにより、トランジスタＴ２及びＴ１が発したホットキャリア光を遮蔽ベタ膜６６で遮蔽することができるため、ホットキャリア光に起因するラッチアップの発生を抑制することができる。 As mentioned above, the logic circuit 13 shown in FIG. 2 is composed of a CMOS circuit. In the case of a CMOS circuit, measures against latch-up are necessary. Meanwhile, transistors emit hot carrier light during operation. This hot carrier light can be a cause of latch-up. Therefore, by providing a solid shielding film 66 between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, the hot carrier light emitted by the transistors T2 and T1 can be blocked by the solid shielding film 66, thereby suppressing the occurrence of latch-up caused by hot carrier light.
　なお、遮蔽ベタ膜６６は、第２半導体層５０の第４の面Ｓ４に直に設けてもよい。この場合、第２半導体層５０は、通常、基準電位が供給されるので、遮蔽ベタ膜６６も第２半導体層５０の基準電位に電位固定される。
　また、図３の画素回路１５に含まれる全ての画素トランジスタを、第１半導体層２０に設けてもよい。
　また、図３では図示しない画素トランジスタを含めて画素回路１５に含まれる画素トランジスタを第１半導体層２０と第２半導体層５０とに適宜分けて配置してもよい。
　また、第１半導体層２０、第２半導体層５０及び第３半導体層８０の少なくとも何れかに、信号処理回路、駆動回路、メモリ回路などを任意に配置してもよい。 The shielding solid film 66 may be provided directly on the fourth surface S4 of the second semiconductor layer 50. In this case, since the second semiconductor layer 50 is usually supplied with a reference potential, the shielding solid film 66 is also fixed to the reference potential of the second semiconductor layer 50.
All of the pixel transistors included in the pixel circuit 15 in FIG.
Furthermore, pixel transistors included in the pixel circuit 15, including pixel transistors not shown in FIG. 3, may be appropriately divided and disposed in the first semiconductor layer 20 and the second semiconductor layer 50.
Furthermore, a signal processing circuit, a driving circuit, a memory circuit, and the like may be arbitrarily disposed in at least one of the first semiconductor layer 20, the second semiconductor layer 50, and the third semiconductor layer 80.
　≪第１実施形態の変形例≫
　上述の第１実施形態では、遮蔽ベタ膜６６と、貫通コンタクト電極５１との間に遮蔽ベタ膜６６と貫通コンタクト電極５１との離間による隙間ができるため、バンドノイズやホットキャリア光などの電磁場が通過する可能性がある。その対策として、図８Ａ及び図８Ｂに示すように、接合パッド６３及び接合パッド７３のうち少なくとも何れか一方を、平面視で遮蔽ベタ膜６６の開口部６６ａの全体と重畳する平面サイズで構成することにより、電磁場が通過しないようにすることができる。図８Ａ及び図８Ｂでは、接合パッド６３及び接合パッド７３の両方を、平面視で遮蔽ベタ膜６６の開口部６６ａの全体と重畳する平面サイズで構成している。 <Modification of the First Embodiment>
In the first embodiment described above, a gap is formed between the shielding solid film 66 and the through contact electrode 51 due to the separation between the shielding solid film 66 and the through contact electrode 51, so that electromagnetic fields such as band noise and hot carrier light may pass through. As a countermeasure, as shown in Figures 8A and 8B, at least one of the bonding pads 63 and 73 is configured to have a planar size that overlaps with the entire opening 66a of the shielding solid film 66 in a planar view, thereby preventing the electromagnetic field from passing through. In Figures 8A and 8B, both the bonding pads 63 and 73 are configured to have a planar size that overlaps with the entire opening 66a of the shielding solid film 66 in a planar view.
　〔第２実施形態〕
　この第２実施形態では、電磁場を遮蔽する遮蔽体として、第１接合パッドと、第２接合パッドとを含む遮蔽構造体について説明する。
　図９は、本技術の第２実施形態に係る固体撮像装置１Ｂの縦断面構造を模式的に示す縦断面図である。
　図１０は、図９の一部を拡大した縦断面図である。
　図１１Ａは、図９に示す遮蔽構造体の縦断面構造を簡略化して示す縦断面図である。
　図１１Ｂは、図９に示す遮蔽構造体の平面パターンを簡略化して示す平面図である。
　図９及び図１０に示すように、この第２実施形態に係る固体撮像装置１Ｂは、基本的に上述の第１実施形態に係る固体撮像装置１Ａと同様の構成になっており、以下の構成が異なっている。 Second Embodiment
In the second embodiment, a shielding structure including a first bonding pad and a second bonding pad as a shield for blocking an electromagnetic field will be described.
FIG. 9 is a longitudinal sectional view that typically illustrates a longitudinal sectional structure of a solid-state imaging device 1B according to the second embodiment of the present technology.
FIG. 10 is an enlarged longitudinal sectional view of a portion of FIG.
FIG. 11A is a vertical cross-sectional view showing, in a simplified form, the vertical cross-sectional structure of the shielding structure shown in FIG.
FIG. 11B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG.
As shown in Figures 9 and 10, the solid-state imaging device 1B according to the second embodiment has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, but differs in the following respects.
　即ち、図９及び図１０に示すように、この第２実施形態に係る固体撮像装置１Ｂは、上述の第１実施形態の図５Ｂに示す遮蔽ベタ膜６６に替えて遮蔽構造体５５Ｂを備えている。その他の構成は、概ね上述の第１実施形態と同様である。遮蔽構造体５５Ｂは、本技術の「遮蔽体」の一具体例に相当する。 That is, as shown in Figs. 9 and 10, the solid-state imaging device 1B according to the second embodiment includes a shielding structure 55B instead of the solid shielding film 66 shown in Fig. 5B of the first embodiment described above. The other configurations are generally similar to those of the first embodiment described above. The shielding structure 55B corresponds to a specific example of a "shield" of the present technology.
　図９及び図１０に示すように、この第２実施形態に係る固体撮像装置１Ｂは、第２半導体層５０と第３半導体層８０との間に遮蔽体としての遮蔽構造体５５Ｂを備えている。 As shown in Figures 9 and 10, the solid-state imaging device 1B according to the second embodiment has a shielding structure 55B between the second semiconductor layer 50 and the third semiconductor layer 80 as a shield.
　図１１Ａ及び図１１Ｂに示すように、遮蔽構造体５５Ｂは、第２半導体層５０と第３半導体層８０との間に設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド６３と、この接合パッド６３の第３半導体層８０側にこの接合パッド６３と接合して設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド７３と、を含む。 As shown in Figures 11A and 11B, the shielding structure 55B includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 and extends linearly in the X direction (first direction) in a planar view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and bonded to the bonding pad 63, and extends linearly in the X direction (first direction) in a planar view.
　図１１Ａ及び図１１Ｂに示すように、遮蔽構造体５５Ｂは、接合パッド６３と、接合パッド７３とが、平面視でＸ方向と交差するＹ方向（第２方向）に相対的に位置をずらした状態で繰り返し配置されている。そして、接合パッド６３の一部と接合パッド７３の一部とが平面視で重畳して接合されている。即ち、遮蔽構造体５５Ｂは、接合パッド６３と接合パッド７３とを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築している。この第２実施形態の遮蔽構造体５５Ｂも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｂも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 11A and 11B, the shielding structure 55B has the bonding pads 63 and 73 repeatedly arranged with their positions relatively shifted in the Y direction (second direction) intersecting the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. That is, the shielding structure 55B combines the bonding pads 63 and 73 to construct a shielding plate that spreads two-dimensionally in a plan view. The shielding structure 55B of the second embodiment is also electrically connected to the wiring to which a potential is applied, like the above-mentioned shielding solid film 66, and the potential is fixed to the potential applied to the wiring. The shielding structure 55B also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　この第２実施形態の遮蔽構造体５５Ｂは、接合パッド６３と接合パッド７３とを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築しているので、下段の第３半導体層８０のトランジスタＴ２と、中段の第２半導体層５０のトランジスタＴ１との間において、一方のトランジスタの動作時のノイズが他方のトランジスタに伝播し、他方のトランジスタの動作に影響するクロストークを抑制することができる。 The shielding structure 55B of the second embodiment is constructed by combining the bonding pads 63 and 73 to form a shielding plate that extends two-dimensionally in a plan view, so that between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, noise generated during operation of one transistor is propagated to the other transistor, and crosstalk that affects the operation of the other transistor can be suppressed.
　したがって、この遮蔽構造体５５Ｂを備えた第２実施形態に係る固体撮像装置１Ｂにおいても、上述の第１実施形態に係る固体撮像装置１Ａと同様の効果が得られる。 Therefore, the solid-state imaging device 1B according to the second embodiment, which is equipped with this shielding structure 55B, also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.
　〔第３実施形態〕
　この第３実施形態では、電磁場を遮蔽する遮蔽体として、第１接合パッドと、第２接合パッドと、第２半導体層を貫通する導体と、を含む遮蔽構造体について説明する。 Third Embodiment
In the third embodiment, a shielding structure including a first bonding pad, a second bonding pad, and a conductor penetrating the second semiconductor layer as a shield for shielding an electromagnetic field will be described.
　図１２Ａは、本技術の第３実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を簡略化して示す縦断面図である。 FIG. 12A is a simplified vertical cross-sectional view showing the vertical cross-sectional structure of a shielding structure mounted on a solid-state imaging device according to a third embodiment of the present technology.
　図１２Ｂは、図１２Ａの遮蔽構造体の平面パターンを簡略化して示す平面図である。 FIG. 12B is a simplified plan view showing the planar pattern of the shielding structure of FIG. 12A.
　この第３実施形態に係る固体撮像装置１Ｃは、上述の第２実施形態の図９に示す遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｃを備えている。その他の構成は、上述の第１実施形態と概ね同様である。 The solid-state imaging device 1C according to the third embodiment has a shielding structure 55C instead of the shielding structure 55B shown in FIG. 9 of the second embodiment described above. The other configurations are generally similar to those of the first embodiment described above.
　図示していないが、図１０を参照して説明すれば、この第３実施形態に係る固体撮像装置１Ｃは、上述の第２実施形態と同様に、第２半導体層５０と第３半導体層８０との間に、遮蔽体として遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｃを備えている。この第３実施形態の遮蔽構造体５５Ｃは、本技術の「遮蔽体」の一具体例に相当する。 Although not shown, referring to FIG. 10, the solid-state imaging device 1C according to the third embodiment has a shielding structure 55C between the second semiconductor layer 50 and the third semiconductor layer 80 as a shielding body instead of the shielding structure 55B, as in the second embodiment described above. The shielding structure 55C of the third embodiment corresponds to a specific example of the "shield" of the present technology.
　図１２Ａ及び図１２Ｂに示すように、遮蔽構造体５５Ｃは、第２半導体層５０と第３半導体層８０（図１０参照）との間に設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド６３と、この接合パッド６３の第３半導体層８０側にこの接合パッド６３と接合して設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド７３と、を含む。そして、遮蔽構造体５５Ｃは、上述の第２実施形態の遮蔽構造体５５Ｂとは異なり、第２半導体層５０の厚さ方向（Ｚ方向）に貫通し、かつ平面視で接合パッド６３と重畳し、かつＸ方向に直線状に延伸する導体５２を更に含む。この導体５２は、貫通コンタクト電極５１と同一工程で形成することができる。この導体５２は、本技術の「導体」の一具体例に相当する。 12A and 12B, the shielding structure 55C includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extends linearly in the X direction (first direction) in a plan view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63 and extends linearly in the X direction (first direction) in a plan view. Unlike the shielding structure 55B of the second embodiment described above, the shielding structure 55C further includes a conductor 52 that penetrates the second semiconductor layer 50 in the thickness direction (Z direction), overlaps with the bonding pad 63 in a plan view, and extends linearly in the X direction. The conductor 52 can be formed in the same process as the through contact electrode 51. The conductor 52 corresponds to a specific example of a "conductor" of the present technology.
　図１２Ａ及び図１２Ｂに示すように、遮蔽構造体５５Ｃは、接合パッド６３と、接合パッド７３とが、平面視でＸ方向と交差するＹ方向（第２方向）に相対的に位置をずらした状態で繰り返し配置されている。そして、接合パッド６３の一部と接合パッド７３の一部とが平面視で重畳して接合されている。即ち、遮蔽構造体５５Ｃにおいても、接合パッド６３と接合パッド７３とを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築している。この第３実施形態の遮蔽構造体５５Ｃも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｃも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 As shown in Figures 12A and 12B, in the shielding structure 55C, the bonding pads 63 and the bonding pads 73 are repeatedly arranged with their positions relatively shifted in the Y direction (second direction) that intersects with the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. That is, in the shielding structure 55C, the bonding pads 63 and the bonding pads 73 are combined to construct a shielding plate that spreads two-dimensionally in a plan view. Like the above-mentioned shielding solid film 66, the shielding structure 55C of the third embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to the wiring. And, in the second semiconductor layer 50 and the third semiconductor layer 80, this shielding structure 55C also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer.
　導体５２は、接合パッド６３にコンタクト電極を介して電気的に接続されている。そして、導体５２は、これに限定されないが、Ｙ方向に繰り返し配置された複数の接合パッド６３のうち、初段に配置された接合パッド６３と平面視で重畳する位置に配置されている共に、最終段に配置された接合パッド６３と平面視で重畳する位置に配置されている。 The conductor 52 is electrically connected to the bonding pad 63 via a contact electrode. Although not limited to this, the conductor 52 is arranged in a position overlapping in plan view with the bonding pad 63 arranged in the first row of the multiple bonding pads 63 arranged repeatedly in the Y direction, and is also arranged in a position overlapping in plan view with the bonding pad 63 arranged in the final row.
　この第３実施形態の遮蔽構造体５５Ｃは、接合パッド６３と接合パッド７３とを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築しているので、下段の第３半導体層８０のトランジスタＴ２と、中段の第２半導体層５０のトランジスタＴ１との間において、一方のトランジスタの動作時のノイズが他方のトランジスタに伝播し、他方のトランジスタの動作に影響するクロストークを抑制することができる。 The shielding structure 55C of the third embodiment combines the bonding pads 63 and 73 to construct a shielding plate that extends two-dimensionally in a plan view, so that between the transistor T2 of the lower third semiconductor layer 80 and the transistor T1 of the middle second semiconductor layer 50, noise generated during operation of one transistor is propagated to the other transistor, and crosstalk that affects the operation of the other transistor can be suppressed.
　また、この実施形態の遮蔽構造体５５Ｃは、第２半導体層５０を貫通する導体５２を備えているので、上述の第２実施形態の遮蔽構造体５５Ｂと比較して遮蔽効率を高めることができる。 In addition, the shielding structure 55C of this embodiment has a conductor 52 that penetrates the second semiconductor layer 50, so the shielding efficiency can be improved compared to the shielding structure 55B of the second embodiment described above.
　したがって、この実施形態に係る固体撮像装置１Ｃによれば、クロストークをより一層に抑制することができる。 Therefore, the solid-state imaging device 1C according to this embodiment can further suppress crosstalk.
　≪第３実施形態の変形例≫
　上述の第３実施形態では、Ｘ方向に延伸する導体５２を含む遮蔽構造体５５Ｃについて説明した。しかしながら、本技術はＸ方向に延伸する導体５２に限定されるものではない。 <Modification of the third embodiment>
In the above-described third embodiment, the shielding structure 55C including the conductor 52 extending in the X direction has been described. However, the present technology is not limited to the conductor 52 extending in the X direction.
　例えば、図１３に示すように、遮蔽構造体として、Ｘ方向に延伸する導体５２に替えて、導体５２と同様に第２半導体層５０を厚さ方向（Ｚ方向）に貫通し、かつ平面視で接合パッド６３と重畳し、かつＸ方向にドット状に複数点在する導体５３を含む構成としてもよい。この場合、導体５３の平面形状は円形状又は方形状でもよい。そして、この場合、導体５３を直線状に一列で配置するよりも千鳥状に配置にすることで、平面方向の遮蔽効率をより高めることができる。この導体５３は、貫通コンタクト電極５１と同一工程で形成することができる。この導体５３は、本技術の「導体」の一具体例に相当する。 For example, as shown in FIG. 13, instead of the conductor 52 extending in the X direction, the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap the bonding pads 63 in a plan view, and are dot-like in the X direction. In this case, the planar shape of the conductors 53 may be circular or rectangular. In this case, the shielding efficiency in the planar direction can be further improved by arranging the conductors 53 in a staggered manner rather than arranging them in a linear row. The conductors 53 can be formed in the same process as the through contact electrodes 51. The conductors 53 correspond to a specific example of a "conductor" in the present technology.
　〔第４実施形態〕
　図１４Ａは、本技術の第４実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を簡略化して示す縦断面図である。
　図１４Ｂは、図１４Ａに示す遮蔽構造体の平面パターンを簡略化して示す平面図である。 Fourth Embodiment
FIG. 14A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a fourth embodiment of the present technology.
FIG. 14B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 14A.
　この第４実施形態に係る固体撮像装置１Ｄは、上述の第２実施形態の図１１Ａ及び図１１Ｂに示す遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｄを備えている。その他の構成は、上述の第１実施形態と概ね同様である。 The solid-state imaging device 1D according to the fourth embodiment has a shielding structure 55D instead of the shielding structure 55B shown in FIGS. 11A and 11B of the second embodiment described above. The other configurations are generally similar to those of the first embodiment described above.
　図１０を参照して説明すれば、この第４実施形態に係る固体撮像装置１Ｄは、上述の第２実施形態と同様に、第２半導体層５０と第３半導体層８０との間に、遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｄを備えている。この第４実施形態の遮蔽構造体５５Ｄは、本技術の「遮蔽体」の一具体例に相当する。 Explaining with reference to FIG. 10, the solid-state imaging device 1D according to the fourth embodiment includes a shielding structure 55D between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B, as in the second embodiment described above. The shielding structure 55D of the fourth embodiment corresponds to a specific example of the "shield" of the present technology.
　図１４Ａ及び図１４Ｂに示すように、遮蔽構造体５５Ｄは、第２半導体層５０と第３半導体層８０（図１０参照）との間に設けられ、かつ平面視でＸ方向（第１方向）に延伸する接合パッド６３と、この接合パッド６３の第３半導体層８０側にこの接合パッド６３と接合して設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド７３と、を含む。そして、遮蔽構造体５５Ｄは、上述の第２実施形態の遮蔽構造体５５Ｂとは異なり、第２半導体層５０を厚さ方向（Ｚ方向）に貫通し、かつ平面視で接合パッド６３と重畳し、かつＸ方向にドット状に複数点在する導体５３を更に含む。 14A and 14B, the shielding structure 55D includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extends in the X direction (first direction) in a plan view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63 and extends linearly in the X direction (first direction) in a plan view. Unlike the shielding structure 55B of the second embodiment described above, the shielding structure 55D further includes conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction), overlap the bonding pad 63 in a plan view, and are dot-like in the X direction.
　遮蔽構造体５５Ｄは、接合パッド６３と、接合パッド７３とが、平面視でＸ方向と交差するＹ方向（第２方向）に相対的に位置をずらした状態で繰り返し配置されている。そして、接合パッド６３の一部と接合パッド７３の一部とが平面視で重畳して接合されている。即ち、遮蔽構造体５５Ｄにおいても、接合パッド６３と接合パッド７３とを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築している。この第４実施形態の遮蔽構造体５５Ｄも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｄも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 In the shielding structure 55D, the bonding pads 63 and the bonding pads 73 are repeatedly arranged with their positions relatively shifted in the Y direction (second direction) that intersects with the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. That is, in the shielding structure 55D, the bonding pads 63 and the bonding pads 73 are combined to construct a shielding plate that spreads two-dimensionally in a plan view. Like the above-mentioned solid shielding film 66, the shielding structure 55D of the fourth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to the wiring. The shielding structure 55D also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　導体５３は、接合パッド６３にコンタクト電極を介して電気的に接続されている。そして、導体５３は、これに限定されないが、Ｙ方向に繰り返し配置された複数の接合パッド６３毎に、Ｘ方向においてドット状に複数点在している。 The conductors 53 are electrically connected to the bonding pads 63 via contact electrodes. Although not limited to this, the conductors 53 are dot-like in the X direction for each of the bonding pads 63 that are repeatedly arranged in the Y direction.
　この第４実施形態に係る固体撮像装置１Ｄにおいても、上述の第３実施形態に係る固体撮像装置１Ｃと同様の効果が得られる。 The solid-state imaging device 1D according to the fourth embodiment also provides the same effects as the solid-state imaging device 1C according to the third embodiment described above.
　≪第４実施形態の変形例≫
　上述の第４実施形態では、遮蔽構造体に含まれる導体として、Ｘ方向に複数点在する導体５３について説明した。しかしながら、本技術はＸ方向に複数点在する導体５３に限定されるものではない。 <Modification of the Fourth Embodiment>
In the above-described fourth embodiment, the conductors 53 that are scattered in the X direction have been described as the conductors included in the shielding structure. However, the present technology is not limited to the conductors 53 that are scattered in the X direction.
　例えば、図１５に示すように、Ｘ方向に直線状に延伸する導体５２と、Ｘ方向にドット状に複数点在する導体５３とを組み合わせてもよい。この場合においても、上述の第１実施形態と同様の効果が得られる。この場合、導体５２が本技術の「第１導体」の一具体例に相当し、導体５３が本技術の「第２導体」の一具体例に相当する。 For example, as shown in FIG. 15, a conductor 52 extending linearly in the X direction may be combined with multiple conductors 53 scattered in a dot pattern in the X direction. In this case, the same effect as in the first embodiment described above can be obtained. In this case, the conductor 52 corresponds to a specific example of the "first conductor" of the present technology, and the conductor 53 corresponds to a specific example of the "second conductor" of the present technology.
　〔第５実施形態〕
　図１６Ａは、本技術の第５実施形態に係る固体撮像装置に搭載された遮蔽構造体の一構成例を簡略化して示す縦断面図である。
　図１６Ｂは、図１６Ａに示す遮蔽構造体の平面パターンを簡略化して示す平面図である。 Fifth Embodiment
FIG. 16A is a longitudinal sectional view showing, in a simplified form, a configuration example of a shielding structure mounted on a solid-state imaging device according to a fifth embodiment of the present technology. FIG.
FIG. 16B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 16A.
　この第５実施形態に係る固体撮像装置１Ｅは、上述の第２実施形態の図１０に示す遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｅを備えている。その他の構成は、上述の第１実施形態と概ね同様である。 The solid-state imaging device 1E according to the fifth embodiment includes a shielding structure 55E instead of the shielding structure 55B shown in FIG. 10 of the second embodiment described above. The other configurations are generally similar to those of the first embodiment described above.
　図示していないが、図１０を参照して説明すれば、この第５実施形態に係る固体撮像装置１Ｅは、上述の第２実施形態と同様に、第２半導体層５０と第３半導体層８０との間に遮蔽体としての遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｅを備えている。遮蔽構造体５５Ｅは、本技術の「遮蔽体」の一具体例に相当する。 Although not shown, referring to FIG. 10, the solid-state imaging device 1E according to the fifth embodiment has a shielding structure 55E between the second semiconductor layer 50 and the third semiconductor layer 80 instead of the shielding structure 55B as a shield, as in the second embodiment described above. The shielding structure 55E corresponds to a specific example of a "shield" of the present technology.
　図１６Ａ及び図１６Ｂに示すように、遮蔽構造体５５Ｅは、第２半導体層５０を厚さ方向（Ｚ方向）に貫通し、かつ平面視でＸ方向に直線状に延伸する導体５２と、第２半導体層５０と第３半導体層８０（図１０参照）との間に設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド６３と、この接合パッド６３の第３半導体層８０側にこの接合パッド６３と接合して設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド７３と、を含む。 As shown in Figures 16A and 16B, the shielding structure 55E includes a conductor 52 that penetrates the second semiconductor layer 50 in the thickness direction (Z direction) and extends linearly in the X direction in a planar view, a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see Figure 10) and extends linearly in the X direction (first direction) in a planar view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63, and extends linearly in the X direction (first direction) in a planar view.
　遮蔽構造体５５Ｅは、導体５２と、接合パッド６３と、接合パッド７３とが、平面視でＸ方向と交差するＹ方向に相対的に位置をずらした状態で繰り返し配置されている。そして、接合パッド６３の一部と接合パッド７３の一部とが平面視で重畳して接合されている。そして、平面視で接合パッド６３と接合パッド７３との間に、接合パッド６３及び７３の各々の一部と重畳して配置されている。即ち、遮蔽構造体５５Ｅは、導体５２と、接合パッド６３と、接合パッド７３とを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築している。導体５２は、接合パッド６３及び７３の各々から離間している。この第５実施形態の遮蔽構造体５５Ｅも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｅも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 In the shielding structure 55E, the conductor 52, the bonding pad 63, and the bonding pad 73 are repeatedly arranged with their positions relatively shifted in the Y direction intersecting the X direction in a plan view. A part of the bonding pad 63 and a part of the bonding pad 73 are joined in an overlapping manner in a plan view. In a plan view, the bonding pad 63 and the bonding pad 73 are arranged between the bonding pad 63 and the bonding pad 73, overlapping with each part of the bonding pads 63 and 73. In other words, the shielding structure 55E combines the conductor 52, the bonding pad 63, and the bonding pad 73 to construct a shielding plate that spreads two-dimensionally in a plan view. The conductor 52 is spaced from each of the bonding pads 63 and 73. Like the above-mentioned solid shielding film 66, the shielding structure 55E of the fifth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to this wiring. This shielding structure 55E also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　この第５実施形態に係る固体撮像装置１Ｅにおいても、上述の第３実施形態に係る固体撮像装置１Ｃと同様の効果が得られる。 The solid-state imaging device 1E according to the fifth embodiment also provides the same effects as the solid-state imaging device 1C according to the third embodiment described above.
　≪第５実施形態の変形例≫
　上述の第５実施形態では、Ｘ方向に延伸する導体５２を含む遮蔽構造体５５Ｅについて説明した。しかしながら、本技術はＸ方向に延伸する導体５２に限定されるものではない。
　例えば、図１７に示すように、遮蔽構造体として、Ｘ方向に延伸する導体５２に替えて、Ｘ方向にドット状に複数点在する導体５３を含む構成としてもよい。 <Modification of Fifth Embodiment>
In the above-described fifth embodiment, the shielding structure 55E including the conductor 52 extending in the X direction has been described. However, the present technology is not limited to the conductor 52 extending in the X direction.
For example, as shown in FIG. 17, the shielding structure may include a plurality of conductors 53 scattered in a dot pattern in the X direction, instead of the conductors 52 extending in the X direction.
　〔第６実施形態〕
　この第６実施形態では、電磁場を遮蔽する遮蔽体として、第１及び第２接合パッドと、配線とを含む遮蔽構造体について説明する。
　図１８Ａは、本技術の第６実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を簡略化して示す縦断面図である。
　図１８Ｂは、図１８Ａの遮蔽構造体の平面パターンを簡略化して示す平面図である。 Sixth Embodiment
In the sixth embodiment, a shielding structure including first and second bonding pads and wiring as a shield for blocking electromagnetic fields will be described.
FIG. 18A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a sixth embodiment of the present technology.
FIG. 18B is a plan view showing, in a simplified form, the planar pattern of the shielding structure of FIG. 18A.
　この第６実施形態に係る固体撮像装置１Ｆは、上述の第２実施形態の図１０に示す遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｆを備えている。その他の構成は、上述の第１実施形態と概ね同様である。
　図１０を参照して説明すると、この第６実施形態に係る固体撮像装置１Ｆは、上述の第２実施形態と同様に、第２半導体層５０と第３半導体層８０との間に、遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｆを備えている。遮蔽構造体５５Ｆは、本技術の「遮蔽体」の一具体例に相当する。 A solid-state imaging device 1F according to the sixth embodiment includes a shielding structure 55F instead of the shielding structure 55B of the second embodiment shown in Fig. 10. The other configurations are generally similar to those of the first embodiment.
10 , a solid-state imaging device 1F according to the sixth embodiment includes, similarly to the above-described second embodiment, a shielding structure 55F instead of the shielding structure 55B between the second semiconductor layer 50 and the third semiconductor layer 80. The shielding structure 55F corresponds to a specific example of a “shield” of the present technology.
　図１８Ａ及び図１８Ｂに示すように、遮蔽構造体５５Ｆは、第２半導体層５０と第３半導体層８０（図１０参照）との間に設けられ、かつ平面視でＸ方向（第１方向）に直線状に延伸する接合パッド６３と、この接合パッド６３の第３半導体層８０側に接合パッド６３と接合して設けられ、かつ平面視でＸ方向に直線状に延伸する接合パッド７３と、を含む。また、遮蔽構造体５５Ｆは、接合パッド７３第３半導体層８０側に設けられ、かつ平面視でＸ方向に直線状に延伸する配線７２ａを更に含む。この配線７２ａは、第４配線層７０に設けられ、接合パッド７３よりも第３半導体層８０側に設けられている。 18A and 18B, the shielding structure 55F includes a bonding pad 63 that is provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extends linearly in the X direction (first direction) in a plan view, and a bonding pad 73 that is provided on the third semiconductor layer 80 side of the bonding pad 63 and is bonded to the bonding pad 63 and extends linearly in the X direction in a plan view. The shielding structure 55F also includes a wiring 72a that is provided on the third semiconductor layer 80 side of the bonding pad 73 and extends linearly in the X direction in a plan view. The wiring 72a is provided in the fourth wiring layer 70 and is provided closer to the third semiconductor layer 80 than the bonding pad 73.
　遮蔽構造体５５Ｆは、接合パッド６３及び７３と、配線７２ａとが平面視でＸ方向と交差するＹ方向（第２方向）に相対的に位置をずらした状態で繰り返し配置されている。そして、接合パッド６３と接合パッド７３とが平面視で重畳して接合されている。そして、配線７２ａが平面視で接合パッド６３と接合パッド６３との間に各々の一部と重畳して配置されている。即ち、遮蔽構造体５５Ｆは、接合パッド６３及び７３と、配線７２ａとを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築している。この第６実施形態の遮蔽構造体５５Ｆも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｆも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 In the shielding structure 55F, the bonding pads 63 and 73 and the wiring 72a are repeatedly arranged with their positions relatively shifted in the Y direction (second direction) intersecting the X direction in a plan view. The bonding pads 63 and 73 are joined in an overlapping manner in a plan view. The wiring 72a is arranged between the bonding pads 63 and 63 in a plan view, overlapping with a part of each. That is, the shielding structure 55F combines the bonding pads 63 and 73 with the wiring 72a to construct a shielding plate that spreads two-dimensionally in a plan view. Like the above-mentioned solid shielding film 66, the shielding structure 55F of the sixth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to the wiring. The shielding structure 55F also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　この第６実施形態に係る固体撮像装置１Ｆにおいても、上述の第２実施形態に係る固体撮像装置１Ｂと同様の効果が得られる。 The solid-state imaging device 1F according to the sixth embodiment also provides the same effects as the solid-state imaging device 1B according to the second embodiment described above.
　〔第７実施形態〕
　図１９Ａは、本技術の第７実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を簡略化して示す縦断面図である。
　図１９Ｂは、図１９Ａに示す遮蔽構造体の平面パターンを簡略化して示す平面図である。
　この第７実施形態に係る固体撮像装置１Ｇは、上述の第２実施形態の図１０に示す遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｇを備えている。その他の構成は、上述の第１実施形態と概ね同様である。 Seventh Embodiment
FIG. 19A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a seventh embodiment of the present technology. FIG.
FIG. 19B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 19A.
A solid-state imaging device 1G according to the seventh embodiment includes a shielding structure 55G instead of the shielding structure 55B of the second embodiment shown in Fig. 10. The other configurations are generally similar to those of the first embodiment.
　図１０を参照して説明すれば、この第７実施形態に係る固体撮像装置１Ｇは、上述の第２実施形態と同様に、第２半導体層５０と第３半導体層８０との間に、遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｇを備えている。この第７実施形態の遮蔽構造体５５Ｇは、本技術の「遮蔽体」の一具体例に相当する。 Referring to FIG. 10, the solid-state imaging device 1G according to the seventh embodiment includes a shielding structure 55G between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B, as in the second embodiment described above. The shielding structure 55G of the seventh embodiment corresponds to a specific example of the "shield" of the present technology.
　図１９Ａ及び図１９Ｂに示すように、遮蔽構造体５５Ｇは、上述の第６実施形態の遮蔽構造体５５Ｆに導体５２を組み込んだ構成になっている。導体５２は、接合パッド６３にコンタクト電極を介して電気的に接続されている。そして、導体５２は、これに限定されないが、Ｙ方向に繰り返し配置された複数の接合パッド６３のうち、初段に配置された接合パッド６３と平面視で重畳する位置に配置されている共に、最終段に配置された接合パッド６３と平面視で重畳する位置に配置されている。そして、接合パッド７３は、コンタクト電極を介して下層の配線７２ａと電気的に接続されている。この第７実施形態の遮蔽構造体５５Ｇも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｇも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 19A and 19B, the shielding structure 55G is configured by incorporating a conductor 52 into the shielding structure 55F of the sixth embodiment described above. The conductor 52 is electrically connected to the bonding pad 63 via a contact electrode. The conductor 52 is arranged, but is not limited to, at a position overlapping the bonding pad 63 arranged in the first row of the multiple bonding pads 63 repeatedly arranged in the Y direction in a planar view, and is also arranged at a position overlapping the bonding pad 63 arranged in the last row in a planar view. The bonding pad 73 is electrically connected to the wiring 72a in the lower layer via a contact electrode. The shielding structure 55G of the seventh embodiment is also electrically connected to the wiring to which a potential is applied, like the shielding solid film 66 described above, and the potential is fixed to the potential applied to the wiring. The shielding structure 55G also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　この第７実施形態に係る固体撮像装置１Ｇにおいても、上述の第３実施形態に係る固体撮像装置１Ｃと同様の効果が得られる。 The solid-state imaging device 1G according to the seventh embodiment also provides the same effects as the solid-state imaging device 1C according to the third embodiment described above.
　≪第７実施形態の変形例≫
　上述の第７実施形態では、Ｘ方向に延伸する導体５２を含む遮蔽構造体５５Ｇについて説明した。しかしながら、本技術はＸ方向に延伸する導体５２に限定されるものではない。 <Modification of Seventh Embodiment>
In the seventh embodiment described above, the shielding structure 55G including the conductor 52 extending in the X direction has been described. However, the present technology is not limited to the conductor 52 extending in the X direction.
　例えば、図２０に示すように、遮蔽構造体として、Ｘ方向に延伸する導体５２に替えて、導体５２と同様に第２半導体層５０を厚さ方向（Ｚ方向）に貫通し、かつ平面視で接合パッド６３と重畳し、かつＸ方向にドット状に複数点在する導体５３を含む構成としてもよい。この場合、導体５３の平面形状は円形状又は方形状でもよい。そして、この場合、導体５３を直線状に一列で配置するよりも千鳥状に配置にすることで、平面方向の遮蔽効率をより高めることができる。 For example, as shown in FIG. 20, instead of the conductor 52 extending in the X direction, the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap with the bonding pads 63 in a planar view, and are dot-like in the X direction. In this case, the planar shape of the conductors 53 may be circular or square. In this case, by arranging the conductors 53 in a staggered pattern rather than arranging them in a straight line, the shielding efficiency in the planar direction can be further improved.
　〔第８実施形態〕
　図２１Ａは、本技術の第８実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を簡略化して示す縦断面図である。
　図２１Ｂは、図２１Ａに示す遮蔽構造体の平面パターンを簡略化して示す平面図である。 Eighth embodiment
FIG. 21A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to an eighth embodiment of the present technology. FIG.
FIG. 21B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 21A.
　この第８実施形態に係る固体撮像装置１Ｈは、上述の第２実施形態の図１０に示す遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｈを備えている。その他の構成は、上述の第１実施形態と概ね同様である。 The solid-state imaging device 1H according to the eighth embodiment includes a shielding structure 55H instead of the shielding structure 55B shown in FIG. 10 of the second embodiment described above. The other configurations are generally similar to those of the first embodiment described above.
　図１０を参照して説明すれば、この第８実施形態に係る固体撮像装置５５Ｈは、上述の第２実施形態と同様に、第２半導体層５０と第３半導体層８０との間に、遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｈを備えている。この第８実施形態の遮蔽構造体５５Ｈは、本技術の「遮蔽体」の一具体例に相当する。 Explaining with reference to FIG. 10, the solid-state imaging device 55H according to the eighth embodiment includes a shielding structure 55H between the second semiconductor layer 50 and the third semiconductor layer 80 in place of the shielding structure 55B, as in the second embodiment described above. The shielding structure 55H of the eighth embodiment corresponds to a specific example of the "shield" of the present technology.
　図２１Ａ及び図２１Ｂに示すように、遮蔽構造体５５Ｈは、基本的に上述の第７実施形態の遮蔽構造体５５Ｇと同様の構成になっている。遮蔽構造体１Ｈと１Ｇとの違いは、導体５２が接合パッド６３毎に設けられている点である。この第８実施形態の遮蔽構造体５５Ｈも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｈも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 As shown in Figures 21A and 21B, the shielding structure 55H is basically configured in the same manner as the shielding structure 55G of the seventh embodiment described above. The difference between the shielding structures 1H and 1G is that a conductor 52 is provided for each bonding pad 63. Like the solid shielding film 66 described above, the shielding structure 55H of the eighth embodiment is also electrically connected to a wiring to which a potential is applied, and the potential is fixed to the potential applied to this wiring. The shielding structure 55H also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　この第８実施形態にかかる固体撮像装置１Ｈにおいても、上述の第４実施形態に係る固体撮像装置１Ｄと同様の効果が得られる。 The solid-state imaging device 1H according to the eighth embodiment also provides the same effects as the solid-state imaging device 1D according to the fourth embodiment described above.
　≪第８実施形態の変形例≫
　上述の第８実施形態では、Ｘ方向に延伸する導体５２を含む遮蔽構造体５５Ｈについて説明した。しかしながら、本技術はＸ方向に延伸する導体５２に限定されるものではない。 <Modification of Eighth Embodiment>
In the above-described eighth embodiment, the shielding structure 55H including the conductor 52 extending in the X direction has been described. However, the present technology is not limited to the conductor 52 extending in the X direction.
　例えば、図２２に示すように、遮蔽構造体として、Ｘ方向に延伸する導体５２に替えて、導体５２と同様に第２半導体層５０を厚さ方向（Ｚ方向）に貫通し、かつ平面視で接合パッド６３と重畳し、かつＸ方向にドット状に複数点在する導体５３を含む構成としてもよい。この場合、導体５３の平面形状は円形状又は方形状でもよい。そして、この変形例では、導体５３を直線状に一列で配置しているが、千鳥状に配置してもよい。 For example, as shown in FIG. 22, instead of the conductor 52 extending in the X direction, the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap the bonding pads 63 in a plan view, and are dot-like in the X direction. In this case, the planar shape of the conductors 53 may be circular or square. And, although the conductors 53 are arranged in a linear row in this modified example, they may also be arranged in a staggered pattern.
　〔第９実施形態〕
　図２３Ａは、本技術の第９実施形態に係る固体撮像装置に搭載された遮蔽構造体の縦断面構造を簡略化して示す縦断面図である。
　図２３Ｂは、図２３Ａに示す遮蔽構造体の平面パターンを簡略化して示す平面図である。 Ninth embodiment
FIG. 23A is a longitudinal sectional view showing, in a simplified manner, a longitudinal sectional structure of a shielding structure mounted on a solid-state imaging device according to a ninth embodiment of the present technology. FIG.
FIG. 23B is a plan view showing, in a simplified form, the planar pattern of the shielding structure shown in FIG. 23A.
　この第９実施形態に係る固体撮像装置１Ｉは、上述の第２実施形態の図１０に示す遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｉを備えている。その他の構成は、上述の第１実施形態と概ね同様である。 The solid-state imaging device 1I according to the ninth embodiment includes a shielding structure 55I instead of the shielding structure 55B shown in FIG. 10 of the second embodiment described above. The other configurations are generally similar to those of the first embodiment described above.
　図１０を参照して説明すれば、この第９実施形態に係る固体撮像装置１Ｉは、上述の第２実施形態と同様に、第２半導体層５０と第３半導体層８０との間に、遮蔽構造体５５Ｂに替えて遮蔽構造体５５Ｉを備えている。この第９実施形態の遮蔽構造体５５Ｉは、本技術の「遮蔽体」の一具体例に相当する。 Referring to FIG. 10, the solid-state imaging device 1I according to the ninth embodiment includes a shielding structure 55I between the second semiconductor layer 50 and the third semiconductor layer 80 instead of the shielding structure 55B, as in the second embodiment described above. The shielding structure 55I of the ninth embodiment corresponds to a specific example of the "shield" of the present technology.
　図２３Ａ及び図２３Ｂに示すように、遮蔽構造体５５Ｉは、第２半導体層５０を厚さ方向に貫通する導体５２と、第２半導体層５０と第３半導体層８０（図１０参照）との間に設けられ、かつ平面視でＸ方向に直線状に延伸する接合パッド６３と、この接合パッド６３の３半導体層８０側に接合パッド６３と接合して設けられ、かつ平面視でＸ方向に直線状に延伸する接合パッド７３と、接合パッド７３よりも第３半導体層８０側に設けられ、かつ平面視でＸ方向に直線状に延伸する配線７２ａと、を含む。そして、遮蔽構造体５５Ｉは、導体５２と、接合パッド６３と、接合パッド７３と、配線７２ａとが、平面視でＸ方向と交差するＹ方向に相対的に位置をずらした状態で繰り返し配置されている。 23A and 23B, the shielding structure 55I includes a conductor 52 penetrating the second semiconductor layer 50 in the thickness direction, a bonding pad 63 provided between the second semiconductor layer 50 and the third semiconductor layer 80 (see FIG. 10) and extending linearly in the X direction in a plan view, a bonding pad 73 provided on the third semiconductor layer 80 side of the bonding pad 63 and bonded to the bonding pad 63, and extending linearly in the X direction in a plan view, and a wiring 72a provided on the third semiconductor layer 80 side of the bonding pad 73 and extending linearly in the X direction in a plan view. In the shielding structure 55I, the conductor 52, the bonding pad 63, the bonding pad 73, and the wiring 72a are repeatedly arranged with their positions relatively shifted in the Y direction that intersects with the X direction in a plan view.
　接合パッド６３と接合パッド７３とは、平面視で各々の一部が重畳して互いに接合されている。配線７２ａは、平面視で互いに隣り合う接合パッド６３と７３との間に、接合パッド６３及び７３の各々の一部と重畳して配置されている。導体５２は、平面視で互いに隣り合う接合パッド６３と７３との間に、接合パッド６３及び７３の各々の一部と重畳して配置されている。そして、配線７２ａと導体５２とは、平面視でＹ方向に交互に配置されている。この遮蔽構造体５５Ｉにおいても、導体５２と、接合パッド６３と、接合パッド７３とを組み合わせて平面視で二次元状に広がる遮蔽プレートを構築している。そして、この第９実施形態の遮蔽構造体５５Ｉも、上述の遮蔽ベタ膜６６と同様に、電位が印加される配線と電気的に接続され、この配線に印加される電位に電位固定される。そして、この遮蔽構造体５５Ｉも、第２半導体層５０及び第３半導体層８０において、一方の半導体層から他方の半導体層へ伝播する電磁場を抑制する。 The bonding pads 63 and 73 are joined together with parts of each overlapping in a plan view. The wiring 72a is arranged between the bonding pads 63 and 73 adjacent to each other in a plan view, overlapping with parts of each of the bonding pads 63 and 73. The conductor 52 is arranged between the bonding pads 63 and 73 adjacent to each other in a plan view, overlapping with parts of each of the bonding pads 63 and 73. The wiring 72a and the conductor 52 are arranged alternately in the Y direction in a plan view. In this shielding structure 55I, the conductor 52, the bonding pad 63, and the bonding pad 73 are combined to construct a shielding plate that spreads two-dimensionally in a plan view. And, like the above-mentioned solid shielding film 66, the shielding structure 55I of the ninth embodiment is also electrically connected to the wiring to which a potential is applied, and the potential is fixed to the potential applied to this wiring. This shielding structure 55I also suppresses the electromagnetic field propagating from one semiconductor layer to the other semiconductor layer in the second semiconductor layer 50 and the third semiconductor layer 80.
　導体５２及び配線７２ａの各々は、接合パッド６３及び７３の各々から離間し、コンタクト電極を介した接合パッド６３及び７３との電気的な接続は行っていない。 The conductor 52 and the wiring 72a are spaced apart from the bonding pads 63 and 73, respectively, and are not electrically connected to the bonding pads 63 and 73 via contact electrodes.
　この第９実施形態にかかる固体撮像装置１Ｉにおいても、上述の第４実施形態に係る固体撮像装置１Ｄと同様の効果が得られる。 The solid-state imaging device 1I according to the ninth embodiment also provides the same effects as the solid-state imaging device 1D according to the fourth embodiment described above.
　≪第９実施形態の変形例≫
　上述の第９実施形態では、Ｘ方向に延伸する導体５２を含む遮蔽構造体５５Ｉについて説明した。しかしながら、本技術はＸ方向に延伸する導体５２に限定されるものではない。 <Modification of the ninth embodiment>
In the above-described ninth embodiment, the shielding structure 55I including the conductor 52 extending in the X direction has been described. However, the present technology is not limited to the conductor 52 extending in the X direction.
　例えば、図２４に示すように、遮蔽構造体として、Ｘ方向に延伸する導体５２に替えて、導体５２と同様に第２半導体層５０を厚さ方向（Ｚ方向）に貫通し、かつ平面視で接合パッド６３と重畳し、かつＸ方向にドット状に複数点在する導体５３を含む構成としてもよい。この場合、導体５３の平面形状は円形状又は方形状でもよい。そして、この変形例では、導体５３を直線状に一列で配置しているが、千鳥状に配置してもよい。 For example, as shown in FIG. 24, instead of the conductor 52 extending in the X direction, the shielding structure may include conductors 53 that penetrate the second semiconductor layer 50 in the thickness direction (Z direction) like the conductor 52, overlap the bonding pads 63 in a plan view, and are dot-like in the X direction. In this case, the planar shape of the conductors 53 may be circular or square. And, although the conductors 53 are arranged in a linear row in this modification, they may also be arranged in a staggered pattern.
　〔第１０実施形態〕
　＜１．電子機器への応用例＞
　次に、図２５に示す本技術の第１０実施形態に係る電子機器１００について説明する。電子機器１００は、固体撮像装置１０１と、光学レンズ１０２と、シャッタ装置１０３と、駆動回路１０４と、信号処理回路１０５とを備えている。電子機器１００は、これに限定されないが、例えば、カメラ等の電子機器である。また、電子機器１００は、固体撮像装置１０１として、上述の固体撮像装置１Ａを備えている。 Tenth Embodiment
<1. Application examples to electronic devices>
Next, an electronic device 100 according to a tenth embodiment of the present technology shown in Fig. 25 will be described. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a driving circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-mentioned solid-state imaging device 1A as the solid-state imaging device 101.
　光学レンズ（光学系）１０２は、被写体からの像光（入射光１０６）を固体撮像装置１０１の撮像面上に結像させる。これにより、固体撮像装置１０１内に一定期間にわたって信号電荷が蓄積される。シャッタ装置１０３は、固体撮像装置１０１への光照射期間及び遮光期間を制御する。駆動回路１０４は、固体撮像装置１０１の転送動作及びシャッタ装置１０３のシャッタ動作を制御する駆動信号を供給する。駆動回路１０４から供給される駆動信号（タイミング信号）により、固体撮像装置１０１の信号転送を行う。信号処理回路１０５は、固体撮像装置１０１から出力される信号（画素信号）に各種信号処理を行う。信号処理が行われた映像信号は、メモリ等の記憶媒体に記憶され、或いはモニタに出力される。 The optical lens (optical system) 102 focuses image light (incident light 106) from the subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period for the solid-state imaging device 101. The drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signal (timing signal) supplied from the drive circuit 104 transfers signals from the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The video signals that have undergone signal processing are stored in a storage medium such as a memory, or output to a monitor.
　このような構成により、電子機器１００では、固体撮像装置１０１としてクロストークが抑制されているため、電子機器１００を信頼性の向上を図ることでできる。 With this configuration, crosstalk is suppressed in the solid-state imaging device 101 of the electronic device 100, which improves the reliability of the electronic device 100.
　なお、電子機器１００は、カメラに限られるものではなく、他の電子機器であっても良い。例えば、携帯電話機等のモバイル機器向けカメラモジュール等の撮像装置であっても良い。 The electronic device 100 is not limited to a camera, but may be other electronic devices. For example, it may be an imaging device such as a camera module for a mobile device such as a mobile phone.
　また、電子機器１００は、固体撮像装置１０１として、第１実施形態及びその変形例のいずれかに係る光検出装置１、又は第１実施形態及びその変形例のうちの少なくとも２つの組み合わせに係る光検出装置１を備えることができる。 The electronic device 100 may also include, as the solid-state imaging device 101, a photodetector 1 according to either the first embodiment or its modified examples, or a photodetector 1 according to a combination of at least two of the first embodiment and its modified examples.
　＜２．移動体への応用例＞ <2. Examples of applications to moving objects>
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the technology disclosed herein may be realized as a device mounted on any type of moving object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.
　図２６は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 26 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図１２に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ（ｉｎｔｅｒｆａｃｅ）１２０５３が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 12, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020. The body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects information inside the vehicle. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ（Ａｄｖａｎｃｅｄ　Ｄｒｉｖｅｒ　Ａｓｓｉｓｔａｎｃｅ　Ｓｙｓｔｅｍ）の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 The microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０２０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 The microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図２６の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information. In the example of FIG. 26, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
　図２７は、撮像部１２０３１の設置位置の例を示す図である。
　図２７では、車両１２１００は、撮像部１２０３１として、撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５を有する。 FIG. 27 is a diagram showing an example of the installation position of the imaging unit 12031.
In FIG. 27 , a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.
　撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２，１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。撮像部１２１０１及び１２１０５で取得される前方の画像は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
　なお、図２７には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 27 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０ｋｍ／ｈ以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the imaging units 12101 to 12104 and recognizes a pedestrian, the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、上述の複数の電子制御ユニット及び撮像部１２０３１に適用され得る。具体的には、上述の第１～第９実施形態の遮蔽体（遮蔽ベタ膜及び遮蔽構造体）は、上述の複数の電子制御ユニット及び撮像部１２０３１に適用することができる。電子制御ユニット及び撮像部１２０３１に本開示に係る技術を適用することにより、クロストークを抑制することができるので、電子制御ユニット及び撮像部１２０３１の信頼性の向上を図ることができる。 Above, an example of a vehicle control system to which the technology disclosed herein can be applied has been described. Of the configurations described above, the technology disclosed herein can be applied to, for example, the multiple electronic control units and imaging unit 12031 described above. Specifically, the shields (solid shielding films and shielding structures) of the first to ninth embodiments described above can be applied to the multiple electronic control units and imaging unit 12031 described above. By applying the technology disclosed herein to the electronic control unit and imaging unit 12031, crosstalk can be suppressed, thereby improving the reliability of the electronic control unit and imaging unit 12031.
　＜３．内視鏡手術システムへの応用例＞
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、内視鏡手術システムに適用されてもよい。 <3. Application example to endoscopic surgery system>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.
　図２８は、本開示に係る技術（本技術）が適用され得る内視鏡手術システムの概略的な構成の一例を示す図である。 FIG. 28 is a diagram showing an example of the general configuration of an endoscopic surgery system to which the technology disclosed herein (the present technology) can be applied.
　図２８では、術者（医師）１１１３１が、内視鏡手術システム１１０００を用いて、患者ベッド１１１３３上の患者１１１３２に手術を行っている様子が図示されている。図示するように、内視鏡手術システム１１０００は、内視鏡１１１００と、気腹チューブ１１１１１やエネルギー処置具１１１１２等の、その他の術具１１１１０と、内視鏡１１１００を支持する支持アーム装置１１１２０と、内視鏡下手術のための各種の装置が搭載されたカート１１２００と、から構成される。 In FIG. 28, an operator (doctor) 11131 is shown using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a patient bed 11133. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.
　内視鏡１１１００は、先端から所定の長さの領域が患者１１１３２の体腔内に挿入される鏡筒１１１０１と、鏡筒１１１０１の基端に接続されるカメラヘッド１１１０２と、から構成される。図示する例では、硬性の鏡筒１１１０１を有するいわゆる硬性鏡として構成される内視鏡１１１００を図示しているが、内視鏡１１１００は、軟性の鏡筒を有するいわゆる軟性鏡として構成されてもよい。 The endoscope 11100 is composed of a lens barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 at a predetermined length, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.
　鏡筒１１１０１の先端には、対物レンズが嵌め込まれた開口部が設けられている。内視鏡１１１００には光源装置１１２０３が接続されており、当該光源装置１１２０３によって生成された光が、鏡筒１１１０１の内部に延設されるライトガイドによって当該鏡筒の先端まで導光され、対物レンズを介して患者１１１３２の体腔内の観察対象に向かって照射される。なお、内視鏡１１１００は、直視鏡であってもよいし、斜視鏡又は側視鏡であってもよい。 The tip of the tube 11101 has an opening into which an objective lens is fitted. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the tube by a light guide extending inside the tube 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.
　カメラヘッド１１１０２の内部には光学系及び撮像素子が設けられており、観察対象からの反射光（観察光）は当該光学系によって当該撮像素子に集光される。当該撮像素子によって観察光が光電変換され、観察光に対応する電気信号、すなわち観察像に対応する画像信号が生成される。当該画像信号は、ＲＡＷデータとしてカメラコントロールユニット（ＣＣＵ：　Ｃａｍｅｒａ　Ｃｏｎｔｒｏｌ　Ｕｎｉｔ）１１２０１に送信される。 An optical system and an image sensor are provided inside the camera head 11102, and the reflected light (observation light) from the object of observation is focused on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to the camera control unit (CCU: Camera Control Unit) 11201 as RAW data.
　ＣＣＵ１１２０１は、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）やＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）等によって構成され、内視鏡１１１００及び表示装置１１２０２の動作を統括的に制御する。さらに、ＣＣＵ１１２０１は、カメラヘッド１１１０２から画像信号を受け取り、その画像信号に対して、例えば現像処理（デモザイク処理）等の、当該画像信号に基づく画像を表示するための各種の画像処理を施す。 The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the overall operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), in order to display an image based on the image signal.
　表示装置１１２０２は、ＣＣＵ１１２０１からの制御により、当該ＣＣＵ１１２０１によって画像処理が施された画像信号に基づく画像を表示する。 The display device 11202, under the control of the CCU 11201, displays an image based on the image signal that has been subjected to image processing by the CCU 11201.
　光源装置１１２０３は、例えばＬＥＤ（Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）等の光源から構成され、術部等を撮影する際の照射光を内視鏡１１１００に供給する。 The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.
　入力装置１１２０４は、内視鏡手術システム１１０００に対する入力インタフェースである。ユーザは、入力装置１１２０４を介して、内視鏡手術システム１１０００に対して各種の情報の入力や指示入力を行うことができる。例えば、ユーザは、内視鏡１１１００による撮像条件（照射光の種類、倍率及び焦点距離等）を変更する旨の指示等を入力する。 The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.
　処置具制御装置１１２０５は、組織の焼灼、切開又は血管の封止等のためのエネルギー処置具１１１１２の駆動を制御する。気腹装置１１２０６は、内視鏡１１１００による視野の確保及び術者の作業空間の確保の目的で、患者１１１３２の体腔を膨らめるために、気腹チューブ１１１１１を介して当該体腔内にガスを送り込む。レコーダ１１２０７は、手術に関する各種の情報を記録可能な装置である。プリンタ１１２０８は、手術に関する各種の情報を、テキスト、画像又はグラフ等各種の形式で印刷可能な装置である。 The treatment tool control device 11205 controls the operation of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity in order to ensure a clear field of view for the endoscope 11100 and to ensure a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.
　なお、内視鏡１１１００に術部を撮影する際の照射光を供給する光源装置１１２０３は、例えばＬＥＤ、レーザ光源又はこれらの組み合わせによって構成される白色光源から構成することができる。ＲＧＢレーザ光源の組み合わせにより白色光源が構成される場合には、各色（各波長）の出力強度及び出力タイミングを高精度に制御することができるため、光源装置１１２０３において撮像画像のホワイトバランスの調整を行うことができる。また、この場合には、ＲＧＢレーザ光源それぞれからのレーザ光を時分割で観察対象に照射し、その照射タイミングに同期してカメラヘッド１１１０２の撮像素子の駆動を制御することにより、ＲＧＢそれぞれに対応した画像を時分割で撮像することも可能である。当該方法によれば、当該撮像素子にカラーフィルタを設けなくても、カラー画像を得ることができる。 The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.
　また、光源装置１１２０３は、出力する光の強度を所定の時間ごとに変更するようにその駆動が制御されてもよい。その光の強度の変更のタイミングに同期してカメラヘッド１１１０２の撮像素子の駆動を制御して時分割で画像を取得し、その画像を合成することにより、いわゆる黒つぶれ及び白とびのない高ダイナミックレンジの画像を生成することができる。 The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The image sensor of the camera head 11102 may be controlled to acquire images in a time-division manner in synchronization with the timing of the change in the light intensity, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.
　また、光源装置１１２０３は、特殊光観察に対応した所定の波長帯域の光を供給可能に構成されてもよい。特殊光観察では、例えば、体組織における光の吸収の波長依存性を利用して、通常の観察時における照射光（すなわち、白色光）に比べて狭帯域の光を照射することにより、粘膜表層の血管等の所定の組織を高コントラストで撮影する、いわゆる狭帯域光観察（Ｎａｒｒｏｗ　Ｂａｎｄ　Ｉｍａｇｉｎｇ）が行われる。あるいは、特殊光観察では、励起光を照射することにより発生する蛍光により画像を得る蛍光観察が行われてもよい。蛍光観察では、体組織に励起光を照射し当該体組織からの蛍光を観察すること（自家蛍光観察）、又はインドシアニングリーン（ＩＣＧ）等の試薬を体組織に局注するとともに当該体組織にその試薬の蛍光波長に対応した励起光を照射し蛍光像を得ること等を行うことができる。光源装置１１２０３は、このような特殊光観察に対応した狭帯域光及び／又は励起光を供給可能に構成され得る。 The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band of light is irradiated compared to the light irradiated during normal observation (i.e., white light), and a predetermined tissue such as blood vessels on the surface of the mucosa is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in special light observation, fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light. In fluorescent observation, excitation light is irradiated to the body tissue and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescent wavelength of the reagent is irradiated to the body tissue to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and/or excitation light corresponding to such special light observation.
　図２９は、図２８に示すカメラヘッド１１１０２及びＣＣＵ１１２０１の機能構成の一例を示すブロック図である。 FIG. 29 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in FIG. 28.
　カメラヘッド１１１０２は、レンズユニット１１４０１と、撮像部１１４０２と、駆動部１１４０３と、通信部１１４０４と、カメラヘッド制御部１１４０５と、を有する。ＣＣＵ１１２０１は、通信部１１４１１と、画像処理部１１４１２と、制御部１１４１３と、を有する。カメラヘッド１１１０２とＣＣＵ１１２０１とは、伝送ケーブル１１４００によって互いに通信可能に接続されている。 The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.
　レンズユニット１１４０１は、鏡筒１１１０１との接続部に設けられる光学系である。鏡筒１１１０１の先端から取り込まれた観察光は、カメラヘッド１１１０２まで導光され、当該レンズユニット１１４０１に入射する。レンズユニット１１４０１は、ズームレンズ及びフォーカスレンズを含む複数のレンズが組み合わされて構成される。 The lens unit 11401 is an optical system provided at the connection with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.
　撮像部１１４０２は、撮像素子で構成される。撮像部１１４０２を構成する撮像素子は、１つ（いわゆる単板式）であってもよいし、複数（いわゆる多板式）であってもよい。撮像部１１４０２が多板式で構成される場合には、例えば各撮像素子によってＲＧＢそれぞれに対応する画像信号が生成され、それらが合成されることによりカラー画像が得られてもよい。あるいは、撮像部１１４０２は、３Ｄ（Ｄｉｍｅｎｓｉｏｎａｌ）表示に対応する右目用及び左目用の画像信号をそれぞれ取得するための１対の撮像素子を有するように構成されてもよい。３Ｄ表示が行われることにより、術者１１１３１は術部における生体組織の奥行きをより正確に把握することが可能になる。なお、撮像部１１４０２が多板式で構成される場合には、各撮像素子に対応して、レンズユニット１１４０１も複数系統設けられ得る。 The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 11402 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is composed of a multi-plate type, multiple lens units 11401 may be provided corresponding to each imaging element.
　また、撮像部１１４０２は、必ずしもカメラヘッド１１１０２に設けられなくてもよい。例えば、撮像部１１４０２は、鏡筒１１１０１の内部に、対物レンズの直後に設けられてもよい。 Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.
　駆動部１１４０３は、アクチュエータによって構成され、カメラヘッド制御部１１４０５からの制御により、レンズユニット１１４０１のズームレンズ及びフォーカスレンズを光軸に沿って所定の距離だけ移動させる。これにより、撮像部１１４０２による撮像画像の倍率及び焦点が適宜調整され得る。 The driving unit 11403 is composed of an actuator, and moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.
　通信部１１４０４は、ＣＣＵ１１２０１との間で各種の情報を送受信するための通信装置によって構成される。通信部１１４０４は、撮像部１１４０２から得た画像信号をＲＡＷデータとして伝送ケーブル１１４００を介してＣＣＵ１１２０１に送信する。 The communication unit 11404 is configured with a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.
　また、通信部１１４０４は、ＣＣＵ１１２０１から、カメラヘッド１１１０２の駆動を制御するための制御信号を受信し、カメラヘッド制御部１１４０５に供給する。当該制御信号には、例えば、撮像画像のフレームレートを指定する旨の情報、撮像時の露出値を指定する旨の情報、並びに／又は撮像画像の倍率及び焦点を指定する旨の情報等、撮像条件に関する情報が含まれる。 The communication unit 11404 also receives control signals for controlling the operation of the camera head 11102 from the CCU 11201, and supplies them to the camera head control unit 11405. The control signals include information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and/or information specifying the magnification and focus of the captured image.
　なお、上記のフレームレートや露出値、倍率、焦点等の撮像条件は、ユーザによって適宜指定されてもよいし、取得された画像信号に基づいてＣＣＵ１１２０１の制御部１１４１３によって自動的に設定されてもよい。後者の場合には、いわゆるＡＥ（Ａｕｔｏ　Ｅｘｐｏｓｕｒｅ）機能、ＡＦ（Ａｕｔｏ　Ｆｏｃｕｓ）機能及びＡＷＢ（Ａｕｔｏ　Ｗｈｉｔｅ　Ｂａｌａｎｃｅ）機能が内視鏡１１１００に搭載されていることになる。 The above-mentioned frame rate, exposure value, magnification, focus, and other imaging conditions may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.
　カメラヘッド制御部１１４０５は、通信部１１４０４を介して受信したＣＣＵ１１２０１からの制御信号に基づいて、カメラヘッド１１１０２の駆動を制御する。 The camera head control unit 11405 controls the operation of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.
　通信部１１４１１は、カメラヘッド１１１０２との間で各種の情報を送受信するための通信装置によって構成される。通信部１１４１１は、カメラヘッド１１１０２から、伝送ケーブル１１４００を介して送信される画像信号を受信する。 The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.
　また、通信部１１４１１は、カメラヘッド１１１０２に対して、カメラヘッド１１１０２の駆動を制御するための制御信号を送信する。画像信号や制御信号は、電気通信や光通信等によって送信することができる。 The communication unit 11411 also transmits to the camera head 11102 a control signal for controlling the operation of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, etc.
　画像処理部１１４１２は、カメラヘッド１１１０２から送信されたＲＡＷデータである画像信号に対して各種の画像処理を施す。 The image processing unit 11412 performs various image processing operations on the image signal, which is the RAW data transmitted from the camera head 11102.
　制御部１１４１３は、内視鏡１１１００による術部等の撮像、及び、術部等の撮像により得られる撮像画像の表示に関する各種の制御を行う。例えば、制御部１１４１３は、カメラヘッド１１１０２の駆動を制御するための制御信号を生成する。 The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100, and the display of the captured images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.
　また、制御部１１４１３は、画像処理部１１４１２によって画像処理が施された画像信号に基づいて、術部等が映った撮像画像を表示装置１１２０２に表示させる。この際、制御部１１４１３は、各種の画像認識技術を用いて撮像画像内における各種の物体を認識してもよい。例えば、制御部１１４１３は、撮像画像に含まれる物体のエッジの形状や色等を検出することにより、鉗子等の術具、特定の生体部位、出血、エネルギー処置具１１１１２の使用時のミスト等を認識することができる。制御部１１４１３は、表示装置１１２０２に撮像画像を表示させる際に、その認識結果を用いて、各種の手術支援情報を当該術部の画像に重畳表示させてもよい。手術支援情報が重畳表示され、術者１１１３１に提示されることにより、術者１１１３１の負担を軽減することや、術者１１１３１が確実に手術を進めることが可能になる。 The control unit 11413 also causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific body parts, bleeding, mist generated when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.
　カメラヘッド１１１０２及びＣＣＵ１１２０１を接続する伝送ケーブル１１４００は、電気信号の通信に対応した電気信号ケーブル、光通信に対応した光ファイバ、又はこれらの複合ケーブルである。 The transmission cable 11400 that connects the camera head 11102 and the CCU 11201 is an electrical signal cable that supports electrical signal communication, an optical fiber that supports optical communication, or a composite cable of these.
　ここで、図示する例では、伝送ケーブル１１４００を用いて有線で通信が行われていたが、カメラヘッド１１１０２とＣＣＵ１１２０１との間の通信は無線で行われてもよい。 In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.
　以上、本開示に係る技術が適用され得る内視鏡手術システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、ＣＣＵ１１２０１や、カメラヘッド１１１０２の撮像部１１４０２に適用され得る。具体的には、上述の第１～第９実施形態の遮蔽体（遮蔽ベタ膜及び遮蔽構造体）は、ＣＣＵ１１２０１や撮像部１０４０２に適用することができる。ＣＣＵ１１２０１及び撮像部１０４０２に本開示に係る技術を適用することにより、ＣＣＵ１１２０１及び撮像部１０４０２の信頼性の向上を図ることができる。 The above describes an example of an endoscopic surgery system to which the technology disclosed herein can be applied. Of the configurations described above, the technology disclosed herein can be applied to, for example, the CCU11201 and the imaging unit 11402 of the camera head 11102. Specifically, the shields (solid shielding films and shielding structures) of the first to ninth embodiments described above can be applied to the CCU11201 and the imaging unit 10402. By applying the technology disclosed herein to the CCU11201 and the imaging unit 10402, the reliability of the CCU11201 and the imaging unit 10402 can be improved.
　なお、ここでは、一例として内視鏡手術システムについて説明したが、本開示に係る技術は、その他、例えば、顕微鏡手術システム等に適用されてもよい。 Note that although an endoscopic surgery system has been described here as an example, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.
　〔その他の実施形態〕
　上記のように、本技術は第１～第９実施形態によって記載したが、この開示の一部をなす論述及び図面は本技術を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。 Other embodiments
As described above, the present technology has been described by the first to ninth embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present technology. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.
　また、本技術は、上述したイメージセンサとしての固体撮像装置の他、ToF（Time of Flight）センサともよばれる距離を測定する測距センサなども含む光検出装置全般に適用することができる。測距センサは、物体に向かって照射光を発光し、その照射光が物体の表面で反射され返ってくる反射光を検出し、照射光が発光されてから反射光が受光されるまでの飛行時間に基づいて物体までの距離を算出するセンサである。この測距センサの構造として、上述した第１導体及び第２導体の構造を採用することができる。また、本技術は、光検出装置以外の半導体装置にも適用可能である。 Furthermore, this technology can be applied to light detection devices in general, including solid-state imaging devices as image sensors described above, as well as distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors. A distance measurement sensor emits light toward an object, detects the light that is reflected back from the surface of the object, and calculates the distance to the object based on the flight time from when the light is emitted to when the reflected light is received. The structure of the first conductor and second conductor described above can be adopted as the structure of this distance measurement sensor. Furthermore, this technology can be applied to semiconductor devices other than light detection devices.
　なお、本技術は、以下のような構成としてもよい。
（１）
　互いに反対側に位置する第１及び第２の面を有し、かつ前記第２の面側から入射した光を光電変換する光電変換部が設けられた第１半導体層と、
　トランジスタを有し、かつ前記第１半導体層の前記第１の面側に設けられた第２半導体層と、
　トランジスタを有し、かつ前記第２半導体層の前記第１半導体層側とは反対側に前記第２半導体層と重畳して設けられた第３半導体層と、
　前記第２半導体層と前記第３半導体層との間に設けられた遮蔽体と、
　を備えている、光検出装置。
（２）
　前記遮蔽体は、前記第２及び第３半導体層の一方から他方へ伝播する電磁場を遮蔽する、上記（１）に記載の光検出装置。
（３）
　前記遮蔽体は、前記第２及び第３半導体層の少なくとも何れか一方の前記トランジスタを含む回路ブロックと平面視で選択的に重畳している、上記（１）又は（２）に記載の光検出装置。
（４）
　前記遮蔽体は、二次元状に広がるプレート形状の遮蔽ベタ膜である、上記（１）から（３）の何れかに記載の光検出装置。
（５）
　前記遮蔽ベタ膜は、前記第２半導体層の前記第３半導体層側の面に固定電荷膜を介して固定されている、上記（１）から（４）の何れかに記載の光検出装置。
（６）
　前記遮蔽ベタ膜は、電位が印加される配線と電気的に接続されている、上記（１）から（５）の何れかに記載の光検出装置。
（７）
　前記第２半導体層を厚さ方向に貫通すると共に前記遮蔽ベタ膜の開口部を貫通する貫通コンタクト電極と、
　前記第２半導体層と前記第３半導体層との間に設けられた第１接合パッドと、
　前記第１接合パッドの前記第３半導体層側に設けられ、かつ前記第１接合パッドと接合された第２接合パッドと、
　を更に備え、
　前記第１及び第２接合パッドの少なくとも何れか一方は、平面視で前記開口部の全体と重畳する平面サイズになっている、上記（１）から（６）の何れかに記載の光検出装置。
（８）
　前記第２半導体層の前記第３半導体層側に設けられ、かつ前記遮蔽ベタ膜及び前記第１接合パッドを含む第１配線層と、
　前記第３半導体層の前記第２半導体層側に前記第１配線層と接合して設けられ、かつ前記第２接合パッドを含む第２配線層と、
　を更に備えている、上記（４）に記載の光検出装置。
（９）
　前記遮蔽体は、
　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
　を含む遮蔽構造体であり、
　前記遮蔽構造体は、前記第１接合パッドと前記第２接合パッドとが、前記第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、上記（１）に記載の光検出装置。
（１０）
　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ前記第１方向に延伸する導体を更に備えている、上記（９）に記載の光検出装置。
（１１）
　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ前記第１方向に複数点在する導体を更に備えている、上記（９）に記載の光検出装置。
（１２）
　前記遮蔽構造体は、
　前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１接合パッドと重畳し、かつ前記第１方向に延伸する第１導体と、
　前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１接合パッドと重畳し、かつ前記第１方向に複数点在する第２導体と、
　を更に備えている、上記（９）に記載の光検出装置。
（１３）
　前記遮蔽体は、
　前記第２半導体層を厚さ方向に貫通する導体と、
　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
　を含む遮蔽構造体であり、
　前記遮蔽構造体は、前記導体と、前記第１接合パッドと、前記第２接合パッドとが、平面視で前記第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、上記（１）に記載の光検出装置。
（１４）
　前記導体は、平面視で前記第１の方向に延伸するストライプ形状になっている、上記（１３）に記載の光検出装置。
（１５）
　前記導体は、平面視で前記第１の方向に複数点在している、上記（１３）に記載の光検出装置。
（１６）
　前記遮蔽体は、
　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
　前記第２接合パッドよりも前記第３半導体層側に設けられ、かつ平面視で前記第１方向に延伸する配線と、
　を含む遮蔽構造体であり、
　前記遮蔽構造体は、前記第１及び第２接合パッドと、前記配線とが、平面視で前記第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、上記（１）に記載の光検出装置。
（１７）
　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ平面視で前記第１方向に延伸する導体を更に備えている、上記（１６）に記載の光検出装置。
（１８）
　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ平面視で前記第１方向に複数点在する導体を更に備えている、上記（１６）に記載の光検出装置。
（１９）
　前記遮蔽体は、
　前記第２半導体層を厚さ方向に貫通する導体と、
　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
　前記第２接合パッドよりも前記第３半導体層側に設けられ、かつ平面視で前記第１方向に延伸する配線と、
　を含む遮蔽構造体であり、
　前記遮蔽構造体は、前記導体と、前記第１接合パッドと、前記第２接合パッドと、前記配線とが、平面視で第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、上記（１）に記載の光検出装置。
（２０）
　前記導体は、平面視で前記第１方向に延伸するストライプ形状になっている、上記（１９）に記載の光検出装置。
（２１）
　前記導体は、平面視で前記第１方向に複数点在している、上記（１９）に記載の光検出装置。
（２２）
　上記（１）から（２１）の何れから記載の光検出装置と、
　被写体からの像光を前記光検出装置の撮像面上に結像させる光学レンズと、
　前記光検出装置から出力される信号に信号処理を行う信号処理回路と、
　を備えている、電子機器。 The present technology may be configured as follows.
(1)
a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side;
a second semiconductor layer having a transistor and provided on the first surface side of the first semiconductor layer;
a third semiconductor layer having a transistor and provided on the second semiconductor layer on a side opposite to the first semiconductor layer;
a shield provided between the second semiconductor layer and the third semiconductor layer;
The optical detection device comprises:
(2)
The photodetector according to claim 1, wherein the shield blocks an electromagnetic field propagating from one of the second and third semiconductor layers to the other.
(3)
The photodetector according to (1) or (2) above, wherein the shield selectively overlaps in a planar view with a circuit block including the transistor in at least one of the second and third semiconductor layers.
(4)
The optical detection device according to any one of (1) to (3) above, wherein the shielding body is a plate-shaped shielding solid film extending two-dimensionally.
(5)
The photodetector device according to any one of (1) to (4) above, wherein the solid shielding film is fixed to the surface of the second semiconductor layer facing the third semiconductor layer via a fixed charge film.
(6)
The light detection device according to any one of (1) to (5) above, wherein the solid shielding film is electrically connected to wiring to which a potential is applied.
(7)
a through contact electrode penetrating the second semiconductor layer in a thickness direction and penetrating an opening of the shielding solid film;
a first bonding pad disposed between the second semiconductor layer and the third semiconductor layer;
a second bonding pad provided on the third semiconductor layer side of the first bonding pad and bonded to the first bonding pad;
Further comprising:
The optical detection device according to any one of (1) to (6) above, wherein at least one of the first and second bonding pads has a planar size that overlaps with the entire opening when viewed in a plane.
(8)
a first wiring layer provided on the second semiconductor layer side of the third semiconductor layer and including the solid shielding film and the first bonding pad;
a second wiring layer provided on the second semiconductor layer side of the third semiconductor layer in contact with the first wiring layer and including the second bonding pad;
The light detection device according to (4) above, further comprising:
(9)
The shielding body is
a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
A shielding structure comprising:
The optical detection device described in (1) above, wherein the shielding structure is such that the first bond pad and the second bond pad are repeatedly arranged with a relative offset position in a second direction intersecting the first direction.
(10)
The photodetector device described in (9) above, wherein the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a planar view, and extends in the first direction.
(11)
The photodetector device described in (9) above, wherein the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a planar view, and is scattered in multiple locations in the first direction.
(12)
The shielding structure includes:
a first conductor penetrating the second semiconductor layer in a thickness direction, overlapping the first bonding pad in a plan view, and extending in the first direction;
a second conductor penetrating the second semiconductor layer in a thickness direction, overlapping the first bonding pad in a plan view, and being scattered in the first direction;
The light detection device according to (9) above, further comprising:
(13)
The shielding body is
A conductor penetrating the second semiconductor layer in a thickness direction;
a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
A shielding structure comprising:
The optical detection device described in (1) above, wherein the shielding structure is arranged such that the conductor, the first bonding pad, and the second bonding pad are repeatedly arranged with their positions relatively shifted in a second direction that intersects the first direction in a planar view.
(14)
The photodetector according to claim 13, wherein the conductor has a stripe shape extending in the first direction in a plan view.
(15)
The photodetector according to claim 13, wherein the conductors are arranged in a plurality of locations in the first direction in a plan view.
(16)
The shielding body is
a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
a wiring provided on the third semiconductor layer side of the second bonding pad and extending in the first direction in a plan view;
A shielding structure comprising:
The shielding structure is a photodetector device described in (1) above, in which the first and second bonding pads and the wiring are repeatedly arranged with their positions relatively shifted in a second direction that intersects the first direction in a planar view.
(17)
The photodetector device described in (16) above, wherein the shielding structure further comprises a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a planar view, and extends in the first direction in a planar view.
(18)
The photodetector device described in (16) above, wherein the shielding structure further includes a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps with the first metal pad in a planar view, and is scattered in multiple locations in the first direction in a planar view.
(19)
The shielding body is
A conductor penetrating the second semiconductor layer in a thickness direction;
a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
a wiring provided on the third semiconductor layer side of the second bonding pad and extending in the first direction in a plan view;
A shielding structure comprising:
The optical detection device described in (1) above, wherein the shielding structure is arranged such that the conductor, the first bonding pad, the second bonding pad, and the wiring are repeatedly arranged with relative positional shifts in a second direction that intersects the first direction in a planar view.
(20)
The photodetector according to claim 19, wherein the conductor has a stripe shape extending in the first direction in a plan view.
(21)
The light detection device according to (19) above, wherein the conductors are scattered in a plurality of locations in the first direction in a plan view.
(22)
A photodetector according to any one of (1) to (21) above;
an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device;
a signal processing circuit for processing a signal output from the photodetector;
An electronic device comprising:
　本技術の範囲は、図示され記載された例示的な実施形態に限定されるものではなく、本技術が目的とするものと均等な効果をもたらす全ての実施形態をも含む。さらに、本技術の範囲は、請求項により画される発明の特徴の組み合わせに限定されるものではなく、全ての開示されたそれぞれの特徴のうち特定の特徴のあらゆる所望する組み合わせによって画されうる。 The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve the same effect as the intended purpose of the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective features disclosed.
　１Ａ～１Ｉ　固体撮像装置
　２　半導体チップ
　２Ａ　センサ画素アレイ部
　２Ｂ　周辺部
　３　センサ画素
　４　垂直駆動回路
　５　カラム信号処理回路
　６　水平駆動回路
　７　出力回路
　８　制御回路
　１０　画素駆動線
　１１　垂直信号線
　１２　水平信号線
　１３　ロジック回路
　１４　ボンディングパッド
　１５　画素回路
　２０　第１半導体層
　２１　光電変換領域
　３０　第１配線層
　３２　配線
　４０　第２配線層
　４１　絶縁膜
　４２　配線
　５０　第２半導体層
　５１　貫通コンタクト電極
　５２，５３　導体
　５５Ｂ～５５Ｉ　遮蔽構造体
　６０　第３配線層
　６２　配線
　６３　接合パッド
　７０　第４配線層
　７２，７２ａ　配線
　７３　接合パッド
　８０　第３半導体層
　９０　集光層
　９１　カラーフィルタ
　９２　オンチップレンズ
　１００　電子機器
　１０１　固体撮像装置
　１０２　光学系（光学レンズ）
　１０３　シャッタ装置
　１０４　駆動回路
　１０５　信号処理回路 1A to 1I Solid-state imaging device 2 Semiconductor chip 2A Sensor pixel array section 2B Peripheral section 3 Sensor pixel 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 10 Pixel drive line 11 Vertical signal line 12 Horizontal signal line 13 Logic circuit 14 Bonding pad 15 Pixel circuit 20 First semiconductor layer 21 Photoelectric conversion region 30 First wiring layer 32 Wiring 40 Second wiring layer 41 Insulating film 42 Wiring 50 Second semiconductor layer 51 Through contact electrode 52, 53 Conductor 55B to 55I Shielding structure 60 Third wiring layer 62 Wiring 63 Bonding pad 70 Fourth wiring layer 72, 72a Wiring 73 Bonding pad 80 Third semiconductor layer 90 Light collecting layer 91 Color filter 92 On-chip lens 100 Electronic device 101 Solid-state imaging device 102 Optical system (optical lens)
103 Shutter device 104 Drive circuit 105 Signal processing circuit

Claims (22)

  1. 　互いに反対側に位置する第１及び第２の面を有し、かつ前記第２の面側から入射した光を光電変換する光電変換部が設けられた第１半導体層と、
    　トランジスタを有し、かつ前記第１半導体層の前記第１の面側に設けられた第２半導体層と、
    　トランジスタを有し、かつ前記第２半導体層の前記第１半導体層側とは反対側に前記第２半導体層と重畳して設けられた第３半導体層と、
    　前記第２半導体層と前記第３半導体層との間に設けられた遮蔽体と、
    　を備えている、光検出装置。     a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side;
    a second semiconductor layer having a transistor and provided on the first surface side of the first semiconductor layer;
    a third semiconductor layer having a transistor and provided on the second semiconductor layer on a side opposite to the first semiconductor layer;
    a shield provided between the second semiconductor layer and the third semiconductor layer;
    The optical detection device comprises:
  2. 　前記遮蔽体は、前記第２及び第３半導体層の一方から他方へ伝播する電磁場を遮蔽する、請求項１に記載の光検出装置。 The optical detection device of claim 1, wherein the shielding body blocks an electromagnetic field propagating from one of the second and third semiconductor layers to the other.
  3. 　前記遮蔽体は、前記第２及び第３半導体層の少なくとも何れか一方の前記トランジスタを含む回路ブロックと平面視で選択的に重畳している、請求項１に記載の光検出装置。 The photodetector device of claim 1, wherein the shield selectively overlaps in plan view with a circuit block including the transistor in at least one of the second and third semiconductor layers.
  4. 　前記遮蔽体は、二次元状に広がるプレート形状の遮蔽ベタ膜である、請求項１に記載の光検出装置。 The optical detection device according to claim 1, wherein the shielding body is a solid shielding film in the shape of a plate that extends two-dimensionally.
  5. 　前記遮蔽ベタ膜は、前記第２半導体層の前記第３半導体層側の面に固定電荷膜を介して固定されている、請求項４に記載の光検出装置。 The photodetector device according to claim 4, wherein the solid shielding film is fixed to the surface of the second semiconductor layer facing the third semiconductor layer via a fixed charge film.
  6. 　前記遮蔽ベタ膜は、電位が印加される配線と電気的に接続されている、請求項４に記載の光検出装置。 The light detection device of claim 4, wherein the shielding solid film is electrically connected to wiring to which a potential is applied.
  7. 　前記第２半導体層を厚さ方向に貫通すると共に前記遮蔽ベタ膜の開口部を貫通する貫通コンタクト電極と、
    　前記第２半導体層と前記第３半導体層との間に設けられた第１接合パッドと、
    　前記第１接合パッドの前記第３半導体層側に設けられ、かつ前記第１接合パッドと接合された第２接合パッドと、
    　を更に備え、
    　前記第１及び第２接合パッドの少なくとも何れか一方は、平面視で前記開口部の全体と重畳する平面サイズになっている、請求項４に記載の光検出装置。     a through contact electrode penetrating the second semiconductor layer in a thickness direction and penetrating an opening of the shielding solid film;
    a first bonding pad disposed between the second semiconductor layer and the third semiconductor layer;
    a second bonding pad provided on the third semiconductor layer side of the first bonding pad and bonded to the first bonding pad;
    Further comprising:
    The light detection device according to claim 4 , wherein at least one of the first and second bonding pads has a planar size such that the planar size overlaps with the entire opening in a plan view.
  8. 　前記第２半導体層の前記第３半導体層側に設けられ、かつ前記遮蔽ベタ膜及び前記第１接合パッドを含む第１配線層と、
    　前記第３半導体層の前記第２半導体層側に前記第１配線層と接合して設けられ、かつ前記第２メタルパッドを含む第２配線層と、
    　を更に備えている、請求項４に記載の光検出装置。     a first wiring layer provided on the second semiconductor layer side of the third semiconductor layer and including the solid shielding film and the first bonding pad;
    a second wiring layer provided on the second semiconductor layer side of the third semiconductor layer in contact with the first wiring layer and including the second metal pad;
    The optical detection device of claim 4 further comprising:
  9. 　前記遮蔽体は、
    　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
    　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
    　を含む遮蔽構造体であり、
    　前記遮蔽構造体は、前記第１接合パッドと前記第２接合パッドとが、前記第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、請求項１に記載の光検出装置。     The shielding body is
    a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
    a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
    A shielding structure comprising:
    The optical detection device of claim 1 , wherein the shielding structure is arranged such that the first bond pads and the second bond pads are repeatedly arranged with their positions relatively shifted in a second direction intersecting the first direction.
  10. 　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ前記第１方向に延伸する導体を更に備えている、請求項９に記載の光検出装置。 The photodetector device of claim 9, wherein the shielding structure further comprises a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a plan view, and extends in the first direction.
  11. 　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ前記第１方向に複数点在する導体を更に備えている、請求項９に記載の光検出装置。 The photodetector device of claim 9, wherein the shielding structure further comprises a conductor that penetrates the second semiconductor layer in the thickness direction, overlaps the first metal pad in a plan view, and is scattered in the first direction.
  12. 　前記遮蔽構造体は、
    　前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１接合パッドと重畳し、かつ前記第１方向に延伸する第１導体と、
    　前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１接合パッドと重畳し、かつ前記第１方向に複数点在する第２導体と、
    　を更に備えている、請求項９に記載の光検出装置。     The shielding structure includes:
    a first conductor penetrating the second semiconductor layer in a thickness direction, overlapping the first bonding pad in a plan view, and extending in the first direction;
    a second conductor penetrating the second semiconductor layer in a thickness direction, overlapping the first bonding pad in a plan view, and being scattered in the first direction;
    The optical detection device of claim 9 further comprising:
  13. 　前記遮蔽体は、
    　前記第２半導体層を厚さ方向に貫通する導体と、
    　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
    　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
    　を含む遮蔽構造体であり、
    　前記遮蔽構造体は、前記導体と、前記第１接合パッドと、前記第２接合パッドとが、平面視で前記第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、請求項１に記載の光検出装置。     The shielding body is
    A conductor penetrating the second semiconductor layer in a thickness direction;
    a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
    a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
    A shielding structure comprising:
    The optical detection device of claim 1 , wherein the shielding structure is arranged such that the conductor, the first bond pad, and the second bond pad are repeatedly arranged with their positions relatively shifted in a second direction that intersects the first direction in a planar view.
  14. 　前記導体は、平面視で前記第１の方向に延伸するストライプ形状になっている、請求項１３に記載の光検出装置。 The photodetector according to claim 13, wherein the conductor has a stripe shape extending in the first direction in a plan view.
  15. 　前記導体は、平面視で前記第１の方向に複数点在している、請求項１３に記載の光検出装置。 The light detection device according to claim 13, wherein the conductors are scattered in a plurality in the first direction in a plan view.
  16. 　前記遮蔽体は、
    　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
    　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
    　前記第２接合パッドよりも前記第３半導体層側に設けられ、かつ平面視で前記第１方向に延伸する配線と、
    　を含む遮蔽構造体であり、
    　前記遮蔽構造体は、前記第１及び第２接合パッドと、前記配線とが、平面視で前記第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、請求項１に記載の光検出装置。     The shielding body is
    a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
    a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
    a wiring provided on the third semiconductor layer side of the second bonding pad and extending in the first direction in a plan view;
    A shielding structure comprising:
    The optical detection device of claim 1 , wherein the shielding structure is arranged such that the first and second bonding pads and the wiring are repeatedly arranged with their positions relatively shifted in a second direction that intersects the first direction in a planar view.
  17. 　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ平面視で前記第１方向に延伸する導体を更に備えている、請求項１６に記載の光検出装置。 The photodetector device of claim 16, wherein the shielding structure further comprises a conductor that penetrates the second semiconductor layer in a thickness direction, overlaps the first metal pad in a plan view, and extends in the first direction in a plan view.
  18. 　前記遮蔽構造体は、前記第２半導体層を厚さ方向に貫通し、かつ平面視で前記第１メタルパッドと重畳し、かつ平面視で前記第１方向に複数点在する導体を更に備えている、請求項１６に記載の光検出装置。 The photodetector device of claim 16, wherein the shielding structure further comprises a conductor that penetrates the second semiconductor layer in the thickness direction, overlaps the first metal pad in a plan view, and is scattered in the first direction in a plan view.
  19. 　前記遮蔽体は、
    　前記第２半導体層を厚さ方向に貫通する導体と、
    　前記第２半導体層と前記第３半導体層との間に設けられ、かつ平面視で第１方向に延伸する第１接合パッドと、
    　前記第１メタルパッドの前記第３半導体層側に前記第１接合パッドと接合して設けられ、かつ平面視で前記第１方向に延伸する第２接合パッドと、
    　前記第２接合パッドよりも前記第３半導体層側に設けられ、かつ平面視で前記第１方向に延伸する配線と、
    　を含む遮蔽構造体であり、
    　前記遮蔽構造体は、前記導体と、前記第１接合パッドと、前記第２接合パッドと、前記配線とが、平面視で第１方向と交差する第２方向に相対的に位置をずらした状態で繰り返し配置されている、請求項１に記載の光検出装置。     The shielding body is
    A conductor penetrating the second semiconductor layer in a thickness direction;
    a first bonding pad provided between the second semiconductor layer and the third semiconductor layer and extending in a first direction in a plan view;
    a second bonding pad provided on the third semiconductor layer side of the first metal pad in contact with the first bonding pad and extending in the first direction in a plan view;
    a wiring provided on the third semiconductor layer side of the second bonding pad and extending in the first direction in a plan view;
    A shielding structure comprising:
    The photodetection device of claim 1 , wherein the shielding structure is arranged such that the conductor, the first bonding pad, the second bonding pad, and the wiring are repeatedly arranged with relative offset positions in a second direction that intersects the first direction in a planar view.
  20. 　前記導体は、平面視で前記第１方向に延伸するストライプ形状になっている、請求項１９に記載の光検出装置。 The light detection device according to claim 19, wherein the conductor has a stripe shape extending in the first direction in a plan view.
  21. 　前記導体は、平面視で前記第１方向に複数点在している、請求項１９に記載の光検出装置。 The light detection device according to claim 19, wherein the conductors are scattered in a plurality in the first direction in a plan view.
  22. 　光検出装置と、
    　被写体からの像光を前記光検出装置の撮像面上に結像させる光学レンズと、
    　前記光検出装置から出力される信号に信号処理を行う信号処理回路と、
    　を備え、
    　前記光検出装置は、
    　互いに反対側に位置する第１及び第２の面を有し、かつ前記第２の面側から入射した光を光電変換する光電変換部が設けられた第１半導体層と、
    　トランジスタを有し、かつ前記第１半導体層の前記第１の面側に設けられた第２半導体層と、
    　トランジスタを有し、かつ前記第２半導体層の前記第１半導体層側とは反対側に前記第２半導体層と重畳して設けられた第３半導体層と、
    　前記第２半導体層と前記第３半導体層との間に設けられた遮蔽体と、
    　を備えている、電子機器。     A photodetector;
    an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device;
    a signal processing circuit for processing a signal output from the photodetector;
    Equipped with
    The light detection device includes:
    a first semiconductor layer having a first surface and a second surface opposite to each other and including a photoelectric conversion portion configured to photoelectrically convert light incident from the second surface side;
    a second semiconductor layer having a transistor and provided on the first surface side of the first semiconductor layer;
    a third semiconductor layer having a transistor and provided on the second semiconductor layer on a side opposite to the first semiconductor layer;
    a shield provided between the second semiconductor layer and the third semiconductor layer;
    An electronic device comprising:
PCT/JP2023/040092 2022-12-15 2023-11-07 Light detection device and electronic apparatus WO2024127853A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022199933 2022-12-15
JP2022-199933 2022-12-15

Publications (1)

Publication Number Publication Date
WO2024127853A1 true WO2024127853A1 (en) 2024-06-20

Family

ID=91485487

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/040092 WO2024127853A1 (en) 2022-12-15 2023-11-07 Light detection device and electronic apparatus

Country Status (1)

Country Link
WO (1) WO2024127853A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012164870A (en) * 2011-02-08 2012-08-30 Sony Corp Solid state image pickup device, manufacturing method of the same and electronic equipment
WO2020262583A1 (en) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and method for producing same
JP2022034522A (en) * 2020-08-18 2022-03-03 三星電子株式会社 Image sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012164870A (en) * 2011-02-08 2012-08-30 Sony Corp Solid state image pickup device, manufacturing method of the same and electronic equipment
WO2020262583A1 (en) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and method for producing same
JP2022034522A (en) * 2020-08-18 2022-03-03 三星電子株式会社 Image sensor

Similar Documents

Publication Publication Date Title
JP7487252B2 (en) Light receiving element
JP2022176838A (en) Solid-state imaging apparatus and electronic apparatus
WO2022270039A1 (en) Solid-state imaging device
WO2022172711A1 (en) Photoelectric conversion element and electronic device
US12034019B2 (en) Light receiving element, solid-state imaging device, and electronic device
WO2024127853A1 (en) Light detection device and electronic apparatus
WO2024214389A1 (en) Light detection device, electronic apparatus, and semiconductor device
WO2024154666A1 (en) Semiconductor device
WO2023210238A1 (en) Light detecting device, and electronic apparatus
WO2024202748A1 (en) Light detection device and electronic device
WO2024202617A1 (en) Semiconductor device, light detection device, and semiconductor device manufacturing method
WO2023248926A1 (en) Imaging element and electronic device
WO2024057814A1 (en) Light-detection device and electronic instrument
WO2024111280A1 (en) Light detection device and electronic equipment
WO2024202672A1 (en) Light detection device and electronic device
WO2024142627A1 (en) Photodetector and electronic apparatus
WO2024181273A1 (en) Light detection device and electronic apparatus
WO2023234069A1 (en) Imaging device and electronic apparatus
WO2023188899A1 (en) Light detecting device and electronic apparatus
WO2024116928A1 (en) Semiconductor device and electronic apparatus
WO2024111457A1 (en) Photodetection device, method for producing same, and electronic device
WO2024116302A1 (en) Photodetector element
WO2023176430A1 (en) Light detection device
WO2024166667A1 (en) Light detection device and electronic apparatus
WO2023248925A1 (en) Imaging element and electronic device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23903151

Country of ref document: EP

Kind code of ref document: A1