WO2024125340A1 - 时钟树闸延时优化方法、系统、设备及计算机存储介质 - Google Patents

时钟树闸延时优化方法、系统、设备及计算机存储介质 Download PDF

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WO2024125340A1
WO2024125340A1 PCT/CN2023/136147 CN2023136147W WO2024125340A1 WO 2024125340 A1 WO2024125340 A1 WO 2024125340A1 CN 2023136147 W CN2023136147 W CN 2023136147W WO 2024125340 A1 WO2024125340 A1 WO 2024125340A1
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clock tree
unit
simulation test
clock
gate delay
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PCT/CN2023/136147
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English (en)
French (fr)
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欧阳可青
吴韦忠
宋存彪
陈寒
梁超
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深圳市中兴微电子技术有限公司
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Publication of WO2024125340A1 publication Critical patent/WO2024125340A1/zh

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  • the clock tree path in the chip uses a large-drive clock unit to reduce the top-level clock delay to reduce the impact of OCV (On-Chip Variation).
  • the input load of the large-drive clock unit is very large, so a customized large-drive clock unit (such as a large-drive buffer) is generally used at the beginning of the clock tree to drive the large-drive inverter.
  • the customized large-drive buffer used to drive the large-drive inverter generally has a higher gate delay, which may affect the rapid convergence of the chip timing.
  • the present application provides a clock tree gate delay optimization method applied to a clock tree gate delay optimization system, comprising: determining a clock tree in a chip under multiple simulation application scenarios; sequentially setting a simulation test circuit corresponding to the clock tree in each of the simulation application scenarios, and performing a simulation test on each of the simulation test circuits; determining a target inverting unit corresponding to the clock tree in each of the simulation application scenarios according to the simulation test results, and storing all the target inverting units in a preset layout in the form of a preset kit; after detecting that there is a clock tree to be run in the chip to be run, determining a target matching inverting unit in the preset layout that matches the clock tree to be run, and connecting the target matching inverting unit to the clock tree to be run for operation.
  • the present application also provides a clock tree gate delay optimization system, a clock tree gate delay optimization system
  • the system comprises a simulation test circuit, which comprises: a small drive standard unit connected to a clock signal input terminal in a chip; a target inverter connected to the small drive standard unit; and a large drive clock unit connected to the target inverter.
  • the present application also provides a clock tree gate delay optimization device, which includes: a memory, a processor, and a clock tree gate delay optimization program stored in the memory and executable on the processor, wherein the clock tree gate delay optimization program implements the steps of the clock tree gate delay optimization method described herein when executed.
  • FIG1 is a flow chart of a clock tree gate delay optimization method of the present application.
  • Figure 2 is a schematic diagram of a clock tree with a large driver buffer
  • the target inverting unit can be stored in the form of a kit.
  • the target inverting unit can be connected to the clock tree path to drive the large drive clock unit of the next level, thereby reducing the gate delay of one inverter, that is, reducing the gate delay in the clock tree.
  • FIG3 it includes a PLL output terminal, a small drive standard unit (including delay x); a reverse unit (including delay y) and a clock unit.
  • the starting point of the implementation method of the present application is to realize a large drive reverse unit with a small input load. In this way, it has the characteristics of a small input load (easy to be pushed) and a large driving force (easy to push long lines). And under the clock tree path, one gate delay is reduced compared to the large drive buffer.
  • the implementation method of the present application uses a kit form, it is easy to replace and easier to implement.
  • step S10 a clock tree in a chip under a plurality of simulation application scenarios is determined.
  • step S20 a simulation test circuit corresponding to the clock tree in each simulation application scenario is constructed in turn, and a simulation test is performed on each simulation test circuit.
  • the simulation test circuit when the simulation test circuit is constructed and the simulation test is performed, it can be performed in the manner shown in Figure 3, which includes a PLL output end, a small drive standard unit (including delay x); a reverse unit (including delay y) and a clock unit, and when the simulation test is performed, the PLL output end takes a load that can be driven by a small drive standard unit as the starting point, drives the reverse unit, and then drives the clock unit through the reverse unit.
  • the clock unit can be a large drive clock unit.
  • the reverse units of various models can be obtained in advance, and each model of the reverse unit can be brought into the simulation test circuit for testing, such as replacing the reverse unit in Figure 3. To obtain the simulation test results corresponding to each reverse unit.
  • step S30 the target inverting unit corresponding to the clock tree in each simulation application scenario is determined according to the simulation test result, and all the target inverting units are stored in a preset layout in the form of a preset kit.
  • the clock tree gate delay optimization system After the clock tree gate delay optimization system completes the simulation test of the clock tree, it will obtain the corresponding simulation test results, and select the best reverse unit in each simulation test result as the target inversion unit corresponding to the clock tree in the simulation application scenario. And for the clock tree in each simulation test scenario, the clock tree gate delay optimization system can use the same method to obtain the corresponding target inversion unit. And after each target inversion unit is determined, the target inversion unit can be stored in a pre-set layout in the form of a pre-set kit. Among them, the port position, port metal layer, port shape and port size of the target inversion unit in the layout remain unchanged. For example, as shown in Figure 4, there are multiple target inversion units in the layout, such as Driving A, Driving B, and Driving C.
  • the target inverting unit may be an inverting unit with the best fit between the input load and the output thrust in the clock tree.
  • the inverting unit or the reverse unit may be an inverter.
  • the preset layout may be an inverter layout set in advance.
  • step S40 after detecting that there is a clock tree to be run in the chip to be run, a target matching inverting unit in the preset layout that matches the clock tree to be run is determined, and the target matching inverting unit is connected to the clock tree to be run for operation.
  • the clock tree gate delay optimization system when the clock tree gate delay optimization system is in actual application, it is found that in a certain scenario, there is a chip to be run, and the clock tree in the chip to be run has not been run at this time, then this clock tree can be used as the clock tree to be run.
  • the minimum thrust that can be provided by the small drive standard unit in the clock tree to be run can be determined, so as to determine the minimum input load of the inverting unit required in the clock tree to be run according to the minimum thrust.
  • the load parameters corresponding to the large drive clock unit in the clock tree to be run so as to determine the estimated thrust that can be provided by the inverting unit required in the clock tree to be run according to the load parameters.
  • the target inverting unit that matches the clock tree to be run is selected in the preset layout, and it is used as the target matching inverting unit. Moreover, the target matching inverting unit can generate the estimated thrust according to the minimum input load. After determining the target matching inverting unit, the target matching inverting unit can be connected to the clock tree to be run for operation, thereby ensuring the timing requirements of the clock tree path in the chip.
  • the application scenario can be designed according to the maximum connection length of the clock tree path in the chip, the fan-out tree, and the input load to be driven; and the test circuit can be designed according to the application scenario; the reverse unit (INVD1) of the initial stage of the clock tree and the large-drive clock unit (INVD2) of the clock tree path are optimized for gate delay design; the thrust parameter of the small-drive standard unit of the PLL output stage is introduced, and the input load of the reverse unit (INVD1) of the initial stage is optimized; the thrust parameter of the reverse unit (INVD1) of the initial stage is introduced into the optimized large-drive clock unit (INVD2) to optimize the gate delay; the reverse unit (IVD1) is designed to have low input load, optimized driving force and adaptability, and is introduced into the clock tree application scenario solution to reduce a gate delay. and perform timing optimization.
  • the maximum clock tree connection length, the maximum fan-out number of the large-drive clock unit, and the driving force of the small-drive standard unit are determined according to the clock tree layout in the actual chip, and then the application scenario of the optimal driving force and the maximum load of the reverse unit is determined, and then the test circuit is designed according to the application scenario, that is, the application scenario of the maximum driving capability is simulated, and the corresponding fan-out number is connected to the output end of the large-drive clock unit that needs to test the delay time, so as to design the test circuit.
  • the reverse unit design of the initial stage of the clock tree can include: (a), the thrust parameter of the small-drive standard unit is brought into the test circuit for simulation test to obtain the minimum input load of the reverse unit; (b), the input load parameter of the large-drive clock unit is brought into the test circuit for simulation test to obtain the estimated thrust of the reverse unit; (c), according to the minimum input load and the estimated thrust, the input load and output thrust of the reverse unit are optimized to obtain the target reverse unit.
  • the target reverse unit can be stored in the layout in the form of a kit, and in the implementation mode of the present application, the layout will store different target reverse units for different test circuits.
  • the port position, port metal layer, port shape and port size of the target inverting unit in the layout will remain unchanged so that it can be easily replaced in subsequent applications.
  • the thrust parameters of the small drive standard unit will be used to optimize the timing of the initial stage reverse unit and the clock tree large drive unit.
  • the reverse unit can be an inverting unit.
  • the target inverting unit under each simulation application scenario is determined according to the simulation test results, thereby enabling the target inverting unit to be set in advance for multiple scenarios.
  • each target inverting unit is stored in a preset layout in the form of a preset kit, so that it can be directly queried and replaced in the preset layout in subsequent use, which is convenient for subsequent replacement.
  • the target matching inverting unit in the preset layout that matches the clock tree to be run is connected to the clock tree to be run for operation.
  • step S20 sequentially constructs a simulation test circuit corresponding to the clock tree in each simulation application scenario, and performs a simulation test on each simulation test circuit, including:
  • Step a traversing the clock tree in each simulation application scenario in turn, determining thrust parameters corresponding to small drive standard units in the traversed clock tree, and determining a minimum input load according to the thrust parameters;
  • Step b determining an input load parameter corresponding to a large drive clock unit in the traversed clock tree, and determining an estimated thrust according to the input load parameter;
  • Step c selecting a prediction inverting unit that satisfies the minimum input load and the estimated thrust from a plurality of preset inverting units;
  • Step d connecting the predicted inversion unit to the traversed clock tree to form a simulation test circuit, and performing a simulation test on the simulation test circuit.
  • the number of simulation application scenarios can be first determined by the clock tree gate delay optimization system, and after determining that the number is multiple, the clock tree in the chip under each simulation application scenario can be determined in turn and traversed. And when traversing, the thrust parameters corresponding to the small drive standard unit in the traversed clock tree can be determined.
  • the thrust parameter includes the thrust that the small drive standard unit can generate, and the load that can be pushed is determined according to the thrust parameter, and it is used as the minimum input load.
  • the large drive clock unit determines the input load parameter corresponding to the large drive clock unit in the traversed clock tree, that is, the input load parameter received by the input end of the large drive clock unit, wherein the large drive clock unit can generate thrust according to the input load parameter to drive the operation of subsequent clock units in the clock tree.
  • an inverting unit that meets the minimum input load and estimated thrust is selected from the multiple inverting units set in advance as the predicted inverting unit.
  • the inverting unit can generate thrust that meets the estimated thrust.
  • the predicted inverting unit can be connected to the traversed clock tree to form a simulation test circuit, and a simulation test is performed to obtain the simulation test results.
  • the simulation test result with the best clock tree timing delay effect is selected from each simulation test result, and the predicted inverting unit corresponding to the simulation test result with the best timing delay effect is used as the target inverting unit.
  • the small drive standard unit is connected to the inverting unit, and the inverting unit is connected to the large drive clock unit. When performing simulation tests, the inverting unit is continuously replaced.
  • the clock tree in each simulation application scenario is traversed in turn, and the minimum input load is determined according to the thrust parameters corresponding to the small drive standard unit in the traversed clock tree, and the estimated thrust is determined according to the input load parameters corresponding to the large drive clock unit, and then the predicted inverting unit is determined according to the estimated thrust and the minimum input load, and the predicted inverting unit is connected to the traversed clock tree to form a simulation test circuit, and a simulation test is performed, thereby ensuring the effective implementation of the simulation test.
  • step d connecting the predicted inversion unit to the traversed clock tree to form a simulation test circuit, and performing a simulation test on the simulation test circuit, includes:
  • Step d1 after there are a plurality of the prediction inversion units, traverse each of the prediction inversion units, connect the traversed prediction inversion units to the traversed clock tree, form a simulation test circuit, perform simulation test on the simulation test circuit, and obtain a simulation test result;
  • Step d2 determining the simulation test results corresponding to each of the predicted inverting units, and selecting a target simulation test result with the best timing delay from each of the simulation test results, and using the predicted inverting unit corresponding to the target simulation test result as the target inverting unit.
  • the predicted inverting unit after detecting that there is only one predicted inverting unit, the predicted inverting unit can be directly used as the target inverting unit. After detecting that there are multiple predicted inverting units, each predicted inverting unit can be simulated and tested. That is, each predicted inverting unit can be traversed, and the traversed predicted inverting unit can be connected to the traversed clock tree to form a simulation test circuit, and then the power is turned on to perform a simulation test to obtain a simulation test result. Among them, the simulation test result may include the timing delay result of the clock tree. And each predicted inverting unit is connected to the traversed clock tree for simulation testing.
  • the predicted inverting unit corresponding to the target simulation test result is used as the target inverting unit, and the target inverting unit is stored in the layout in the form of a kit.
  • each predicted inverting unit is simulated and tested to obtain a simulation test result, and the predicted inverting unit corresponding to the target simulation test result with the best timing delay is selected as the target inverting unit, thereby ensuring the effectiveness of determining the target inverting unit.
  • step b determining the input load parameter corresponding to the large drive clock unit in the traversed clock tree, includes:
  • Step b1 determining the fan-out number corresponding to the large driving clock unit in the traversed clock tree, and determining the maximum clock tree connection length corresponding to the traversed clock tree, and determining the input load parameter according to the maximum clock tree connection length and the fan-out number.
  • the fan-out number corresponding to the large drive clock unit in the traversed clock tree can be obtained.
  • the fan-out number can be the number corresponding to the large drive clock unit.
  • determine the maximum clock tree connection length corresponding to the traversed clock tree that is, the connection length of the branch with the most large drive clock units in the clock tree. Then determine the load value corresponding to the maximum clock tree connection length and the load value corresponding to the fan-out number, and use the sum of these two load values as the input load parameter.
  • the input load parameter is determined according to the fan-out number corresponding to the large driving clock unit in the traversed clock tree and the maximum clock tree connection length, thereby ensuring the validity of the determined input load parameter.
  • determining a target matching inverting unit in the preset layout that matches the clock tree to be executed includes:
  • Step e determining scenario parameters in the clock tree to be run, wherein the scenario parameters include at least one of an input load parameter and a thrust parameter of the clock tree to be run;
  • Step f using the target inverting unit in the preset layout that meets the scenario parameters as the target matching inverting unit that matches the clock tree to be run.
  • the clock tree gate delay optimization system selects When the target matching inverting unit is selected, it can be first screened according to the scenario parameters in the clock tree to be run in the current scenario. And because the scenario parameters include at least one of the input load parameters and thrust parameters of the clock tree to be run, when the target inverting unit is screened in the preset layout, it is also necessary to screen according to the actual scenario parameters.
  • scenario parameters include the input load parameters and thrust parameters of the clock tree to be run, where the thrust parameter is the thrust generated by the small drive standard unit
  • the minimum input load can be determined according to the thrust
  • the target thrust can be determined according to the input load parameters of the large drive clock unit in the clock tree to be run
  • the target inverting unit in the preset layout that can output the target thrust or output greater than the target thrust according to the minimum input load is selected as the target matching inverting unit.
  • connecting the target matching inverting unit to the clock tree to be run for operation includes:
  • Step g connecting the target matching inverting unit to the clock tree to be run, and driving the target matching inverting unit to run with the small driving standard unit in the clock tree to be run, and driving the large driving clock unit in the clock tree to be run with the target matching inverting unit.
  • the target matching inverting unit after determining the target matching inverting unit, can be connected to the clock tree to be run, and after the power is turned on, the target matching inverting unit is driven to run with a small drive standard unit through the PLL output end, and then the large drive clock unit in the clock tree to be run is driven to run through the target matching inverting unit.
  • the target matching inverting unit is connected to the clock tree to be operated, the small driving standard unit drives the target matching inverting unit to operate, and the target matching inverting unit drives the large driving clock unit to operate, thereby ensuring the effective operation of the clock tree.
  • the present application further provides a clock tree gate delay optimization system
  • the clock tree gate delay optimization system includes a simulation test circuit
  • the simulation test circuit includes:
  • a small driver standard unit connected to the clock signal input terminal in the chip
  • a target inverter connected to the small driver standard unit
  • a large driving clock unit is connected to the target inverter.
  • the clock tree gate delay optimization system includes a preset layout, and the preset layout is used to store the target inversion unit in the form of a preset kit.
  • the implementation methods of the clock tree gate delay optimization system of the present application are basically the same as the implementation methods of the clock tree gate delay optimization method described above, and will not be repeated here.
  • the present application also provides a clock tree gate delay optimization device, which includes a memory, a processor, and a clock tree gate delay optimization program stored in the memory and executable on the processor.
  • a clock tree gate delay optimization program stored in the memory and executable on the processor.
  • FIG8 is a schematic diagram of the structure of the clock tree gate delay optimization device of the present invention.
  • the clock tree gate delay optimization device includes a processor, and optionally also includes an internal bus, a network interface, and a memory.
  • the memory may include a memory, such as a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage, etc.
  • the clock tree gate delay optimization device may also include hardware required for other services.
  • the processor, the network interface, and the memory may be interconnected through an internal bus, and the internal bus may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc.
  • the bus may be divided into an address bus, a data bus, a control bus, etc.
  • FIG8 only uses a bidirectional arrow to represent the bus, but it does not mean that there is only one bus or one type of bus.
  • the memory is used to store programs.
  • the program may include a program code, and the program code includes a computer operation instruction.
  • the processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a shared resource access control device at the logical level.
  • the processor executes the program stored in the memory and is used to perform the steps of the clock tree gate delay optimization method.
  • the implementation of the clock tree gate delay optimization device of the present application is basically the same as the implementation of the clock tree gate delay optimization method described above, and will not be repeated here.
  • the present application also provides a computer-readable storage medium, on which a clock tree gate delay optimization program is stored.
  • a clock tree gate delay optimization program is stored on which a clock tree gate delay optimization program is stored.
  • the computer-readable storage medium implementation of the present application is basically the same as the implementations of the clock tree gate delay optimization method described above, and will not be described in detail here.
  • the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each implementation method of the present invention.
  • a storage medium such as ROM/RAM, magnetic disk, optical disk
  • a terminal device which can be a mobile phone, computer, server, or network device, etc.

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Abstract

本申请提供了一种时钟树闸延时优化方法、系统、设备及计算机存储介质，时钟树闸延时优化方法包括：确定多个仿真应用场景下的芯片中的时钟树；依次设置每个所述仿真应用场景下所述时钟树对应的仿真测试电路，并对每个所述仿真测试电路进行仿真测试；根据仿真测试结果确定每个所述仿真应用场景下所述时钟树对应的目标反相单元，并将所有所述目标反相单元以预设套件的形式存储至预设版图；在检测到存在待运行芯片中的待运行时钟树之后，确定所述预设版图中和所述待运行时钟树匹配的目标匹配反相单元，并将所述目标匹配反相单元接入至所述待运行时钟树进行运行。

Description

时钟树闸延时优化方法、系统、设备及计算机存储介质
相关申请的交叉引用
本申请要求2022年12月12日提交给中国专利局的第202211598446.X号专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本申请涉及但不限于芯片技术领域。
背景技术
在IC(Integrated Circuit，集成电路)设计中，芯片中的时钟树路径采用大驱动时钟单元来降低顶层时钟延迟，来减小OCV(On-Chip Variation，片上误差)带来的影响，而大驱动时钟单元的输入负载非常大，因此一般都会在时钟树初始的时候采用定制的大驱动时钟单元(如大驱动Buffer(缓冲器))来推动大驱动反相器。然而用于推动大驱动反相器的定制大驱动Buffer一般具有较高的闸延时，可能会影响芯片时序的快速收敛。
发明内容
本申请提供一种时钟树闸延时优化方法应用于时钟树闸延时优化系统，包括：确定多个仿真应用场景下的芯片中的时钟树；依次设置每个所述仿真应用场景下所述时钟树对应的仿真测试电路，并对每个所述仿真测试电路进行仿真测试；根据仿真测试结果确定每个所述仿真应用场景下所述时钟树对应的目标反相单元，并将所有所述目标反相单元以预设套件的形式存储至预设版图；在检测到存在待运行芯片中的待运行时钟树之后，确定所述预设版图中和所述待运行时钟树匹配的目标匹配反相单元，并将所述目标匹配反相单元接入至所述待运行时钟树进行运行。
本申请还提供一种时钟树闸延时优化系统，时钟树闸延时优化 系统包括仿真测试电路，所述仿真测试电路包括：小驱动标准单元，与芯片中的时钟信号输入端连接；目标反相器，与所述小驱动标准单元连接；大驱动时钟单元，与所述目标反相器连接。
本申请还提供一种时钟树闸延时优化设备，所述时钟树闸延时优化设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的时钟树闸延时优化程序，所述时钟树闸延时优化程序被执行时实现如本文所述的时钟树闸延时优化方法的步骤。
本申请还提供一种计算机存储介质，所述计算机存储介质上存储有时钟树闸延时优化程序，所述时钟树闸延时优化程序被处理器执行时实现如本文所述的时钟树闸延时优化方法的步骤。
附图说明
图1是本申请时钟树闸延时优化方法的流程示意图；
图2是时钟树中具有大驱动Buffer的示意图；
图3是本申请时钟树闸延时优化方法中具有反向单元的时钟树的示意图；
图4是本申请时钟树闸延时优化方法中预设版图的示意图；
图5是本申请时钟树闸延时优化方法中时钟树优化的示意图；
图6是本申请时钟树闸延时优化方法的流程示意图；
图7是本申请时钟树闸延时优化系统的示意图；
图8是本申请时钟树闸延时优化设备的结构示意图。
具体实施方式
应当理解，此处所描述的示例性实施方式仅仅用以解释本发明，并不用于限定本发明。
由于随着先进工艺制程不断演进，芯片规模尺寸越来越大，工作频率、速度越来越快；芯片时钟树关键路径下的时序要求对整个芯片的时序收敛至关重要，如果能够在时钟树的关键路径下减少闸延时，则能够直接且有效的优化整体时钟频率、提高芯片效能，从而保证整 个芯片时序的快速收敛。
一般在时钟树路径采用大驱动时钟单元来降低顶层时钟延迟，有助于减小OCV带来的影响，但大驱动时钟单元的输入负载非常大，因此会在时钟树初始的时候采用定制大驱动Buffer来推动大驱动反相器，由于大驱动Buffer具有较低的输入负载的优势，从而可以在PLL(锁相环电路)输出端使用一个小驱动的标准单元即可推动定制大驱动Buffer，再由大驱动Buffer来推动下一级时钟树路径的大驱动反相器，以此做法来保证芯片时钟树路径的时序要求，从而得到更好的芯片性能。例如，如图2所示，包括输出端PLL，小驱动标准单元(包括延迟x)，大驱动Buffer(包括延迟y和延迟z)，以及时钟单元。
然而用于推动大驱动反相器的定制大驱动Buffer一般具有较高的闸延时，因此在本申请实施方式中，是根据在芯片中的时钟树路径的输出端能以一个小驱动的标准单元能够推动的负载为出发点，设置一个低输入负载的大驱动反相单元(如目标反相单元)，同时以此反相单元来推动时钟树路径中的大驱动时钟单元。其中，可以将大驱动反相单元设置在时钟树路径的起点位置。相对于采用大驱动Buffer来进行推动的时钟树路径，直接减少了一个闸延时，并能有效且直接的优化时钟树关键路径延时，能提高效能、更好的达到时序收敛。并且本申请实施方式是可以进行反相单元输入负载与输出推力之最优化适配性设置，并能定制适配驱动力，最优化推动力的闸延时。并在确定对应的目标反相单元后，可以以套件形式对目标反相单元进行存储。并能在时钟树路径运行时，将目标反相单元接入时钟树路径，用以推动下一级的大驱动时钟单元，得到减少一个反相器闸延时的效果，即降低了时钟树中的闸延时。例如，如图3所示，包括PLL输出端、小驱动标准单元(包括延迟x)；反向单元(包括延迟y)和时钟单元。此时图3中的闸延时＝x+y，而图2中的闸延时＝x+y+z；因此本实施方式相对于采用大驱动Buffer的方式明显少了一个闸延时。
此外，在时钟树路径中如果有长线连接，虽然可以采用大驱动时钟单元来推动长线，但由于大驱动时钟单元的推力大，因此输入负载 也特别大，因此无法放在第一级被推动。在实现上也就必须使用大驱动Buffer作为第一级，因为Buffer的输入负载较小，容易被推动。而Buffer与反相器的差别在于多了一个闸延时，因此本申请实施方式的出发点就在于实现一个小输入负载的大驱动反向单元，如此，同时具备了小的输入负载(易于被推动)同时拥有大驱动力(易于推动长线)的特点。并且在时钟树路径下，与大驱动Buffer的方式相较减少了一个闸延时。另外，本申请实施方式由于使用了套件形式，易于替换、更容易实现。
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请的一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
参照图1，本申请提供一种时钟树闸延时优化方法，可以应用于时钟树闸延时优化系统，所述方法可以包括步骤S10至S40。
在步骤S10，确定多个仿真应用场景下的芯片中的时钟树。
由于5G通讯、高速CPU、GPU、DSP等大芯片的时钟树比较特殊，一般是H Tree，具有大驱动时钟单元需求，因此对于具有大驱动时钟单元需求的应用场景可以采用本实施方式进行。并且在本实施方式中，为了后续芯片中的时钟树在实际的应用场景中能直接以最优的反相器进行运行，以降低时钟树中的闸延时，会提前设置多个仿真应用场景，并对每个仿真应用场景下的芯片中的时钟树进行仿真测试。而在构建仿真应用场景时可以是根据时钟树的构造不同进行设置的仿真应用场景。也就是在本实施方式中，可以根据不同的时钟树连线长度、或根据不同的时钟树的扇出数、或者根据时钟树中大驱动时钟单元的最大扇出数的不同、或者根据不同的小驱动标准单元的驱动力来构建多个仿真应用场景。例如，根据实际芯片中时钟树布局，确定最大的时钟树连线长度、大驱动时钟单元最大的扇出个数、小驱动标准单元的驱动力，进而确定反向单元最优驱动力以及最大负载的应用 场景。并在构建好仿真应用场景后，时钟树闸延时优化系统需要确定仿真应用场景下的芯片中的时钟树，以便对时钟树进行仿真测试。其中，时钟树可以是芯片中的时钟结构。
在步骤S20，依次构建每个所述仿真应用场景下所述时钟树对应的仿真测试电路，并对每个所述仿真测试电路进行仿真测试。
在本实施方式中，在构建多个仿真应用场景后，并且时钟树闸延时优化系统确定每个仿真应用场景下的时钟树后，若需要对各个时钟树进行仿真测试，则需要为每个时钟树都构建与之对应的仿真测试电路。
并且在构建完成仿真测试电路，并进行仿真测试时，可以是按照如图3所示的方式进行，在图3中包括PLL输出端、小驱动标准单元(包括延迟x)；反向单元(包括延迟y)和时钟单元，并且在进行仿真测试时，是PLL输出端以一个小驱动标准单元能推动的负载为出发点，推动反向单元，再通过反向单元来推动时钟单元。其中，时钟单元可以是大驱动时钟单元。而且在进行仿真测试时，可以提前获取各个型号的反向单元，并将每个型号的反向单元带入至仿真测试电路中进行测试，如对图3中的反向单元进行替换。以得到每个反向单元对应的仿真测试结果。
在步骤S30，根据仿真测试结果确定每个所述仿真应用场景下所述时钟树对应的目标反相单元，并将所有所述目标反相单元以预设套件的形式存储至预设版图。
在本实施方式中，在时钟树闸延时优化系统完成对时钟树的仿真测试后，会获取到相应的仿真测试结果，并在各个仿真测试结果中选择效果最好的反向单元作为该仿真应用场景下时钟树对应的目标反相单元。并且针对每个仿真测试场景下的时钟树，时钟树闸延时优化系统可以采用相同的方式来获取与之对应的目标反相单元。并且在每确定一个目标反相单元后，就可以将目标反相单元以提前设置好的套件的形式存储至提前设置好的版图中。其中，版图中的目标反相单元的端口位置、端口金属层、端口形状和端口大小都保持不变。例如，如图4所示，在版图中存在多个目标反相单元，如Driving A、Driving  B、Driving C、Driving X、Driving Z等。并且每个目标反相单元的IN接口和OUT接口都保持不变。其中，目标反相单元可以是时钟树中输入负载与输出推力之间的最优适配的反相单元。其中，反相单元或反向单元可以是反相器。其中，预设版图可以是提前设置的反相器版图。
在步骤S40，在检测到存在待运行芯片中的待运行时钟树之后，确定所述预设版图中和所述待运行时钟树匹配的目标匹配反相单元，并将所述目标匹配反相单元接入至所述待运行时钟树进行运行。
在本实施方式中，当时钟树闸延时优化系统在进行实际的应用中，发现在某一场景下，存在有待运行芯片，并且此时待运行芯片中的时钟树还未运行，则可以将此时钟树作为待运行时钟树。此时就可以确定该待运行时钟树中小驱动标准单元所能提供的最小推力，以便根据最小推力确定待运行时钟树中所需要的反相单元的最低输入负载。以及待运行时钟树中大驱动时钟单元对应的负载参数，以便根据负载参数确定待运行时钟树中所需要的反相单元能提供的预估推力。然后在根据最低输入负载和预估推力在预设版图中选择和待运行时钟树匹配的目标反相单元，并将其作为目标匹配反相单元。而且，目标匹配反相单元正好能根据最低输入负载来生成预估推力。并在确定目标匹配反相单元后，就可以将目标匹配反相单元接入到待运行时钟树中进行运行，从而保障芯片中时钟树路径的时序要求。
此外，为辅助理解本实施方式中的时钟树闸延时优化原理理解，下面进行举例说明。
例如，如图5所示，可以根据芯片中时钟树路径的最大连线长度、扇出树和欲推动的输入负载设计应用场景；并根据应用场景设计测试电路；时钟树初始级的反向单元(INVD1)与时钟树路径大驱动时钟单元(INVD2)最优化闸延时设计；PLL输出级小驱动标准单元推力参数带入，并优化初始级的反向单元(INVD1)的输入负载；初始级反向单元(INVD1)推力参数带入优化大驱动时钟单元(INVD2)，进行优化闸延时；设计得到反向单元(IVD1)具备低输入负载、最优化驱动力与适配性，并带入时钟树应用场景方案，用以减少一个闸延 时并进行时序优化。
也就是在本申请实施方式中，会根据实际芯片中时钟树布局，确定最大的时钟树连线长度、大驱动时钟单元最大的扇出个数、小驱动标准单元的驱动力，进而确定反向单元最优驱动力以及最大负载的应用场景，再根据应用场景进行测试电路的设计，也就是模拟最大驱动能力的应用场景，并在需要测试延迟时间的大驱动时钟单元的输出端连接相应的扇出个数，以此设计测试电路。然后进行时钟树初始级的反向单元设计，可以包括：(a)、小驱动标准单元推力参数带入至测试电路中进行仿真测试，得到反相单元的最低输入负载；(b)、大驱动时钟单元输入负载参数带入至测试电路中进行仿真测试，得到反相单元的预估推力；(c)、根据最低输入负载和预估推力进行反相单元输入负载与输出推力之最优化适配，以得到目标反相单元。并在确定目标反相单元后，可以将目标反相单元以套件形式存入至版图中，并且在本申请实施方式中，版图会针对不同的测试电路存储不同的目标反相单元。且版图中的目标反相单元的端口位置、端口金属层、端口形状和端口大小都会保持不变，以便后续在应用时能进行轻易的替换。而且在对测试电路中，对反相单元进行时序优化时，会使用小驱动标准单元推力参数带入，进行初始级反向单元以及时钟树大驱动单元的时序优化，同时针对测试环境以及仿真应用场景的搭建，用于仿真时序与闸延时进行迭代，得到最优化的时序延时条件。其中，反向单元可以是反相单元。
在本实施方式中，通过确定多个仿真应用场景下芯片中的时钟树，并对每个仿真应用场景下时钟树对应的仿真测试电路进行仿真测试，根据仿真测试结果确定每个仿真应用场景下的目标反相单元，从而可以实现提前设置应用于多个场景下的目标反相单元。并且是将每个目标反相单元以预设套件形式存储至预设版图，从而可以实现在后续使用中直接在预设版图中进行查询替换，便于后续的替换。并且在检测到待运行时钟树之后，将预设版图中和待运行时钟树匹配的目标匹配反相单元接入至待运行时钟树进行运行。相对于传统的采用大驱动Buffer来进行推动的时钟树路径，明显减少了一个闸延时，能有 效地优化时钟树的关键路径延时，实现了降低时钟树中的闸延时。
基于上述本申请的实施方式，提出本申请时钟树闸延时优化方法的另一实施方式，在本实施方式中，参照图6，上述步骤S20，依次构建每个所述仿真应用场景下所述时钟树对应的仿真测试电路，并对每个所述仿真测试电路进行仿真测试，包括：
步骤a，依次遍历每个所述仿真应用场景下的所述时钟树，确定遍历的所述时钟树中小驱动标准单元对应的推力参数，并根据所述推力参数确定最低输入负载；
步骤b，确定遍历的所述时钟树中大驱动时钟单元对应的输入负载参数，并根据所述输入负载参数确定预估推力；
步骤c，在预设的多个反相单元中选择满足所述最低输入负载和所述预估推力的预测反相单元；
步骤d，将所述预测反相单元接入至遍历的所述时钟树，形成仿真测试电路，对所述仿真测试电路进行仿真测试。
在本实施方式中，在构建仿真测试电路，进行仿真测试时，可以先通过时钟树闸延时优化系统确定仿真应用场景的数量，并在确定数量为多个之后，可以依次确定每个仿真应用场景下芯片中的时钟树，并进行遍历。并且在进行遍历时，可以确定遍历的时钟树中小驱动标准单元对应的推力参数。其中，推力参数包括小驱动标准单元能产生的推力，并根据推力参数来确定能推动的负载，并将其作为最低输入负载。然后再确定该遍历的时钟树中，大驱动时钟单元对应的输入负载参数，即大驱动时钟单元输入端接收到的输入负载参数，其中，大驱动时钟单元能根据输入负载参数产生推力推动时钟树中后续时钟单元的运行。
然后在提前设置的多个反相单元中选择满足最低输入负载和预估推力的反相单元作为预测反相单元。此时，若将最低输入负载输入至反相单元中，反相单元可以产生满足预估推力的推力。并在检测到预测反相单元存在多个之后，就可以将预测反相单元接入至遍历的时钟树中，形成仿真测试电路，并进行仿真测试，得到仿真测试结果， 然后在各个仿真测试结果中选择时钟树时序延时效果最好的仿真测试结果，并将时序延时效果最好的仿真测试结果对应的预测反相单元作为目标反相单元。其中，仿真测试电路中，小驱动标准单元连接反相单元，反相单元再和大驱动时钟单元连接。在进行仿真测试时，对反相单元进行不断替换。
在本实施方式中，通过依次遍历每个仿真应用场景下的时钟树，并根据遍历的时钟树中小驱动标准单元对应的推力参数确定最低输入负载，并根据大驱动时钟单元对应的输入负载参数确定预估推力，再根据预估推力和最低输入负载确定预测反相单元，将预测反相单元接入至遍历的时钟树中形成仿真测试电路，并进行仿真测试，从而保障了仿真测试的有效进行。
在一实施方式中，步骤d，将所述预测反相单元接入至遍历的所述时钟树，形成仿真测试电路，对所述仿真测试电路进行仿真测试，包括：
步骤d1，在存在多个所述预测反相单元之后，遍历每个所述预测反相单元，将遍历的所述预测反相单元接入至遍历的所述时钟树，形成仿真测试电路，对所述仿真测试电路进行仿真测试，得到仿真测试结果；
步骤d2，确定每个所述预测反相单元对应的仿真测试结果，并在每个所述仿真测试结果中选择时序延时最优的目标仿真测试结果，并将所述目标仿真测试结果对应的预测反相单元作为目标反相单元。
在本实施方式中，在检测到只存在一个预测反相单元之后，就可以直接将此预测反相单元作为目标反相单元。在检测到存在多个预测反相单元之后，就可以对每个预测反相单元进行仿真测试。即可以对每个预测反相单元进行遍历，并将遍历的预测反相单元接入至遍历的时钟树中，形成仿真测试电路，再接通电源进行仿真测试，以得到仿真测试结果。其中，仿真测试结果可以包括时钟树的时序延时结果。并且将每个预测反相单元都接入至遍历的时钟树中进行仿真测试。以获取每个预测反相单元对应的仿真测试结果，然后在各个仿真测试结果中选择时序延时最优(即最少)的仿真测试结果，将其作为目标仿 真测试结果。并将此目标仿真测试结果对应的预测反相单元作为目标反相单元，并将目标反相单元以套件的形式存储至版图中。
在本实施方式中，通过在检测到存在多个预测反相单元之后，对每个预测反相单元进行仿真测试，得到仿真测试结果，并选择时序延时最优的目标防真测试结果对应的预测反相单元作为目标反相单元，从而保障了确定目标反相单元的有效性。
在一实施方式中，步骤b，确定遍历的所述时钟树中大驱动时钟单元对应的输入负载参数，包括：
步骤b1，确定遍历的所述时钟树中大驱动时钟单元对应的扇出数，并确定遍历的所述时钟树对应的最大时钟树连线长度，根据所述最大时钟树连线长度和所述扇出数确定输入负载参数。
在本实施方式中，在确定大驱动时钟单元对应的输入负载参数时，需要根据大确定时钟单元后续需要进行推动的负载来进行确定。即可以获取遍历的时钟树中大驱动时钟单元对应的扇出数。其中，扇出数可以是大驱动时钟单元对应的数量。并确定遍历的时钟树对应的最大时钟树连线长度，也就是时钟树中具有最多的大驱动时钟单元的分支的连线长度。然后再确定最大时钟树连线长度对应的负载数值和扇出数对应的负载数值，并将这两个负载数值之间的和值作为输入负载参数。
在本实施方式中，通过根据遍历的时钟树中大驱动时钟单元对应的扇出数和最大时钟树连线长度来确定输入负载参数，从而保障了确定的输入负载参数的有效性。
在一实施方式中，确定所述预设版图中和所述待运行时钟树匹配的目标匹配反相单元，包括：
步骤e，确定所述待运行时钟树中的场景参数，其中，所述场景参数包括所述待运行时钟树的输入负载参数和推力参数中的至少一种；
步骤f，将所述预设版图中满足所述场景参数的目标反相单元作为和所述待运行时钟树匹配的目标匹配反相单元。
在本实施方式中，在时钟树闸延时优化系统在预设版图中筛选 目标匹配反相单元时，可以先根据当前场景下待运行时钟树中的场景参数进行筛选。并且由于场景参数至少包括待运行时钟树的输入负载参数和推力参数中的至少一种，因此在预设版图中进行目标反相单元筛选时，也需要根据实际的场景参数进行筛选，若场景参数包括待运行时钟树的输入负载参数和推力参数，其中，推力参数为小驱动标准单元产生的推力，此时就可以根据该推力确定最小输入负载，再根据待运行时钟树中大驱动时钟单元的输入负载参数来确定目标推力，并将预设版图中满足能根据最小输入负载输出目标推力或输出大于目标推力的目标反相单元，并将其作为目标匹配反相单元。
在本实施方式中，通过根据待运行时钟树中的场景参数在预设版图中选择目标匹配反相单元，从而保障了选择的目标匹配反相单元的有效性。
在一实施方式中，将所述目标匹配反相单元接入至所述待运行时钟树进行运行，包括：
步骤g，将所述目标匹配反相单元接入至所述待运行时钟树，并以所述待运行时钟树中的小驱动标准单元驱动所述目标匹配反相单元运行，以所述目标匹配反相单元驱动所述待运行时钟树中的大驱动时钟单元运行。
在本实施方式中，通过在确定目标匹配反相单元之后，就可以将目标匹配反相单元接入至待运行时钟树，并在接通电源后，且通过PLL输出端以小驱动标准单元驱动目标匹配反相单元运行，再通过目标匹配反相单元驱动所述待运行时钟树中的大驱动时钟单元运行。
在本实施方式中通过将目标匹配反相单元接入至待运行时钟树，以小驱动标准单元驱动目标匹配反相单元运行，并以目标匹配反相单元驱动大驱动时钟单元运行，从而保障了时钟树的有效运行。
此外，参照图7，本申请还提供一种时钟树闸延时优化系统，时钟树闸延时优化系统包括仿真测试电路，所述仿真测试电路包括：
小驱动标准单元，与芯片中的时钟信号输入端连接；
目标反相器，与所述小驱动标准单元连接；
大驱动时钟单元，与所述目标反相器连接。
进一步地，时钟树闸延时优化系统包括预设版图，所述预设版图，用于以预设套件的形式存储目标反相单元。
本申请时钟树闸延时优化系统的实施方式与上述时钟树闸延时优化方法各实施方式基本相同，在此不再赘述。
此外，本申请还提供一种时钟树闸延时优化设备，时钟树闸延时优化设备包括存储器、处理器及存储在存储器上并可在处理器上运行的时钟树闸延时优化程序，时钟树闸延时优化程序被处理器执行时实现如上述的时钟树闸延时优化方法的步骤。
此外，图8为本发明的时钟树闸延时优化设备的结构示意图，如图8所示，在一个实施方式中，在硬件层面，该时钟树闸延时优化设备包括处理器，可选地还包括内部总线、网络接口、存储器。其中，存储器可包含内存，例如高速随机存取存储器(Random-Access Memory，RAM)，也还可包括非易失性存储器(non-volatile memory)，例如至少1个磁盘存储器等。当然，该时钟树闸延时优化设备还可包括其他业务所需要的硬件。处理器、网络接口和存储器可以通过内部总线相互连接，该内部总线可以是ISA(Industry Standard Architecture，工业标准体系结构)总线、PCI(Peripheral Component Interconnect，外设部件互连标准)总线或EISA(Extended Industry Standard Architecture，扩展工业标准结构)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图8中仅用一个双向箭头表示总线，但并不表示仅有一根总线或一种类型的总线。存储器，用于存储程序。示例性地，程序可以包括程序代码，所述程序代码包括计算机操作指令。处理器从非易失性存储器中读取对应的计算机程序到存储器中然后运行，在逻辑层面上形成共享资源访问控制装置。处理器，执行存储器所存放的程序，并用于执行上述时钟树闸延时优化方法的步骤。
本申请时钟树闸延时优化设备实施方式与上述时钟树闸延时优化方法各实施方式基本相同，在此不再赘述。
此外，为实现上述目的，本申请还提供一种计算机可读存储介质，计算机可读存储介质上存储有时钟树闸延时优化程序，时钟树闸 延时优化程序被处理器执行时实现如上述的时钟树闸延时优化方法的步骤。
本申请计算机可读存储介质实施方式与上述时钟树闸延时优化方法各实施方式基本相同，在此不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本发明实施方式序号仅仅为了描述，不代表实施方式的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施方式方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明各个实施方式所述的方法。
以上仅为本发明的示例性实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种时钟树闸延时优化方法，应用于时钟树闸延时优化系统，包括：
    确定多个仿真应用场景下的芯片中的时钟树；
    依次构建每个所述仿真应用场景下所述时钟树对应的仿真测试电路，并对每个所述仿真测试电路进行仿真测试；
    根据仿真测试结果确定每个所述仿真应用场景下所述时钟树对应的目标反相单元，并将所有所述目标反相单元以预设套件的形式存储至预设版图；
    在检测到存在待运行芯片中的待运行时钟树之后，确定所述预设版图中和所述待运行时钟树匹配的目标匹配反相单元，并将所述目标匹配反相单元接入至所述待运行时钟树进行运行。
  2. 如权利要求1所述的时钟树闸延时优化方法，其中，依次构建每个所述仿真应用场景下所述时钟树对应的仿真测试电路，并对每个所述仿真测试电路进行仿真测试，包括：
    依次遍历每个所述仿真应用场景下的所述时钟树，确定遍历的所述时钟树中小驱动标准单元对应的推力参数，并根据所述推力参数确定最低输入负载；
    确定遍历的所述时钟树中大驱动时钟单元对应的输入负载参数，并根据所述输入负载参数确定预估推力；
    在预设的多个反相单元中选择满足所述最低输入负载和所述预估推力的预测反相单元；
    将所述预测反相单元接入至遍历的所述时钟树，形成仿真测试电路，对所述仿真测试电路进行仿真测试。
  3. 如权利要求2所述的时钟树闸延时优化方法，其中，将所述预测反相单元接入至遍历的所述时钟树，形成仿真测试电路，对所述仿真测试电路进行仿真测试，包括：
    在存在多个所述预测反相单元之后，遍历每个所述预测反相单元，将遍历的所述预测反相单元接入至遍历的所述时钟树，形成仿真测试电路，对所述仿真测试电路进行仿真测试，得到仿真测试结果；
    确定每个所述预测反相单元对应的仿真测试结果，并在每个所述仿真测试结果中选择时序延时最优的目标仿真测试结果，并将所述目标仿真测试结果对应的预测反相单元作为目标反相单元。
  4. 如权利要求2所述的时钟树闸延时优化方法，其中，所述确定遍历的所述时钟树中大驱动时钟单元对应的输入负载参数，包括：
    确定遍历的所述时钟树中大驱动时钟单元对应的扇出数，并确定遍历的所述时钟树对应的最大时钟树连线长度，根据所述最大时钟树连线长度和所述扇出数确定输入负载参数。
  5. 如权利要求1所述的时钟树闸延时优化方法，其中，所述确定所述预设版图中和所述待运行时钟树匹配的目标匹配反相单元，包括：
    确定所述待运行时钟树中的场景参数，其中，所述场景参数包括所述待运行时钟树的输入负载参数和推力参数中的至少一种；
    将所述预设版图中满足所述场景参数的目标反相单元作为和所述待运行时钟树匹配的目标匹配反相单元。
  6. 如权利要求1所述的时钟树闸延时优化方法，其中，将所述目标匹配反相单元接入至所述待运行时钟树进行运行，包括：
    将所述目标匹配反相单元接入至所述待运行时钟树，并以所述待运行时钟树中的小驱动标准单元驱动所述目标匹配反相单元运行，以所述目标匹配反相单元驱动所述待运行时钟树中的大驱动时钟单元运行。
  7. 一种时钟树闸延时优化系统，其中，所述时钟树闸延时优化系统包括仿真测试电路，所述仿真测试电路包括：
    小驱动标准单元，与芯片中的时钟信号输入端连接；
    目标反相器，与所述小驱动标准单元连接；
    大驱动时钟单元，与所述目标反相器连接。
  8. 一种时钟树闸延时优化系统，其中，所述时钟树闸延时优化系统包括预设版图，所述预设版图，用于以预设套件的形式存储目标反相单元。
  9. 一种时钟树闸延时优化设备，其中，所述时钟树闸延时优化设备包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的时钟树闸延时优化程序，所述时钟树闸延时优化程序被执行时实现如权利要求1-6任一项所述的时钟树闸延时优化方法的步骤。
  10. 一种计算机存储介质，其中，所述计算机存储介质上存储有时钟树闸延时优化程序，所述时钟树闸延时优化程序被处理器执行时实现如权利要求1-6任一项所述的时钟树闸延时优化方法的步骤。
PCT/CN2023/136147 2022-12-12 2023-12-04 时钟树闸延时优化方法、系统、设备及计算机存储介质 WO2024125340A1 (zh)

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CN110619166A (zh) * 2019-09-09 2019-12-27 中国人民解放军国防科技大学 一种低功耗时钟树的设计方法
CN110807295A (zh) * 2019-10-23 2020-02-18 上海大学 集成电路时钟树综合优化方法

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US20070016833A1 (en) * 2005-07-18 2007-01-18 Chih-Wen Lin Method For Performing Built-In And At-Speed Test In System-On-Chip
CN107908884A (zh) * 2017-11-20 2018-04-13 北京华大九天软件有限公司 一种通过调整时钟树分支改善时序的交互式eco方法
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