WO2024124365A1

WO2024124365A1 - Methods and apparatus to perform convert operations using direct memory access

Info

Publication number: WO2024124365A1
Application number: PCT/CN2022/138276
Authority: WO
Inventors: Ding ZHANG; Hongyu Wang
Original assignee: Intel Corporation
Filing date: 2022-12-12
Publication date: 2024-06-20

Abstract

Methods, apparatus, systems, and articles of manufacture for performance of convert operations using direct memory access are disclosed. Example instructions cause processor circuitry to acquire a source tensor from a memory, the source tensor including data and acquired through direct memory access from the memory, perform a data conversion on the source tensor to obtain a destination tensor, the performing of the data conversion implemented through direct memory access, and apply the destination tensor to the memory, the destination tensor applied through direct memory access to the memory.

Description

METHODS AND APPARATUS TO PERFORM CONVERT OPERATIONS USING DIRECT MEMORY ACCESS

FIELD OF THE DISCLOSURE

This disclosure relates generally to memory operations in computing devices and, more particularly, to methods and apparatus to perform convert operations using direct memory access.

BACKGROUND

Convert operations are applied to neural networks (e.g., machine learning models, artificial intelligence, etc. ) to perform element-wise conversions on input tensors to a defined destination data type. Convert operations are generally implemented at runtime (e.g., a phase of a computer program in which the program is run or executed on a computer system) via instructions issued by a central processing unit (CPU) .

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of an example direct memory access platform.

FIG. 2 is a block diagram of an example memory conversion circuitry.

FIG. 3 is a flowchart representative of example machine readable instructions and/or example operations that may be executed by example processor circuitry to implement the example direct memory access platform of FIG. 1.

FIG. 4 is a flowchart representative of example machine readable instructions and/or example operations that may be executed by example processor circuitry to implement the example memory conversion circuitry of FIG. 2.

FIG. 5 is a flowchart representative of example machine readable instructions and/or example operations that may be executed by example processor circuitry to implement example data type conversion circuitry as represented in FIG. 2.

FIG. 6 is a block diagram of an example processing platform including processor circuitry structured to execute the example machine readable instructions and/or the example operations of FIG. 3 to implement the example direct memory access platform of FIG. 1 and the example memory conversion circuitry of FIG. 2.

FIG. 7 is a block diagram of an example implementation of the processor circuitry of FIG. 6.

FIG. 8 is a block diagram of another example implementation of the processor circuitry of FIG. 6.

FIG. 9 is a block diagram of an example software distribution platform (e.g., one or more servers) to distribute software (e.g., software corresponding to the example machine readable instructions of FIGS. 3, 4, and/or 5) to client devices associated with end users and/or consumers (e.g., for license, sale, and/or use) , retailers (e.g., for sale, re-sale, license, and/or sub-license) , and/or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and/or to other end users such as direct buy customers) .

In general, the same reference numbers will be used throughout the drawing (s) and accompanying written description to refer to the same or like parts. The figures are not to scale.

Unless specifically stated otherwise, descriptors such as “first, ” “second, ” “third, ” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third. ” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.

As used herein, the phrase “in communication, ” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

As used herein, “processor circuitry” is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation (s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors) , and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors) . Examples of processor circuitry include programmable microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs) , Graphics Processor Units (GPUs) , Digital Signal Processors (DSPs) , XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs) . For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface (s) (API (s) ) that may assign computing task (s) to whichever one (s) of the multiple types of processor circuitry is/are best suited to execute the computing task (s) .

DETAILED DESCRIPTION

Neural networks usually perform convert operations by issuing instructions from a CPU to retrieve a source tensor (e.g., the tensor in which the convert operation is to be performed on) from memory (e.g., a Connection MatrixX SRAM memory (CMX) ) and send the source tensor to a kernel (e.g., the main layer of software between the operating system (OS) and underlying computer hardware such as the CPU, memory, etc. ) to perform the convert operation on the source tensor. Once the convert operation is performed on the source tensor to transform the source tensor into a destination tensor, the destination tensor is then sent back to the memory.

In using a separate kernel to perform the convert operations, the neural network suffers from additional clock cycles needed to perform the transfer of information to and from the kernel. In large-scale convert operations (e.g., converting a large amount of data) , these clock cycles escalate and become cumbersome to the neural network’s efficiency and utilizes computing resources that could be used elsewhere in the neural network. Therefore, there exists a need to optimize convert operations in neural networks to eliminate the need for an additional kernel operation.

FIG. 1 is a schematic illustration of an example direct memory access platform 100 to perform a convert operation through direct memory access (DMA) . The example direct memory access platform 100 includes a memory 110, source memory circuitry 120, memory conversion circuitry 130, and destination memory circuitry 140.

The source memory circuitry 120, memory conversion circuitry 130, and destination memory circuitry 140of FIG. 1 may be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc. ) by processor circuitry such as a central processing unit executing instructions. Additionally or alternatively, the source memory circuitry 120, memory conversion circuitry 130, and destination memory circuitry 140 of FIG. 1 may be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc. ) by an ASIC or an FPGA structured to perform operations corresponding to the instructions. It should be understood that some or all of the circuitry of FIG. 1 may, thus, be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads executing concurrently on hardware and/or in series on hardware. Moreover, in some examples, some or all of the circuitry of FIG. 1 may be implemented by microprocessor circuitry executing instructions to implement one or more virtual machines and/or containers.

The memory 110 communicates directly with the source memory circuitry 120 to send a source tensor (e.g., a source data point) to the source memory circuitry 120. Additionally, the memory 110 communicates with the destination memory circuitry 140 to receive a destination tensor (e.g., a converted source tensor to a different data type) from the destination memory circuitry 140. In the examples disclosed herein, the memory 110 can be any one or more of a volatile memory (e.g., Random Access Memory (RAM) of any type, etc. ) , or a non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM) , FLASH memory, an HDD, an SSD, etc. ) . In some examples, the direct memory access platform 100 is housed directly on a memory device in which the memory 110 is stored (e.g., on a processor housed on the memory device) .

The source memory circuitry 120 acquires the source tensor from the memory 110. In some examples, the source memory circuitry 120 is instantiated by processor circuitry executing source memory instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 3.

In some examples, the direct memory access platform 100 includes means for acquiring a source tensor from the memory 110. For example, the means for acquiring may be implemented by source memory circuitry 120. In some examples, the source memory circuitry 120 may be instantiated by processor circuitry such as the example processor circuitry 612 of FIG. 6. For instance, the source memory circuitry 120 may be instantiated by the example microprocessor 700 of FIG. 7 executing machine executable instructions such as those implemented by at least block 310 of FIG. 3. In some examples, the source memory circuitry 120 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry 800 of FIG. 8 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the source memory circuitry 120 may be instantiated by any other combination of hardware, software, and/or firmware. For example, the source memory circuitry 120 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

The memory conversion circuitry 130 performs a data conversion on the source tensor to obtain the destination tensor. In some examples, the memory conversion circuitry 130 is instantiated by processor circuitry executing memory conversion instructions and/or configured to perform operations such as those represented by the flowcharts of FIGS. 3, 4, and/or 5.

In some examples, the direct memory access platform 100 includes means for performing a data conversion on the source tensor to obtain the destination tensor. For example, the means for performing may be implemented by memory conversion circuitry 130. In some examples, the memory conversion circuitry 130 may be instantiated by processor circuitry such as the example processor circuitry 612 of FIG. 6. For instance, the memory conversion circuitry 130 may be instantiated by the example microprocessor 700 of FIG. 7 executing machine executable instructions such as those implemented by at least blocks 320 of FIG. 3, 410, 420, 430, and 440 of FIG. 4, and 510, 520, 530, 540, and 550 of FIG. 5. In some examples, the memory conversion circuitry 130 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry 800 of FIG. 8 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the memory conversion circuitry 130 may be instantiated by any other combination of hardware, software, and/or firmware. For example, the memory conversion circuitry 130 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

The destination memory circuitry 140 applies the destination tensor to the memory 110. In some examples, the destination memory circuitry 140 is instantiated by processor circuitry executing destination memory instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 3.

In some examples, the direct memory access platform 100 includes means for applying a destination tensor to the memory 110. For example, the means for applying may be implemented by destination memory circuitry 140. In some examples, the destination memory circuitry 140 may be instantiated by processor circuitry such as the example processor circuitry 612 of FIG. 6. For instance, the destination memory circuitry 140 may be instantiated by the example microprocessor 700 of FIG. 7 executing machine executable instructions such as those implemented by at least block 330 of FIG. 3. In some examples, the destination memory circuitry 140 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry 800 of FIG. 8 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the destination memory circuitry 140 may be instantiated by any other combination of hardware, software, and/or firmware. For example, the destination memory circuitry 140 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

While an example manner of implementing the direct memory access platform 100 of FIG. 1 is illustrated in FIG. 1, one or more of the elements, processes, and/or devices illustrated in FIG. 1 may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example source memory circuitry 120, the example memory conversion circuitry 130, the example destination memory circuitry 140, and/or, more generally, the example direct memory access platform 100 of FIG. 1, may be implemented by hardware alone or by hardware in combination with software and/or firmware. Thus, for example, any of the example source memory circuitry 120, the example memory conversion circuitry 130, the example destination memory circuitry 140, and/or, more generally, the example direct memory access platform 100, could be implemented by processor circuitry, analog circuit (s) , digital circuit (s) , logic circuit (s) , programmable processor (s) , programmable microcontroller (s) , graphics processing unit (s) (GPU (s) ) , digital signal processor (s) (DSP (s) ) , application specific integrated circuit (s) (ASIC (s) ) , programmable logic device (s) (PLD (s) ) , and/or field programmable logic device (s) (FPLD (s) ) such as Field Programmable Gate Arrays (FPGAs) . Further still, the example direct memory access platform 100 of FIG. 1 may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated in FIG. 1, and/or may include more than one of any or all of the illustrated elements, processes and devices.

FIG. 2 is a block diagram of the example memory conversion circuitry 130 of FIG. 1 to do implement a convert operation using direct memory access (DMA) . The memory conversion circuitry 130 of FIG. 2 may be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc. ) by processor circuitry such as a central processing unit executing instructions. Additionally or alternatively, the example memory conversion circuitry 130 of FIG. 2 may be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc. ) by an ASIC or an FPGA structured to perform operations corresponding to the instructions. It should be understood that some or all of the circuitry of FIG. 2 may, thus, be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads executing concurrently on hardware and/or in series on hardware. Moreover, in some examples, some or all of the circuitry of FIG. 2 may be implemented by microprocessor circuitry executing instructions to implement one or more virtual machines and/or containers.

The memory conversion circuitry 130 of FIG. 2 includes input identification circuitry 220, output identification circuitry 230, data type conversion circuitry 240, and output circuitry 250.

The input identification circuitry 220 identifies the source tensor data type. In the examples disclosed herein, the input identification circuitry 220 receives the source tensor by communicating with the source memory circuitry 120 via the I/O interface 210. In some examples, the input identification circuitry 220 is instantiated by processor circuitry executing input identification instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 4.

In some examples, the memory conversion circuitry 130 includes means for identifying the data type of the source tensor. For example, the means for identifying may be implemented by input identification circuitry 220. In some examples, the input identification circuitry 220 may be instantiated by processor circuitry such as the example processor circuitry 612 of FIG. 6. For instance, the input identification circuitry 220 may be instantiated by the example microprocessor 700 of FIG. 7 executing machine executable instructions such as those implemented by at least block 410 of FIG. 4. In some examples, the input identification circuitry 220 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry 800 of FIG. 8 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the input identification circuitry 220 may be instantiated by any other combination of hardware, software, and/or firmware. For example, the input identification circuitry 220 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the means for identifying the data type (of the source tensor) further identifies a shape of the source tensor.

The output identification circuitry 230 determines the destination tensor data type to convert the source tensor to. In the examples disclosed herein, the output identification circuitry 230 determines the destination tensor data type by communicating with the source memory circuitry 120 via the I/O interface 210 to receive instructions on the data type to convert the source tensor to. In some examples, the output identification circuitry 230 is instantiated by processor circuitry executing output identification instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 4.

In some examples, the memory conversion circuitry 130 includes means for determining the destination tensor data type to convert the source tensor to. For example, the means for determining may be implemented by output identification circuitry 230. In some examples, the output identification circuitry 230 may be instantiated by processor circuitry such as the example processor circuitry 612 of FIG. 6. For instance, the output identification circuitry 230 may be instantiated by the example microprocessor 700 of FIG. 7 executing machine executable instructions such as those implemented by at least block 420 of FIG. 4. In some examples, the output identification circuitry 230 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry 800 of FIG. 8 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the output identification circuitry 230 may be instantiated by any other combination of hardware, software, and/or firmware. For example, the output identification circuitry 230 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

The data type conversion circuitry 240 converts the source tensor to the destination tensor data type to obtain the destination tensor. In some examples, the data type conversion circuitry 240 is instantiated by processor circuitry executing data type conversion instructions and/or configured to perform operations such as those represented by the flowcharts of FIGS. 4 and/or 5.

In some examples, the memory conversion circuitry 130 includes means for converting the source tensor to the destination tensor data type. For example, the means for converting may be implemented by data type conversion circuitry 240. In some examples, the data type conversion circuitry 240 may be instantiated by processor circuitry such as the example processor circuitry 612 of FIG. 6. For instance, the data type conversion circuitry 240 may be instantiated by the example microprocessor 700 of FIG. 7 executing machine executable instructions such as those implemented by at least blocks 430 of FIG. 4 and 510, 520, 530, 540, and 550 of FIG. 5. In some examples, the data type conversion circuitry 240 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry 800 of FIG. 8 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the data type conversion circuitry 240 may be instantiated by any other combination of hardware, software, and/or firmware. For example, the data type conversion circuitry 240 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the means for converting the source tensor (to the destination tensor data type) further selects values to fill in empty space in the destination tensor when the destination tensor data type is larger than the source tensor data type. In other examples, the means for converting the source tensor further selects data to remove from the source tensor when the destination tensor data type is smaller than the data type of the source tensor.

The output circuitry 250 outputs the destination tensor. In the examples disclosed herein, the output circuitry 250 outputs the destination tensor by communicating with the destination memory circuitry 140 via the I/O interface. In some examples, the output circuitry 250 is instantiated by processor circuitry executing output instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 4.

In some examples, the memory conversion circuitry 130 includes means for outputting the destination tensor For example, the means for outputting may be implemented by output circuitry 250. In some examples, the output circuitry 250 may be instantiated by processor circuitry such as the example processor circuitry 612 of FIG. 6. For instance, the output circuitry 250 may be instantiated by the example microprocessor 700 of FIG. 7 executing machine executable instructions such as those implemented by at least block 440 of FIG. 4. In some examples, the output circuitry 250 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry 800 of FIG. 8 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the output circuitry 250 may be instantiated by any other combination of hardware, software, and/or firmware. For example, the output circuitry 250 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

While an example manner of implementing the memory conversion circuitry 130 of FIG. 1 is illustrated in FIG. 2, one or more of the elements, processes, and/or devices illustrated in FIG. 2 may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example input identification circuitry 220, example output identification circuitry 230, example data type conversion circuitry 240, and example output circuitry 250, and/or, more generally, the example memory conversion circuitry 130 of FIG. 1, may be implemented by hardware alone or by hardware in combination with software and/or firmware. Thus, for example, any of the example input identification circuitry 220, example output identification circuitry 230, example data type conversion circuitry 240, and example output circuitry 250, and/or, more generally, the example memory conversion circuitry 130, could be implemented by processor circuitry, analog circuit (s) , digital circuit (s) , logic circuit (s) , programmable processor (s) , programmable microcontroller (s) , graphics processing unit (s) (GPU (s) ) , digital signal processor (s) (DSP (s) ) , application specific integrated circuit (s) (ASIC (s) ) , programmable logic device (s) (PLD (s) ) , and/or field programmable logic device (s) (FPLD (s) ) such as Field Programmable Gate Arrays (FPGAs) . Further still, the example memory conversion circuitry 130 of FIG. 1 may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated in FIG. 2, and/or may include more than one of any or all of the illustrated elements, processes and devices.

Flowcharts representative of example machine readable instructions, which may be executed to configure processor circuitry to implement the direct memory access platform 100 of FIG. 1, is shown in FIGS. 3, 4, and/or 5. The machine readable instructions may be one or more executable programs or portion (s) of an executable program for execution by processor circuitry, such as the processor circuitry 612 shown in the example processor platform 600 discussed below in connection with FIG. 6 and/or the example processor circuitry discussed below in connection with FIGS. 7 and/or 8. The program may be embodied in software stored on one or more non-transitory computer readable storage media such as a compact disk (CD) , a floppy disk, a hard disk drive (HDD) , a solid-state drive (SSD) , a digital versatile disk (DVD) , a Blu-ray disk, a volatile memory (e.g., Random Access Memory (RAM) of any type, etc. ) , or a non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM) , FLASH memory, an HDD, an SSD, etc. ) associated with processor circuitry located in one or more hardware devices, but the entire program and/or parts thereof could alternatively be executed by one or more hardware devices other than the processor circuitry and/or embodied in firmware or dedicated hardware. The machine readable instructions may be distributed across multiple hardware devices and/or executed by two or more hardware devices (e.g., a server and a client hardware device) . For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a user) or an intermediate client hardware device (e.g., a radio access network (RAN) ) gateway that may facilitate communication between a server and an endpoint client hardware device) . Similarly, the non-transitory computer readable storage media may include one or more mediums located in one or more hardware devices. Further, although the example program is described with reference to the flowcharts illustrated in FIGS. 3, 4, and/or 5, many other methods of implementing the example direct memory access platform 100 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp) , a logic circuit, etc. ) structured to perform the corresponding operation without executing software or firmware. The processor circuitry may be distributed in different network locations and/or local to one or more hardware devices (e.g., a single-core processor (e.g., a single core central processor unit (CPU) ) , a multi-core processor (e.g., a multi-core CPU, an XPU, etc. ) in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, a CPU and/or a FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings, etc. ) .

The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine readable instructions as described herein may be stored as data or a data structure (e.g., as portions of instructions, code, representations of code, etc. ) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices and/or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc. ) . The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and/or stored on separate computing devices, wherein the parts when decrypted, decompressed, and/or combined form a set of machine executable instructions that implement one or more operations that may together form a program such as that described herein.

In another example, the machine readable instructions may be stored in a state in which they may be read by processor circuitry, but require addition of a library (e.g., a dynamic link library (DLL) ) , a software development kit (SDK) , an application programming interface (API) , etc., in order to execute the machine readable instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc. ) before the machine readable instructions and/or the corresponding program (s) can be executed in whole or in part. Thus, machine readable media, as used herein, may include machine readable instructions and/or program (s) regardless of the particular format or state of the machine readable instructions and/or program (s) when stored or otherwise at rest or in transit.

The machine readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML) , Structured Query Language (SQL) , Swift, etc.

As mentioned above, the example operations of FIGS. 3, 4, and/or 5 may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on one or more non-transitory computer and/or machine readable media such as optical storage devices, magnetic storage devices, an HDD, a flash memory, a read-only memory (ROM) , a CD, a DVD, a cache, a RAM of any type, a register, and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information) . As used herein, the terms non-transitory computer readable medium, non-transitory computer readable storage medium, non-transitory machine readable medium, and non-transitory machine readable storage medium are expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media. As used herein, the terms “computer readable storage device” and “machine readable storage device” are defined to include any physical (mechanical and/or electrical) structure to store information, but to exclude propagating signals and to exclude transmission media. Examples of computer readable storage devices and machine readable storage devices include random access memory of any type, read only memory of any type, solid state memory, flash memory, optical discs, magnetic disks, disk drives, and/or redundant array of independent disks (RAID) systems. As used herein, the term “device” refers to physical structure such as mechanical and/or electrical equipment, hardware, and/or circuitry that may or may not be configured by computer readable instructions, machine readable instructions, etc., and/or manufactured to execute computer readable instructions, machine readable instructions, etc.

“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc. ) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

As used herein, singular references (e.g., “a” , “an” , “first” , “second” , etc. ) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an” ) , “one or more” , and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.

FIG. 3 is a flowchart representative of example machine readable instructions and/or example operations that may be executed and/or instantiated by processor circuitry to implement the direct memory access platform 100 of FIG. 1. The example direct memory access (DMA) process 300 of FIG. 3 begin at block 310, at which the source memory circuitry 120 acquires a source tensor from the memory 110.

The memory conversion circuitry 130 then performs a data conversion on the source tensor to obtain a destination tensor. (Block 320) . In some examples, the data conversion performed by the memory conversion circuitry 130 converts a larger source tensor (e.g., an unsigned 16-bit integer) into a smaller destination tensor (e.g., an unsigned 8-bit integer) . In other examples, the memory conversion circuitry 130 converts a smaller source tensor (e.g., an unsigned 8-bit integer) into a larger destination tensor (e.g., an unsigned 16-bit integer) . In some examples, the memory conversion circuitry 130 may convert the source tensor to a destination tensor of the same bit value (e.g., unsigned integer to unsigned integer, signed integer to signed integer, etc. )

Once the memory conversion circuitry 130 performs the data conversion, the destination memory circuitry 140 then applies the destination tensor to the memory 110. (Block 330) . In some examples, the destination memory circuitry 140 applies the destination tensor to the same space in the memory 110 in which the source memory circuitry 120 acquired the source tensor. In other examples, the destination memory circuitry 140 applies the destination tensor to a different space in the memory 110 or a different memory altogether (e.g., a different memory source) . Once the destination memory circuitry 140 applies the destination tensor to the appropriate memory, the example DMA process 300 concludes. The example DMA process 300 can be performed as many times as necessary to convert as many source tensor as the neural network requires.

FIG. 4 is a flowchart representative of example machine readable instructions and/or example operations that may be executed and/or instantiated by processor circuitry to implement the example memory conversion circuitry 130 of FIG. 2. The example data conversion operation 320 of FIG. 4 begin at block 410, at which the input identification circuitry 220 identifies the source tensor data type and shape (e.g., properties of the source tensor) . The data type can be any logical data type, such as an unsigned 8-bit integer and the like. In some examples, the input identification circuitry 220 identifies the properties of the source tensor via the I/O interface 210 to retrieve the source tensor from the source memory circuitry 120. In some examples, the shape of the source tensor is representative of a number of elements housed within the source tensor. The shape can be a matrix representation of the data within the source tensor, such as a 2x1, 3x1, 4x1, etc. matrix to logically represent a single line of data in memory.

Once the properties of the source tensor have been identified by the input identification circuitry 220, the output identification circuitry 230 determines the destination data type to convert the source tensor to. (Block 420) . In some examples, the destination data type is a larger data type than the source tensor (e.g., the source tensor is expanded to fit a larger data type) . In other examples, the destination data type is a smaller data type than the source tensor (e.g., the source tensor is shrunk to fit a smaller data type) .

Once the destination data type has been determined by the output identification circuitry 230, the data type conversion circuitry 240 then converts the source tensor to the destination tensor data type to obtain the destination tensor. (Block 430) . Further information on an example process for converting the source tensor to the destination tensor is disclosed in reference to FIG. 5 below.

Once the destination tensor is obtained by the data type conversion circuitry 240, the output circuitry 250 then outputs the destination tensor. (Block 440) . In some examples, the output circuitry 250 outputs the destination tensor by communicating the destination tensor to the destination memory circuitry 140 via the I/O interface 210. Once the destination tensor has been output by the output circuitry 250, then the example data conversion operation 320 concludes. The example data conversion operation 320 can be repeated as many times as necessary to perform the convert operation on as much data as necessary.

FIG. 5 is a flowchart representative of example machine readable instructions and/or example operations that may be executed and/or instantiated by processor circuitry to implement the example data type conversion circuitry 240 of FIG. 2. The example destination tensor creation process 430 of FIG. 5 begin at block 510, at which the data type conversion circuitry 240 identifies the data type (or width) of the destination tensor as determined by the output identification circuitry 230.

Once the data type conversion circuitry 240 identifies the data type of the destination tensor, the data type conversion circuitry 240 determines whether the source tensor can fit within the data type of the destination tensor. (Block 520) . In examples disclosed herein, the data type of the destination tensor is different than the data type of the source tensor.

When the data type conversion circuitry 240 determines that the source tensor can fit within the data type of the destination tensor (e.g., block 520 returns a result of YES) , the data type conversion circuitry 240 fills in the empty space (e.g., excess space in the destination tensor data type once the source tensor has been converted) in the destination tensor data type with pre-defined values. (Block 530) . In such an example, the data type of the destination tensor is any data type that is larger than that of the source tensor. In the examples disclosed herein, the pre-defined values can be logical 0’s so as to not change the value of the source tensor. However, any other pre-defined value can be included in the empty space of the destination tensor.

When the data type conversion circuitry 240 determines that the source tensor cannot fit within the data type of the destination tensor (e.g., block 520 returns a result of NO) , the data type conversion circuitry 240 ignores/deletes the least significant bits of the source tensor. (Block 540) . In such an example, the data type of the destination tensor is any data type that is smaller than that of the source tensor. In the examples disclosed herein, the ignoring/deleting the least significant bits of the source tensor results in precision loss of the source tensor but reduces memory allocation for the source tensor on the memory 110. Such a reduction in memory allocation may be desired for a given neural network to be able to allocate computational resources and memory elsewhere.

When the data type conversion circuitry 240 determines the appropriate approach to manage the source tensor based on the data type of the destination tensor (e.g., block 530 or 540) , then the data type conversion circuitry 240 creates the destination tensor by mapping the source tensor to the data type of the destination tensor. (Block 550) . Once the source tensor has been mapped to the data type of the destination tensor, the example destination tensor creation process 430 ends.

FIG. 6 is a block diagram of an example processor platform 600 structured to execute and/or instantiate the machine readable instructions and/or the operations of FIGS. 3, 4, and/or 5 to implement the direct memory access platform 100 of FIG. 1. The processor platform 600 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network) , a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad ^TM) , a personal digital assistant (PDA) , an Internet appliance, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc. ) or other wearable device, or any other type of computing device.

The processor platform 600 of the illustrated example includes processor circuitry 612. The processor circuitry 612 of the illustrated example is hardware. For example, the processor circuitry 612 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry 612 may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, processor circuitry 612 implements source memory circuitry 120, memory conversion circuitry 130, destination memory circuitry 140, input identification circuitry 220, output identification circuitry 230, data type conversion circuitry 240, and output circuitry 250.

The processor circuitry 612 of the illustrated example includes a local memory 613 (e.g., a cache, registers, etc. ) . The processor circuitry 612 of the illustrated example is in communication with a main memory including a volatile memory 614 and a non-volatile memory 616 by a bus 618. The volatile memory 614 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM) , Dynamic Random Access Memory (DRAM) ,

Dynamic Random Access Memory

and/or any other type of RAM device. The non-volatile memory 616 may be implemented by flash memory and/or any other desired type of memory device. Access to the

main memory

614, 616 of the illustrated example is controlled by a memory controller 617.

The processor platform 600 of the illustrated example also includes interface circuitry 620. The interface circuitry 620 may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a

interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface.

In the illustrated example, one or more input devices 622 are connected to the interface circuitry 620. The input device (s) 622 permit (s) a user to enter data and/or commands into the processor circuitry 612. The input device (s) 622 can be implemented by, for example, an audio sensor, a microphone, a camera (still or video) , a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

One or more output devices 624 are also connected to the interface circuitry 620 of the illustrated example. The output device (s) 624 can be implemented, for example, by display devices (e.g., a light emitting diode (LED) , an organic light emitting diode (OLED) , a liquid crystal display (LCD) , a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc. ) , a printer, and/or speaker. The interface circuitry 620 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.

The interface circuitry 620 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network 626. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, an optical connection, etc.

The processor platform 600 of the illustrated example also includes one or more mass storage devices 628 to store software and/or data. Examples of such mass storage devices 628 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices and/or SSDs, and DVD drives.

The machine readable instructions 632, which may be implemented by the machine readable instructions of FIGS. 3, 4, and/or 5, may be stored in the mass storage device 628, in the volatile memory 614, in the non-volatile memory 616, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

FIG. 7 is a block diagram of an example implementation of the processor circuitry 612 of FIG. 6. In this example, the processor circuitry 612 of FIG. 6 is implemented by a microprocessor 700. For example, the microprocessor 700 may be a general purpose microprocessor (e.g., general purpose microprocessor circuitry) . The microprocessor 700 executes some or all of the machine readable instructions of the flowcharts of FIGS. 3, 4, and/or 5 to effectively instantiate the source memory circuitry 120, the memory conversion circuitry 130, and/or the destination memory circuitry 140 as logic circuits to perform the operations corresponding to those machine readable instructions. In some such examples, the source memory circuitry 120, the memory conversion circuitry 130, and/or the destination memory circuitry 140 is instantiated by the hardware circuits of the microprocessor 700 in combination with the instructions. For example, the microprocessor 700 may be implemented by multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores 702 (e.g., 1 core) , the microprocessor 700 of this example is a multi-core semiconductor device including N cores. The cores 702 of the microprocessor 700 may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 702 or may be executed by multiple ones of the cores 702 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores 702. The software program may correspond to a portion or all of the machine readable instructions and/or operations represented by the flowcharts of FIGS. 3, 4, and/or 5.

The cores 702 may communicate by a first example bus 704. In some examples, the first bus 704 may be implemented by a communication bus to effectuate communication associated with one (s) of the cores 702. For example, the first bus 704 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 704 may be implemented by any other type of computing or electrical bus. The cores 702 may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry 706. The cores 702 may output data, instructions, and/or signals to the one or more external devices by the interface circuitry 706. Although the cores 702 of this example include example local memory 720 (e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache) , the microprocessor 700 also includes example shared memory 710 that may be shared by the cores (e.g., Level 2 (L2 cache) ) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory 710. The local memory 720 of each of the cores 702 and the shared memory 710 may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the

main memory

614, 616 of FIG. 6) . Typically, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

Each core 702 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 702 includes control unit circuitry 714, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 716, a plurality of registers 718, the local memory 720, and a second example bus 722. Other structures may be present. For example, each core 702 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry 714 includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core 702. The AL circuitry 716 includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core 702. The AL circuitry 716 of some examples performs integer based operations. In other examples, the AL circuitry 716 also performs floating point operations. In yet other examples, the AL circuitry 716 may include first AL circuitry that performs integer based operations and second AL circuitry that performs floating point operations. In some examples, the AL circuitry 716 may be referred to as an Arithmetic Logic Unit (ALU) . The registers 718 are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry 716 of the corresponding core 702. For example, the registers 718 may include vector register (s) , SIMD register (s) , general purpose register (s) , flag register (s) , segment register (s) , machine specific register (s) , instruction pointer register (s) , control register (s) , debug register (s) , memory management register (s) , machine check register (s) , etc. The registers 718 may be arranged in a bank as shown in FIG. 7. Alternatively, the registers 718 may be organized in any other arrangement, format, or structure including distributed throughout the core 702 to shorten access time. The second bus 722 may be implemented by at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus

Each core 702 and/or, more generally, the microprocessor 700 may include additional and/or alternate structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs) , one or more converged/common mesh stops (CMSs) , one or more shifters (e.g., barrel shifter (s) ) and/or other circuitry may be present. The microprocessor 700 is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages. The processor circuitry may include and/or cooperate with one or more accelerators. In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and/or efficiently than can be done by a general purpose processor. Examples of accelerators include ASICs and FPGAs such as those discussed herein. A GPU or other programmable device can also be an accelerator. Accelerators may be on-board the processor circuitry, in the same chip package as the processor circuitry and/or in one or more separate packages from the processor circuitry.

FIG. 8 is a block diagram of another example implementation of the processor circuitry 812 of FIG. 8. In this example, the processor circuitry 812 is implemented by FPGA circuitry 800. For example, the FPGA circuitry 800 may be implemented by an FPGA. The FPGA circuitry 800 can be used, for example, to perform operations that could otherwise be performed by the example microprocessor 700 of FIG. 7 executing corresponding machine readable instructions. However, once configured, the FPGA circuitry 800 instantiates the machine readable instructions in hardware and, thus, can often execute the operations faster than they could be performed by a general purpose microprocessor executing the corresponding software.

More specifically, in contrast to the microprocessor 700 of FIG. 7 described above (which is a general purpose device that may be programmed to execute some or all of the machine readable instructions represented by the flowcharts of FIGS. 3, 4, and/or 5 but whose interconnections and logic circuitry are fixed once fabricated) , the FPGA circuitry 800 of the example of FIG. 8 includes interconnections and logic circuitry that may be configured and/or interconnected in different ways after fabrication to instantiate, for example, some or all of the machine readable instructions represented by the flowcharts of FIGS. 3, 4, and/or 5. In particular, the FPGA circuitry 800 may be thought of as an array of logic gates, interconnections, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnections, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuitry 800 is reprogrammed) . The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by input circuitry. Those operations may correspond to some or all of the software represented by the flowcharts of FIGS. 3, 4, and/or 5. As such, the FPGA circuitry 800 may be structured to effectively instantiate some or all of the machine readable instructions of the flowcharts of FIGS. 3, 4, and/or 5 as dedicated logic circuits to perform the operations corresponding to those software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuitry 800 may perform the operations corresponding to the some or all of the machine readable instructions of FIGS. 3, 4, and/or 5 faster than the general purpose microprocessor can execute the same.

In the example of FIG. 8, the FPGA circuitry 800 is structured to be programmed (and/or reprogrammed one or more times) by an end user by a hardware description language (HDL) such as Verilog. The FPGA circuitry 800 of FIG. 8, includes example input/output (I/O) circuitry 802 to obtain and/or output data to/from example configuration circuitry 804 and/or external hardware 806. For example, the configuration circuitry 804 may be implemented by interface circuitry that may obtain machine readable instructions to configure the FPGA circuitry 800, or portion (s) thereof. In some such examples, the configuration circuitry 804 may obtain the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (AI/ML) model to generate the instructions) , etc. In some examples, the external hardware 806 may be implemented by external hardware circuitry. For example, the external hardware 806 may be implemented by the microprocessor 700 of FIG. 7. The FPGA circuitry 800 also includes an array of example logic gate circuitry 808, a plurality of example configurable interconnections 810, and example storage circuitry 812. The logic gate circuitry 808 and the configurable interconnections 810 are configurable to instantiate one or more operations that may correspond to at least some of the machine readable instructions of FIGS. 3, 4, and/or 5 and/or other desired operations. The logic gate circuitry 808 shown in FIG. 8 is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc. ) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry 808 to enable configuration of the electrical structures and/or the logic gates to form circuits to perform desired operations. The logic gate circuitry 808 may include other electrical structures such as look-up tables (LUTs) , registers (e.g., flip-flops or latches) , multiplexers, etc.

The configurable interconnections 810 of the illustrated example are conductive pathways, traces, vias, or the like that may include electrically controllable switches (e.g., transistors) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 808 to program desired logic circuits.

The storage circuitry 812 of the illustrated example is structured to store result (s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry 812 may be implemented by registers or the like. In the illustrated example, the storage circuitry 812 is distributed amongst the logic gate circuitry 808 to facilitate access and increase execution speed.

The example FPGA circuitry 800 of FIG. 8 also includes example Dedicated Operations Circuitry 814. In this example, the Dedicated Operations Circuitry 814 includes special purpose circuitry 816 that may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry 816 include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry 800 may also include example general purpose programmable circuitry 818 such as an example CPU 820 and/or an example DSP 822. Other general purpose programmable circuitry 818 may additionally or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

Although FIGS. 7 and 8 illustrate two example implementations of the processor circuitry 612 of FIG. 6, many other approaches are contemplated. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU 820 of FIG. 8. Therefore, the processor circuitry 612 of FIG. 6 may additionally be implemented by combining the example microprocessor 700 of FIG. 7 and the example FPGA circuitry 800 of FIG. 8. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowcharts of FIGS. 3, 4, and/or 5 may be executed by one or more of the cores 702 of FIG. 7, a second portion of the machine readable instructions represented by the flowcharts of FIGS. 3, 4, and/or 5 may be executed by the FPGA circuitry 800 of FIG. 8, and/or a third portion of the machine readable instructions represented by the flowcharts of FIGS. 3, 4, and/or 5 may be executed by an ASIC. It should be understood that some or all of the circuitry of FIGS. 1 and/or 2 may, thus, be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads executing concurrently and/or in series. Moreover, in some examples, some or all of the circuitry of FIGS. 1 and/or 2 may be implemented within one or more virtual machines and/or containers executing on the microprocessor.

In some examples, the processor circuitry 612 of FIG. 6 may be in one or more packages. For example, the microprocessor 700 of FIG. 7 and/or the FPGA circuitry 800 of FIG. 8 may be in one or more packages. In some examples, an XPU may be implemented by the processor circuitry 612 of FIG. 6, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in still yet another package.

A block diagram illustrating an example software distribution platform 905 to distribute software such as the example machine readable instructions 632 of FIG. 6 to hardware devices owned and/or operated by third parties is illustrated in FIG. 9. The example software distribution platform 905 may be implemented by any computer server, data facility, cloud service, etc., capable of storing and transmitting software to other computing devices. The third parties may be customers of the entity owning and/or operating the software distribution platform 905. For example, the entity that owns and/or operates the software distribution platform 905 may be a developer, a seller, and/or a licensor of software such as the example machine readable instructions 632 of FIG. 6. The third parties may be consumers, users, retailers, OEMs, etc., who purchase and/or license the software for use and/or re-sale and/or sub-licensing. In the illustrated example, the software distribution platform 905 includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions 632, which may correspond to the example machine readable instructions of FIGS. 3, 4, and/or 5, as described above. The one or more servers of the example software distribution platform 905 are in communication with an example network 910, which may correspond to any one or more of the Internet and/or any of the example networks 626 described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and/or license of the software may be handled by the one or more servers of the software distribution platform and/or by a third party payment entity. The servers enable purchasers and/or licensors to download the machine readable instructions 632 from the software distribution platform 905. For example, the software, which may correspond to the example machine readable instructions of FIGS. 3, 4, and/or 5, may be downloaded to the example processor platform 600, which is to execute the machine readable instructions 632 to implement the direct memory access platform 100. In some examples, one or more servers of the software distribution platform 905 periodically offer, transmit, and/or force updates to the software (e.g., the example machine readable instructions 632 of FIG. 6) to ensure improvements, patches, updates, etc., are distributed and applied to the software at the end user devices.

From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that perform convert operations using direct memory access. Disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by eliminating the need for an external kernel to perform a memory conversion operation. Disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvement (s) in the operation of a machine such as a computer or other electronic and/or mechanical device.

Example methods, apparatus, systems, and articles of manufacture to perform convert operations using direct memory access are disclosed herein. Further examples and combinations thereof include the following:

Example 1 includes an apparatus comprising at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to acquire a source tensor from the memory, the source tensor including data, the source tensor acquired through direct memory access from the memory, perform a data conversion on the source tensor to obtain a destination tensor, the performance of the data conversion occurring through direct memory access, and apply the destination tensor to the memory, the destination tensor applied through direct memory access to the memory.

Example 2 includes the apparatus of example 1, wherein the processor circuitry is to identify a first data type corresponding to the source tensor.

Example 3 includes the apparatus of example 2, wherein the processor circuitry is to identify a shape of the source tensor.

Example 4 includes the apparatus of example 2, wherein the processor circuitry is to determine a second data type corresponding to the destination tensor.

Example 5 includes the apparatus of example 4, wherein to perform the data conversion, the processor circuitry is to convert the source tensor from the first data type to the second data type.

Example 6 includes the apparatus of example 5, wherein the processor circuitry is to select values to fill in empty space in the destination tensor.

Example 7 includes the apparatus of example 5, wherein the processor circuitry is to select data from the source tensor to remove.

Example 8 includes the apparatus of example 1, wherein the processor circuitry is to output the destination tensor before application of the destination tensor to the memory.

Example 9 includes an apparatus to perform convert operations comprising means for acquiring a source tensor from a memory, the source tensor including data and acquired through direct memory access from the memory, means for performing a data conversion on the source tensor to obtain a destination tensor, and means for applying the destination tensor to the memory, the destination tensor applied through direct memory access to the memory, wherein the acquiring means, the performing means, and the applying means are implemented using direct memory access.

Example 10 includes the apparatus of example 9, further including means for identifying a first data type corresponding to the source tensor.

Example 11 includes the apparatus of example 10, wherein the means for identifying is to identify a shape of the source tensor.

Example 12 includes the apparatus of example 10, further including means for determining a second data type corresponding to the destination tensor.

Example 13 includes the apparatus of example 12, further including means for converting the source tensor from the first data type to the second data type.

Example 14 includes the apparatus of example 13, wherein the means for converting is to select values to fill in empty space in the destination tensor.

Example 15 includes the apparatus of example 13, wherein the means for converting is to select data from the source tensor to remove.

Example 16 includes the apparatus of example 9, further including means for outputting the destination tensor before applying the destination tensor to the memory.

Example 17 includes a non-transitory machine readable storage medium comprising instructions that, when executed, cause processor circuitry to at least acquire a source tensor from a memory, the source tensor including data and acquired through direct memory access from the memory, perform a data conversion on the source tensor to obtain a destination tensor, the performing of the data conversion implemented through direct memory access, and apply the destination tensor to the memory, the destination tensor applied through direct memory access to the memory.

Example 18 includes the non-transitory machine readable storage medium of example 17, wherein the instructions, when executed, further cause the processor circuitry to identify a first data type corresponding to the source tensor.

Example 19 includes the non-transitory machine readable storage medium of example 18, wherein the instructions, when executed, further cause the processor circuitry to identify a shape of the source tensor.

Example 20 includes the non-transitory machine readable storage medium of example 18, wherein the instructions, when executed, further cause the processor circuitry to determine a second data type corresponding to the destination tensor.

Example 21 includes the non-transitory machine readable storage medium of example 20, wherein the instructions, when executed, further cause the processor circuitry to perform the data conversion by converting the source tensor from the first data type to the second data type.

Example 22 includes the non-transitory machine readable storage medium of example 21, wherein the instructions, when executed, further cause the processor circuitry to select values to fill in empty space in the destination tensor.

Example 23 includes the non-transitory machine readable storage medium of example 21, wherein the instructions, when executed, further cause the processor circuitry to select data from the source tensor to remove.

Example 24 includes the non-transitory machine readable storage medium of example 17, wherein the instructions, when executed, further cause the processor circuitry to output the destination tensor before applying the destination tensor to the memory platform storage.

Example 25 includes a method to perform convert operations comprising acquiring a source tensor from a memory, the source tensor including data, performing a data conversion on the source tensor to obtain a destination tensor, and applying the destination tensor to the memory, wherein the acquiring, performing, and applying are all employed using direct memory access.

Example 26 includes the method of example 25, further including identifying a first data type corresponding to the source tensor.

Example 27 includes the method of example 26, further including identifying a shape of the source tensor.

Example 28 includes the method of example 26, further including determining a second data type corresponding to the destination tensor.

Example 29 includes the method of example 28, further including converting the source tensor from the first data type to the second data type.

Example 30 includes the method of example 29, further including selecting values to fill in empty space in the destination tensor.

Example 31 includes the method of example 29, further including selecting data from the source tensor to remove.

Example 32 includes the method of example 25, further including outputting the destination tensor before applying the destination tensor to the memory.

The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.

Claims

An apparatus comprising:

at least one memory;

machine readable instructions; and

processor circuitry to at least one of instantiate or execute the machine readable instructions to:

acquire a source tensor from the memory, the source tensor including data, the source tensor acquired through direct memory access from the memory;

perform a data conversion on the source tensor to obtain a destination tensor, the performance of the data conversion occurring through direct memory access; and

apply the destination tensor to the memory, the destination tensor applied through direct memory access to the memory.
The apparatus of claim 1, wherein the processor circuitry is to identify a first data type corresponding to the source tensor.
The apparatus of claim 2, wherein the processor circuitry is to identify a shape of the source tensor.
The apparatus of claim 2, wherein the processor circuitry is to determine a second data type corresponding to the destination tensor.
The apparatus of claim 4, wherein to perform the data conversion, the processor circuitry is to convert the source tensor from the first data type to the second data type.
The apparatus of claim 5, wherein the processor circuitry is to select values to fill in empty space in the destination tensor.
The apparatus of claim 5, wherein the processor circuitry is to select data from the source tensor to remove.
The apparatus of claim 1, wherein the processor circuitry is to output the destination tensor before application of the destination tensor to the memory.
An apparatus to perform convert operations comprising:

means for acquiring a source tensor from a memory, the source tensor including data and acquired through direct memory access from the memory;

means for performing a data conversion on the source tensor to obtain a destination tensor; and

means for applying the destination tensor to the memory, the destination tensor applied through direct memory access to the memory;

wherein the acquiring means, the performing means, and the applying means are implemented using direct memory access.
The apparatus of claim 9, further including means for identifying a first data type corresponding to the source tensor.
The apparatus of claim 10, wherein the means for identifying is to identify a shape of the source tensor.
The apparatus of claim 10, further including means for determining a second data type corresponding to the destination tensor.
The apparatus of claim 12, further including means for converting the source tensor from the first data type to the second data type.
The apparatus of claim 13, wherein the means for converting is to select values to fill in empty space in the destination tensor.
The apparatus of claim 13, wherein the means for converting is to select data from the source tensor to remove.
The apparatus of claim 9, further including means for outputting the destination tensor before applying the destination tensor to the memory.
A non-transitory machine readable storage medium comprising instructions that, when executed, cause processor circuitry to at least:

acquire a source tensor from a memory, the source tensor including data and acquired through direct memory access from the memory;

perform a data conversion on the source tensor to obtain a destination tensor, the performing of the data conversion implemented through direct memory access; and

apply the destination tensor to the memory, the destination tensor applied through direct memory access to the memory.
The non-transitory machine readable storage medium of claim 17, wherein the instructions, when executed, further cause the processor circuitry to identify a first data type corresponding to the source tensor.
The non-transitory machine readable storage medium of claim 18, wherein the instructions, when executed, further cause the processor circuitry to identify a shape of the source tensor.
The non-transitory machine readable storage medium of claim 18, wherein the instructions, when executed, further cause the processor circuitry to determine a second data type corresponding to the destination tensor.
The non-transitory machine readable storage medium of claim 20, wherein the instructions, when executed, further cause the processor circuitry to perform the data conversion by converting the source tensor from the first data type to the second data type.
The non-transitory machine readable storage medium of claim 21, wherein the instructions, when executed, further cause the processor circuitry to select values to fill in empty space in the destination tensor.
The non-transitory machine readable storage medium of claim 21, wherein the instructions, when executed, further cause the processor circuitry to select data from the source tensor to remove.
The non-transitory machine readable storage medium of claim 17, wherein the instructions, when executed, further cause the processor circuitry to output the destination tensor before applying the destination tensor to the memory platform storage.
A method to perform convert operations comprising:

acquiring a source tensor from a memory, the source tensor including data;

performing a data conversion on the source tensor to obtain a destination tensor; and

applying the destination tensor to the memory;

wherein the acquiring, performing, and applying are all employed using direct memory access.