WO2024114812A1 - Encoding method, decoding method, and communication apparatus - Google Patents

Abstract

The present application relates to the field of communications, and in particular, to an encoding method, a decoding method, and a communication apparatus. The solution can be applied to a WLAN system, for example, a communication system defined by an 802.11be standard, an 802.11bf standard, a Wi-Fi 8 standard, or another future standard. In the method, an encoding end performs LDPC encoding on a data bit, the data bit comprising an information bit and a CRC bit, so that by introducing a CRC bit, decoding can be assisted on the basis of the CRC bit in a decoding iteration process. In addition, the position of the CRC bit is related to the robustness of the position of at least one data bit, so that the reliability of the CRC bit can be ensured as much as possible, and the probability that a decoding end successfully receives the CRC bit is improved, such that the decoding end can perform assisted decoding on the basis of the CRC bit, thereby improving the decoding efficiency.

Description

Coding method, decoding method and communication device

This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office of China on December 2, 2022, with application number 202211534348.X, and the priority of the Chinese patent application with the invention name "Encoding method, decoding method and communication device", all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of channel coding, and more specifically, to a coding method, a decoding method and a communication device.

Background technique

In the field of channel coding, low density parity check (LDPC) is a relatively mature and widely used channel coding scheme. LDPC code not only has good performance close to the Shannon limit, but also has low decoding complexity and flexible structure. Therefore, IEEE's 802.11n, 802.11ac, 802.11ax and other protocols propose to use LDPC as the standard channel coding scheme for wireless local area networks (WLAN). How to improve the decoding efficiency of LDPC codes is a question worth considering.

Summary of the invention

The present application provides an encoding method, a decoding method and a communication device to improve decoding efficiency.

On the first aspect, a coding method is provided, which can be executed by a coding device, or can also be executed by a component (for example, a chip, a circuit or a module, etc.) used in the coding device, and the present application does not limit this.

The method may include: performing low-density parity check (LDPC) coding on data bits to obtain a coded LDPC code stream, wherein the data bits include information bits and cyclic redundancy check (CRC) bits generated according to the information bits; and outputting the LDPC code stream. Optionally, the position of the CRC bit is related to the robustness of the data bit position in the LDPC code stream.

In a second aspect, a decoding method is provided, which may be executed by a decoding device, or may be executed by a component (eg, a chip, a circuit or a module, etc.) used in the decoding device, and the present application does not limit this.

The method may include: obtaining a low-density parity check (LDPC) code stream to be decoded, wherein the LDPC code stream includes data bits, wherein the data bits include cyclic redundancy check (CRC) bits and information bits; and decoding the LDPC code stream. Optionally, the position of the CRC bit is related to the robustness of the data bit position in the LDPC code stream.

Based on the above technical solution, by adding CRC bits to the LDPC code stream, it is possible to assist in decoding based on the CRC bits during the decoding iteration process, that is, to determine whether the decoding is successful at the auxiliary decoding end. For example, after the decoding device decodes the data bits (or information bits), the CRC bits can be further used to verify the decoded information bits. If the CRC bit verification is correct, it is considered that the information bits are successfully decoded, that is, the decoding is correct; otherwise, the decoding can be continued until the decoding is correct. In addition, the position of the CRC bit can be related to the robustness of the position of the data bit in the LDPC code stream, so that the position of the CRC bit can be selected according to actual needs. For example, if the reliability of the CRC bit is to be improved, the position with higher robustness can be preferentially selected as the position of the CRC bit, that is, the CRC bit is placed at a position with higher robustness, so that the reliability of the CRC bit can be improved, and then the information bits in the LDPC code stream can be assisted in decoding based on the CRC bit.

In combination with the first aspect or the second aspect, in some implementations, the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, including: the robustness of the position of the CRC bit is higher than the robustness of the position of at least one information bit in the LDPC code stream.

Based on the above technical solution, the robustness of the position where the CRC bit is located in the LDPC code stream is higher than the robustness of the position where at least one information bit is located. In this way, by preferentially selecting a position with higher robustness as the position of the CRC bit, that is, placing the CRC bit at a position with higher robustness, the reliability of the CRC bit can be improved, and then the information bits in the LDPC code stream can be assisted in decoding based on the CRC bit.

In combination with the first aspect or the second aspect, in some implementations, the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, including: when the robustness of at least two data bit positions in the LDPC code stream is consistent, the position of the CRC bit is located at the front position of the at least two data bits.

Based on the above technical solution, when the robustness of at least two data bit positions is consistent, by placing the CRC bit in the front position, the decoding end can quickly obtain the CRC bit, and then the signal in the LDPC code stream can be assisted in decoding based on the CRC bit. Interest bit.

In combination with the first aspect or the second aspect, in some implementations, the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, including any of the following:

When the code length of the LDPC code stream is 1944 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream; or,

When the code length of the LDPC code stream is 1944 and the code rate is 2/3, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4; or,

When the code length of the LDPC code stream is 1944 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6; or,

When the code length of the LDPC code stream is 1944 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10; or,

When the code length of the LDPC code stream is 1296 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream; or,

When the code length of the LDPC code stream is 1296 and the code rate is 2/3, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3; or,

When the code length of the LDPC code stream is 1296 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7; or,

When the code length of the LDPC code stream is 1296 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12, column 13, column 14, column 15, column 16; or,

When the code length of the LDPC code stream is 648 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 5, column 9; or,

When the code length of the LDPC code stream is 648 and the code rate is 2/3, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3; or,

When the code length of the LDPC code stream is 648 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5; or,

When the code length of the LDPC code stream is 648 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12, column 14, column 15, column 16, column 17, column 18, column 19, and column 20.

On the third aspect, a decoding method is provided, which can be executed by a decoding device, or can also be executed by a component (for example, a chip, a circuit or a module, etc.) used in the decoding device, and the present application does not limit this.

The method may include: obtaining a low-density parity check (LDPC) code to be decoded; decoding the LDPC code based on a check matrix with a dimension of M×N to obtain an LDPC codeword, wherein M is the number of check nodes, N is the number of variable nodes, and M and N are integers greater than 1; judging whether to stop decoding based on the LDPC codeword, and M1 check equations and/or N1 variable nodes, wherein the M check equations obtained based on the check matrix include M1 check equations, the N variable nodes in the check matrix include N1 variable nodes, N1 is a positive integer less than N, and M1 is a positive integer less than M.

Based on the above technical solution, by determining whether a certain proportion of the check equations are correct instead of all the check equations; or by determining whether a certain proportion of the variable nodes meet the reliability conditions instead of all the variable nodes, the decoding overhead can be reduced.

In combination with the third aspect, in some implementations of the third aspect, M1=M·f1, and f1 is greater than 0 and less than 1.

In combination with the third aspect, in certain implementations of the third aspect, determining whether to stop decoding is performed based on the LDPC codeword and M1 check equations, including: calculating, based on the LDPC codeword, a companion vector obtained based on M1 check equations and N variable nodes; if the companion vector is an all-zero vector, determining to stop decoding; or, if the companion vector is not an all-zero vector, determining not to stop decoding, and continuing decoding iterations; or, if the companion vector is not an all-zero vector and the maximum number of decoding iterations is reached, determining to stop decoding, and determining a decoding error.

In conjunction with the third aspect, in certain implementations of the third aspect, if the syndrome vector is an all-zero vector, then it is determined that decoding is stopped. The method further Includes: outputting LDPC codewords.

In combination with the third aspect, in some implementations of the third aspect, N1=N·f2, and f2 is greater than 0 and less than 1.

In combination with the third aspect, in certain implementations of the third aspect, determining whether to stop decoding is based on the LDPC codeword and N1 variable nodes, including: determining whether the N1 variable nodes meet the reliability conditions based on the LDPC codeword; if the N1 variable nodes meet the reliability conditions, determining to stop decoding.

In combination with the third aspect, in certain implementations of the third aspect, the reliability condition is that the signs of the N1 variable nodes fed back by all check nodes connected to the N1 variable nodes in the previous decoding iteration are the same.

In combination with the third aspect, in certain implementations of the third aspect, the LDPC code stream includes cyclic redundancy check CRC bits.

For the relevant design of CRC bits in the LDPC code stream, please refer to the description in the first aspect and the second aspect.

In a fourth aspect, a communication device is provided, the device being used to execute the method provided in any one of the first to third aspects. Specifically, the device may include a unit and/or module, such as a processing unit and/or a communication unit, for executing the method provided in any one of the above implementations of any one of the first to third aspects.

In one implementation, the apparatus is a device (such as an encoding device or a decoding device). When the apparatus is a device, the communication unit may be a transceiver or an input/output interface; the processing unit may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input/output interface may be an input/output circuit.

In another implementation, the device is a chip, circuit or module used in a device. When the device is a chip, circuit or module used in a terminal device, the communication unit may be an input/output interface, interface circuit, output circuit, input circuit, pin or related circuit on the chip, chip system or circuit; the processing unit may be at least one processor, processing circuit or logic circuit.

In a fifth aspect, a communication device is provided, comprising a processor for calling and running a computer program stored in a memory, and controlling a transceiver to send and receive signals, so that the communication device executes a method as in any aspect of the first to third aspects, or any possible implementation of these aspects.

Optionally, the communication device may further include the memory for storing the computer program, and the communication device may further include the transceiver.

In one implementation, the apparatus is a device (such as an encoding device or a decoding device).

In another implementation, the apparatus is a chip, a circuit or a module used in a device.

In a sixth aspect, a communication device is provided, comprising a processor, wherein the processor is used to process data and/or information so that a method as in any aspect of the first to third aspects, or any possible implementation of these aspects, is executed.

Optionally, the communication device may further include a communication interface, the communication interface being used to receive data and/or information and transmit the received data and/or information to the processor. Optionally, the communication interface is also used to output the data and/or information processed by the processor.

In one implementation, the apparatus is a device (such as an encoding device or a decoding device).

In another implementation, the apparatus is a chip, a circuit or a module used in a device.

In a seventh aspect, a chip is provided, comprising a processor, the processor being used to run a program or an instruction, so that the chip executes the method in any one of the first to third aspects, or any possible implementation of these aspects. Optionally, the chip may also include a memory, the memory being used to store the program or the instruction. Optionally, the chip may also include the transceiver.

In an eighth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to implement a method as in any aspect of the first to third aspects, or any possible implementation of these aspects.

In a ninth aspect, a computer program product is provided, the computer program product comprising a computer program code, the computer program code being used to implement a method as in any aspect of the first to third aspects, or any possible implementation of any aspect of these aspects.

In a tenth aspect, a wireless communication system is provided, comprising an encoding device and a decoding device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a system architecture applicable to an embodiment of the present application.

FIG2 is a schematic diagram of a check matrix of LDPC.

FIG3 is a schematic diagram of a Tanner graph corresponding to a check matrix.

FIG4 is a schematic diagram of the LDPC encoding steps.

FIG. 5 is a schematic diagram of a decoding method 500 provided in an embodiment of the present application.

6-13 show the relationship between the event probabilities of various decision events and the number of CRC bits when the CRC decoding stop criteria is adopted.

14-17 are schematic diagrams showing comparisons of event probabilities and additional iteration times of various decision events when using known decoding stop criteria and CRC decoding stop criteria.

FIG18 is a schematic diagram of a decoding method 1800 provided in an embodiment of the present application.

19 to 22 are schematic diagrams showing the relationship between the event probabilities of various decision events and f1 when the check node rule (CNR) decoding stop rule is adopted.

Figures 23 to 26 are schematic diagrams of the relationship between the event probability of various decision events and f2 when the variable node rule (VNR) decoding stop criterion is adopted.

FIG. 27 is a schematic block diagram of a communication device 2700 provided in an embodiment of the present application.

FIG. 28 is a schematic diagram of another communication device 2800 provided according to an embodiment of the present application.

FIG. 29 is a schematic diagram of a chip system 2900 provided according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

The technical solution provided in this application can be applicable to wireless local area network (WLAN) systems. For example, it can be applicable to communication systems defined by IEEE 802.11 related standards, such as the 802.11ax standard, the 802.11be standard, the 802.11bf standard, the Wi-Fi 8 standard, or other future standards.

The embodiments of the present application are mainly described by taking the deployment of WLAN networks, especially networks using the IEEE 802.11 system standard as an example. It is easy for those skilled in the art to understand that the various aspects involved in the present application can be extended to other networks that adopt various standards or protocols, such as high performance radio local area networks (HIPERLAN), wireless wide area networks (WWAN), wireless personal area networks (WPAN) or other networks now known or developed later. Therefore, regardless of the coverage range and wireless access protocol used, the various aspects provided in the present application can be applied to any suitable wireless network.

The embodiments of the present application may also be applicable to wireless local area network systems such as the Internet of Things (IoT) network or the Vehicle to X (V2X). Of course, the embodiments of the present application may also be applicable to other possible communication systems, such as the Long Term Evolution (LTE) system, the LTE frequency division duplex (FDD) system, the LTE time division duplex (TDD) system, the universal mobile telecommunication system (UMTS), the worldwide interoperability for microwave access (WiMAX) communication system, the fifth generation (5G) communication system, and the future sixth generation (6G) communication system.

The above-mentioned communication system applicable to the present application is only an example, and the communication system applicable to the present application is not limited to this. A unified description is given here and no further elaboration is given below.

See FIG. 1 , which is a schematic diagram of a system architecture applicable to an embodiment of the present application.

The technical solution provided in the present application is applicable to data communication between an access point (AP) and at least one station (STA). As shown in (a) of Figure 1, the technical solution provided in the present application is applicable to data communication between an AP and a single STA, such as data communication between AP1 and STA1. As shown in (b) of Figure 1, the technical solution provided in the present application is also applicable to data communication between an AP and multiple STAs, such as data communication between AP1 and STA1, STA2, and STA3. As an example, data communication between an AP and multiple STAs may include: downlink transmission in which an AP sends signals to multiple STAs at the same time, and uplink transmission in which multiple STAs send signals to an AP at the same time.

The technical solution provided by the present application can also be applied to data communication between APs, as shown in (a) of Figure 1, the technical solution provided by the present application is applicable to data communication between AP1 and AP2. The technical solution provided by the present application can also be applied to data communication between STAs, as shown in (b) of Figure 1, the technical solution provided by the present application is applicable to data communication between STA2 and STA3.

Among them, the access point can be the access point for the terminal (for example, mobile phone) to enter the wired (or wireless) network. It is mainly deployed in homes, buildings and parks, with a typical coverage radius of tens to hundreds of meters. Of course, it can also be deployed outdoors. The access point is equivalent to a bridge connecting the wired network and the wireless network. Its main function is to connect various wireless network clients together and then connect the wireless network to the Ethernet.

As an example, an access point may be a terminal or network device with a Wi-Fi chip, and the network device may be a router, a relay station, a vehicle-mounted device, a wearable device, a network device in a 5G network, a network device in a future 6G network, or a network device in a public land mobile network (PLMN), etc., and the embodiments of the present application are not limited thereto. The access point may also be a device that supports the 802.11be standard. The access point may also be a device that supports multiple WLAN standards of the 802.11 family, such as 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11a, and 802.11be next generation. The access point in this application may be a high efficiency (high It can also be an access point that is applicable to a future generation of Wi-Fi standards.

Among them, the site can be a wireless communication chip, a wireless sensor or a wireless communication terminal, etc., and can also be called a user, user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent or a user device.

As an example, the site can be a mobile phone supporting Wi-Fi communication function, a tablet supporting Wi-Fi communication function, a set-top box supporting Wi-Fi communication function, a smart TV supporting Wi-Fi communication function, a smart wearable device supporting Wi-Fi communication function, a vehicle-mounted communication device supporting Wi-Fi communication function, a computer supporting Wi-Fi communication function, an IoT node supporting Wi-Fi communication function, a sensor, etc., a smart home supporting Wi-Fi communication function, such as a smart camera, a smart remote control, a smart water meter, and a sensor in a smart city. Optionally, the site can support the 802.11be standard. The site can also support multiple WLAN standards of the 802.11 family, such as 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11a, and 802.11be next generation.

It can be understood that FIG1 is only a simplified schematic diagram for ease of understanding, and the system architecture may further include other APs or other STAs, which are not shown in FIG1 .

To facilitate understanding of the embodiments of the present application, a brief description of the terms involved in the present application is given.

1. Hybrid automatic repeat request (HARQ): In the process of data transmission, transmission bit errors or packet loss may occur. The robustness of data transmission can be improved through the HARQ mechanism. HARQ is a retransmission mechanism that combines forward error correction (FEC) and automatic repeat request (ARQ). FEC: It is an error control method, which means that before the signal is sent to the transmission channel, the sender pre-encodes it according to the algorithm and adds redundant codes with the characteristics of the signal itself; the receiver decodes the received signal according to the corresponding algorithm to find out the error code generated during the transmission process and correct it. ARQ: It means that the receiver determines whether the received data is correct by checking the information through cyclic redundancy check (CRC), and feeds back the judgment result to the sender; if the reception is wrong, the sender resends the data after receiving the feedback information until the receiver receives it correctly.

If the receiving end receives erroneous data, it will request retransmission. Although these erroneous data packets cannot be correctly decoded independently, they still contain some useful information. Therefore, soft combining is proposed in the HARQ mechanism. Soft combining means that the receiving end saves the received erroneous data packets in a HARQ buffer and combines them with the retransmitted data packets received subsequently, and then decodes the combined data packets. If the decoding still fails, it requests retransmission again and then combines the data packets to obtain a more reliable data packet than decoding alone. Two gains can be obtained through soft combining: 1) signal energy gain obtained when retransmitting the same coded bits, and 2) coding gain obtained by sending additional check bits during retransmission. According to whether the bit information of the retransmission is the same as the bit information of the initial transmission, soft combining can also be divided into chase combining (CC) and incremental redundancy (IR). In chase combining, the bit information of the retransmission is the same as the bit information of the initial transmission, and in incremental redundancy, the bit information of the retransmission does not need to be the same as the bit information of the initial transmission.

In chase combining, the sender adds CRC to the original information bits and generates a coded bit set through encoding. This coded bit set is sent regardless of the initial transmission or retransmission. The bit information of each retransmission is the same as the bit information of the initial transmission, which can improve the signal-to-noise ratio.

In incremental redundancy, the bit information of each retransmission can be different from the bit information of the initial transmission. The sender can generate multiple sets of coded bits, each of which carries the same information. Whenever a retransmission is required, a different set of coded bits is usually transmitted, and the receiver merges the retransmitted data with the previously transmitted data. Each retransmitted set of coded bits is called a redundancy version (RV). In incremental redundancy, the sender sends additional redundant information through retransmission. As the number of retransmissions increases, the redundant information accumulates, thereby obtaining better decoding results.

2. Coding rate: In the channel coding process, it is used to indicate the ratio of data bits (such as information bits) to coding bits. For example, if the length of data bits is k and the length of coding bits is n, then the coding rate is k/n. The coding rate can be referred to as the code rate.

3. Low density parity check (LDPC) code: a type of linear block code with a sparse check matrix, that is, the number of zero elements in the check matrix is much greater than the number of non-zero elements, or the row and column weights of the check matrix are very small compared to the code length of the LDPC. An [n, k] linear block code can be understood as encoding data bits of length k to obtain coded bits of length N. An LDPC code with a data bit length equal to k and a code length equal to n can be uniquely determined by its check matrix.

The check matrix of LDPC can be represented by a Tanner graph. The Tanner graph contains two types of nodes: one type of node represents codeword bits, which can be called variable nodes; the other type of node represents check nodes, which represent check constraint relationships, and each check node represents a check constraint relationship. The following is an explanation in conjunction with Figures 2 and 3.

See Figure 2, which is a schematic diagram of the LDPC check matrix. In Figure 2, {V _i } represents a variable node set, and {C _j } represents a check node set. Each row of the check matrix represents a check equation, and each column represents a codeword bit. In Figure 2, there are 8 variable nodes, such as i = 1, 2, ..., 8; there are 4 check nodes, such as j = 1, 2, 3, 4. If a code word bit is included in the corresponding check equation, a line is used to connect the bit node and the check node involved to obtain a Tanner graph.

See FIG. 3, which is a schematic diagram of the Tanner graph corresponding to the check matrix. As shown in FIG. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. Each circular node in FIG. 3 is a variable node, and each square node is a check node. Among them, the n variable nodes correspond to the n columns of the check matrix H, respectively, and the m check nodes correspond to the m rows of the check matrix H, respectively. The cycle in the Tanner graph is composed of vertices connected to each other. The cycle uses one vertex in this group of vertices as both the starting point and the end point, and only passes through each node once. The variable nodes in the Tanner graph correspond to each column of the check matrix H, that is, to each codeword bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, that is, to the check bits of the LDPC. The connection between the two types of nodes corresponds to the values of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the value of the element (i, j) in the check matrix H is 1. If there is no connection, the corresponding element is 0.

As mentioned above, LDPC code is a linear block code. The linear block code divides the data bits to be encoded into groups of k bits, and then the encoder performs linear operations on the k data bits to obtain m check bits. Then, the k data bits are combined with the m check bits to obtain a code group of length n = k + m. The mapping relationship from k-bit data to a code group of length n bits is usually represented by a corresponding check matrix H. According to the check matrix H, the coding bits can be generated accordingly to complete the coding process. After the coding bits are transmitted through the channel, the receiving end decodes the received signal accordingly to determine the original data bits.

In the case of long code length, the LDPC check matrix H will be very large, so H is usually represented in blocks: the complete check matrix H is regarded as generated by multiple z×z sub-matrices. Specifically, the complete check matrix H can be represented by a base matrix _Hb , each element in _Hb corresponds to a z×z sub-matrix, and each sub-matrix can be represented by the number of cyclic shift bits, thereby greatly reducing the storage space required for the complete check matrix H.

As an example, the embodiment of the present application can adopt the check matrix in the 802.11ac or 802.11ax standard, supporting code lengths of 1944, 1296 and 648. These three code lengths all support a code rate of 1/2. Based on the base matrix H _b and the expansion factor z given by the 802.11ac or 802.11ax standard, the base matrix can be expanded to a complete check matrix for encoding or decoding.

Among them, the LDPC used in the IEEE 802.11ac and 802.11ax standards is the quasi-cyclic low density parity check (QC-LDPC) code. QC-LDPC code is a type of structured LDPC. Due to the unique structure of its check matrix, it can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC.

IEEE 802.11ac and 802.11ax adopt a total of 12 LDPC check matrices, which support three code lengths, namely 648, 1296 and 1944. Each code length supports four different code rates, namely 1/2, 2/3, 3/4 and 5/6. The check bit parts of the 12 check matrices have the same structure.

For example, the check matrix H of the LDPC with a code length of 1944 and a code rate of 5/6 in 802.11ac is as follows:

It can be seen that the size of the check matrix H is 4 rows and 24 columns. Each element in the check matrix H represents a square matrix of order z = N/24. The element 0 in the check matrix H represents a square matrix of size z×z with all zeros. represents a cyclic permutation matrix, i represents a cyclic shift value, where 0≤i≤z-1, i is an integer. In addition, "-" in the matrix represents an all-zero matrix, and "0" represents a unit matrix.

For example, As follows:

When LDPC encoding is performed in WLAN, the transmitter selects the corresponding check matrix from the above 12 check matrices according to the target code length and target code rate. Among them, 12 check matrices are different from each other.

4. LDPC coding: According to the WLAN standard (e.g., IEEE 802.11n/ac standard), due to the use of orthogonal frequency division multiplexing (OFDM) technology, the LDPC coding module needs to encode the data bits and put them into an integer number of OFDM symbols, and these encoded bits can be placed in an integer number of LDPC codewords. Specifically, first determine the minimum number of OFDM symbols required for this transmission, such as N _SYM ; then determine the total number of coded bits that can be placed in all OFDM symbols based on N _SYM and the current coding and modulation scheme, that is, N _TCB = N _CBPS · N _SYM , where N _CBPS represents the number of coded bits that can be placed in each OFDM symbol; finally, determine the LDPC code length and the number of codewords required for the current transmission based on the above results. In the above process, for most combinations of the length of the data bit to be encoded and the coding and modulation scheme, the data bits may not fill the information bit part in the LDPC codeword, so a shortening operation can be performed before generating the check bits. The shortening operation refers to filling a certain number of 0 bits in the information bit part before the LDPC code generates the check bits, and then deleting these 0 bits after the code generates the check bits.

Referring to FIG. 4 , FIG. 4 is a schematic diagram of the LDPC encoding steps. As an example, as shown in FIG. 4 , LDPC may include the following steps. Step 1: Determine the payload bit, that is, determine the data bit to be encoded. Step 2: Determine the length of the LDPC codeword and the number of codewords. Step 3: Shortening operation, that is, shortening the data bit, adding a shortening zero bit. Step 4: Generate check bits, that is, generate check bits using data bits and shortening zero bits, such as parity bits. After the check bits are generated, the shortening zero bits added in step 3 are deleted, and the check bits are such as parity bits.

5. LDPC code decoding stop criteria: can be used to end the decoding iteration of the decoder, and can also be used for HARQ transmission based on codeword retransmission. Generally, the purpose of introducing decoding stop criteria for LDPC codes includes:

1) Data verification: The decoding stop criterion provides a reliability indication for the transmitted data packet, which can be used to provide feedback to the upper layer of the data transmission whether the data packet is received correctly, or to generate control information for HARQ transmission (e.g., acknowledgment (ACK) information or negative acknowledgment (NACK));

2) Saving energy and delay: The decoding stop criterion can avoid the waste of decoding energy and decoding delay by avoiding unnecessary redundant iterations. Unnecessary redundant iterations refer to iterations when the current codeword cannot be decoded correctly or when the current codeword has been correctly recovered.

Generally speaking, decoding stopping criteria can be divided into type A stopping criteria and type B stopping criteria.

Among them, the type A stopping criterion is used to determine whether the decoder correctly determines that the current codeword has been decoded correctly, that is, to provide a reliability indication as to whether the current codeword has been correctly recovered.

Among them, the B-type stopping criterion is used to determine whether the current codeword is unrecoverable, that is, to feedback the unrecoverable error as early as possible, thereby avoiding unnecessary decoding iterations to reduce energy consumption and save time.

From the above, it can be seen that a good decoding stop criterion can effectively end the decoding iteration of the decoder early, thereby achieving the purpose of reducing energy consumption and decoding delay.

6. Judgment events: Judgment events that may occur during the decoding process when the decoding stop criteria is adopted.

Before giving various judgment events, we first introduce the genie aided stopping rule, which is the ideal situation for decoding judgment. This genie aided stopping rule generally does not exist, and is mainly used here to compare with the various decoding stopping rules proposed in this application. The genie aided stopping rule means that after each iterative decoding, the information bits obtained by the iterative decoding are compared with the information bits actually transmitted, and if the two are the same, the decoding iteration is stopped.

As an example, Table 1 lists possible decision events when the decoding stop criterion is adopted. Before introducing Table 1, the following description is made first.

1) Reliability indication: used to indicate whether the decoding end has decoded correctly. The reliability indication can be expressed as: reliable packet indication (such as indicated by c) or unreliable packet indication (such as indicated by w).

For example, if the correct information bit is recovered within n _MAX iterations, the decoding end feeds back a reliable packet indication, which can be used to indicate that the decoding end has successfully received the data. As an example, the decoding end can also feed back the minimum number of iterations required, where n _MAX represents the maximum number of iterations.

For another example, if the current codeword is erroneous and unrecoverable, the decoding end immediately stops decoding iterations and feeds back an unreliable packet indication, which may be used to indicate that the decoding end has not successfully received data.

To distinguish, _ed is used to represent the reliability indication when a general decoding stop criterion (i.e., a decoding stop criterion other than the perfect decoding stop criterion) is adopted, and e _g is used to represent the reliability indication when the perfect decoding stop criterion is adopted. _ed ∈[c,w], e _g ∈[c,w].

2) Number of decoding iterations required: indicates the number of decoding iterations required by the decoding end to decode the received codeword.

To distinguish, n _d is used to represent the number of seconds required when using a general decoding stop criterion (i.e., a decoding stop criterion other than the perfect decoding stop criterion). The number of decoding iterations, n _g represents the number of decoding iterations required when the perfect decoding stopping criterion is adopted. n _d ∈[0,n _MAX ], n _g ∈[0,n _MAX ].

3) ‘True’ reliable indication: indicates the true status of the information bit fed back by the decoder when the general decoding stop criteria (i.e., the decoding stop criteria other than the perfect decoding stop criteria) are adopted. For simplicity, true is used to represent the ‘true’ reliable indication, true∈[c,w]. Where c indicates that the information bit fed back by the decoder is correct, and w indicates that the information bit fed back by the decoder is wrong.

Table 1

As shown in Table 1, when _ed is c, e _g is c, true is c, and n _d ≥ n _g , the event name of the decision event is detected correct (DC). Successful and correct detection: The decoding end declares that no error occurs, that is, when the general decoding stop criterion (that is, the decoding stop criterion other than the perfect decoding stop criterion) is adopted, the HARQ fed back by the decoding end is correct. In this case, the decoding end feeds back ACK, indicating that the data is successfully received, wherein the ACK fed back by the decoding end is correct. In this case, the decoding end can also feed back a non-negative number of wasted iterations (such as called the extra iteration number): Δ = (n _d - n _g ).

As shown in Table 1, when _ed is c, e _g is w, true is c, and n _d ≥ n _g , the event name of the judgment event is false alarm (FA). FA: There is no error in the codeword information bit part, but the decoding end declares a decoding error, that is, when the general decoding stop criterion (that is, the decoding stop criterion other than the perfect decoding stop criterion) is adopted, the HARQ fed back by the decoding end is wrong. In this case, the decoding end feeds back a wrong NACK, wherein the NACK fed back by the decoding end is wrong, thus causing unnecessary retransmission.

As shown in Table 1, when _ed is c, e _g is w, true is w, and _nd < _ng , the event name of the judgment event is false detected error (FDE). FDE: The decoder declares that there is an unrecoverable error, but the error is actually recoverable (for example, the error can be recovered by increasing the number of decoding iterations). In this case, the decoder feeds back a not necessary NACK (Not nec. NACK), which may increase the detected frame error rate (FER) and the actual FER.

As shown in Table 1, when _ed is w, e _g is c, true is w, and n _d ≥0＝ _ng , the event name of the judgment event is undetected error (UE). Undetected error: The decoding end declares that there is no error, but there is actually an unrecoverable error, that is, when the general decoding stop criterion (that is, the decoding stop criterion other than the perfect decoding stop criterion) is adopted, the HARQ fed back by the decoding end is wrong. In this case, the decoding end feeds back a wrong ACK, wherein the ACK fed back by the decoding end is wrong, which may reduce the detected FER but does not change the real FER.

As shown in Table 1, when _ed is c, e _g is c, true is w, and _nd < _ng , the event name of the judgment event is false undetected error (FUE). FUE: The decoder declares that there is no error, but there is actually a recoverable error, that is, when the general decoding stop criterion (that is, the decoding stop criterion other than the perfect decoding stop criterion) is adopted, the HARQ fed back by the decoder is wrong. In this case, the decoder feeds back a wrong NACK and a non-necessary ACK (not necessary ACK, Not nec.ACK), where the NACK fed back by the decoder is wrong. FUE is more harmful than undetected error because FUE may increase the actual FER but does not change the detected FER. FER.

As shown in Table 1, _ed is w, e _g is w, true is w, and when n _d ≥ 0, the event name of the decision event is successfully error detected (DE). Successful error detection: The decoding end correctly declares an unrecoverable error.

It can be understood that the above Table 1 is for illustrative purposes only and is not intended to be limiting.

In the prior art, the decoding stop criterion is to calculate whether all the check equations contained in the check matrix are satisfied according to the check matrix of the LDPC code and the current decoding codeword result. If satisfied, the decoding is declared correct, otherwise it enters the next decoding iteration. The mathematical expression is as shown in Formula 1.
H·c ^T ＝s ^T

Formula 1

Where H represents the check matrix of the LDPC code. c represents the decoding decision codeword sequence after the current decoding iteration, c = [c ₁ ,c ₂ ,…,c _N ]. s represents the syndrome vector obtained by multiplying the check matrix and the current decision, s = [s ₁ ,s ₂ ,…,s _M ]. The superscript T represents the transpose, such as c ^T represents the transpose of the matrix (or vector) c. If s is an all-zero vector, the current decoding decision is correct, the decoding iteration can be stopped, and the current decision codeword can be output as the decoding result.

The above decoding stop criteria need to determine that all the check equations included in the check matrix are correct before the decoding iteration can be stopped. In this way, the information codeword may be decoded correctly, but due to the incorrectness of some check equations, the decoding cannot be ended early, resulting in waste of power consumption and increased decoding delay. In addition, the receiving end only needs the information bit. Since the above decoding stop criteria need to determine that all the check equations included in the check matrix are correct before declaring the decoding correct, if the error only exists in the check bit part, the decoder will also declare the decoding failed, resulting in unnecessary retransmission.

In view of this, the present application provides a solution that can reduce the power consumption waste and delay increase caused by additional iterations and unnecessary retransmissions.

The above briefly describes the terms involved in this application, which will not be repeated in the following embodiments. In addition, the above description of terms is only for ease of understanding and does not limit the protection scope of the embodiments of this application.

It can be understood that the term "and/or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character "/" in this article generally indicates that the associated objects before and after are in an "or" relationship.

The method provided by the embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. The embodiment provided by the present application can be applied to any communication scenario in which a transmitting device (such as an encoding device) and a receiving device (such as a decoding device) communicate, such as being applied to the communication system shown in Figure 1 above.

In the following embodiments, the interaction between the encoding device and the decoding device is taken as an example for description. The encoding device may be an encoding device or a component of an encoding device (such as a chip, circuit or module, etc.), and the decoding device may be a decoding device or a component of a decoding device (such as a chip, circuit or module, etc.).

Referring to Fig. 5, Fig. 5 is a schematic diagram of an encoding method 500 provided in an embodiment of the present application. The method 500 may include the following steps.

510. The encoding device performs LDPC encoding on the data bits to obtain an encoded LDPC code stream, where the data bits include information bits and CRC bits generated according to the information bits.

Specifically, the encoding device performs LDPC encoding on the bits to be encoded (i.e., data bits) to obtain an encoded LDPC code stream, wherein the bits to be encoded include information bits to be encoded and CRC bits. The CRC bits can be generated based on all or part of the information bits, so for ease of description, the CRC bits can also be referred to as CRC bits of the information bits.

Optionally, the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream. Based on this, the position of the CRC bit can be determined according to the robustness of at least one data bit position in the LDPC code stream; in other words, the position of the CRC bit is a position where the robustness meets certain conditions. For example, if the robustness of a certain position meets certain conditions, then the position can be the position of the CRC bit, that is, the CRC bit is placed at this position.

Among them, the robustness of the data bit position, that is, the robustness of the position where the data bit is located, can reflect the degree to which the data bit is affected by noise during channel transmission. For the sake of simplicity, the robustness of the data bit position is referred to as the robustness of the data bit below. Exemplarily, the robustness of a data bit that is easily affected by noise is lower than the robustness of a data bit that is not easily affected by noise. It can also be said that the more susceptible the data bit is to noise, the more sensitive it is to noise, and the lower its robustness; conversely, the less susceptible the data bit is to noise, the less sensitive it is to noise, and the higher its robustness. Alternatively, robustness can also be referred to as confidence or reliability, etc.

As an example, the log-likelihood ratio (LLR) can characterize the robustness of a data bit. Specifically, the absolute value |LLR| can be used as a robustness feature to determine the robustness ranking of the data bits, where the smaller the |LLR|, the more sensitive the bit position corresponding to the |LLR| is and the lower the robustness is.

It is understandable that using LLR to characterize the robustness of data bits is only an exemplary description and is not limiting. For example, the structure of the data bits themselves may also be used to characterize the robustness of the data bits.

Optionally, the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, including: the robustness of the position of the CRC bit is higher than the robustness of the position of at least one information bit in the LDPC code stream. Based on this method, the robustness of the position of the CRC bit in the LDPC code stream is higher than the robustness of the position of at least one information bit, so that by preferentially selecting a position with higher robustness as the position of the CRC bit, that is, placing the CRC bit at a position with higher robustness, the reliability of the CRC bit can be improved, and then the information bit in the LDPC code stream can be assisted in decoding based on the CRC bit.

For example, the LDPC code stream includes X data bits, and at least two information bits among the X data bits have different robustness. Then the robustness of the position where the CRC bit is located is higher than the robustness of at least one information bit among the X information bits. That is to say, among the X data bits, the robustness of the position where the CRC bit is located is not the lowest.

In one possible implementation, the position where the CRC bit is located has the highest robustness, that is, the position where the CRC bit is located is the position where the data bit in the LDPC code stream has the highest robustness. It can be understood that the above implementation is an exemplary description and is not limited to this. For example, the position where the CRC bit is located is the position where the data bit in the LDPC code stream has the second highest robustness.

Optionally, the position of the CRC bit is related to the robustness of at least one data bit in the LDPC code stream, including: when the robustness of at least two data bits in the LDPC code stream is consistent, the position of the CRC bit is located at a front position in the at least two data bits. Based on this method, when the robustness of at least two data bits is consistent, by placing the CRC bit at a front position, it is convenient for the decoding end to obtain the CRC bit more quickly, and then the information bit in the LDPC code stream can be assisted in decoding based on the CRC bit.

For example, assuming that the robustness of two data bits is consistent, and the first data bit is located in the front and the second data bit is located in the back, such as the first data bit is located in the a1th column of the check matrix and the second data bit is located in the a2th column of the check matrix, and a1 is less than a2, then the CRC bit can be located in the position of the first data bit, that is, the CRC bit can be located in the a1th column of the check matrix.

Wherein, the robustness of the data bits is consistent, indicating that the robustness of the data bits is the same or similar. For example, if the robustness of at least two data bits is the same, it can be considered that the robustness of the at least two data bits is consistent. For another example, if the difference in the robustness of at least two data bits is within a preset range, it can also be considered that the robustness of the at least two data bits is consistent. Wherein, the difference in the robustness of at least two data bits is within a preset range, which means that the robustness of at least two data bits is not much different, such as the difference in the absolute value |LLR| of the LLR of at least two data bits is within a preset range. Wherein, the preset range can be a specific value, or it can also be a numerical range, which is not limited. The preset range can be predefined, such as predefined by a standard; or it can also be preconfigured; or it can also be estimated based on historical circumstances, which is not limited.

Optionally, the parameters of the CRC bits are not limited. The parameters of the CRC bits include, for example: the number of CRC bits and/or a generator polynomial. As an example, Table 2 shows an example of the number of CRC bits.

Table 2

It can be understood that the above Table 2 is for illustrative purposes only and is not intended to be limiting.

520, the encoding device sends the LDPC code stream to the decoding device. Correspondingly, the decoding device receives the LDPC code stream.

Optionally, method 500 also includes step 530 .

530, the decoding device decodes the LDPC code.

The decoding device decodes the LDPC to obtain corresponding information bits.

In an embodiment of the present application, by adding CRC bits to the LDPC code stream, auxiliary decoding can be performed based on the CRC bits during the decoding iteration process, that is, the auxiliary decoding end determines whether the decoding is successful. For example, after the decoding device decodes the data bits (or information bits), the CRC bits can be further used to verify the decoded information bits. If the CRC bit verification is correct, it is considered that the information bits are successfully decoded, that is, the decoding is correct; otherwise, the decoding can continue until the decoding is correct. In addition, the position of the CRC bit can be related to the robustness of the data bits in the LDPC code stream, so that the position of the CRC bit can be selected according to actual needs. For example, if the reliability of the CRC bit is to be improved, the position with higher robustness can be preferentially selected as the position of the CRC bit, that is, the CRC bit is placed in a position with higher robustness, so that the reliability of the CRC bit can be improved, and then the information bits in the LDPC code stream can be assisted in decoding based on the CRC bit.

Under different code lengths and code rates, the positions of the CRC bits may be different.

As an example, the possible positions of CRC bits under different code lengths and code rates are shown below in combination with Tables 3 to 14. In the following example, the absolute value of LLR |LLR| is used as an example to characterize robustness. The specific method for calculating LLR is not limited, for example, it can be calculated in a known or unknown manner.

Example 1: When the code length of the LDPC code stream is 1944 and the code rate is 1/2, the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 1/2, a data bit length of 972, and a code length of 1944 and their reliability ranking can be shown in Table 3.

table 3

In the first row of Table 3, "Robustness Sorting", each element a(b) represents the ath column of the check matrix, and the column weight of the ath column is b. The |LLR| corresponding to the ath column represents the absolute value of the LLR of the data bit corresponding to the ath column, which can reflect the robustness of the data bit corresponding to the column, wherein the larger the |LLR|, the higher the robustness; conversely, the smaller the |LLR|, the lower the robustness.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 3 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, that is, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (11). As an example, the absolute value of the LLR at this position is 126.7955.

In another possible implementation, the CRC bit is located at the position with the second highest robustness. Taking the example shown in Table 3 as an example, the CRC bit can be located at the position with the second largest absolute value of the LLR, that is, the CRC bit can be located at the 9th column in the check matrix, that is, the position 9 (11), and as an example, the absolute value of the LLR at this position is 126.7682.

It can be understood that the above implementation is for illustrative purposes only and is not intended to limit this. For example, the CRC bit may also be located at other positions, such as the CRC bit may also be located at the 5th column in the check matrix, that is, position 5(11).

Example 2: When the code length of the LDPC code stream is 1944 and the code rate is 2/3, the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 2/3, a data bit length of 1296, and a code length of 1944 and their robustness ranking can be shown in Table 4.

Table 4

For the meaning of each element in Table 4, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 4 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (8); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2 (8); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3 (8); or, the CRC bit can be located in the fourth column of the check matrix, that is, the position of 4 (8). As an example, the absolute value of the LLR at the above position is 147.9562. Optionally, if the position of the CRC bit is located at the front position of at least two data bits under the condition that the robustness of at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (8).

In another possible implementation, the CRC bit is located at a position with the second highest robustness. Taking the example shown in Table 4 as an example, the CRC bit may be located at the fifth column in the check matrix, that is, position 5(6).

It is understood that the above implementation is for exemplary purposes only and is not intended to limit this. For example, the CRC bits may also be located at other positions.

Example 3, when the code length of the LDPC code stream is 1944 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 3/4, a data bit length of 1458, and a code length of 1944 and their robustness ranking can be shown in Table 5.

table 5

For the meaning of each element in Table 5, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 5 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (6); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2 (6); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3 (6); or, the CRC bit can be located in the fourth column of the check matrix, that is, the position of 4 (6); or, the CRC bit can be located in the fifth column of the check matrix, that is, the position of 5 (6); or, the CRC bit can be located in the sixth column of the check matrix, that is, the position of 6 (6). As an example, the absolute value of the LLR at the above position is 81.8940. Optionally, if the position of the CRC bit is located at the front position of at least two data bits under the condition that the robustness of at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (6).

It can be understood that the above implementation is an exemplary description and is not limited to this. For example, the CRC bit can also be located at or other positions.

Example 4: When the code length of the LDPC code stream is 1944 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, and column 10.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 5/6, a data bit length of 1620, and a code length of 1944 and their robustness ranking can be shown in Table 6.

Table 6

For the meaning of each element in Table 6, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 6 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (4); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2 (4); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3 (4); or, the CRC bit can be located in the fourth column of the check matrix, that is, the position of 4 (4); or, the CRC bit can be located in the fifth column of the check matrix, that is, the position of 5 (4); or, the CRC bit can be located in the sixth column of the check matrix, that is, the position of 6 (4); or, the CRC bit can be located in the seventh column of the check matrix, that is, the position of 7 (4); or, the CRC bit can be located in the eighth column of the check matrix, that is, the position of 8 (4); or, the CRC bit can be located in the ninth column of the check matrix, that is, the position of 9 (4); or, the CRC bit can be located in the tenth column of the check matrix, that is, the position of 10 (4). As an example, the absolute value of the LLR at the above position is 111.6094. Optionally, if the position of the CRC bit is located at the front position of the at least two data bits when the robustness of the at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1(4).

It is understood that the above implementation is for exemplary purposes only and is not intended to limit this. For example, the CRC bits may also be located at other positions.

Example 5: When the code length of the LDPC code stream is 1296 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 1/2, a data bit length of 648, and a code length of 1296 and their robustness ranking can be shown in Table 7.

Table 7

For the meaning of each element in Table 7, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 7 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, that is, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (11). As an example, the absolute value of the LLR of the data bit is 144.4487.

In another possible implementation, the CRC bit is located at the position with the second highest robustness. Taking the example shown in Table 7 as an example, the CRC bit can be located at the position with the second largest absolute value of the LLR, that is, the CRC bit can be located at the 9th column in the check matrix, that is, the position 9 (11). As an example, the absolute value of the LLR of the data bit is 144.3379.

It can be understood that the above implementation is for illustrative purposes only and is not intended to limit this. For example, the CRC bit may also be located at other positions, such as the CRC bit may also be located at the 5th column in the check matrix, that is, position 5(11).

Example 6, when the code length of the LDPC code stream is 1296 and the code rate is 2/3, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 2/3, a data bit length of 864, and a code length of 1296 and their robustness ranking can be shown in Table 8.

Table 8

For the meaning of each element in Table 8, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 8 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (8); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2 (8); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3 (8). As an example, the absolute value of the LLR at the above position is 147.3210. Optionally, if the position of the CRC bit is located at the front position of at least two data bits when the robustness of at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (8).

In another possible implementation, the CRC bit is located at the position with the second highest robustness. Taking the example shown in Table 8 as an example, the CRC bit can be located at the position with the second largest absolute value of the LLR, that is, the CRC bit can be located at the 5th column in the check matrix, that is, position 5(7).

It is understood that the above implementation is for exemplary purposes only and is not intended to limit this. For example, the CRC bits may also be located at other positions.

Example 7, when the code length of the LDPC code stream is 1296 and the code rate is 3/4, the position of the CRC bit is located in the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 3/4, a data bit length of 972, and a code length of 1296 and their robustness ranking can be shown in Table 9.

Table 9

For the meaning of each element in Table 9, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 9 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (6); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2 (6); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3 (6); or, the CRC bit can be located in the fourth column of the check matrix, that is, the position of 4 (6); or, the CRC bit can be located in the fifth column of the check matrix, that is, the position of 5 (6); or, the CRC bit can be located in the sixth column of the check matrix, that is, the position of 6 (6); or, the CRC bit can be located in the seventh column of the check matrix, that is, the position of 7 (6). As an example, the absolute value of the LLR at the above position is 81.9962. Optionally, if the position of the CRC bit is located at the front position of the at least two data bits under the condition that the robustness of at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (6).

It can be understood that the above implementation is an exemplary description and is not limited to this. For example, the CRC bit can also be located at or other positions.

Example 8. When the code length of the LDPC code stream is 1296 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12, column 13, column 14, column 15, and column 16.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 5/6, a data bit length of 1080, and a code length of 1296 and their robustness ranking can be shown in Table 10.

Table 10

For the meaning of each element in Table 10, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 10 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1(3); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2(3); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3(3); or, the CRC bit can be located in the fourth column of the check matrix, that is, the position of 4(3); or, the CRC bit can be located in the fifth column of the check matrix, that is, the position of 5(3); or, the CRC bit can be located in the sixth column of the check matrix, that is, the position of 6(3); or, the CRC bit can be located in the seventh column of the check matrix, that is, the position of 7(4); or, the CRC bit can be located in the eighth column of the check matrix, that is, 8(4); or, the CRC bit may be located at the 9th column in the check matrix, i.e., the 9(4) position; or, the CRC bit may be located at the 10th column in the check matrix, i.e., the 10(4) position; or, the CRC bit may be located at the 11th column in the check matrix, i.e., the 11(4) position; or, the CRC bit may be located at the 12th column in the check matrix, i.e., the 12(4) position; or, the CRC bit may be located at the 13th column in the check matrix, i.e., the 13(4) position; or, the CRC bit may be located at the 14th column in the check matrix, i.e., the 14(4) position; or, the CRC bit may be located at the 15th column in the check matrix, i.e., the 15(4) position; or, the CRC bit may be located at the 16th column in the check matrix, i.e., the 16(4) position. As an example, the absolute value of the LLR at the above position is 53.5355. Optionally, if the CRC bit is located at a front position in the at least two data bits when the robustness of at least two data bits is consistent, the CRC bit may be located in the first column of the check matrix, that is, position 1(3).

It is understood that the above implementation is for exemplary purposes only and is not intended to limit this. For example, the CRC bits may also be located at other positions.

Example 9, when the code length of the LDPC code stream is 648 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 5, column 9.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 1/2, a data bit length of 324, and a code length of 648 and their robustness ranking can be shown in Table 11.

Table 11

For the meaning of each element in Table 11, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 11 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (12); or, the CRC bit can be located in the fifth column of the check matrix, that is, the position of 5 (12); or, the CRC bit can be located in the ninth column of the check matrix, that is, the position of 9 (12). As an example, the absolute value of the LLR at the above position is 199.0153. Optionally, if the position of the CRC bit is located at the front position of at least two data bits when the robustness of at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (12).

It is understood that the above implementation is for exemplary purposes only and is not intended to limit this. For example, the CRC bits may also be located at other positions.

Example 10, when the code length of the LDPC code stream is 648 and the code rate is 2/3, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 2/3, a data bit length of 456, and a code length of 648 and their robustness ranking can be shown in Table 12.

Table 12

For the meaning of each element in Table 12, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 12 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (8); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2 (8); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3 (8). As an example, the absolute value of the LLR at the above position is 140.6811. Optionally, if the position of the CRC bit is located at the front position of at least two data bits when the robustness of at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (8).

It is understood that the above implementation is for exemplary purposes only and is not intended to limit this. For example, the CRC bits may also be located at other positions.

Example 11, when the code length of the LDPC code stream is 648 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 3/4, a data bit length of 486, and a code length of 648 and their robustness ranking can be shown in Table 13.

Table 13

For the meaning of each element in Table 13, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 13 as an example, the CRC bit is located at the position with the largest absolute value of the LLR, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (6); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2 (6); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3 (6); or, the CRC bit can be located in the fourth column of the check matrix, that is, the position of 4 (6); or, the CRC bit can be located in the fifth column of the check matrix, that is, the position of 5 (6). As an example, the absolute value of the LLR at the above position is 113.0070. Optionally, if the position of the CRC bit is located at the front position of at least two data bits under the condition that the robustness of at least two data bits is consistent, the CRC bit can be located in the first column of the check matrix, that is, the position of 1 (6).

It can be understood that the above implementation is an exemplary description and is not limited to this. For example, the CRC bit can also be located at or other positions.

Example 12, when the code length of the LDPC code stream is 648 and the code rate is 5/6, the position of the CRC bit is located in the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12, column 14, column 15, column 16, column 17, column 18, column 19, and column 20.

For example, the absolute value of LLR of the data bits in the check matrix corresponding to the LDPC codeword with a code rate of 5/6, a data bit length of 540, and a code length of 648 and their robustness ranking can be shown in Table 14.

Table 14

For the meaning of each element in Table 14, please refer to the description in Table 3, which will not be repeated here.

In a possible implementation, the CRC bit is located at the position with the highest robustness. Taking the example shown in Table 14 as an example, the CRC bit is located at the position where the absolute value of the LLR is the largest, such as the CRC bit can be located in the first column of the check matrix, that is, the position of 1(3); or, the CRC bit can be located in the second column of the check matrix, that is, the position of 2(3); or, the CRC bit can be located in the third column of the check matrix, that is, the position of 3(3); or, the CRC bit can be located in the fourth column of the check matrix, that is, the position of 4(3); or, the CRC bit can be located in the fifth column of the check matrix, that is, the position of 5(3); or, the CRC bit can be located in the sixth column of the check matrix, that is, the position of 6(4); or, the CRC bit can be located in the seventh column of the check matrix, that is, the position of 7(4); or, the CRC bit can be located in the eighth column of the check matrix, that is, the position of 8(4); or, the CRC bit can be located in the ninth column of the check matrix, that is, the position of 9(4); or, The CRC bit may be located at the 10th column, i.e., position 10(4) in the check matrix; or, the CRC bit may be located at the 11th column, i.e., position 11(4) in the check matrix; or, the CRC bit may be located at the 12th column, i.e., position 12(4) in the check matrix; or, the CRC bit may be located at the 14th column, i.e., position 14(4) in the check matrix; or, the CRC bit may be located at the 15th column, i.e., position 15(4) in the check matrix; or, the CRC bit may be located at the 16th column, i.e., position 16(4) in the check matrix; or, the CRC bit may be located at the 17th column, i.e., position 17(4) in the check matrix; or, the CRC bit may be located at the 18th column, i.e., position 18(4) in the check matrix; or, the CRC bit may be located at the 19th column, i.e., position 19(4) in the check matrix; or, the CRC bit may be located at the 20th column, i.e., position 20(4) in the check matrix. As an example, the absolute value of the LLR at the above position is 73.4420. Optionally, if the CRC bit is located at a front position in the at least two data bits when the robustness of at least two data bits is consistent, the CRC bit may be located in the first column of the check matrix, that is, position 1(3).

It is understood that the above implementation is for exemplary purposes only and is not intended to limit this. For example, the CRC bits may also be located at other positions.

In any of the above examples, by preferentially selecting a position with higher robustness (such as the highest position or the second highest position) as the position of the CRC bit, that is, placing the CRC bit at a position with higher robustness, the reliability of the CRC bit can be improved, and then the information bits in the LDPC code stream can be assisted in decoding based on the CRC bit. In addition, when the robustness of at least two data bits is consistent, by placing the CRC bit at a front position, it is convenient for the decoding end to obtain the CRC bit more quickly, and then the information bits in the LDPC code stream can be assisted in decoding based on the CRC bit.

It can be understood that the above Tables 3 to 14 are exemplary illustrations and are not limited thereto. The variations of Tables 3 to 14 are applicable to the embodiments of the present application. For example, the CRC bit may be located at the first X positions with higher robustness, where X is an integer greater than 1 or equal to 1. For another example, the CRC bit may be located at the Yth position in the robustness ranking, where Y is an integer greater than 1 or equal to 1, and Y may be predefined, such as predefined by the standard. For another example, the information to be expressed in Tables 3 to 14 may also be recorded in other variations. For another example, the absolute value of the LLR of the data bit in Tables 3 to 14 may be replaced by other indicators that can characterize robustness. For another example, the absolute value of the LLR of the data bit in Tables 3 to 14 may be other values. For another example, the column weight of each column in Tables 3 to 14 may be other values.

Optionally, in an embodiment of the present application, the number of bits of CRC is determined according to possible decision events. If the number of bits of CRC is small, that is, a small number of CRC bits are added to the codeword information bit part, then in the decoding iteration, some decision events as shown in Table 1 may occur, affecting the decoding performance; if the number of bits of CRC is large, that is, a large number of CRC bits are added to the codeword information bit part, then the overhead will be increased. Therefore, the number of bits of CRC can be determined according to the decision events that may occur when the CRC decoding stop criterion is adopted, so as to achieve a balance between performance and the overhead caused by adding CRC bits as much as possible. For ease of description, the method proposed by method 500, that is, the method including CRC bits in the LDPC code stream, is denoted as the CRC decoding stop criterion.

Referring to Fig. 6-Fig. 13, Fig. 6-Fig. 13 are the relations between the event probabilities of various decision events and the number of bits of CRC when the CRC decoding stopping criteria is adopted. As an example, Fig. 6-Fig. 13 takes the following decision events as examples for exemplary description: missed detection error (UE), false missed detection error (FUE), successful error detection (DE). When the CRC decoding stopping criteria is adopted, the false alarm (FA) and false error detection (FDE) probabilities are both close to 0, so these two curves are not given in the simulation curves shown in Fig. 6-Fig. 13.

In FIG. 6 to FIG. 13 , the horizontal axis is the number of bits of CRC, and the vertical axis is the event probability (event probability) and the number of excess iterations (excess iterations). The curves represent the change of the event probability of various decision events with the number of bits of CRC, and the change of FER and the number of iterations with the number of bits of CRC. Among them, the number of excess iterations represents the number of iterations wasted when the CRC decoding stop criterion is adopted compared with the perfect decoding stop criterion. For example, if the number of iterations when the perfect decoding stop criterion is adopted is _ng , and the number of iterations when the CRC decoding stop criterion is adopted is _nd , then the number of excess iterations _Δit = _nd - _ng . For simplicity, as an example, the value of the event probability is represented by a format with "E", taking 1.E-05 as an example, which represents: 1· ^10-5 . The curves in FIG. 6 to FIG. 13 also represent the change of the average number of iterations when the perfect decoding stop criterion is adopted with the number of bits of CRC (represented by itGA).

In FIG6 , the code length N=648, the code rate R=1/2, the maximum number of iterations n _MAX =50, and the FER is approximately 1E-1.

In FIG7 , the code length N=648, the code rate R=2/3, the maximum number of iterations n _MAX =50, and the FER is approximately 1E-1.

In FIG8 , the code length N=648, the code rate R=3/4, the maximum number of iterations n _MAX =50, and the FER is approximately 1E-1.

In FIG9 , the code length N=648, the code rate R=5/6, the maximum number of iterations n _MAX =50, and the FER is approximately 1E-1.

In FIG10 , the code length N=648, the code rate R=1/2, the maximum number of iterations n _MAX =50, and the FER is approximately 1E-2.

In FIG11 , the code length N=648, the code rate R=2/3, the maximum number of iterations n _MAX =50, and the FER is approximately 1E-2.

In FIG12 , the code length N=648, the code rate R=3/4, the maximum number of iterations n _MAX =50, and the FER is approximately 1E-2.

In FIG13 , the code length N=648, the code rate R=5/6, the maximum number of iterations n _MAX =50, and the FER is about 1E-2.

As can be seen from the examples in Figures 6 to 13, the event probabilities of different decision events are related to the number of CRC bits. For example, the probability of missed detection errors (UE) and false missed detection errors (FUE) will decrease as the number of CRC bits increases. As can be seen from Figures 6 to 13, when the number of CRC bits is 16 bits, the probability of missed detection errors (UE) and false missed detection errors (FUE) is less than ^10-4 , and the additional overhead caused by the CRC bits is approximately 1.2% to 4.8%. Therefore, when the number of CRC bits is 16, a better balance can be achieved between performance and overhead. If the CRC decoding stop criterion is combined with the CNR decoding stop criterion or the VNR decoding stop criterion described below, when the number of CRC bits is less than 16 (such as the number of CRC bits is 8 bits or 10 bits), a better balance can also be achieved between performance and overhead. The CNR decoding stop criterion and the VNR decoding stop criterion will be described in detail later in conjunction with Figure 18.

Referring to FIG. 14-FIG. 17, FIG. 14-FIG. 17 are comparisons of event probabilities and additional iteration times of various decision events when using known decoding stop criteria (such as calculating whether all check equations contained in the check matrix are satisfied according to the check matrix of the LDPC code and the current decoding codeword result as described above) and CRC decoding stop criteria. For simplicity, the known decoding stop criteria are denoted as CXR in FIG. 14-17. As an example, FIG. 14-FIG. 17 takes the following decision events as examples for exemplary description: missed detection error (UE), false missed detection error (FUE), and false alarm (FA).

In FIG. 14 to FIG. 17 , the horizontal axis is _Es / _N0 , the unit is dB, _Es / _N0 represents the signal noise ratio (SNR), the vertical axis represents the event probability and the additional number of iterations, and the curves represent the change of the event probability of various events with _Es / _N0 when the known decoding stop criteria and the CRC decoding stop criteria are adopted, and the change of FER and the additional number of iterations _Δit with _Es / _N0 . The curves in FIG. 14 to FIG. 17 also represent the change of the average number of iterations with _Es / _N0 when the perfect decoding stop criteria are adopted (represented by itGA).

In FIG14 , the code length N=1944, the code rate R=1/2, and the number of iterations is 50.

In FIG15 , the code length N=1944, the code rate R=5/6, and the number of iterations is 50.

In FIG16 , the code length N=648, the code rate R=1/2, and the number of iterations is 50.

In FIG17 , the code length N=648, the code rate R=5/6, and the number of iterations is 50.

As can be seen from the examples in Figures 14 to 17, when the known decoding stop criteria or the CRC decoding stop criteria are used, the probability of missed detection errors (UE) will decrease as the SNR increases, and the probability of missed detection errors (UE) is lower when the known decoding stop criteria are used. For example, for the scenario of R=1/2, the probability of missed detection errors (UE) is about one order of magnitude different when the known decoding stop criteria and the CRC decoding stop criteria are used. The probability of false missed detection errors (FUE) is almost constant relative to the SNR, and the probability of false missed detection errors (FUE) is about two orders of magnitude lower when the known decoding stop criteria are used compared to the CRC decoding stop criteria. The probability of false alarms (FA) when the known decoding stop criteria are used is about two orders of magnitude lower than the FER. The main difference between using the known decoding stop criteria or the CRC decoding stop criteria is that the probability of false alarms (FA) is almost 0 when the CRC decoding stop criteria are used, and the probability of false alarms (FA) is about two orders of magnitude lower when the known decoding stop criteria are used compared to the FER. It can be seen that if the two decoding stop criteria are combined, the event probabilities of various decision events can be reduced.

The CRC decoding stop criteria are introduced above in conjunction with Figure 5, and other decoding stop criteria proposed by the present application are introduced below in conjunction with Figure 18. The decoding criteria provided below can be used in conjunction with the above CRC decoding stop criteria, or can be used alone without limitation.

Referring to Fig. 18, Fig. 18 is a schematic diagram of a decoding method 1800 provided in an embodiment of the present application. The method 1800 may include the following steps.

1810, the decoding device obtains the LDPC code stream to be decoded. For example, the decoding device receives the LDPC code stream to be decoded from the encoding device. Specifically, the encoding device sends the LDPC code stream.

Specifically, the encoding device performs LDPC encoding on the data bits to obtain an encoded LDPC code stream. Optionally, the data bits include information bits and CRC bits generated according to the information bits. Further optionally, the position of the CRC bit can be related to the robustness of at least one data bit in the LDPC code stream. For the relevant scheme of the CRC bit, reference can be made to the relevant description in method 500, which will not be repeated here.

1820. A decoding device decodes the LDPC code based on a check matrix of dimension M×N to obtain an LDPC codeword.

Wherein, M is the number of check nodes, N is the number of variable nodes, and M and N are integers greater than 1.

1830 , determine whether to stop decoding according to the LDPC codeword, and the M1 check equations and/or the N1 variable nodes.

The M check equations obtained based on the check matrix include M1 check equations, the N variable nodes in the check matrix include N1 variable nodes, N1 is a positive integer less than N, and M1 is a positive integer less than M.

Among them, step 1830 may include the following three solutions.

Scheme 1, based on the LDPC codeword and M1 check equations, determines whether to stop decoding. Based on this scheme, by determining whether a certain proportion of check equations are correct, rather than all check equations, the decoding overhead can be reduced. For ease of description, Scheme 1 is referred to as the CNR decoding stop criterion below.

Optionally, M1=M·f1, f1 is greater than 0 and less than 1. In this way, by introducing a ratio value f1, when actually performing decoding judgment, the check equations with a ratio of f1 among all the check equations (such as M) are taken to participate in the verification, that is, whether the f1·M check equations satisfy the check relationship.

A possible implementation manner is to calculate a syndrome vector obtained based on f1·M check equations and N variable nodes.

For example, if the syndrome vector obtained according to the f1·M check equations and the N variable nodes is an all-zero vector, the decoding is determined to be correct. Optionally, in this case, the decoding end feeds back the output codeword of the current decoding iteration and declares the decoding successful.

For another example, if the syndrome vector obtained according to the f1·M check equations and the N variable nodes is not an all-zero vector, it is determined not to stop decoding. Optionally, in this case, the decoding iteration is continued.

For another example, if the syndrome vector obtained according to the f1·M check equations and the N variable nodes is not an all-zero vector and the maximum number of decoding iterations is reached, it is determined to stop decoding and determine that a decoding error has occurred.

Optionally, f1 is related to the probability of a decision event, that is, f1 can be determined according to the probability of a possible decision event.

Since the CNR decoding stop criterion is to make a decoding judgment by judging whether a certain proportion (i.e., f1) of the check equations satisfies the check relationship, it may cause a certain loss in performance. Considering that various decision events are related to the value of f1, the value of f1 can be determined according to the decision events that may occur when the CNR decoding stop criterion is adopted, so as to achieve a balance between performance and power consumption caused by decoding as much as possible.

Referring to FIG. 19 to FIG. 22, FIG. 19 to FIG. 22 show the relationship between the event probability of various decision events and f1 when the CNR decoding stop criterion is adopted. As an example, FIG. 19 to FIG. 22 take the following decision events as examples for exemplary description: missed detection error (UE), false missed detection error (FUE), false alarm (FA), successful error detection (DE).

In Figures 19 to 22, the horizontal axis is f1, the vertical axis is event probability and additional number of iterations, and the curves represent the changes in event probability of various decision events with the value of f1, as well as the changes in FER and additional number of iterations _Δit with the value of f1.

In FIG19 , the code length N=1944, the code rate R=1/2, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 6.89.

In FIG20 , the code length N=1944, the code rate R=2/3, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 5.12.

In FIG21 , the code length N=1944, the code rate R=3/4, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 4.71.

In FIG. 22 , the code length N=1944, the code rate R=5/6, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 3.36.

As can be seen from the examples in Figures 19 to 22, the event probabilities of different decision events are related to the value of f1. For example, the smaller the value of f1, the smaller the number of additional iterations _Δit , the lower the probability of false alarm FA, and the probability of missed detection error (UE) and false missed detection error (FUE) may increase. In addition, it can be seen from the examples in Figures 19 to 22 that FER is basically a constant value horizontal line and almost coincides with the curve of successful error detection (DE).

Scheme 2 determines whether to stop decoding based on the LDPC codeword and N1 variable nodes. Based on this scheme, the decoding overhead is reduced by determining whether a certain proportion of variable nodes meet the reliability condition instead of all variable nodes. For ease of description, Scheme 2 is referred to as the VNR decoding stop criterion below.

Optionally, N1=N·f2, f2 is greater than 0 and less than 1. In this way, a ratio value f2 is introduced, and when actually performing decoding judgment, variable nodes with a ratio of f2 among all variable nodes (such as N) are selected to participate in verification, that is, whether f2·N variable nodes meet the reliability condition.

In one possible implementation, the reliability condition of a variable node is that all adjacent check nodes connected to the variable node have the same sign as the variable node in the previous decoding iteration feedback, that is, they are all fed back as positive or negative, so that all adjacent check nodes' external information feedback on the variable node indicates that the variable node is 0 or 1.

Optionally, f2 is related to the probability of a decision event, that is, f2 may be determined according to a possible decision event.

Since the VNR decoding stop criterion is to make a decoding judgment by judging whether a certain proportion (i.e., f2) of the variable nodes meet the reliability condition, it may cause a certain loss in performance. Considering that various decision events are related to the value of f2, the value of f2 can be determined according to the decision events that may occur when the VNR decoding stop criterion is adopted, so as to achieve a balance between performance and power consumption caused by decoding as much as possible.

Referring to Fig. 23-Fig. 26, Fig. 23-Fig. 26 show the relationship between the event probability of various decision events and f2 when the VNR decoding stop criterion is adopted. As an example, Fig. 23-Fig. 26 takes the following decision events as examples for exemplary description: missed detection error (UE), false missed detection error (FUE), false alarm (FA), successful error detection (DE).

In Figures 23-26, the horizontal axis is f2, the vertical axis is event probability and additional number of iterations, and the curves represent the changes in event probability of various decision events with the value of f2, as well as the changes in FER and additional number of iterations _Δit with the value of f2.

In FIG23 , the code length N=1944, the code rate R=1/2, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 7.53.

In FIG. 24 , the code length N=1944, the code rate R=2/3, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 5.12.

In FIG. 25 , the code length N=1944, the code rate R=3/4, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 4.21.

In FIG26 , the code length N=1944, the code rate R=5/6, the maximum number of iterations n _MAX =25, and the average number of iterations when the perfect decoding stop criterion is 3.36.

As can be seen from the examples in Figures 23 to 26, the event probabilities of different decision events are related to the value of f2. For example, the smaller the value of f2, the smaller the number of additional iterations _Δit , the lower the probability of false alarm FA, and the probability of missed detection error (UE) and false missed detection error (FUE) may increase. In addition, it can be seen from the examples in Figures 23 to 26 that FER is basically a constant value horizontal line and almost coincides with the curve of successful error detection (DE).

Solution 3 determines whether to stop decoding based on the LDPC codeword, M1 check equations, and N1 variable nodes. Based on this solution, the decoding overhead is reduced by determining whether a certain proportion of check equations are correct, rather than all check equations, and determining whether a certain proportion of variable nodes meet the reliability conditions, rather than all variable nodes. Solution 3 can be understood as a combination of Solution 1 and Solution 2, and will not be described in detail here.

The CNR decoding criterion and the VNR decoding criterion are introduced above in conjunction with Figure 18. It can be understood that the CNR decoding criterion and/or the VNR decoding criterion can be used in combination with the CRC decoding criterion described in method 500, or can be used alone without limitation.

It can be understood that some optional features in the embodiments of the present application may not depend on other features in some scenarios, and may also be combined with other features in some scenarios, without limitation.

It can also be understood that the solutions in the various embodiments of the present application can be used in reasonable combination, and the explanations or descriptions of the various terms appearing in the embodiments can be mutually referenced or explained in the various embodiments, without limitation.

The method provided by the embodiment of the present application is described in detail above in conjunction with Figures 5 to 26. The device provided by the embodiment of the present application is described in detail below in conjunction with Figures 27 to 29. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment. Therefore, the content not described in detail can be referred to the method embodiment above, and for the sake of brevity, it will not be repeated here.

Referring to FIG. 27 , FIG. 27 is a schematic block diagram of a communication device 2700 provided in an embodiment of the present application. The device 2700 includes a transceiver unit 2710 and a processing unit 2720. The transceiver unit 2710 can be used to implement corresponding communication functions. The transceiver unit 2710 can also be referred to as a communication interface or a communication unit. The processing unit 2720 can be used to perform processing, such as encoding or decoding.

Optionally, the device 2700 may further include a storage unit, which may be used to store instructions and/or data, and the processing unit 2720 may read the instructions and/or data in the storage unit so that the device implements the aforementioned method embodiment.

As a design, the device 2700 is used to execute the steps or processes executed by the encoding device in the above method embodiment, the transceiver unit 2710 is used to execute the transceiver-related operations on the encoding device side in the above method embodiment, and the processing unit 2720 is used to execute the processing-related operations on the encoding device side in the above method embodiment. In a possible implementation, the device 2700 is used to execute the embodiment shown in FIG. 5 or FIG. 18 The steps or processes performed by the encoding device in .

Optionally, the processing unit 2720 is used to perform low-density parity check LDPC encoding on the data bits to obtain an encoded LDPC code stream, wherein the data bits include information bits and CRC bits generated according to the information bits; the transceiver unit 2710 is used to output the LDPC code stream. Further optionally, the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream.

As another design, the device 2700 is used to execute the steps or processes executed by the decoding device in the above method embodiment, the transceiver unit 2710 is used to execute the transceiver-related operations on the decoding device side in the above method embodiment, and the processing unit 2720 is used to execute the processing-related operations on the decoding device side in the above method embodiment. In a possible implementation, the device 2700 is used to execute the steps or processes executed by the decoding device in the embodiment shown in Figure 5 or Figure 18.

Optionally, the transceiver unit 2710 is used to obtain a low-density parity check LDPC code stream to be decoded, the LDPC code stream includes data bits, the data bits include information bits and CRC bits of the information bits; the processing unit 2720 is used to decode the LDPC code stream. Further optionally, the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream.

It should be understood that the specific process of each unit executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

It should also be understood that the device 2700 here is embodied in the form of a functional unit. The term "unit" here may refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit and/or other suitable components that support the described functions. In an optional example, those skilled in the art can understand that the device 2700 can be specifically a communication device (such as an encoding device, and also a decoding device) in the above-mentioned embodiments, and can be used to execute the various processes and/or steps corresponding to the communication device in the above-mentioned method embodiments. To avoid repetition, it will not be repeated here.

The device 2700 of each of the above schemes has the function of implementing the corresponding steps performed by the communication device (such as an encoding device, and also such as a decoding device) in the above method. The function can be implemented by hardware, or by hardware executing the corresponding software implementation. The hardware or software includes one or more modules corresponding to the above functions; for example, the transceiver unit can be replaced by a transceiver (for example, the sending unit in the transceiver unit can be replaced by a transmitter, and the receiving unit in the transceiver unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, respectively performing the sending and receiving operations and related processing operations in each method embodiment.

In addition, the above-mentioned transceiver unit 2710 can also be a transceiver circuit (for example, can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit.

It should be noted that the device in FIG. 27 may be the device in the aforementioned embodiment, or may be a chip or a chip system, such as a system on chip (SoC). The transceiver unit may be an input and output circuit or a communication interface; the processing unit may be a processor or a microprocessor or an integrated circuit integrated on the chip. This is not limited here.

Referring to FIG. 28 , FIG. 28 is a schematic diagram of another communication device 2800 provided in an embodiment of the present application. The device 2800 includes a processor 2810, the processor 2810 is coupled to a memory 2820, the memory 2820 is used to store computer programs or instructions and/or data, and the processor 2810 is used to execute the computer program or instructions stored in the memory 2820, or read the data stored in the memory 2820, so as to execute the methods in the above method embodiments.

Optionally, there are one or more processors 2810 .

Optionally, memory 2820 is one or more.

Optionally, the memory 2820 is integrated with the processor 2810 or provided separately.

Optionally, as shown in Fig. 28, the device 2800 further includes a transceiver 2830, and the transceiver 2830 is used for receiving and/or sending signals. For example, the processor 2810 is used to control the transceiver 2830 to receive and/or send signals.

As an example, the processor 2810 may have the function of the processing unit 2720 shown in Figure 27, the memory 2820 may have the function of the storage unit, and the transceiver 2830 may have the function of the transceiver unit 2710 shown in Figure 27.

As a solution, the device 2800 is used to implement the operations performed by the communication device (such as the encoding device or the decoding device) in the above method embodiments.

For example, the processor 2810 is used to execute the computer program or instructions stored in the memory 2820 to implement the relevant operations of the communication device (such as the encoding device, and also such as the decoding device) in the above various method embodiments.

It should be understood that the processor mentioned in the embodiments of the present application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or a processor. The processor may also be any conventional processor, etc.

It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory and/or a non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM). For example, a RAM may be used as an external cache. By way of example and not limitation, RAM includes the following forms: static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) can be integrated into the processor.

It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

Referring to FIG. 29 , FIG. 29 is a schematic diagram of a chip system 2900 provided in an embodiment of the present application. The chip system 2900 (or also referred to as a processing system) includes a logic circuit 2910 and an input/output interface 2920.

Among them, the logic circuit 2910 can be a processing circuit in the chip system 2900. The logic circuit 2910 can be coupled to the storage unit and call the instructions in the storage unit so that the chip system 2900 can implement the methods and functions of each embodiment of the present application. The input/output interface 2920 can be an input/output circuit in the chip system 2900, outputting information processed by the chip system 2900, or inputting data or signaling information to be processed into the chip system 2900 for processing.

Specifically, for example, if the chip system 2900 is installed in the encoding device, the logic circuit 2910 can be used to perform LDPC encoding on the data bits, the logic circuit 2910 is coupled to the input/output interface 2920, and the logic circuit 2910 can send the encoded LDPC code stream to the decoding device through the input/output interface 2920. For another example, if the chip system 2900 is installed in the decoding device, the logic circuit 2910 is coupled to the input/output interface 2920, and the input/output interface 2920 can input the LDPC code from the encoding device to the logic circuit 2910 for processing.

As a solution, the chip system 2900 is used to implement the operations performed by the communication device (such as the encoding device or the decoding device) in the above method embodiments.

For example, the logic circuit 2910 is used to implement the processing-related operations performed by the communication device (such as an encoding device, or a decoding device) in the above method embodiments; the input/output interface 2920 is used to implement the sending and/or receiving-related operations performed by the communication device (such as an encoding device, or a decoding device) in the above method embodiments.

An embodiment of the present application also provides a computer-readable storage medium on which computer instructions for implementing the methods executed by a communication device (such as an encoding device or a decoding device) in the above-mentioned method embodiments are stored.

For example, when the computer program is executed by a computer, the computer can implement the method performed by a communication device (such as an encoding device or a decoding device) in each embodiment of the above method.

An embodiment of the present application also provides a computer program product, comprising instructions, which, when executed by a computer, implement the methods performed by a communication device (such as an encoding device or a decoding device) in the above-mentioned method embodiments.

The embodiment of the present application also provides a communication system, which includes the encoding device and decoding device in the above embodiments. For example, the system includes the encoding device and decoding device in the embodiment shown in Figure 5. For another example, the system includes the encoding device and decoding device in the embodiment shown in Figure 18.

The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or instructions described in the embodiments of the present application are generated. Function. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer may be a personal computer, a server, or a network device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD), etc. For example, the aforementioned available medium includes, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (14)

1. A coding method, characterized by comprising:

   Performing low-density parity check (LDPC) encoding on data bits to obtain an encoded LDPC code stream, wherein the data bits include information bits and cyclic redundancy check (CRC) bits generated according to the information bits, and a position of the CRC bits is related to the robustness of at least one data bit position in the LDPC code stream;

   Output the LDPC code stream.
2. The method according to claim 1, characterized in that the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, comprising:

   The robustness of the position where the CRC bit is located is higher than the robustness of the position where at least one information bit in the LDPC code stream is located.
3. The method according to claim 1 or 2, characterized in that the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, comprising:

   When the robustness of at least two data bit positions in the LDPC code stream is consistent, the position of the CRC bit is located at a front position of the at least two data bits.
4. The method according to any one of claims 1 to 3, characterized in that the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, including any of the following:

   When the code length of the LDPC code stream is 1944 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream; or,

   When the code length of the LDPC code stream is 1944 and the code rate is 2/3, the position of the CRC bit is located at a data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, and the fourth column; or,

   When the code length of the LDPC code stream is 1944 and the code rate is 3/4, the position of the CRC bit is located at a data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, and the sixth column; or,

   When the code length of the LDPC code stream is 1944 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any one of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, the sixth column, the seventh column, the eighth column, the ninth column, and the tenth column; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 2/3, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, and the third column; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, the sixth column, and the seventh column; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any one of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, the sixth column, the seventh column, the eighth column, the ninth column, the tenth column, the eleventh column, the twelfth column, the thirteenth column, the fourteenth column, the fifteenth column, and the sixteenth column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the fifth column, and the ninth column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 2/3, the position of the CRC bit is located at a data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, and the third column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, and the fifth column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any one of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12, column 14, column 15, column 16, column 17, column 18, column 19, and column 20.
5. A decoding method, characterized by comprising:

   Acquire a low-density parity check (LDPC) code stream to be decoded, wherein the LDPC code stream includes data bits, the data bits include information bits and cyclic redundancy check (CRC) bits of the information bits, and the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream;

   The LDPC code stream is decoded.
6. The method according to claim 5, characterized in that the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, comprising:

   The robustness of the position where the CRC bit is located is higher than the robustness of the position where at least one information bit in the LDPC code stream is located.
7. The method according to claim 5 or 6, characterized in that the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, including:

   When the robustness of at least two data bit positions in the LDPC code stream is consistent, the position of the CRC bit is located at a front position of the at least two data bits.
8. The method according to any one of claims 5 to 7, characterized in that the position of the CRC bit is related to the robustness of at least one data bit position in the LDPC code stream, including any of the following:

   When the code length of the LDPC code stream is 1944 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream; or,

   When the code length of the LDPC code stream is 1944 and the code rate is 2/3, the position of the CRC bit is located at a data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, and the fourth column; or,

   When the code length of the LDPC code stream is 1944 and the code rate is 3/4, the position of the CRC bit is located at a data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, and the sixth column; or,

   When the code length of the LDPC code stream is 1944 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any one of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, the sixth column, the seventh column, the eighth column, the ninth column, and the tenth column; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to the first column in the check matrix of the LDPC code stream; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 2/3, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, and the third column; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, the sixth column, and the seventh column; or,

   When the code length of the LDPC code stream is 1296 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any one of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, the fifth column, the sixth column, the seventh column, the eighth column, the ninth column, the tenth column, the eleventh column, the twelfth column, the thirteenth column, the fourteenth column, the fifteenth column, and the sixteenth column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 1/2, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the fifth column, and the ninth column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 2/3, the position of the CRC bit is located at a data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, and the third column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 3/4, the position of the CRC bit is located at the data bit position corresponding to any of the following columns in the check matrix of the LDPC code stream: the first column, the second column, the third column, the fourth column, and the fifth column; or,

   When the code length of the LDPC code stream is 648 and the code rate is 5/6, the position of the CRC bit is located at the data bit position corresponding to any one of the following columns in the check matrix of the LDPC code stream: column 1, column 2, column 3, column 4, column 5, column 6, column 7, column 8, column 9, column 10, column 11, column 12, column 14, column 15, column 16, column 17, column 18, column 19, and column 20.
9. A communication device, characterized by comprising: a unit or a module for executing the method according to any one of claims 1 to 8.
10. A communication device, characterized in that it comprises a processor, wherein the processor is used to execute a computer program or instruction stored in a memory so that the device executes the method according to any one of claims 1 to 8.
11. The device according to claim 10, characterized in that the device further comprises the memory and/or the communication interface, wherein the communication interface is coupled to the processor,

    The communication interface is used to input and/or output information.
12. A computer-readable storage medium, characterized in that it is used to store a computer program, wherein the computer program includes instructions for implementing the method according to any one of claims 1 to 8.
13. A chip, characterized in that it comprises: a processor and an interface, used to call and run a computer program stored in a memory from the memory to execute the method as claimed in any one of claims 1 to 8.
14. A computer program product, characterized in that it comprises computer program code, wherein the computer program code is used to implement the method according to any one of claims 1 to 8.