WO2024113868A1 - 时间同步异常的处理方法、授时端、电子设备及存储介质 - Google Patents
时间同步异常的处理方法、授时端、电子设备及存储介质 Download PDFInfo
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- the present application belongs to the field of communication technology, and specifically relates to a method for processing time synchronization anomalies, a timing terminal, an electronic device and a storage medium.
- the 1588V2 standard is a high-precision time synchronization standard. Since the first version of the standard was released in 2008, it has been widely used in aerospace, industry and other fields. After entering the 5G era, the requirements for time synchronization in indoor positioning, Internet of Things and other fields have become increasingly higher, which has led to the emergence of ultra-high-precision time synchronization technology based on 1588V2, which in turn has expanded the application field of 1588V2.
- 1588V2 provides ultra-high-precision time synchronization technology, it does not provide a method for monitoring whether there are any abnormalities in the time synchronization of devices. As a result, when abnormalities occur in the time synchronization of devices, the entire network may be greatly affected.
- the embodiments of the present application provide a method for processing time synchronization anomalies, a timing terminal, an electronic device, and a storage medium, which can detect and process time synchronization anomalies of a device and reduce the impact on the entire network.
- an embodiment of the present application provides a method for processing time synchronization anomalies, the method being executed by a main control board of a timing end, the method comprising: obtaining a first timestamp added by a line card of the timing end to a target message, wherein the first timestamp is the time point at which the line card receives the target message; determining based on the first timestamp that a time synchronization anomaly occurs; and handling the anomaly according to a preset anomaly handling method. Exception handling is performed in a reasonable manner.
- an embodiment of the present application provides a timing end, which includes: a line card, used to add a first timestamp to a received target message, and send the first timestamp to a main control board, wherein the first timestamp is the time point when the line card receives the target message; the main control board, used to determine whether an abnormality occurs in time synchronization based on the first timestamp; and perform exception handling according to a preset exception handling method.
- an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the method described in the first aspect.
- an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.
- an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.
- FIG1 is a schematic flow chart of a method for processing a time synchronization anomaly provided in an embodiment of the present application
- FIG2 is a flow chart of another method for processing time synchronization anomalies provided in an embodiment of the present application.
- FIG3 is a schematic diagram of the structure of a distributed timestamp processing system provided in an embodiment of the present application.
- FIG4 is a schematic diagram of the structure of another distributed timestamp processing system provided in an embodiment of the present application.
- FIG5 is a schematic diagram of the structure of a timing terminal provided in an embodiment of the present application.
- FIG. 6 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
- first, second, etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first”, “second”, etc. are generally of one type, and the number of objects is not limited.
- the first object can be one or more.
- “and/or” in the specification and claims represents at least one of the connected objects, and the character “/" generally indicates that the objects associated with each other are in an "or” relationship.
- each device will send an Announce message to other devices.
- the Best Master Clock (BCM) algorithm determines the time source and the timing (Master) and tracking (Slave) ends of each device in the network based on the parameters of the Announce message.
- the Slave end tracks the time of the Master end.
- this node can still send Announce messages normally. Since the time source device in the network is running normally, the parameters carried in the Announce message sent by this node are still the information of the time source device, so that the downstream device cannot know that the device has a fault and still tracks the wrong time information from this device, causing problems in the entire network.
- an embodiment of the present application provides a method for handling time synchronization anomalies, which is mainly aimed at fault handling in the case of PTP time synchronization anomalies.
- fault detection is performed on the Master side.
- exception handling is performed according to a preset exception handling method to control the fault as much as possible at the current faulty node and no longer transmit it downstream, thereby reducing the impact on the network.
- FIG. 1 shows a flow chart of a method for processing time synchronization anomalies provided by an embodiment of the present application.
- the method can be executed by the main control board of the timing end. As shown in Figure 1, the method can include the following steps:
- Step 101 Acquire a first timestamp added by the line card of the timing end to a target message, wherein the first timestamp is a time point when the line card receives the target message.
- Step 102 Based on the first timestamp, determine that time synchronization is abnormal.
- Step 103 Perform exception handling according to a preset exception handling method.
- the time point when the line card receives the target message is reflected by the first timestamp, it is determined that an abnormality in time synchronization occurs, and then the abnormality in time synchronization is handled in accordance with the abnormality handling method pre-set for the abnormal situation; the problem that the abnormal time synchronization failure cannot be detected and resolved is solved, that is, the abnormal time synchronization failure of the device can be detected according to the first timestamp, and when the device has a time synchronization abnormality, the failure can be handled abnormally, thereby reducing the impact of the abnormal time synchronization failure on the entire network.
- the target message may include: a target synchronization message (sync message) sent by the timing end.
- whether the time synchronization of the timing end is abnormal can be determined by the first timestamp added by the line card of the timing end to the target synchronization message sent by the timing end.
- the main control board of the timing end sends the target synchronization message to the line card of the timing end, and the line card of the timing end adds the first timestamp to the target synchronization message, and then sends the target synchronization message to the tracking end.
- the line card of the timing end can return the first timestamp to the main control board, so that the main control board can determine whether the time synchronization is abnormal according to the first timestamp.
- the target message may include: a target delay request message (delay_req message) received by the timing end.
- whether the time synchronization of the timing end is abnormal can be determined by the first timestamp added by the line card of the timing end to the target delay request message received by the timing end. For example, when the line card of the timing end receives the target delay request message sent by the tracking end, the line card of the timing end adds the first timestamp to the target delay request message, and then sends the target delay request message to the main control board of the timing end, so that the main control board can determine whether the time synchronization is abnormal according to the first timestamp.
- FIG2 shows a flow chart of another method for handling time synchronization anomalies provided by an embodiment of the present application in an implementation manner, and the method can be executed by a main control board of a timing service end. As shown in FIG2 , the method can include the following steps:
- Step 201 Obtain the first timestamp added by the line card of the timing end to the target message, wherein: The first timestamp is the time point when the line card receives the target message.
- Step 202 Based on the first timestamp, obtain target information, wherein the target information includes at least one of the following: packet sending transmission delay, packet sending time interval, packet receiving transmission delay and packet receiving time interval.
- Step 203 When it is determined that the target information is abnormal, it is determined that the time synchronization is abnormal.
- Step 204 Perform exception handling according to a preset exception handling method.
- the target information carried by the first timestamp is obtained, and the target information provides at least one of the packet sending transmission delay, the packet sending time interval, the packet receiving transmission delay and the packet receiving time interval.
- the target information provides at least one of the packet sending transmission delay, the packet sending time interval, the packet receiving transmission delay and the packet receiving time interval.
- the packet transmission delay includes: a difference between a second timestamp added by the main control board when sending the target synchronization message and the first timestamp added by the line card to the target synchronization message.
- the second timestamp added when the main control board sends the target synchronization message records the time of sending the target synchronization message
- the line card adds a first timestamp to the target synchronization message to record the time of receiving the target synchronization message sent by the main control board.
- the time taken for the target synchronization message to be sent from the main control board to the line card is determined by the difference between the second timestamp and the first timestamp, which is the packet transmission delay.
- the packet receiving transmission delay includes: a difference between a second timestamp added by the main control board when receiving the target delay request message and the first timestamp added by the line card to the target delay request message.
- the target delay request message is first transmitted to the line card, the line card adds a first timestamp to the target delay request message to record the time when the line card receives the target delay request message, and then transmits it to the main control board, the main control board adds a second timestamp to the target delay request message to record the time when the main control board receives the target delay request message, and the time taken for the target delay request message to be transmitted from the line card to the main control board is determined by the difference between the second timestamp and the first timestamp, which is the packet transmission delay.
- the packet transmission time interval includes: two adjacent target synchronization messages The time interval between the first timestamps.
- the main control board sends multiple target synchronization messages to the line card, and the line card adds a first timestamp to the multiple target synchronization messages.
- the time interval between the first timestamps of two adjacent target synchronization messages can determine the time interval between two adjacent packet sending messages.
- the time interval between the first timestamps of each two adjacent target synchronization messages can determine a packet sending time interval. Multiple packet sending time intervals can be determined based on multiple target synchronization messages.
- the packet receiving time interval includes: a time interval between the first timestamps of two adjacent target delay request messages.
- the line card receives multiple target delay request messages and simultaneously stamps the multiple target delay request messages with a first timestamp.
- the time interval between two adjacent target delay request messages can be used to determine the time interval between two adjacent packet receiving messages.
- the time interval between the first timestamps of each two adjacent target delay request messages can determine a packet receiving time interval. Multiple packet receiving time intervals can be determined based on multiple target delay request messages.
- the above-mentioned determining that the target information is abnormal includes at least one of the following:
- the packet sending time intervals are inconsistent, for example, among the first timestamps that the line card stamps on the plurality of target synchronization messages, the time intervals between the first timestamps of two adjacent target synchronization messages are not completely the same;
- the packet receiving time intervals are inconsistent. For example, among the first timestamps added by the line card to the plurality of target delay request messages, the time intervals between the first timestamps of two adjacent target delay request messages are not completely the same.
- the packet transmission delay exceeds the first threshold, that is, when the time taken for the target synchronization message to be sent from the main control board to the line card exceeds the first threshold, it is determined that the target information is abnormal; when it is determined that the time interval between the first timestamps of two adjacent target synchronization messages is inconsistent with the packet transmission interval, that is, when there is a situation where the packet transmission time interval is inconsistent with the packet transmission interval among multiple packet transmission time intervals determined by multiple target synchronization messages, it is determined that the target information is abnormal; when it is determined that the packet receiving transmission delay exceeds the second threshold, that is, the target delay request message is sent from When the time taken by the line card to transmit to the main control board exceeds the second threshold, it is determined that the target information is abnormal; when it is determined that the time interval between the first timestamps of two adjacent target delay request
- the first timestamp mentioned above can be a timestamp added by the line card using the transparent clock (TC) time
- the second timestamp can be a timestamp added by the main control board using the TC time.
- the TC time can be used to add the timestamp to improve the stability of the timing.
- the above step 103 may include at least one of the following:
- the exception handling includes at least one of the following: performing exception handling on the Announce message sent by the timing end, and sending the Announce message after the exception handling to the downstream device, so that the downstream device can determine that there is an abnormality in time synchronization by receiving the Announce message after the exception handling, triggering the Best Master Clock (BMC) algorithm to recalculate, so that the downstream device no longer tracks the erroneous time path; sending an alarm message to the tracking end of the timing end, and the tracking end of the timing end receives the alarm message, so the tracking end no longer tracks the erroneous time path, and the downstream device no longer tracks the erroneous time path, thereby reducing the impact on the entire network.
- BMC Best Master Clock
- the above-mentioned abnormal processing of the Announce message sent by the timing terminal may include: modifying the parameters of the Announce message; or stopping sending the Announce message to the tracking terminal.
- the parameters of the Announce message are modified, so that when the downstream device receives the Announce message and detects that the parameters of the Announce message have changed, it is considered that the time path is abnormal, triggering the BMC algorithm to recalculate and switch to tracking the time path of normal devices; or stop sending Announce messages to the tracking end, so that the tracking end cannot send Announce messages to the downstream device, and the time synchronization anomaly is controlled in the current device.
- the downstream device detects that the Announce message is lost, triggers the BMC algorithm to recalculate, and the downstream device The device no longer tracks the wrong time path and switches to tracking the time path of the normal device.
- the above-mentioned modification of the parameters of the Announce message may include: modifying the initial time parameter of the Announce message to the time parameter of the main control board.
- the initial time parameters of the Announce message are modified to the time parameters of the main control board.
- the downstream device receives the Announce message including the time parameters of the main control board, it considers that the time path is abnormal, triggers the BMC algorithm to recalculate, and switches to tracking the time path of normal devices; the time parameters of the Announce message may include parameters such as ClockClass and Priority.
- This embodiment obtains the first timestamp added by the line card of the timing end to the target message, determines whether the information of packet transmission delay, packet transmission time interval, packet reception transmission delay and packet reception time interval provided by the first timestamp is abnormal, and determines whether time synchronization is abnormal; when it is determined that time synchronization is abnormal, by modifying the parameters of the Announce message or stopping sending the Announce message to the tracking end and sending alarm information to the tracking end of the timing end, these abnormal processing operations can not only detect the time synchronization abnormality in time, but also process the time synchronization abnormality, control the time synchronization abnormality fault to the current device, trigger the BMC algorithm to recalculate, so that the downstream device no longer tracks the wrong time path, solves the problem that the time synchronization abnormality fault cannot be detected and cannot be solved, and reduces the impact of the time synchronization abnormality fault on the entire network.
- the above method can be applied to the distributed timestamp processing system as shown in FIG3 , including a main control board 31 and a line card 32 at the timing end, a main control board 33 and a line card 34 at the tracking end, and performing the following steps:
- Step 301 the main control board 31 sends a target synchronization message and adds a T 1 ′ timestamp.
- Step 302 The line card 32 receives the target synchronization message sent by the main control board 31 and adds a T1 timestamp.
- Step 303 The line card 32 transmits the T1 timestamp to the main control board 31 via a custom signaling message.
- Step 305 When the packet transmission delay does not meet the expected transmission delay or the packet transmission time interval is inconsistent with the packet transmission interval, it is determined that time synchronization is abnormal and the abnormality is handled, such as sending an alarm message to the tracking end and modifying the parameters of the Announce message.
- Step 306 the main control board 33 sends a target delay request message to the line card 34 , and the line card 34 then sends a target delay request message to the line card 32 .
- Step 307 The line card 32 receives the target delay request message and adds a T4 timestamp.
- Step 308 the line card 32 sends the target delay request message carrying the T 4 timestamp to the main control board 31 .
- Step 309 the main control board 31 receives the target delay request message carrying the T 4 timestamp and adds a T 4 ′ timestamp.
- Step 311 When the packet receiving transmission delay does not meet the expected transmission delay or the packet receiving time interval is inconsistent with the packet receiving interval, it is determined that time synchronization is abnormal and the abnormality is handled, such as sending an alarm message to the tracking end and modifying the parameters of the Announce message.
- the above method can also be applied to a distributed timestamp processing system with a correction domain, including a main control board 41 and a line card 42 at a timing end, and a main control board 43 and a line card 44 at a tracking end, and performing the following steps:
- Step 401 the main control board 41 uses the system time to stamp T1 , sends the target synchronization message and stamps CF out1 with TC time.
- Step 403 The line card 42 transmits the CF 12 to the main control board 41 via a Signaling message.
- Step 404 The main control board 41 determines whether CF 12 meets the expected transmission delay; and checks whether the T1 timestamp is equal to the system time at the time of stamping; and the main control board 41 calculates the packet sending time interval
- T11 is the first T1 timestamp
- T12 is the second R 1 timestamps
- T 1 3 is the third T 1 timestamp
- T 1 N-1 is the N-1th T 1 timestamp
- T 1 N is the Nth T 1 timestamp
- Step 405 When CF 12 does not meet the expected transmission delay or the T 1 timestamp is not equal to the system time at the time of stamping or there is a packet sending time interval inconsistent with the packet sending time interval, it is determined that time synchronization is abnormal and the abnormality is handled, such as sending an alarm message to the tracking end and stopping sending Announce messages to the tracking end.
- Step 406 the main control board 43 sends a target delay request message to the line card 44 , and the line card 44 then sends a target delay request message to the line card 42 .
- Step 407 The line card 42 receives the target delay request message and stamps it with the CF int3 timestamp using the TC time.
- Step 408 the line card 42 sends the target delay request message carrying the CF int3 timestamp to the main control board 41 .
- Step 409 the main control board 41 receives the target delay request message carrying the CF int3 timestamp and stamps it with the CF int4 timestamp and the T4 timestamp using the TC time.
- Step 411 When CF 34 does not meet the expected transmission delay or the T 4 timestamp is not equal to the system time at the time of stamping or there is a packet receiving time interval inconsistent with the packet receiving time interval, it is determined that time synchronization is abnormal and the abnormality is handled, such as sending an alarm message to the tracking end and stopping sending Announce messages to the tracking end.
- the main control board of the timing end determines that the time synchronization is normal. For example, when the packet transmission delay, packet sending time interval, packet receiving transmission delay and packet receiving time interval are all normal, the main control board of the timing end determines that the time synchronization is normal.
- FIG5 is a schematic diagram of the structure of a timing end according to the embodiment of the present application.
- the timing end may include: a line card 510, which is used to add a first timestamp to the received target message and send the first timestamp to the target message. Sent to the main control board 520, wherein the first timestamp is the time point when the line card 510 receives the target message; the main control board 520 is used to determine that an abnormality occurs in time synchronization based on the first timestamp; and perform exception handling according to a preset exception handling method.
- the main control board 520 can be used to obtain target information based on the first timestamp, wherein the target information includes at least one of the following: packet sending transmission delay, packet sending time interval, packet receiving transmission delay and packet receiving time interval; when it is determined that the target information is abnormal, it is determined that the time synchronization is abnormal.
- the main control board 520 may be used to perform exception processing on the Announce message sent by the timing end; and send alarm information to the tracking end of the timing end.
- the main control board 520 may be used to modify the parameters of the Announce message; or stop sending the Announce message to the tracking end.
- the main control board 520 may be used to modify the initial time parameter of the Announce message to the time parameter of the main control board.
- the main control board of the timing end provided in the embodiment of the present application can implement each process implemented in the method embodiments of Figures 1 to 4. To avoid repetition, they will not be described here.
- FIG6 is a schematic diagram of the structure of an electronic device that implements each embodiment of the present application.
- the electronic device may have relatively large differences due to different configurations or performances, and may include a processor (processor) 610, a communication interface (Communications Interface) 620, a memory (memory) 630 and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other through the communication bus 640.
- the processor 610 can call a computer program stored in the memory 630 and can be run on the processor 610 to perform the following steps:
- a first timestamp added by the line card of the timing end to the target message is obtained, wherein the first timestamp is a time point when the line card receives the target message.
- the specific execution steps can refer to the various steps of the above-mentioned time synchronization exception processing method embodiment, and can achieve the same technical effect. To avoid repetition, they will not be repeated here.
- the electronic devices in the embodiments of the present application include: servers, terminals or other devices except terminals.
- the above electronic device structure does not constitute a limitation on the electronic device.
- the electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.
- the input unit may include a graphics processing unit (GPU) and a microphone
- the display unit may be configured with a display panel in the form of a liquid crystal display, an organic light-emitting diode, etc.
- the user input unit includes a touch panel and at least one of other input devices.
- the touch panel is also called a touch screen.
- Other input devices may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.
- the memory can be used to store software programs and various data.
- the memory may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc.
- the memory may include a volatile memory or a non-volatile memory, or the memory may include both volatile and non-volatile memories.
- the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.
- ROM read-only memory
- PROM programmable read-only memory
- EPROM erasable programmable read-only memory
- EEPROM electrically erasable programmable read-only memory
- flash memory a flash memory.
- Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (Synch link DRAM, SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DRRAM).
- the processor may include one or more processing units; optionally, the processor integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to the operating system, user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor.
- An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored.
- a program or instruction is stored.
- each process of the above-mentioned time synchronization exception processing method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
- the processor is a processor in the electronic device described in the above embodiment.
- the readable storage medium includes a computer readable storage medium, such as a computer read-only memory (Read-Only Memory). Memory, ROM), Random Access Memory (Random Access Memory, RAM), disk or CD, etc.
- An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned time synchronization exception processing method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.
- the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.
- the technical solution of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.
- a storage medium such as ROM/RAM, a disk, or an optical disk
- a terminal which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.
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Abstract
本申请公开了一种时间同步异常的处理方法、授时端、电子设备及存储介质。所述方法应用授时端的主控板，包括：获取所述授时端的线卡为目标报文添加的第一时间戳，其中，所述第一时间戳为所述线卡接收到所述目标报文的时间点；基于所述第一时间戳，确定时间同步出现异常；按照预设的异常处理方式进行异常处理。
Description
交叉引用
本申请要求在2022年11月28日提交中国专利局、申请号为202211502238.5、名称为“时间同步异常的处理方法、授时端、电子设备及存储介质”的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
本申请属于通信技术领域，具体涉及一种时间同步异常的处理方法、授时端、电子设备及存储介质。
1588V2标准是一个关于高精度时间同步的标准，自从2008年第一版标准面世以来，已经广泛地应用于航天、工业等多个领域。进入5G时代之后，室内定位、物联网等领域对时间同步的要求越来越高，从而引发了基于1588V2的超高精度时间同步技术的产生，这又使得1588V2的应用领域更加广阔。
虽然1588V2提供了超高精度的时间同步技术，但是并没能给出如何监测设备的时间同步是否出现异常，从而可能导致在设备的时间同步出现异常时，对整个网络造成较大的影响。
发明内容
本申请实施例提供一种时间同步异常的处理方法、授时端、电子设备及存储介质，能够检测到设备的时间同步异常并进行处理，减少对整个网络的影响。
第一方面，本申请实施例提供了一种时间同步异常的处理方法，该方法由授时端的主控板执行，该方法包括：获取所述授时端的线卡为目标报文添加的第一时间戳，其中，所述第一时间戳为所述线卡接收到所述目标报文的时间点；基于所述第一时间戳，确定时间同步出现异常；按照预设的异常处
理方式进行异常处理。
第二方面，本申请实施例提供了一种授时端，该授时端包括：线卡，用于为接收到的目标报文添加第一时间戳，并将所述第一时间戳发送给主控板，其中，所述第一时间戳为所述线卡接收到所述目标报文的时间点；所述主控板，用于基于所述第一时间戳，确定时间同步出现异常；按照预设的异常处理方式进行异常处理。
第三方面，本申请实施例提供了一种电子设备，该电子设备包括处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如第一方面所述的方法的步骤。
第四方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第一方面所述的方法的步骤。
第五方面，本申请实施例提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如第一方面所述的方法。
图1是本申请实施例提供的一种时间同步异常的处理方法的流程示意图；
图2是本申请实施例提供的另一种时间同步异常的处理方法的流程示意图；
图3是本申请实施例提供的一种分布式时戳处理系统的结构示意图；
图4是本申请实施例提供的另一种分布式时戳处理系统的结构示意图；
图5是本申请实施例提供的一种授时端的结构示意图；
图6是本申请实施例提供的一种电子设备的结构示意图。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是
全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
在精准时间协议(Precision Timing Protocol，PTP)时间同步网络中，正常情况下，每个设备会向其他设备发出通告(Announce)报文，最佳主时钟(Best Master Clock，BCM)算法根据Announce报文的参数，决策出时间源以及网络中各个设备的授时(Master)端和跟踪(Slave)端。Slave端跟踪Master端的时间。当线路上的Announce报文中断，或者Announce中携带的参数内容发生改变的时候，1588网络进行重构，选举出新的时间源以及在每个设备重新决策出Master端和Slave端，使得整个网络处于正常的时间同步状态。
但是对于某些故障，例如，Master端网元发送的1588时戳存在问题，但是这个节点依然可以正常发送Announce报文，由于网络中时间源设备运行正常，因此这个节点发送出去的Announce报文携带的参数依然是时间源设备的信息，从而使得下游设备无法得知这个设备出现了故障，依然还跟踪从这个设备来的错误的时间信息，导致整个网络出现问题。
基于此，本申请实施例提供了一种时间同步异常的处理方法，该方法主要针对在PTP时间同步异常情况下的故障处理，在本申请实施列中，在Master端进行故障检测，进一步地，在本申请实施例的可选的实现中，在发现这些故障的时候按照预设的异常处理方式进行异常处理，以尽量将故障控制在当前故障节点不再向下游传递，从而减少对网络的影响。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的一种时间同步异常的处理方法、授时端、电子设备及存储介质进行详细地说明。
图1示出本申请的一个实施例提供的一种时间同步异常的处理方法的流
程示意图，该方法可以由授时端的主控板执行。如图1所示，该方法可以包括如下步骤：
步骤101：获取所述授时端的线卡为目标报文添加的第一时间戳，其中，所述第一时间戳为所述线卡接收到所述目标报文的时间点。
步骤102：基于所述第一时间戳，确定时间同步出现异常。
步骤103：按照预设的异常处理方式进行异常处理。
在本申请实施例中，通过获取授时端的线卡为目标报文添加的第一时间戳，根据该第一时间戳反映线卡接收到所述目标报文的时间点，确定时间同步出现异常情况，然后按照预先针对异常情况设置的异常处理方式对时间同步异常情况进行处理；解决了时间同步异常故障未能被检测以及未能得到解决的问题，即能够根据第一时间戳检测到设备时间同步出现异常的故障，并且在设备出现时间同步异常时能够针对故障进行异常处理，减少时间同步异常故障对整个网络的影响。
在一种实现方式中，所述目标报文可以包括：所述授时端发送的目标同步报文(sync报文)。在该可选的实现方式，可以通过授时端的线卡为授时端发送的目标同步报文添加的第一时间戳来确定授时端的时间同步是否异常，例如，授时端的主控板发送目标同步报文到授时端的线卡，授时端的线卡为该目标同步报文添加第一时间戳后，将目标同步报文发送给跟踪端，而且，授时端的线卡可以将第一时间戳返回给主控板，从而使得主控板可以根据第一时间戳判断时间同步是否异常。
在另一种实现方式中，所述目标报文可以包括：所述授时端接收的目标延时请求报文(delay_req报文)。在该可选的实现方式，可以通过授时端的线卡为授时端接收的目标延时请求报文添加的第一时间戳来确定授时端的时间同步是否异常，例如，授时端的线卡在接收到跟踪端发送目标延时请求报文时，授时端的线卡为该目标延时请求报文添加第一时间戳后，将目标延时请求报文发送给授时端的主控板，从而使得主控板可以根据第一时间戳判断时间同步是否异常。
图2示出在一种实现方式中本申请实施例提供的另一种时间同步异常的处理方法的流程示意图，该方法可以由授时端的主控板执行。如图2所示，该方法可以包括如下步骤：
步骤201：获取所述授时端的线卡为目标报文添加的第一时间戳，其中，
所述第一时间戳为所述线卡接收到所述目标报文的时间点。
步骤202：基于所述第一时间戳，获取目标信息，其中，所述目标信息包括以下至少之一：发包传输时延、发包时间间隔、收包传输时延和收包时间间隔。
步骤203：在确定所述目标信息出现异常的情况下，确定时间同步出现异常。
步骤204：按照预设的异常处理方式进行异常处理。
在本申请实施例中，在获取到授时端的线卡为目标报文添加的第一时间戳之后，获取该第一时间戳携带的目标信息，该目标信息提供了发包传输时延、发包时间间隔、收包传输时延和收包时间间隔中的至少之一，根据发包传输时延、发包时间间隔、收包传输时延和收包时间间隔出现异常，能够确定时间同步出现异常，从而检测到了时间同步异常的故障，并且按照预先设置的处理方式对时间同步异常的故障进行异常处理，解决了时间同步异常的故障未能被检测到以及未能得到解决的问题，减少时间同步异常的故障对整个网络的影响。
在一种实现方式中，所述发包传输时延包括：所述主控板发送所述目标同步报文时添加的第二时间戳与所述线卡为所述目标同步报文添加的所述第一时间戳之间的差值。
其中，主控板发送目标同步报文时添加的第二时间戳记录了发送目标同步报文的时间，线卡为目标同步报文添加第一时间戳记录了接收到主控板发送的目标同步报文的时间，通过第二时间戳与第一时间戳之间的差值确定目标同步报文从主控板发送到线卡所用的时间，即为发包传输时延。
在一种实现方式中，所述收包传输时延包括：所述主控板接收所述目标延时请求报文时添加的第二时间戳与所述线卡为所述目标延时请求报文添加的所述第一时间戳之间的差值。
其中，目标延时请求报文先传输到线卡，线卡为目标延时请求报文添加第一时间戳记录线卡接收到目标延时请求报文的时间，再传输到主控板，主控板为目标延时请求报文添加第二时间戳记录主控板接收到目标延时请求报文的时间，通过第二时间戳与第一时间戳之间的差值确定目标延时请求报文从线卡传输到主控板所用的时间，即为收包传输时延。
在一种实现方式中，所述发包时间间隔包括：相邻的两个目标同步报文
的所述第一时间戳之间的时间间隔。
其中，主控板发送多个目标同步报文到线卡，线卡为多个目标同步报文打上第一时间戳，通过相邻的两个目标同步报文的第一时间戳之间的时间间隔能够确定相邻两个发包时间间隔，每相邻的两个目标同步报文的第一时间戳之间的时间间隔都能确定一个发包时间间隔，根据多个目标同步报文能够确定多个发包时间间隔。
在一种实现方式中，所述收包时间间隔包括：相邻的两个目标延时请求报文的所述第一时间戳之间的时间间隔。
其中，线卡接收到多个目标延时请求报文，同时为多个目标延时请求报文打上第一时间戳，通过相邻的两个目标延时请求报文的第一时间戳之间的时间间隔能够确定相邻两个收包时间间隔，每相邻的两个目标延时请求报文的第一时间戳之间的时间间隔都能确定一个收包时间间隔，根据多个目标延时请求报文能够确定多个收包时间间隔。
在一种实现方式中，上述的确定所述目标信息出现异常，包括以下至少之一：
确定所述发包传输时延超过第一阈值；
确定所述发包时间间隔不一致，例如，线卡为多个所述目标同步报文打上的第一时间戳中，两两相邻的目标同步报文的第一时间戳之间的时间间隔不完全相同；
确定所述收包传输时延超过第二阈值；
确定所述收包时间间隔不一致，例如，线卡为多个所述目标延时请求报文打上的第一时间戳中，两两相邻的目标延时请求报文的第一时间戳之间的时间间隔不完全相同。
也就是说，在上述至少一种情况下，确定时间同步出现异常。
在本申请实施例中，根据获取的第一时间戳提供的发包传输时延、发包时间间隔、收包传输时延和收包时间间隔信息，在确定发包传输时延超过第一阈值时，即目标同步报文从主控板发送到线卡所用的时间超过了第一阈值时，确定目标信息出现异常；在确定相邻的两个目标同步报文的所述第一时间戳之间的时间间隔与发包间隔不一致时，即多个目标同步报文确定的多个发包时间间隔中存在发包时间间隔与发包间隔不一致的情况时，确定目标信息出现异常；在确定收包传输时延超过第二阈值时，即目标延时请求报文从
线卡传输到主控板所用的时间超过了第二阈值时，确定目标信息出现异常；在确定相邻的两个目标延时请求报文的所述第一时间戳之间的时间间隔与收包间隔不一致时，即多个目标延时请求报文确定的多个收包时间间隔中存在收包时间间隔与收包间隔不一致的情况时，确定目标信息出现异常；在确定目标信息出现异常时，就能够确定时间同步出现异常，然后按照预设的异常处理法进行异常处理。
在一种实现方式中，上述的第一时间戳可以为所述线卡使用透传时钟(Transparent Clock，TC)时间添加的时间戳，而第二时间戳可以为所述主控板使用TC时间添加的时间戳。
其中，在主控板和线卡接收或发送目标报文时进行打时间戳存在授时不稳定的情况时，可以使用TC时间添加时间戳，提高授时的稳定性。
在一种实现方式中，上述的步骤103可以包括以下至少之一：
(1)对所述授时端发送的Announce报文进行异常处理；
(2)向所述授时端的跟踪端发送告警信息。
在本申请实施例中，在确定时间同步存在异常时，异常处理包括以下至少之一：对授时端发送的Announce报文进行异常处理，将经过异常处理后的Announce报文发送给下游设备，下游设备通过接收该异常处理后的Announce报文能够确定时间同步出现异常，触发最佳主时钟算法(Best Master Clock，BMC)进行重新计算，使得下游设备不再跟踪错误的时间路径；向授时端的跟踪端发送告警信息，授时端的跟踪端接收到该告警信息，故跟踪端不再跟踪错误的时间路径，下游设备也不再跟踪错误的时间路径，从而减少对整个网络的影响。
在一种实现方式中，上述的对所述授时端发送的Announce报文进行异常处理可以包括：修改所述Announce报文的参数；或，停止向所述跟踪端发送所述Announce报文。
其中，在时间同步出现异常时，对Announce报文的参数进行修改，使得下游设备在接收到该Announce报文并检测到Announce报文参数发生变化时，认为该时间路径出现异常，触发BMC算法进行重新计算，切换为跟踪正常设备的时间路径；或者停止向跟踪端发送Announce报文，从而跟踪端也不能向下游设备发送Announce报文，将时间同步异常控制在当前设备，下游设备检测到Announce报文丢失，触发BMC算法进行重新计算，下游设
备不再跟踪错误的时间路径，切换为跟踪正常设备的时间路径。
在一种实现方式中，上述的修改所述Announce报文的参数可以包括：将所述Announce报文的初始时间参数修改为所述主控板的时间参数。
其中，在时间同步出现异常时，将Announce报文的初始时间参数修改为主控板的时间参数，下游设备在收到包括主控板的时间参数的Announce报文时，认为该时间路径出现异常，触发BMC算法进行重新计算，切换为跟踪正常设备的时间路径；Announce报文的时间参数可以包括ClockClass、Priority等参数。
本实施例通过获取授时端的线卡为目标报文添加的第一时间戳，判断该第一时间戳提供的发包传输时延、发包时间间隔、收包传输时延和收包时间间隔信息是否发生异常，确定时间同步是否出现异常；在确定时间同步出现异常，通过修改所述Announce报文的参数或者停止向所述跟踪端发送所述Announce报文以及向所述授时端的跟踪端发送告警信息这些异常处理操作，既能够及时地检测到时间同步出现异常，也能够对时间同步异常进行处理，将时间同步异常故障控制在当前设备，触发BMC算法进行重新计算，使得下游设备不再跟踪错误的时间路径，解决了时间同步异常的故障未能被检测以及未能得到解决的问题，减少时间同步异常的故障对整个网络的影响。
在一种实施例中，上述方法可以应用于如图3所示的分布式时戳处理系统，包括授时端的主控板31和线卡32，跟踪端的主控板33和线卡34，执行如下步骤：
步骤301：主控板31发送目标同步报文并打上T1′时间戳。
步骤302：线卡32接收主控板31发送的目标同步报文并打上T1时间戳。
步骤303：线卡32将T1时间戳通过自定义信号(Signaling)报文传送给主控板31。
步骤304：主控板31通过计算发包传输时延T1_delay＝T1-T'1，并判断发包传输时延是否符合预期传输时延；并且主控板31连续获取多个T1时间戳，计算发包时间间隔其中T1
1为第一个目标同步报文的T1时间戳，T1
2为第二个目标同步报文的T1时间戳，T1
3为第三个目标同步报文的T1时间戳，T1
N-1为第N-1个目标同步报文的T1时间戳，T1
N为第N个目标同步报文的T1时间戳，并判断每个发包时间间隔与发包间隔是否一致。
步骤305：在发包传输时延不符合预期传输时延时或存在发包时间间隔与发包间隔不一致，确定时间同步出现异常，并进行异常处理，例如向跟踪端发送告警信息以及修改Announce报文的参数。
步骤306：主控板33向线卡34发送目标延时请求报文，线卡34再向线卡32发送目标延时请求报文。
步骤307：线卡32接收目标延时请求报文并打上T4时间戳。
步骤308：线卡32将携带T4时间戳的目标延时请求报文发送给主控板31。
步骤309：主控板31接收携带T4时间戳的目标延时请求报文并打上T4′时间戳。
步骤310：主控板31通过计算收包传输时延T4_delay＝T'4-T4，并判断收包传输时延是否符合预期传输时延；并且主控板31连续获取多个T4时间戳，计算收包时间间隔其中T4
1为第一个目标延时请求报文的T4时间戳，T4
2为第二个目标延时请求报文的T4时间戳，T4
3为第三个目标延时请求报文的T4时间戳，T1
N-1为第N-1个目标延时请求报文的T4时间戳，T4
N为第N个目标延时请求报文的T4时间戳，并判断每个收包时间间隔与收包间隔是否一致。
步骤311：在收包传输时延不符合预期传输时延时或存在收包时间间隔与收包间隔不一致，确定时间同步出现异常，并进行异常处理，例如向跟踪端发送告警信息以及修改Announce报文的参数。
在一种实施例中，上述方法还可以应用于带修正域的分布式时戳处理系统，包括授时端的主控板41和线卡42，跟踪端的主控板43和线卡44，执行如下步骤：
步骤401：主控板41使用系统时间打上T1时间戳，发送目标同步报文并用TC时间打CFout1时间戳。
步骤402：线卡42接收主控板41发送的目标同步报文并用TC时间打CFout2时间戳，计算CF12＝CFout2-CFout1。
步骤403：线卡42将CF12通过Signaling报文传送给主控板41。
步骤404：主控板41判断CF12是否符合预期传输时延；并且校验T1时间戳与打戳时的系统时间是否相等；并且主控板41计算发包时间间隔其中T1
1为第一个T1时间戳，T1
2为第二
个R1时间戳，T1
3为第三个T1时间戳，T1
N-1为第N-1个T1时间戳，T1
N为第N个T1时间戳，并判断每个发包时间间隔与发包间隔是否一致。
步骤405：在CF12不符合预期传输时延时或T1时间戳与打戳时的系统时间不相等或存在发包时间间隔与发包间隔不一致，确定时间同步出现异常，并进行异常处理，例如向跟踪端发送告警信息以及停止向跟踪端发送Announce报文。
步骤406：主控板43向线卡44发送目标延时请求报文，线卡44再向线卡42发送目标延时请求报文。
步骤407：线卡42接收目标延时请求报文并用TC时间打上CFint3时间戳。
步骤408：线卡42将携带CFint3时间戳的目标延时请求报文发送给主控板41。
步骤409：主控板41接收携带CFint3时间戳的目标延时请求报文并用TC时间打上CFint4时间戳以及打上T4时间戳。
步骤410：主控板41通过计算收包传输时延CF34＝CFint4-CFint3，并判断CF34是否符合预期传输时延；并且校验T4时间戳与打戳时的系统时间是否相等；并且主控板41计算收包时间间隔其中T4
1为第一个T4时间戳，T4
2为第二个T4时间戳，T4
3为第三个T4时间戳，T1
N-1为第N-1个T4时间戳，T4
N为第N个T4时间戳，并判断每个收包时间间隔与收包间隔是否一致。
步骤411：在CF34不符合预期传输时延时或T4时间戳与打戳时的系统时间不相等或存在收包时间间隔与收包间隔不一致，确定时间同步出现异常，并进行异常处理，例如向跟踪端发送告警信息以及停止向跟踪端发送Announce报文。
在本申请上述的一个或多个实现方式中，在目标信息正常的情况下，授时端的主控板确定时间同步正常，例如，在发包传输时延、发包时间间隔、收包传输时延和收包时间间隔均正常的情况下，授时端的主控板确定时间同步正常。
基于同一发明构思，本申请实施例还提供了一种授时端，图5是根据本申请实施例的一种授时端的结构示意图。如图5所示，授时端可以包括：线卡510，用于为接收到的目标报文添加第一时间戳，并将所述第一时间戳发
送给主控板520，其中，所述第一时间戳为所述线卡510接收到所述目标报文的时间点；所述主控板520，用于基于所述第一时间戳，确定时间同步出现异常；按照预设的异常处理方式进行异常处理。
在一种实现方式中，所述主控板520可以用于基于所述第一时间戳，获取目标信息，其中，所述目标信息包括以下至少之一：发包传输时延、发包时间间隔、收包传输时延和收包时间间隔；在确定所述目标信息出现异常的情况下，确定时间同步出现异常。
在一种实现方式中，所述主控板520可以用于对所述授时端发送的Announce报文进行异常处理；向所述授时端的跟踪端发送告警信息。
在一种实现方式中，所述主控板520可以用于修改所述Announce报文的参数；或，停止向所述跟踪端发送所述Announce报文。
在一种实现方式中，主控板520可以用于将所述Announce报文的初始时间参数修改为所述主控板的时间参数。
本申请实施例提供的授时端的主控板能够实现图1至图4的方法实施例中实现的各个过程，为避免重复，这里不再赘述。
基于相同的技术构思，本申请实施例还提供了一种电子设备，该电子设备用于执行上述的时间同步异常的处理方法，图6为实现本申请各个实施例的一种电子设备的结构示意图。电子设备可因配置或性能不同而产生比较大的差异，可以包括处理器(processor)610、通信接口(Communications Interface)620、存储器(memory)630和通信总线640，其中，处理器610，通信接口620，存储器630通过通信总线640完成相互间的通信。处理器610可以调用存储在存储器630上并可在处理器610上运行的计算机程序，以执行下述步骤：
获取所述授时端的线卡为目标报文添加的第一时间戳，其中，所述第一时间戳为所述线卡接收到所述目标报文的时间点。
基于所述第一时间戳，确定时间同步出现异常。
按照预设的异常处理方式进行异常处理。
具体执行步骤可以参见上述时间同步异常的处理方法实施例的各个步骤，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，本申请实施例中的电子设备包括：服务器、终端或除终端之外的其他设备。
以上电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，例如，输入单元，可以包括图形处理器(Graphics Processing Unit，GPU)和麦克风，显示单元可以采用液晶显示器、有机发光二极管等形式来配置显示面板。用户输入单元包括触控面板以及其他输入设备中的至少一种。触控面板也称为触摸屏。其他输入设备可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器可用于存储软件程序以及各种数据。存储器可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器可以包括易失性存储器或非易失性存储器，或者，存储器可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。
处理器可包括一个或多个处理单元；可选的，处理器集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器中。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述时间同步异常的处理方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器(Read-Only
Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等。
本申请实施例另提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现上述时间同步异常的处理方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。
Claims (15)
- 一种时间同步异常的处理方法，应用授时端的主控板，所述方法包括：获取所述授时端的线卡为目标报文添加的第一时间戳，其中，所述第一时间戳为所述线卡接收到所述目标报文的时间点；基于所述第一时间戳，确定时间同步出现异常；按照预设的异常处理方式进行异常处理。
- 根据权利要求1所述的方法，其中，所述目标报文包括：所述授时端发送的目标同步报文和/或所述授时端接收的目标延时请求报文。
- 根据权利要求2所述的方法，其中，基于所述第一时间戳，确定时间同步出现异常，包括：基于所述第一时间戳，获取目标信息，其中，所述目标信息包括以下至少之一：发包传输时延、发包时间间隔、收包传输时延和收包时间间隔；在确定所述目标信息出现异常的情况下，确定时间同步出现异常。
- 根据权利要求3所述的方法，其中，所述发包传输时延包括：所述主控板发送所述目标同步报文时添加的第二时间戳与所述线卡为所述目标同步报文添加的所述第一时间戳之间的差值。
- 根据权利要求3所述的方法，其中，所述收包传输时延包括：所述主控板接收所述目标延时请求报文时添加的第二时间戳与所述线卡为所述目标延时请求报文添加的所述第一时间戳之间的差值。
- 根据权利要求3所述的方法，其中，所述发包时间间隔包括：相邻的两个目标同步报文的所述第一时间戳之间的时间间隔。
- 根据权利要求3所述的方法，其中，所述收包时间间隔包括：相邻的两个目标延时请求报文的所述第一时间戳之间的时间间隔。
- 根据权利要求2至7任一项所述的方法，其中，确定所述目标信息出现异常，包括以下至少之一：确定所述发包传输时延超过第一阈值；确定所述发包时间间隔不一致；确定所述收包传输时延超过第二阈值；确定所述收包时间间隔不一致。
- 根据权利要求4或5所述的方法，其中，所述第一时间戳为所述线卡使用透传时钟TC时间添加的时间戳，所述第二时间戳为所述主控板使用TC时间添加的时间戳。
- 根据权利要求1至7任一项所述的方法，其中，按照预设的异常处理方式进行异常处理，包括以下至少之一：对所述授时端发送的通告Announce报文进行异常处理；向所述授时端的跟踪端发送告警信息。
- 根据权利要求10所述的方法，其中，对所述授时端发送的通告Announce报文进行异常处理，包括：修改所述通告Announce报文的参数；或，停止向所述跟踪端发送所述通告Announce报文。
- 根据权利要求11所述的方法，其中，所述修改所述通告Announce报文的参数，包括：将所述通告Announce报文的初始时间参数修改为所述主控板的时间参数。
- 一种授时端，包括：线卡，用于为接收到的目标报文添加第一时间戳，并将所述第一时间戳发送给主控板，其中，所述第一时间戳为所述线卡接收到所述目标报文的时间点；所述主控板，用于基于所述第一时间戳，确定时间同步出现异常；按照预设的异常处理方式进行异常处理。
- 一种电子设备，包括处理器，存储器及存储在所述存储器上并可 在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如权利要求1-12任一项所述的时间同步异常的处理方法的步骤。
- 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求1-12任一项所述的时间同步异常的处理方法的步骤。
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| CN104954156A (zh) * | 2014-03-26 | 2015-09-30 | 中兴通讯股份有限公司 | 时钟同步网元异常处理方法、装置及其系统 |
| CN112154614A (zh) * | 2019-08-29 | 2020-12-29 | 上海飞来信息科技有限公司 | 传感系统、传感设备及其控制方法、可移动平台和存储介质 |
| WO2021049233A1 (ja) * | 2019-09-11 | 2021-03-18 | ソニー株式会社 | 情報処理装置、情報処理方法、及びプログラム |
| CN113765612A (zh) * | 2020-06-04 | 2021-12-07 | 中兴通讯股份有限公司 | 节点状态确定方法、装置、设备和存储介质 |
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