WO2024113838A1

WO2024113838A1 - Processor setting method and apparatus, electronic device, and storage medium

Info

Publication number: WO2024113838A1
Application number: PCT/CN2023/104067
Authority: WO
Inventors: 商家玮; 李祖松
Original assignee: 北京微核芯科技有限公司
Priority date: 2022-11-28
Filing date: 2023-06-29
Publication date: 2024-06-06
Also published as: CN115543449B; CN115543449A

Abstract

Provided in the present disclosure are a processor setting method and apparatus, an electronic device, and a storage medium. The specific solution is as follows: determining a valid field corresponding to an instruction item in a processor, wherein the valid field has a corresponding bit width; reading from a target register a valid identification value corresponding to the instruction item; and then, according to the bit width, the valid field and the valid identification value, setting the instruction item invalid.

Description

Processor setting method, device, electronic device and storage medium

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the Chinese patent application with application number 202211498291.2 and application date November 28, 2022, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference.

Technical Field

The present disclosure relates to the field of computer technology, and in particular to a processor setting method, device, electronic device and storage medium.

Background technique

A processor (eg, cache memory, register) is an important unit in the hierarchical structure of a computer storage system. During the application of the processor, it is necessary to perform invalid settings on the processor.

In the related art, when invalid settings are performed on a processor, a relatively cumbersome setting operation is required, and a large functional overhead is required, which will affect the performance of the processor.

Summary of the invention

The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

To this end, the purpose of the present disclosure is to propose a processor setting method, device, electronic device and storage medium, which can combine invalid setting information and valid identification values to efficiently invalidate instruction items in the processor, thereby effectively ensuring the processor setting effect while effectively saving the processor's functional overhead, thereby effectively improving the processor's performance.

The processor setting method proposed in the embodiment of the first aspect of the present disclosure includes: determining a valid field corresponding to an instruction item in a processor, wherein the valid field has a corresponding bit width; reading a valid identification value corresponding to the instruction item from a target register; and invalidating the instruction item according to the bit width, the valid field and the valid identification value.

The processor setting method proposed in the embodiment of the first aspect of the present disclosure determines the valid field corresponding to the instruction item in the processor, wherein the valid field has a corresponding bit width, and reads the valid identification value corresponding to the instruction item from the target register, and then invalidates the instruction item according to the bit width, the valid field and the valid identification value. Thus, it is possible to combine the bit width, the valid field and the valid identification value to efficiently invalidate the instruction item in the processor, thereby effectively ensuring the processor setting effect while effectively saving the functional overhead of the processor, thereby effectively improving the performance of the processor.

The processor setting device proposed in the second aspect embodiment of the present disclosure includes: a determination module, used to determine the valid field corresponding to the instruction item in the processor, wherein the valid field has a corresponding bit width; a reading module, used to read the valid identification value corresponding to the instruction item from the target register; and a setting module, used to invalidate the instruction item according to the bit width, the valid field and the valid identification value.

The processor setting device proposed in the second aspect of the embodiment of the present disclosure determines a valid field corresponding to an instruction item in the processor, wherein the valid field has a corresponding bit width, and reads a valid identification value corresponding to the instruction item from a target register, and then invalidates the instruction item according to the bit width, the valid field and the valid identification value. Thus, it is possible to combine the bit width, the valid field and the valid identification value to efficiently invalidate the instruction item in the processor, thereby effectively ensuring the processor setting effect while effectively saving the functional overhead of the processor, thereby effectively improving the processor's performance.

The third aspect of the present disclosure provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the processor setting method provided in the first aspect of the present disclosure is implemented.

The fourth aspect embodiment of the present disclosure proposes a non-temporary computer-readable storage medium, on which a computer program is stored. When the program is executed by the memory, the processor setting method proposed in the first aspect embodiment of the present disclosure is implemented.

The fifth aspect embodiment of the present disclosure proposes a computer program product. When the instructions in the computer program product are executed by a processor, the processor setting method proposed in the first aspect embodiment of the present disclosure is executed.

Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

FIG1 is a schematic flow chart of a processor setting method according to an embodiment of the present disclosure;

FIG2 is a flowchart of a processor setting method according to another embodiment of the present disclosure;

FIG3 is a schematic diagram of the structure of a processor setting device proposed in an embodiment of the present disclosure;

FIG4 is a schematic diagram of the structure of a processor setting device proposed in another embodiment of the present disclosure;

FIG5 shows a block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure.

Detailed ways

Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and should not be construed as limitations on the present disclosure. On the contrary, the embodiments of the present disclosure include all changes, modifications, and equivalents that fall within the spirit and connotation of the appended claims.

FIG. 1 is a schematic flow chart of a processor setting method according to an embodiment of the present disclosure.

It should be noted that the executor of the processor setting method of this embodiment is a processor setting device, which can be implemented by software and/or hardware. The device can be configured in an electronic device, and the electronic device can include but is not limited to a terminal, a server, etc.

As shown in FIG. 1 , the processor setting method includes steps S101 to S103 .

S101: Determine a valid field corresponding to an instruction item in a processor, wherein the valid field has a corresponding bit width.

Among them, the processor can be specifically, for example, a translation lookaside buffer (TLB), a cache, a register stack, etc.

The embodiment of the present disclosure will specifically explain the processor setting method by assuming that the processor is configured as a cache memory.

The instruction item may specifically be, for example, an instruction memory (icache) in a cache, and the instruction item may be one item or multiple items.

Among them, the instruction item in the memory may have a corresponding valid field (valid field), and the field may have a corresponding bit width (bit). When the bit width (bit) is 1, the value of the valid field is 1, indicating that the corresponding instruction item is valid, and the value is 0, indicating that the corresponding instruction item is invalid. When the bit width (bit) is not 1, the instruction item may be set invalid based on the bit width, the valid field and the valid identification value. For details, please refer to the subsequent embodiments, which will not be repeated here.

In some embodiments, determining the valid field corresponding to the instruction item in the memory may be determining the usage status corresponding to the processor, and determining the valid field corresponding to the instruction item in the memory based on the usage status corresponding to the processor determined above, without limitation.

For example, it can be determined whether the processor is in the startup state. If the processor is in the startup state, then all instruction items in the processor are in an invalid state. Accordingly, it can be determined that the valid field value corresponding to the instruction item in the memory is 0.

In other embodiments, determining the valid field corresponding to an instruction item in the processor may also be performed by directly identifying the value of a corresponding status bit (valid bit) for each instruction item in the processor to obtain the valid field corresponding to the instruction item in the processor, and there is no limitation on this.

S102: Read the valid identification value corresponding to the instruction item from the target register.

In the embodiment of the present disclosure, after determining the valid field corresponding to the instruction item in the processor, wherein the valid field has a corresponding bit width, the valid identification value corresponding to the instruction item can be read from the target register.

The effective identification value refers to the real identification value in the effective field corresponding to the instruction item, and the effective identification value can be stored in the register corresponding to the corresponding instruction item (the register can be called the target register).

In an embodiment of the present disclosure, reading a valid identification value corresponding to an instruction item from a target register may be performed by storing the valid identification value corresponding to the instruction item in the processor in a corresponding target register before executing a processor setting method, and then, during the execution of the processor setting method, reading the valid identification value corresponding to the instruction item from the target register, and then, based on the valid identification value, performing an invalid setting on the instruction item in the processor.

S103: Invalidate the instruction item according to the bit width, the valid field and the valid identification value.

The instruction item in the processor may refer to an instruction memory (icache) in the memory, and the instruction item may be one or multiple items.

That is to say, in the embodiments of the present disclosure, the instruction item is set according to the invalid setting information and the valid identification value. It can be that a certain instruction memory (icache) in the memory is set according to the invalid setting information and the valid identification value, or multiple instruction memories (icache) in the memory are set.

In some embodiments, the instruction item is set according to the invalid setting information and the valid identification value, which may be a result. The invalid setting information and the valid identification value are combined to invalidate the instruction item, that is, when the bit width, the valid field and the valid identification value meet the set conditions, an item in the memory, or multiple instruction memories (icache) can be invalidated.

For example, after receiving an invalid setting instruction (eg, fencei instruction), invalid setting is performed on a certain item or multiple instruction memories (icache) in the memory according to the invalid setting information and the valid identification value.

In some embodiments, the instruction item is invalidated based on the bit width, valid field and valid identification value. When the bit width is 1, the valid field is adjusted to 0 to invalidate the instruction item. When the bit width is greater than 1, the instruction item is invalidated based on the valid field and the valid identification value.

That is to say, in the embodiments of the present disclosure, the bit width of the valid field corresponding to the instruction item in the processor can be judged. If the bit width is 1, the valid field is adjusted to 0 to invalidate the instruction item. If the bit width is greater than 1, the instruction item is invalidated based on the valid field and the valid identification value.

In an embodiment of the present disclosure, if the bit width is greater than 1 and when the valid field of the instruction item is 0, the corresponding instruction item can be determined to be invalid. Thus, the instruction item is set to be invalid based on the valid field and the valid identification value, and the valid field can be adjusted to 0 to set the instruction item to be invalid.

In this embodiment, by determining the valid field corresponding to the instruction item in the processor, wherein the valid field has a corresponding bit width, and reading the valid identification value corresponding to the instruction item from the target register, and then setting the instruction item invalid according to the bit width, the valid field and the valid identification value, it is possible to combine the bit width, the valid field and the valid identification value to efficiently set the instruction item in the processor invalid, thereby effectively ensuring the processor setting effect while effectively saving the processor's functional overhead, thereby effectively improving the processor's performance.

FIG. 2 is a schematic flow chart of a processor setting method according to another embodiment of the present disclosure.

As shown in FIG. 2 , the processor setting method includes steps S201 to S205 .

S201: configuring a corresponding target register for an instruction item in a processor, where the target register is used to store a valid identification value corresponding to the instruction item.

In the embodiment of the present disclosure, in the initial stage of executing the processor setting method, a corresponding register can be configured for the instruction item in the processor, and the register can be called a target register. The target register can be used to store a valid identification value corresponding to the instruction item.

S202: Determine a valid field corresponding to an instruction item in a processor, wherein the valid field has a corresponding bit width.

S203: Read the valid identification value corresponding to the instruction item from the target register.

The description of S202 - S203 can be specifically referred to the above embodiment, which will not be repeated here.

S204: invalidate a single instruction item according to the valid field and the valid identification value, wherein the single instruction item is an instruction item to be invalidated among the multiple instruction items.

The single instruction item is an instruction item to be invalidated among the multiple instruction items.

In some embodiments, a single instruction item is invalidated based on a valid field and a valid identification value. The single instruction item can be determined from multiple instruction items based on the valid identification value, and the valid field is adjusted to a target field value to invalidate the single instruction item.

Among them, in the process of invalidating a single instruction item, the preset field predetermined for the valid field The value can be called the target field value, and the target field value is different from the effective identification value.

In the embodiment of the present disclosure, the instruction item to be invalidated can be determined from multiple instruction items as a single instruction item based on the valid identification value, that is, the instruction item whose valid identification value is not the target field value can be determined from multiple instruction items as a single instruction item, and then, the valid field can be adjusted to adjust the valid field to a target field value different from the valid identification value, thereby achieving invalidation of the single instruction item.

S205: Invalidate all instruction items according to the valid fields and valid identification values.

In the embodiment of the present disclosure, the number of processor instruction items may be multiple, and thus, all instruction items may be set to be invalid according to the valid fields and valid identification values.

In some embodiments, before invalidating all instruction items according to the valid fields and valid identification values, an invalidation identification condition may be determined according to the bit width, wherein the invalidation identification condition is used to invalidate the instruction items.

In the disclosed embodiment, when invalidating all instruction items, corresponding invalidation identification conditions may be set for valid identification values of corresponding instruction items, and then the instruction items may be invalidated in combination with the invalidation identification conditions.

In the embodiment of the present disclosure, the invalid identification condition can be determined as 2N-1 according to the bit width, where N is the bit width of the valid field.

In the embodiment of the present disclosure, the valid identification value and the valid field may have corresponding reset values. For example, the reset value of the valid identification value may be 1, and the reset value of the valid field may be 0.

In some embodiments, all instruction items are invalidated based on the valid field and the valid identification value. It can be determined whether the valid identification value satisfies the invalid identification condition, and when the valid identification value satisfies the invalid identification condition, the valid identification value is adjusted to the first preset identification value, and the valid field of each instruction item is adjusted to the first preset field to invalidate the instruction item. When the valid identification value does not satisfy the invalid identification condition, the valid identification value is increased by 1 to invalidate the instruction item.

Among them, when the valid identification value meets the invalid identification condition, the identification value pre-set for the valid identification value can be called the first preset identification value (the first identification value can be specifically, for example, 1), and accordingly, the field pre-set for the valid field of each instruction item can be called the first preset field (the first preset field can be specifically, for example, 0).

That is to say, in the embodiment of the present disclosure, the valid identification value may be adjusted to 1 and the valid field of each instruction item may be adjusted to 0 to invalidate the instruction item when the valid identification value satisfies 2N-1.

Among them, when the valid identification value does not meet the invalid identification condition, 1 is added to the valid identification value and the valid field is kept unchanged to invalidate the instruction item.

For example, when the bit width N is 2, when the instruction item is set invalid, the values of the valid identification value (vid) and the valid field (valid) can be specifically as shown in Table 1:

Table 1

It is understood that each element in the above Table 1 exists independently. These elements are exemplarily listed in the same table, but it does not mean that all elements in the table must exist at the same time as shown in the table. The value of each element is independent of the value of any other element in Table 1. Therefore, those skilled in the art can understand that the value of each element in Table 1 is an independent embodiment.

In the disclosed embodiment, by configuring a corresponding target register for an instruction item in a processor, the target register is used to store a valid identification value corresponding to the instruction item, and determine a valid field corresponding to the instruction item in the processor, wherein the valid field has a corresponding bit width, and then read the valid identification value corresponding to the instruction item from the target register, and according to the valid field and the valid identification value, invalidate a single instruction item, wherein the single instruction item is an instruction item to be invalidated among multiple instruction items, and then invalidate all instruction items according to the valid field and the valid identification value, thereby achieving efficient invalidation of instruction items in the processor by combining the bit width, the valid field and the valid identification value, thereby effectively ensuring the setting effect of the processor while effectively saving the functional overhead of the processor, thereby effectively improving the performance of the processor.

FIG. 3 is a schematic diagram of the structure of a processor setting device proposed in an embodiment of the present disclosure.

As shown in FIG3 , the processor setting device 30 includes:

A determination module 301 is used to determine a valid field corresponding to an instruction item in a processor, wherein the valid field has a corresponding bit width;

A reading module 302, used for reading a valid identification value corresponding to an instruction item from a target register;

The setting module 303 is used to set the instruction item to be invalid according to the bit width, the valid field and the valid identification value.

In some embodiments of the present disclosure, as shown in FIG. 4 , FIG. 4 is a processor device according to another embodiment of the present disclosure. The structural diagram of the setting device, wherein the setting module 303 includes:

The first setting submodule 3031 is used to adjust the valid field to 0 when the bit width is 1, so as to perform invalid setting on the instruction item;

The second setting submodule 3032 is used to set the instruction item to be invalid according to the valid field and the valid identification value when the bit width is greater than 1.

In some embodiments of the present disclosure, the number of instruction items is multiple;

The second setting submodule 3032 is further used for:

Invalidate a single instruction item according to the valid field and the valid identification value, wherein the single instruction item is the instruction item to be invalidated among the multiple instruction items; and/or

Invalidate all instruction items based on valid fields and valid identification values.

In some embodiments of the present disclosure, the second setting submodule 3032 is further used to:

Determine a single instruction item from a plurality of instruction items according to a valid identification value;

The valid field is adjusted so that the adjusted valid field and the valid identification value are different, so as to invalidate the setting of a single instruction item.

Before invalidating all instruction items according to the valid fields and the valid identification values, determining an invalid identification condition according to the bit width, wherein the invalid identification condition is used to invalidate the instruction items;

Determine whether the valid field meets the invalid identification condition;

If the valid field meets the invalid identification condition, the valid identification value is adjusted to the first preset identification value, and the valid field of each instruction item is adjusted to the first preset field, so as to set the instruction item invalid;

If the valid field does not satisfy the invalid identification condition, the valid identification value is increased by 1 to invalidate the instruction item.

In some embodiments of the present disclosure, the processor setting device 30 further includes:

The configuration module 304 is used to configure a corresponding target register for the instruction item in the processor before determining the valid field corresponding to the instruction item in the processor, and the target register is used to store the valid identification value corresponding to the instruction item.

Corresponding to the processor setting method provided in the embodiments of Figures 1 to 2 above, the present disclosure further provides a processor setting device. Since the processor setting device provided in the embodiments of the present disclosure corresponds to the processor setting method provided in the embodiments of Figures 1 to 2 above, the implementation method of the processor setting method is also applicable to the processor setting device provided in the embodiments of the present disclosure, and will not be described in detail in the embodiments of the present disclosure.

In the disclosed embodiment, by determining the valid field corresponding to the instruction item in the processor, wherein the valid field has a corresponding bit width, and reading the valid identification value corresponding to the instruction item from the target register, and then setting the instruction item invalid according to the bit width, the valid field and the valid identification value, it is possible to combine the bit width, the valid field and the valid identification value to efficiently set the instruction item in the processor invalid, thereby effectively ensuring the setting effect of the processor while effectively saving the functional overhead of the processor, thereby effectively improving the performance of the processor.

In order to implement the above embodiments, the present disclosure further proposes an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the above embodiments of the present disclosure are implemented. A processor setting method is proposed in an embodiment.

In order to implement the above embodiments, the present disclosure further proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the processor setting method proposed in the above embodiments of the present disclosure is implemented.

In order to implement the above embodiments, the present disclosure further proposes a computer program product. When the instruction processor in the computer program product executes, the processor setting method proposed in the above embodiments of the present disclosure is executed.

Fig. 5 shows a block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure. The electronic device 12 shown in Fig. 5 is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

5 , the electronic device 12 is in the form of a general purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more memories or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a memory or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnection (PCI) bus.

The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and/or cache memory 32. The electronic device 12 may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media (not shown in FIG. 5 , commonly referred to as a “hard drive”).

Although not shown in FIG. 5 , a disk drive for reading and writing to a removable nonvolatile disk (e.g., a “floppy disk”) and an optical disk drive for reading and writing to a removable nonvolatile optical disk (e.g., a Compact Disc Read Only Memory (hereinafter referred to as CD-ROM), a Digital Video Disc Read Only Memory (hereinafter referred to as DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and/or methods of the embodiments described in the present disclosure.

The electronic device 12 may also be connected to one or more external devices 14 (e.g., a keyboard, a pointing device, a display 24 The electronic device 12 may communicate with one or more devices that enable a user to interact with the electronic device 12, and/or any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may be performed through an input/output (I/O) interface 22. In addition, the electronic device 12 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and/or a public network, such as the Internet) through a network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 through a bus 18. It should be understood that, although not shown in the figure, other hardware and/or software modules may be used in conjunction with the electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the processor setting method mentioned in the above embodiment.

Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing module or may be Each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are illustrative and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

A processor setting method, comprising:

Determining a valid field corresponding to the instruction item in the processor, wherein the valid field has a corresponding bit width;

Reading a valid identification value corresponding to the instruction item from a target register;

The instruction item is invalidated according to the bit width, the valid field and the valid identification value.
The method of claim 1, wherein the invalidating the instruction item according to the bit width, the valid field, and the valid identification value comprises:

In response to the bit width being 1, adjusting the valid field to 0 to invalidate the instruction item;

In response to the bit width being greater than 1, the instruction item is invalidated according to the valid field and the valid identification value.
The method according to claim 2, wherein the number of the instruction items is multiple;

The step of setting the instruction item to be invalid according to the valid field and the valid identification value includes:

According to the valid field and the valid identification value, invalidate a single instruction item, wherein the single instruction item is the instruction item to be invalidated among the multiple instruction items; and/or

According to the valid field and the valid identification value, all the instruction items are set to be invalid.
The method of claim 3, wherein the step of setting a single instruction item invalid according to the valid field and the valid identification value comprises:

Determine the single instruction item from the plurality of instruction items according to the effective identification value;

The valid field is adjusted to a target field value to invalidate the single instruction item, wherein the target field value is different from the valid identification value.
The method according to claim 3, wherein, before the step of setting all the instruction items to be invalid according to the valid field and the valid identification value, further comprising:

Determining an invalid flag condition according to the bit width, wherein the invalid flag condition is used to invalidate the instruction item;

The step of setting all the instruction items to be invalid according to the valid field and the valid identification value includes:

Determining whether the valid identification value satisfies the invalid identification condition;

In response to the valid identification value satisfying the invalid identification condition, adjusting the valid identification value to a first preset identification value, and adjusting the valid field of each of the instruction items to the first preset field, so as to invalidate the instruction item;

In response to the valid identification value not satisfying the invalid identification condition, the valid identification value is increased by 1 to invalidate the instruction item.
The method of claim 1, wherein, before determining the valid field corresponding to the instruction item in the processor, the method further comprises:

The corresponding target register is configured for the instruction item in the processor, and the target register is used to store Store the valid identification value corresponding to the instruction item.
A processor setting device, comprising:

A determination module, configured to determine a valid field corresponding to an instruction item in a processor, wherein the valid field has a corresponding bit width;

A reading module, used for reading a valid identification value corresponding to the instruction item from a target register;

A setting module is used to set the instruction item to be invalid according to the bit width, the valid field and the valid identification value.
The apparatus according to claim 7, wherein the setting module comprises:

A first setting submodule, configured to adjust the valid field to 0 in response to the bit width being 1, so as to perform an invalid setting on the instruction item;

The second setting submodule is used for, in response to the bit width being greater than 1, performing invalid setting on the instruction item according to the valid field and the valid identification value.
The apparatus according to claim 8, wherein the number of the instruction items is multiple;

Wherein, the second setting submodule is further used for:

According to the valid field and the valid identification value, invalidate a single instruction item, wherein the single instruction item is the instruction item to be invalidated among the multiple instruction items; and/or

According to the valid field and the valid identification value, all the instruction items are set to be invalid.
The apparatus according to claim 9, wherein the second setting submodule is further used to:

Determine the single instruction item from the plurality of instruction items according to the effective identification value;

The valid field is adjusted to a target field value to invalidate the single instruction item, wherein the target field value is different from the valid identification value.
The apparatus according to claim 9, wherein the second setting submodule is further used to:

Before performing invalid setting on all the instruction items according to the valid field and the valid identification value, determining an invalid identification condition according to the bit width, wherein the invalid identification condition is used to perform invalid setting on the instruction item;

Determine whether the valid field satisfies the invalid identification condition;

In response to the valid field satisfying the invalid identification condition, adjusting the valid identification value to a first preset identification value, and adjusting the valid field of each of the instruction items to the first preset field, so as to set the instruction item to be invalid;

In response to the valid field not satisfying the invalid identification condition, the valid identification value is increased by 1 to invalidate the instruction item.
The apparatus of claim 7, further comprising:

A configuration module is used to configure the corresponding target register for the instruction item in the processor before determining the valid field corresponding to the instruction item in the processor, and the target register is used to store the valid identification value corresponding to the instruction item.
An electronic device, comprising:

at least one processor; and

a memory communicatively connected to the at least one processor; wherein,

The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.
A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 6.
A computer program product, wherein when instructions in the computer program product are executed by a processor, the method according to any one of claims 1 to 6 is performed.