WO2024109730A1 - Variable modular multiplier, operation method, and related device - Google Patents

Abstract

A variable modular multiplier, an operation method, and a related device. The variable modular multiplier provided by the present application comprises n controlled variable modular adders and n-1 variable double modular multipliers which are alternately cascaded. Constants in the controlled variable modular adders and the variable double modular multipliers comprise moduli. A modular multiplication operation is converted into n controlled variable modular addition operations and n-1 variable double modular multiplication operations, thereby achieving the solution of the modular multiplication operation of two pieces of inputted data to be multiplied and a modulus.

Description

Variable modular multiplication operator, operation method and related device

This application claims the priority of the Chinese patent application filed with the China Patent Office on November 21, 2022, with application number 202211473091.1, titled “Variable double modular multiplication operator, operation method and related device”, and claims the priority of the Chinese patent application filed with the China Patent Office on November 22, 2022, with application number 202211465294.6, titled “Variable modular multiplication operator, operation method and related device”, and claims the priority of the Chinese patent application filed with the China Patent Office on November 22, 2022, with application number 202211465284.2, titled “Variable modular addition operator, operation method and related device based on constant addition and subtraction”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of quantum computing technology, and in particular to a variable modular multiplication operator, an operation method and related devices.

Background technique

Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because they have the ability to process mathematical problems more efficiently than ordinary computers. For example, they can speed up the time to crack RSA keys from hundreds of years to a few hours.

Modular operations are widely used in number theory and cryptography, from the identification of odd and even numbers to prime numbers, from Sun Tzu's theorem to Caesar's cipher, from finite fields to the realization of block cipher field towers, from elliptic curves over finite fields to public key cryptography based on elliptic curves, all of which are filled with modular operations. Therefore, modular operations are the most commonly used function in computing components, and the same is true for quantum computing. How to implement variable modular multiplication operations, variable modular addition operations based on constant addition and subtraction, and variable double modular multiplication operations are technical problems that need to be solved urgently in quantum computing.

Summary of the invention

The purpose of this application is to provide a variable modular multiplication operator, operation method and related devices, aiming to realize the modular multiplication operation of any two input data and a preset modulus in quantum computing. The specific technical solution is as follows:

In a first aspect of the present application, a variable modulo adder based on constant addition and subtraction is provided, wherein the variable modulo adder comprises a first adder, a first constant subtractor, a first CNOT gate and a first controlled constant adder which are cascaded in sequence, wherein the constants in the first constant subtractor and the first controlled constant adder are both moduli, and the variable modulo adder is used to calculate the result of the modulo addition operation of two input data to be added and the moduli.

In a possible embodiment, the four input ends of the variable modular adder are respectively connected to the three input ends of the first adder and one of the input ends of the first CNOT gate, and the four input ends of the variable modular adder are used to input the quantum states corresponding to the two data to be added, the initial calculation auxiliary data and the initial comparison auxiliary data.

In a possible embodiment, one output terminal of the first adder is connected to the input terminal of the first constant subtractor, the output terminal of the first constant subtractor is connected to the other input terminal of the first CNOT gate, and two output terminals of the first CNOT gate are connected to two input terminals of the first controlled constant adder.

In a possible embodiment, the output end of the first constant subtractor includes a data output end and a sign output end, one of the input ends of the first controlled constant adder includes a data input end and a sign input end, the sign output end of the first constant subtractor is connected to the other input end of the first CNOT gate, and one of the output ends of the first CNOT gate is connected to the first controlled constant adder. A controlled constant adder is connected to the sign input terminal.

In a possible embodiment, the two output ends of the first controlled constant adder are used to output the quantum state corresponding to the analog addition operation result and the intermediate comparison auxiliary data, respectively, and the other two output ends of the first adder are used to output the quantum state corresponding to one of the data to be added and the intermediate calculation auxiliary data.

In a possible embodiment, the first adder, the first constant subtractor, the first CNOT gate and the first controlled constant adder are analog addition operation modules, and the analog addition operation module is used to calculate the analog addition operation result and the intermediate comparison auxiliary data based on the input initial comparison auxiliary data and two data to be added. The variable analog addition operator also includes an auxiliary data reset module connected to the analog addition operation module, and the auxiliary data reset module is used to reset the intermediate comparison auxiliary data to the initial comparison auxiliary data.

In a possible embodiment, the auxiliary data reset module includes a subtractor, a first NOT gate, a second CONT gate, a second NOT gate and a second adder which are cascaded in sequence, the four input ends of the auxiliary data reset module are respectively connected to the three input ends of the subtractor and one of the input ends of the second CNOT gate, the four output ends of the auxiliary data reset module are respectively connected to the three output ends of the second adder and one of the output ends of the second CONT gate, the three output ends of the second adder are used to output the analog addition operation result, one of the data to be added and the quantum state corresponding to the initial calculation auxiliary data, and one of the output ends of the second CONT gate is used to output the quantum state corresponding to the initial comparison auxiliary data.

In a possible embodiment, the three output ends of the subtractor are respectively connected to the input end of the first NOT gate and two of the input ends of the second adder, the output end of the first NOT gate is connected to the other input end of the second CNOT gate, the other output end of the second CNOT gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate is connected to the other input end of the second adder.

In a possible embodiment, one of the output ends of the subtractor includes a data output end and a sign output end, the other input end of the second adder includes a data input end and a sign input end, the sign output end of the subtractor is connected to the input end of the first NOT gate, and the output end of the second NOT gate is connected to the sign input end of the second adder.

In a possible embodiment, four output terminals of the variable modular adder are respectively connected to two output terminals of the first controlled constant adder and the other two output terminals of the first adder.

In a second aspect of the present application, a variable double modular multiplication operator is provided, which includes a double operation module and a modulus operation module cascaded in sequence, the constant in the modulus operation module includes a modulus, the double operation module is used to determine the double of the input data to be multiplied, and the modulus operation module is used to calculate the modulus operation result of the double of the data to be multiplied and the modulus.

In a possible embodiment, the doubling operation module includes one of the following operations: an operation of staggered storage of data, an adder, and a SWAP gate.

In a possible embodiment, one of the input ends of the variable double modular multiplication operator is connected to the input end of the double operation module, the output end of the double operation module is connected to one of the input ends of the modulus operation module, the other input end of the variable double modular multiplication operator is connected to the other input end of the modulus operation module, one of the input ends of the variable double modular multiplication operator is used to input the quantum state corresponding to the data to be multiplied, and the other input end of the variable double modular multiplication operator is used to input the quantum state corresponding to the data to be multiplied. The input end is used to input the quantum state corresponding to the initial auxiliary data.

In a possible embodiment, the modulus operation module includes a second constant subtractor, a third CNOT gate, and a second controlled constant adder which are cascaded in sequence, and the constants in the second constant subtractor and the second controlled constant adder are the modulus.

In a possible embodiment, the output end of the second constant subtractor includes a data output end and a sign output end, one of the input ends of the second controlled constant adder includes a data input end and a sign input end, the data output end of the second constant subtractor is connected to the data input end of the second controlled constant adder, the sign output end of the second constant subtractor is connected to one of the input ends of the third CNOT gate, and the two output ends of the third CNOT gate are respectively connected to the sign input end and another input end of the second controlled constant adder.

In a possible embodiment, the two output terminals of the second controlled constant adder are respectively used to output a quantum state corresponding to a modulus operation result of twice the data to be multiplied and the modulus and a quantum state corresponding to the intermediate auxiliary data.

In a possible embodiment, two output terminals of the second controlled constant adder are respectively connected to two output terminals of the variable double modular multiplication operator.

In a possible embodiment, the second constant subtractor, the third CNOT gate and the second controlled constant adder are a first operator module, and the modulus operation module also includes a second operator module cascaded with the first operator module, and the second operator module is used to reset the intermediate auxiliary data to the initial auxiliary data.

In a possible embodiment, the second sub-operation module includes a third NOT gate, a fourth CNOT gate and a fourth NOT gate cascaded in sequence, one of the output ends of the second controlled constant adder includes a low-order output end and a non-low-order output end, the low-order output end of the second controlled constant adder is connected to the input end of the third NOT gate, and the other output end of the second controlled constant adder is connected to one of the input ends of the fourth CNOT gate.

In a possible embodiment, the output end of the third NOT gate is connected to the other input end of the fourth CNOT gate, and the other output end of the fourth CNOT gate is connected to the input end of the fourth NOT gate.

In a possible embodiment, the output end of the fourth NOT gate and the non-low-order output end of the second controlled constant adder are used to output the quantum state corresponding to the modulus operation result of twice the data to be multiplied and the modulus, and one of the output ends of the fourth CNOT gate is used to output the quantum state corresponding to the initial auxiliary data.

In a possible embodiment, the output end of the fourth NOT gate and the non-low-order output end of the second controlled constant adder are connected to one of the output ends of the variable double modular multiplication operator, and one of the output ends of the fourth CNOT gate is connected to the other output end of the variable double modular multiplication operator.

In the third aspect of the present application, a variable modular multiplication operator is provided, which includes n controlled variable modular addition operators as described in the above embodiment and n-1 variable double modular multiplication operators as described in the above embodiment, which are alternately cascaded, and the constants in the controlled variable modular addition operator and the variable double modular multiplication operator include a modulus, and the variable modular multiplication operator is used to calculate the modular multiplication result of two input data to be multiplied and the modulus.

In a fourth aspect of the present application, a variable modular addition method based on constant addition and subtraction is provided, the method comprising:

Obtaining the variable modular addition operator and the two data to be added as described in the above embodiment;

Input the two data to be added into the variable modulo adder, and run the variable modulo adder to obtain two a quantum state corresponding to a result of a modular addition operation of the data to be added and the modulus;

The result of the modular addition operation is determined based on a quantum state corresponding to the result of the modular addition operation.

In a fifth aspect of the present application, a variable double modular multiplication operation method is provided, the method comprising:

Obtaining the variable double modular multiplication operator and the data to be multiplied as described in the above embodiment;

Inputting the data to be multiplied into the variable double modular multiplication operator, and running the variable double modular multiplication operator to obtain a quantum state corresponding to a modular operation result of twice the data to be multiplied and the modulus;

The modulus operation result of twice the data to be multiplied and the modulus is determined based on the quantum state corresponding to the modulus operation result.

In a sixth aspect of the present application, a variable modular multiplication operation method is provided, the method comprising:

Obtaining a variable modular multiplication operator and two data to be multiplied as described in the above embodiment;

Inputting the two data to be multiplied into the variable modular multiplication operator, and running the variable modular multiplication operator to obtain a quantum state corresponding to a modular multiplication operation result of the two data to be multiplied and the modulus;

The modular multiplication result of the two data to be multiplied and the modulus is determined based on the quantum state corresponding to the modular multiplication result.

In a seventh aspect of the present application, a variable modular addition operation device based on constant addition and subtraction is provided, the device comprising:

An acquisition unit, used for acquiring the variable modular addition operator and the two data to be added as described in the above embodiment;

A calculation unit, used for inputting the two data to be added into the variable modular addition operator, and running the variable modular addition operator to obtain a quantum state corresponding to a result of modular addition operation of the two data to be added and the modulus;

A determination unit is used to determine the result of the analog addition operation based on the quantum state corresponding to the result of the analog addition operation.

The acquisition unit is further used to acquire the variable double modular multiplication operator and the data to be multiplied as described in the above embodiment;

The computing unit is further configured to input the data to be multiplied into the variable double modular multiplication operator, and to operate the variable double modular multiplication operator to obtain a quantum state corresponding to a modular operation result of twice the data to be multiplied and the modulus;

The determining unit is further used to determine a modulus operation result of twice the data to be multiplied and the modulus based on a quantum state corresponding to the modulus operation result.

The acquisition unit is further used to acquire the variable modular multiplication operator and two data to be multiplied as described in the above embodiment;

The computing unit is further used to input the two data to be multiplied into the variable modular multiplication operator, and to run the variable modular multiplication operator to obtain a quantum state corresponding to a modular multiplication operation result of the two data to be multiplied and the modulus;

The determining unit is further used to determine the modular multiplication result of the two data to be multiplied and the modulus based on the quantum state corresponding to the modular multiplication result.

In the eighth aspect of the present application, a storage medium is further provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of the fourth aspect, the fifth aspect and the sixth aspect are implemented.

In the ninth aspect of the present application, an electronic device is also provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the method steps described in any one of the fourth, fifth and sixth aspects above.

Beneficial effects of the embodiments of the present application:

The variable modular multiplication operator provided in the present application comprises n controlled variable modular addition operators alternately cascaded and n-1 variable double modular multiplication operators. Arithmetic unit. The variable modulo-addition operator comprises a first adder, a constant subtractor, a first CNOT gate and a first controlled constant adder which are cascaded in sequence. The constants in the first constant subtractor and the first controlled constant adder are moduli. The variable modulo-addition operator is used to calculate the modulo-addition operation result of two input data to be added and the moduli. For any two input data to be added, the modulo-addition operation result of the two data and the moduli preset in the variable modulo-addition operator can be calculated. The variable double modular multiplication operator comprises a double operation module and a modulo operation module which are cascaded in sequence. The constant in the modulo operation module comprises the moduli. The double operation module is used to determine the double of the input data to be multiplied. The modulo operation module is used to calculate the modulo-addition operation result of the two data to be multiplied and the moduli. For the input data to be multiplied, the double operation module can calculate the double of the two data and the moduli. Then, the modulo operation module calculates the modulo result of the two data and the preset moduli. Based on this, the constants in the controlled variable modular addition operator and the variable double modular multiplication operator include the modulus. By converting the modular multiplication operation into n controlled variable modular addition operations and n-1 variable double modular multiplication operations, the modular multiplication operation of the two input data to be multiplied and the modulus can be solved.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

FIG1 is a hardware structure block diagram of a computer terminal of a variable modular addition operation method based on constant addition and subtraction provided by an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a variable modulo addition operator based on constant addition and subtraction provided in an embodiment of the present application;

FIG3 is a schematic diagram of the structure of another variable modulo adder based on constant addition and subtraction provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of an auxiliary data reset module provided in an embodiment of the present application;

FIG5 is a flow chart of a variable modular addition operation method based on constant addition and subtraction provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of a variable double modular multiplication operator provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of another variable double modular multiplication operator provided in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of a modulus-to-digital operation module provided in an embodiment of the present application;

FIG9 is a schematic diagram of the structure of another analog-to-digital operation module provided in an embodiment of the present application;

FIG10 is a flow chart of a variable double modular multiplication operation method provided in an embodiment of the present application;

FIG11 is a schematic diagram of the structure of a variable modular multiplication operator provided in an embodiment of the present application;

FIG12 is a flow chart of a variable modular multiplication operation method provided in an embodiment of the present application;

FIG13 is a schematic diagram of the structure of a variable modular addition operation device based on constant addition and subtraction provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution, and advantages of the present application more clearly understood, the present application is further described in detail with reference to the accompanying drawings and examples. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field belong to the scope of protection of the present application.

The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

The embodiment of the present application first provides a variable modular multiplication method, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.

The following is a detailed description of it by taking running on a computer terminal as an example. FIG. 1 is a hardware structure block diagram of a computer terminal of a variable modular addition operation method based on constant addition and subtraction provided in an embodiment of the present application. As shown in FIG. 1 , the computer terminal may include one or more (only one is shown in FIG. 1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing the variable modular multiplication operation method. Optionally, the computer terminal may also include a transmission device 106 and an input/output device 108 for a communication function. It will be appreciated by those skilled in the art that the structure shown in FIG. 1 is only for illustration and does not limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than those shown in FIG. 1 , or have a configuration different from that shown in FIG. 1 .

The memory 104 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to the variable modular multiplication operation method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly.

It should be noted that a true quantum computer is a hybrid structure, which consists of two parts: one part is a classical computer, which is responsible for performing classical calculations and control; the other part is a quantum device, which is responsible for running quantum programs and thus realizing quantum computing. A quantum program is a sequence of instructions written in a quantum language such as QRunes that can be run on a quantum computer, which supports quantum logic gate operations and ultimately realizes quantum computing. Specifically, a quantum program is a sequence of instructions that operate quantum logic gates in a certain sequence.

In practical applications, due to the development of quantum device hardware, it is usually necessary to perform quantum computing simulation to verify quantum algorithms, quantum applications, etc. Quantum computing simulation is the process of simulating the operation of quantum programs corresponding to specific problems by using a virtual architecture (i.e., quantum virtual machine) built with the resources of ordinary computers. Usually, it is necessary to build a quantum program corresponding to a specific problem. The quantum program referred to in the embodiment of the present application is a program that characterizes quantum bits and their evolution written in classical languages, in which quantum bits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.

Quantum circuits, as a manifestation of quantum programs, are also called quantum logic circuits. They are the most commonly used general quantum computing model. They represent circuits that operate on quantum bits in an abstract concept. They are composed of quantum bits, circuits (timelines), and various quantum logic gates. Finally, the results often need to be read out through quantum measurement operations.

Unlike traditional circuits that are connected by metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be viewed as Connected by time, the state of the quantum bit evolves naturally over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated on.

A quantum program as a whole corresponds to a total quantum circuit, and the quantum program described in this application refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits in the quantum program. It can be understood that a quantum program can be composed of a quantum circuit, a measurement operation on the quantum bits in the quantum circuit, a register for storing the measurement results, and a control flow node (jump instruction). A quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution process of a quantum program is the process of executing all quantum logic gates in a certain sequence. It should be noted that the sequence is the time order in which a single quantum logic gate is executed.

It should also be noted that the present application relates to quantum computers. In ordinary computing devices based on silicon chips, the units that process the chips are CMOS tubes. Such computing units are not limited by time and intermittency, that is, such computing units are not limited by the length of use and are available at any time. In addition, at present, in silicon chips, the number of such computing units is sufficient, that is, the number of computing units in a chip is currently in the tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by CMOS tubes is fixed, for example: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the computing effect.

Different from such logic units in ordinary computing devices, the basic computing unit in current quantum computers is the quantum bit. The input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the length of use and is not available at any time. Making full use of the quantum bit within the available length of use of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. Given that the number of quantum bits is limited, the logical functions in the field of quantum computing are diverse, such as Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. Quantum logic gates are generally represented by unitary matrices, and unitary matrices are not only in the form of matrices, but also a kind of operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix on the left by the matrix corresponding to the quantum state right vector. During quantum computing, the operation effect is achieved by combining a limited number of quantum bits with a variety of logical functions.

Based on these differences in quantum computers, the design of the logical function acting on quantum bits (including the design of whether the quantum bits are used or not and the design of the efficiency of the use of each quantum bit) is the key to improving the computing performance of quantum computers, and requires special design. The above-mentioned design for quantum bits is a technical problem that ordinary computing devices do not need to consider or face. Based on this, in order to realize variable modular multiplication operations, variable modular addition operations, and variable double modular multiplication operations in quantum computing, this application proposes a variable modular multiplication operator, operation method and related devices, which aims to realize modular addition operations and double modular multiplication operations of input data and preset moduli in quantum computing, and then realize modular multiplication operations.

Referring to Fig. 2, Fig. 2 is a schematic diagram of the structure of a variable modulo adder based on constant addition and subtraction provided in an embodiment of the present application. The variable modulo adder 200 includes a first adder (QAdder) 210, a first constant subtractor (ΦSUB(N)) 220, a first CNOT gate 230 and a first controlled constant adder (ΦADD(N)) 240 which are cascaded in sequence, the constants in the first constant subtractor 220 and the first controlled constant adder 240 are both moduli, and the variable modulo adder 200 is used to calculate the result of the modulo addition operation of two input data to be added and the moduli.

If p represents the modulus, x and y represent two data to be added, and the value range of x and y is an integer between [0, p-1], then the modular addition operation is x+y mod p. The quantum states corresponding to the data to be added are encoded with n quantum bits, so the number of quantum bits required for the quantum circuit corresponding to the embodiment of the present application is 2n+2, where

Among them, the four input terminals 200a1, 200a2, 200a3, and 200a4 of the variable modular addition operator 200 are respectively connected to the three input terminals 210a1, 210a2, and 210a3 of the first adder 210 and one of the input terminals 230a1 of the first CNOT gate 230, and the four input terminals 200a1, 200a2, 200a3, and 200a4 of the variable modular addition operator 200 are used to input the quantum states corresponding to the two data to be added x and y, the initial calculation auxiliary data, and the initial comparison auxiliary data.

Among them, the quantum bits corresponding to the encoded initial calculation auxiliary data are used to assist in addition or subtraction calculations, and the quantum bits corresponding to the initial comparison auxiliary data are used to assist in comparison calculations.

It should be noted that the input items and output items corresponding to the input end and the output end can be quantum bits, the data is encoded in the quantum state of the quantum bit, and each quantum logic gate acts on the quantum bit to make the quantum state of the quantum bit evolve.

The initial calculation auxiliary data is 0, which is encoded by another auxiliary bit, and the auxiliary bit is used to assist in addition or subtraction calculations. The input items and output items corresponding to the input and output ends can be quantum bits, and the data is encoded on the quantum state of the quantum bit. Each quantum logic gate acts on the quantum bit to make the quantum state of the quantum bit evolve.

As shown in Figure 2, both x and y are encoded with n quantum bits to obtain the quantum state |x> corresponding to the data to be added x and the quantum state |y> corresponding to the data to be added y, and then |x> is used as the input item of input terminal 200a1, and |y> is used as the input item of input terminal 200a2.

The initial calculation auxiliary data and the initial comparison auxiliary data may be, for example, 0 or other values, which are not limited here. In an embodiment of the present invention, the initial calculation auxiliary data and the initial comparison auxiliary data are both set to 0, encoded with one quantum bit, and the encoded |0> is used as the input item of the input terminals 200a3 and 200a4.

Optionally, one of the output terminals 210b1 of the first adder 210 is connected to the input terminal 220a of the first constant subtractor 220, the output terminal 220b of the first constant subtractor 220 is connected to the other input terminal 230a2 of the first CNOT gate 230, and the two output terminals 230b1 and 230b2 of the first CNOT gate 230 are connected to the two input terminals 240a1 and 240a2 of the first controlled constant adder 240.

In a possible embodiment, the output terminal 220b of the first constant subtractor 220 includes a data output terminal 220bm and a sign output terminal 220bn, one of the input terminals 240a2 of the first controlled constant adder 240 includes a data input terminal 240a2m and a sign input terminal 240a2n, the sign output terminal 220bn of the first constant subtractor 220 is connected to the other input terminal 230a2 of the first CNOT gate 230, and one of the output terminals 230b2 of the first CNOT gate 230 is connected to the sign input terminal 240a2n of the first controlled constant adder 240.

In a possible embodiment, the two output terminals 240b1 and 240b2 of the first controlled constant adder 240 are respectively used to output the quantum state corresponding to the analog addition operation result and the intermediate comparison auxiliary data, and the other two output terminals 210b2 and 210b3 of the first adder 210 are used to output the quantum state corresponding to one of the data to be added and the intermediate calculation auxiliary data.

In one embodiment of the present application, the four output terminals 200b1, 200b2, 200b3 and 200b4 of the variable modulo adder 200 are respectively connected to the two output terminals 240b1, 240b2 of the first controlled constant adder 240 and the other output terminals 210b2, 210b3 of the first adder 210.

Assuming that the output of the previous variable double modular multiplication operator is |z>, the specific principle is:

The quantum state |y>|z>|0> is evolved into |y>|y+z>|0> by the first adder 210, where the quantum bit corresponding to the encoding initial calculation auxiliary data is reset to |0> after assisting the first adder to perform the addition calculation;

The quantum state |y+z> passes through the first constant subtractor 220 and evolves into |y+z-p>.

If y+z-p＞0, the quantum bit corresponding to the sign bit is |0>, the first CNOT gate 230 will not be executed, the quantum state of the quantum bit used to encode the initial comparison auxiliary data 0 is still |0>, the first controlled constant adder 240 will not be executed, the quantum state corresponding to the data y to be added output by the output terminal 200b1 is |y>, the result of the modular addition operation output by the output terminal 200b2 is |y+z-p>, the quantum state corresponding to the intermediate calculation auxiliary data output by the output terminal 200b3 is |0>, and the quantum state corresponding to the intermediate comparison auxiliary data output by the output terminal 200b4 is |0>;

If y+z-p＜0, the quantum bit corresponding to the sign bit is |1>, the first CNOT gate 230 is executed, and the quantum state of the quantum bit used to encode the initial comparison auxiliary data 0 evolves to |1>, the first controlled constant adder 240 is also executed, and the output terminal 200b1 outputs the quantum state |y> corresponding to the data y to be added, and the modular addition operation result output by the output terminal 200b2 is |y+z>, the quantum state corresponding to the intermediate calculation auxiliary data output by the output terminal 200b3 is |0>, and the quantum state corresponding to the intermediate comparison auxiliary data output by the output terminal 200b4 is |1>.

It can be seen that for y+z-p＞0, the quantum bits corresponding to the initial comparison auxiliary data can be reused without resetting; for y+z-p＜0, the quantum bits corresponding to the initial comparison auxiliary data need to be reset before they can be reused, so an auxiliary data reset module needs to be introduced. However, whether x+y-N＞0 or x+y-N＜0, x+y mod N can be calculated.

Referring to Fig. 3, Fig. 3 is a schematic diagram of the structure of another variable modulo adder based on constant addition and subtraction provided in an embodiment of the present application. The variable modulo adder 200 in the controlled variable modulo adder includes a modulo addition operation module 200A and an auxiliary data reset module 200B cascaded in sequence, the modulo addition operation module 200A includes the first adder 210, the first constant subtractor 220, the first CNOT gate 230 and the first controlled constant adder 240, the modulo addition operation module 200A is used to calculate the modulo addition operation result and the intermediate comparison auxiliary data based on the input initial comparison auxiliary data and two data to be added, and the auxiliary data reset module 200B is used to reset the intermediate comparison auxiliary data to the initial comparison auxiliary data.

Among them, one of the two data to be added in the modular addition operation module 200A is y, and the other is the output of the previous variable double modular multiplication operator. The initial comparison auxiliary data is 0 and is encoded by an auxiliary bit, which is used to assist in comparison calculation.

For example, for the 0th analog addition operation module, the initial comparison auxiliary data is 0, and the two data to be added are y and 0; for the 1st analog addition operation module, the initial comparison auxiliary data is still 0, and the two data to be added are y and 2(x_(n-1)y mod p). The inputs of the remaining analog addition operation modules can be inferred based on the formula in the previous embodiment, and will not be repeated here.

The intermediate comparison auxiliary data is evolved from the initial comparison auxiliary data, and may be 0 or 1. If it is different from the initial comparison auxiliary data, it needs to be reset by the auxiliary data reset module 200B.

Referring to FIG. 4 , FIG. 4 is a schematic diagram of the structure of an auxiliary data reset module provided in an embodiment of the present application. The auxiliary data reset module 200B includes a subtractor 250 (QSubtractor), a first inverter 260, a second CONT gate 270, a second inverter 280, and a second adder 290, which are cascaded in sequence. The four input terminals 200c1, 200c2, 200c3, and 200c4 of the auxiliary data reset module 200B are respectively connected to the three input terminals 250a1, 250a2, and 250a3 of the subtractor 250 and one of the second CNOT gates 270. Input terminal 270a1 is connected.

Among them, the three output terminals 250b1, 250b2, and 250b3 of the subtractor 250 are respectively connected to the input terminal 260a of the first NOT gate 260 and two input terminals 290a2 and 290a3 of the second adder 290, the output terminal 260b of the first NOT gate 260 is connected to the other input terminal 270a2 of the second CNOT gate 270, the other output terminal 270b1 of the second CNOT gate 270 is connected to the input terminal 280a of the second NOT gate 280, and the output terminal 280b of the second NOT gate 280 is connected to the other input terminal 290a1 of the second adder 290.

Among them, one of the output terminals 250b1 of the subtractor 250 includes a data output terminal 250b1m and a sign output terminal 250b1n, another input terminal 290a1 of the second adder 290 includes a data input terminal 290a1m and a sign input terminal 290a1n, the sign output terminal 250b1n of the subtractor 250 is connected to the input terminal 260a of the first NOT gate 260, and the output terminal 280b of the second NOT gate 280 is connected to the sign input terminal 290a1n of the second adder 290.

Among them, the four output ends 200d1, 200d2, 200d3, and 200d4 of the auxiliary data reset module 200B are respectively connected to the three output ends 290b1, 290b2, and 290b3 of the second adder 290 and one of the output ends 270b2 of the second CONT gate 270, and the three output ends 290b1, 290b2, and 290b3 of the second adder 290 are used to output the analog addition operation result, one of the data to be added and the quantum state corresponding to the initial calculation auxiliary data, and one of the output ends 270b2 of the second CONT gate 270 is used to output the quantum state corresponding to the initial comparison auxiliary data.

The specific principles are:

If y+z-p＞0, the quantum state |y+z-p> passes through the subtractor 250 and evolves to |y-p>; then passes through the first NOT gate 260, the quantum state |y-p> evolves to |p-y>; p-y＞0, the control bit of the second CNOT gate 270 is |0>, and the second CNOT gate 270 will not be executed; then passes through the second NOT gate 280, the quantum state |p-y> evolves to |y-p>; finally passes through the second adder 290, the quantum state |y-p> evolves to |y+z-p>, that is, the output of the output terminal 200d1 is |y+z-p>, and at the same time, the other quantum states remain unchanged, and the outputs of the output terminals 200d2, 200d3, and 200d4 are |y>, |0>, and |0> respectively;

If y+z-p＜0, the quantum state |y+z> passes through the subtractor 250 and evolves to |y>; then passes through the first NOT gate 260, the quantum state |y> evolves to |-y>; -y＜0, the control bit of the second CNOT gate 270 is |1>, the second CNOT gate 270 will be executed, and after the second CNOT gate 270, the quantum state |1> and the quantum state |-y> corresponding to the intermediate comparison auxiliary data evolve to |0> and |-y> respectively, where the quantum state |1> corresponding to the intermediate comparison auxiliary data is reset to |0>; then passes through the second NOT gate 280, the quantum state |-y> evolves to |y>; finally passes through the second adder 290, the quantum state |y> evolves to |y+z>, that is, the output terminal 200d1 outputs |y+z>, and at the same time, the other quantum states remain unchanged, and the output terminals 200d2, 200d3, and 200d4 output |y>, |0>, and |0> respectively.

It can be seen that the embodiment of the present application resets the auxiliary comparison bit so that the reset auxiliary comparison bit can be used for other calculations, saving computing resources; at the same time, after the embodiment of the present application resets the auxiliary comparison bit, it can be used for inversion to realize variable subtraction and modular addition operations.

It should be noted that the subtractor in the embodiment of the present application can be obtained by inverting the quantum circuit corresponding to the adder. Specifically, the first adder and the second adder can be implemented through the adder interface QAdderIgnorecarry() in QPanda, and the subtractor can be implemented through QAdderIgnorecarry()dagger().

Similarly, the constant subtractor can be obtained by inverting the quantum circuit corresponding to the constant adder. Specifically, the constant subtractor and the quantum circuit affected by Controlled constant addition can be implemented through the adder in the Chinese patent document with application number "202211114262.1" and application name "Constant adder, operation method and related device based on quantum Fourier transform".

Among them, the adder and subtractor can realize the addition and subtraction of any two input data, while the constant adder and constant subtractor can only realize the addition and subtraction of any one input data and the constant encoded in the constant adder and constant subtractor.

Of course, in addition to the specific implementation methods provided above, the adder, subtractor, constant adder, and constant subtractor in the embodiments of the present application may also have other implementation methods, which are not limited here.

Referring to FIG5 , FIG5 is a flow chart of a variable modular addition operation method based on constant addition and subtraction provided in an embodiment of the present application. The method comprises:

Step 501, obtaining a variable modulo addition operator and two data to be added as in the above embodiment;

Step 502, inputting two data to be added into a variable modular addition operator, and running the variable modular addition operator to obtain a quantum state corresponding to a modular addition operation result of the two data to be added and the modulus;

Step 503, determining the result of the modular addition operation based on the quantum state corresponding to the result of the modular addition operation.

Applying the above embodiment, the variable modulo adder includes a first adder, a first constant subtractor, a first CNOT gate and a first controlled constant adder which are cascaded in sequence, the constants in the first constant subtractor and the first controlled constant adder are moduli, and the variable modulo adder is used to calculate the modulo addition result of two input data to be added and the modulus. For any two input data to be added, the modulo addition result of the two data and the modulus preset in the variable modulo adder can be calculated.

Referring to Fig. 6, Fig. 6 is a schematic diagram of the structure of a variable double modular multiplication operator provided in an embodiment of the present application. The variable double modular multiplication operator 300 includes a double operation module 310 and a modulus operation module 320 which are cascaded in sequence, the constant in the modulus operation module 320 includes the modulus, the double operation module 310 is used to determine the double of the input data to be multiplied, and the modulus operation module 320 is used to calculate the modulus operation result of the double of the data to be multiplied and the modulus.

The input and output of the variable double modular multiplication operator 300, double operation module 310 and modular operation module 320 are all quantum bits, and the classical data is encoded into the quantum state of the quantum bit, and the encoding method can be angle encoding, amplitude encoding, ground state encoding, etc. The double operation module 310 and the modular operation module 320 can include quantum logic gates, which act on the quantum state to make the quantum state evolve.

The data to be multiplied is k, for example, for the 0th variable double modular multiplication operator 300, k= _xn-1y mod p, for the 1st variable double modular multiplication operator 300, k= _xn-2y +2( _xn-1y mod p)mod p, and the inputs of the remaining modular addition operation modules can be inferred according to the formulas in the previous embodiment, which will not be repeated here.

For example, the data k to be multiplied is encoded into the quantum state |k> of the quantum bit, and then used as the input of the variable double modular multiplication operator, that is, the input of the double operation module 310; after the action of the double operation module 310, the quantum state evolves into |2k>, and then inputs into the modular operation module 320, and after the action evolution, |2k mod p> is obtained, that is, the output of the variable double modular multiplication operator 300. Among them, p is the modulus; finally, |2k mod p> is converted into classical data, that is, the modular operation result 2k mod p of the double of the data k to be multiplied and the modulus p can be obtained.

The doubling operation module 310 includes one of the following operations: an operation of staggered storage of data, an adder, and a SWAP gate.

For example, data is encoded by n+1 quantum bits, in binary k=|k ₀ >|k ₁ >···|k _n-1 >, then 2k=|0>|k ₀ >|k ₁ >···|k _n-1 >.

Perform a staggered storage operation on the data, that is, skip the 0th quantum bit and directly store k ₀ on the 1st quantum bit, store k ₁ on the 2nd quantum bit, ..., store k _n-1 on the nth quantum bit, and finally obtain |0>|k ₀ >|k ₁ >···|k _n-1 >;

Alternatively, k and k may be added by an adder to finally obtain |0>|k ₀ >|k ₁ >···|k _n-1 >;

It is also possible to store the first n quantum bits as |k ₀ >|k ₁ >···|k _n-1 >, and store |0> in the last quantum bit. Through n SWAP gates, the |0> stored in the last quantum bit is shifted to the 0th quantum bit, and the |k ₀ > on the 0th quantum bit is shifted to the 1st quantum bit,..., and the |k _n-1 > on the n-2th quantum bit is shifted to the last quantum bit. Finally, |0>|k ₀ >|k ₁ >···|k _n-1 > can be obtained.

Referring to Fig. 7, Fig. 7 is a schematic diagram of the structure of another variable double modular multiplication operator provided in an embodiment of the present application. One of the input terminals 300a1 of the variable double modular multiplication operator 300 is connected to the input terminal 310a of the double operation module 310, the output terminal 310b of the double operation module 310 is connected to one of the input terminals 320a1 of the modular operation module 320, another input terminal 300a2 of the variable double modular multiplication operator 300 is connected to another input terminal 320a2 of the modular operation module 320, one of the input terminals 300a1 of the variable double modular multiplication operator 300 is used to input the quantum state corresponding to the data to be multiplied, and another input terminal 300a2 of the variable double modular multiplication operator 300 is used to input the quantum state corresponding to the initial auxiliary data. One output terminal 300b1 of the variable double modular multiplication operator 300 is connected to the output terminal 320b1 of the modular operation module 320, and the other output terminal 300b2 of the variable double modular multiplication operator 300 is connected to the output terminal 320b2 of the modular operation module 320.

Among them, the quantum state corresponding to the initial auxiliary data is |0>, which is encoded by the auxiliary bit.

Referring to Fig. 8, Fig. 8 is a schematic diagram of the structure of a modulus operation module provided in an embodiment of the present application. The modulus operation module 320 includes a cascaded first operator module 320A and a second operator module 320B, wherein the first operator module 320A is used to evolve the quantum state corresponding to the data to be multiplied and the quantum state corresponding to the initial auxiliary data into a modulus operation result of twice the data to be multiplied and the modulus, and the second operator module 320B is used to reset the intermediate auxiliary data to the initial auxiliary data.

Among them, referring to Figure 9, Figure 9 is a structural schematic diagram of another modulus operation module provided in an embodiment of the present application, the first operation submodule 320A includes a second constant subtractor 321, a third CNOT gate 322 and a second controlled constant adder 323 which are cascaded in sequence, and the constants in the second constant subtractor 321 and the second controlled constant adder 323 are the modulus p.

Among them, the output terminal 321b of the second constant subtractor 321 includes a data output terminal 321bm and a sign output terminal 321bn, one of the input terminals 323a1 of the second controlled constant adder 323 includes a data input terminal 323a1m and a sign input terminal 323a1n, the data output terminal 321bm of the second constant subtractor 321 is connected to the data input terminal 323a1m of the second controlled constant adder 323, the sign output terminal 321bn of the second constant subtractor 321 is connected to one of the input terminals 322a1 of the third CNOT gate 322, and the two output terminals 322b1 and 322b2 of the third CNOT gate 322 are respectively connected to the sign input terminal 323a1n and the other input terminal 323a2 of the second controlled constant adder 323.

Among them, the two output terminals 323b1 and 323b2 of the second controlled constant adder 323 are respectively used to output the quantum state |2k mod p> corresponding to the modulus operation result of twice the data to be multiplied and the modulus and the quantum state corresponding to the intermediate auxiliary data.

The two output terminals 323b1 and 323b2 of the second controlled constant adder 323 are connected to the two output terminals 300b1 and 300b2 of the variable double modular multiplication operator 300 respectively.

In some embodiments of the present application, the initial auxiliary data is 0, and the corresponding quantum state is |0>. After the second constant subtractor 321, the quantum state evolves to |2k-p>, and then the third CNOT gate 322 compares the size of 2k and p.

If 2k≥p, the quantum state of the quantum bit used to represent the 2k-p symbol is |0>, the third CNOT gate 322 and the second controlled constant adder 323 will not be executed, the quantum state corresponding to the modulus operation result of the output double of the data to be multiplied and the modulus is |2k-p>, and the quantum state corresponding to the intermediate auxiliary data is |0>;

On the contrary, if 2k＜p, the quantum state of the quantum bit used to represent the 2k-p symbol is |1>, the third CNOT gate 322 and the second controlled constant adder 323 will both be executed, and the quantum state corresponding to the modulus operation result of the output double of the data to be multiplied and the modulus is |2k>, and the quantum state corresponding to the intermediate auxiliary data is |1>.

It can be seen that in the design of the quantum circuit in the embodiment of the present application, 2k mod p can be calculated regardless of whether 2k is greater than or equal to or less than p. However, if 2k is less than p, the quantum state of the auxiliary bit used to encode the initial auxiliary data will evolve from |0> to |1>, resulting in the inability to reuse the quantum bit for subsequent other calculations.

In order to solve the above problem that the auxiliary bits used to encode the initial auxiliary data cannot be reused, it is necessary to introduce the second operation submodule 320B.

Still referring to Figure 8, the second sub-operation module 320B includes a third NOT gate 324, a fourth CNOT gate 325 and a fourth NOT gate 326 which are cascaded in sequence, one of the output terminals 323b1 of the second controlled constant adder 323 includes a low-order output terminal 323b1m and a non-low-order output terminal 323b1n, the low-order output terminal 323b1m of the second controlled constant adder 323 is connected to the input terminal 324a of the third NOT gate 324, and the other output terminal 323b2 of the second controlled constant adder 323 is connected to one of the input terminals 325a1 of the fourth CNOT gate 325.

The output terminal 324 b of the third NOT gate 324 is connected to the other input terminal 325 a 2 of the fourth CNOT gate 325 , and the other output terminal 325 b 2 of the fourth CNOT gate 325 is connected to the input terminal 326 a of the fourth NOT gate 326 .

Among them, the output end 326b of the fourth NOT gate 326 and the non-low-order output end 323b1n of the second controlled constant adder 323 are used to output the quantum state corresponding to the modulus operation result of twice the data to be multiplied and the modulus, and one of the output ends 325b1 of the fourth CNOT gate 325 is used to output the quantum state corresponding to the initial auxiliary data.

Among them, the output end 326b of the fourth NOT gate 326 and the non-low-order output end 323b1n of the second controlled constant adder 323 are connected to one of the output ends 300b1 of the variable double modular multiplication operator 300, and one of the output ends 325b1 of the fourth CNOT gate 325 is connected to the other output end 300b2 of the variable double modular multiplication operator 300.

It can be seen that if 2k≥p, the output |2k-p> is an odd number, so the quantum state output by the low-order output terminal 323b1m is |1>, and the third NOT gate 324 evolves to |0> after the action, and the fourth CNOT gate 325 will not be executed. The fourth NOT gate 326 evolves to |1> again after the action. The quantum state corresponding to the modulus operation result of the double of the data to be multiplied and the modulus is still |2k-p>, and the quantum state corresponding to the auxiliary quantum bit is |0>;

If 2k＜p, the output |2k> is an even number, so the quantum state output by the low-order output terminal 323b1m is |0>, and the third NOT gate 324 evolves to |1>, and the fourth CNOT gate 325 will be executed, and the quantum state corresponding to the auxiliary bit is reset from |1> to |0>, and the fourth NOT gate 326 evolves the exchanged |1> to |0> again, so that the quantum state corresponding to the modulus operation result of the double of the data to be multiplied and the modulus is still |2k>, but the quantum state corresponding to the auxiliary bit is reset to |0>.

It can be seen that in the design of the quantum circuit in the embodiment of the present application, no matter 2k is greater than or equal to p or less than p, 2k mod p can be calculated, and the quantum state of the auxiliary bit used to encode the initial auxiliary data is also reset, which can be used for other calculations later.

The constant subtractor and controlled constant addition can be implemented by the adder in the Chinese patent document with application number "202211113262.1" and application name "Constant adder, operation method and related device based on quantum Fourier transform". There may also be other implementation methods, which are not limited here.

See Figure 10, which is a flow chart of a variable double modular multiplication method provided in an embodiment of the present application. The method includes:

Step 1001, obtaining the variable double modular multiplication operator and the data to be multiplied in the above embodiment;

Step 1002, inputting the data to be multiplied into a variable double modular multiplication operator, and running the variable double modular multiplication operator to obtain a quantum state corresponding to a modular operation result of twice the data to be multiplied and the modulus;

Step 1003, determining a modulus operation result of twice the data to be multiplied and the modulus based on the quantum state corresponding to the modulus operation result.

Applying the above embodiment, the variable double modular multiplication operator includes a double operation module and a modulus operation module cascaded in sequence, the constant in the modulus operation module includes a modulus, the double operation module is used to determine the double of the input data to be multiplied, and the modulus operation module is used to calculate the modulus operation result of the double of the data to be multiplied and the modulus. For the input data to be multiplied, its double can be calculated by the double operation module, and then the modulus operation module can calculate the modulus result of its double and the preset modulus.

Referring to Fig. 11, Fig. 11 is a schematic diagram of the structure of a variable modular multiplication operator provided in an embodiment of the present application. The variable modular multiplication operator 400 includes n controlled variable modular addition operators 200 and n-1 variable double modular multiplication operators 300 that are alternately cascaded, the constants in the controlled variable modular addition operators 200 and the variable double modular multiplication operators 300 include a modulus, and the variable modular multiplication operator 400 is used to calculate the modular multiplication result of two input data to be multiplied and the modulus.

The variable modular addition operator and variable double modular multiplication operator in this article can not only be used to form the above-mentioned variable modular multiplication operator, but can also be applied to other scenarios that require modular addition and double modular multiplication operations. Therefore, this article does not impose any restrictions on the above-mentioned variable modular multiplication operator.

The modulus p is a prime number, the data to be multiplied x, y∈[0, p-1], and the number of qubits used to encode x, y are

For binary

It can be seen that the modular multiplication operation of two input data to be multiplied and the preset modulus can be converted into modular addition operations of n controlled variables and n-1 variable double modular multiplication operations.

As shown in FIG11 , in the embodiment of the present application, the variable modular multiplication operator 400 includes 5 input items, and the input of one input item is the quantum state |x> corresponding to one of the data to be multiplied, and its binary corresponding quantum state |x _n-1 > is used to control whether to execute the variable modular addition operator 200, and the n-1-ith variable modular addition operator 200 is controlled by |x _i >. As shown in FIG11 , the n-1-ith variable modular addition operator The device 200 is controlled by |x ₀ > and |x ₁ >, and the inputs of the other three input items are the quantum states |y>, |0>, |0>, and |0> corresponding to the other data y to be multiplied. It can be seen from the above formula that x _n-1 y mod p can be regarded as x _n-1 y+0mod p, so the n quantum bits corresponding to one |0> are used as data bits for calculation, and the other two quantum bits corresponding to |0> are used as auxiliary bits for calculation. Finally, the five output items included in the variable modular multiplication operator 400 are used to output |x>, |y>, |x·y mod p>, |0>, and |0> respectively.

Among them, n controlled variable modulo adders 200 are alternately cascaded with n-1 variable double modulo multipliers 300, that is, the output of the previous controlled variable modulo adder 200 is used as the input of the current variable double modulo multiplier 300, and the output of the current variable double modulo multiplier 300 and |y> are used as the input of the next controlled variable modulo adder. The input of the 0th controlled variable modulo adder 200 is |y> and |0>.

Referring to FIG. 12 , FIG. 12 is a flow chart of a variable modular multiplication operation method provided in an embodiment of the present application. The method comprises:

Step 1201, obtaining the variable modular multiplication operator and two data to be multiplied in the above embodiment;

Step 1202, inputting two data to be multiplied into a variable modular multiplication operator, and running the variable modular multiplication operator to obtain a quantum state corresponding to a modular multiplication operation result of the two data to be multiplied and the modulus;

Step 1203, determining the modular multiplication result of the two data to be multiplied and the modulus based on the quantum state corresponding to the modular multiplication result.

Applying the above embodiments, the variable modular multiplication operator provided in the present application includes n controlled variable modular addition operators and n-1 variable double modular multiplication operators that are alternately cascaded, and the constants in the controlled variable modular addition operator and the variable double modular multiplication operator include the modulus. By converting the modular multiplication operation into n controlled variable modular addition operations and n-1 variable double modular multiplication operations, the modular multiplication operation of two input data to be multiplied and the modulus is solved.

Referring to FIG. 13 , FIG. 13 is a schematic diagram of the structure of a variable modular addition operation device based on constant addition and subtraction according to an embodiment of the present application, wherein the device comprises:

An acquiring unit 1301 is used to acquire the variable modular addition operator and the two data to be added as described in the above embodiment;

The calculation unit 1302 is used to input the two data to be added into the variable modular addition operator, and run the variable modular addition operator to obtain a quantum state corresponding to the modular addition operation result of the two data to be added and the modulus;

The determination unit 1303 is used to determine the result of the modular addition operation based on the quantum state corresponding to the result of the modular addition operation.

The acquisition unit is further used to acquire the variable double modular multiplication operator and the data to be multiplied as described in the above embodiment;

The computing unit is further configured to input the data to be multiplied into the variable double modular multiplication operator, and to operate the variable double modular multiplication operator to obtain a quantum state corresponding to a modular operation result of twice the data to be multiplied and the modulus;

The determining unit is further used to determine a modulus operation result of twice the data to be multiplied and the modulus based on a quantum state corresponding to the modulus operation result.

The acquisition unit is further used to acquire the variable modular multiplication operator and two data to be multiplied as described in the above embodiment;

The computing unit is further used to input the two data to be multiplied into the variable modular multiplication operator, and to run the variable modular multiplication operator to obtain a quantum state corresponding to a modular multiplication operation result of the two data to be multiplied and the modulus;

The determining unit is further used to determine the modular multiplication result of the two data to be multiplied and the modulus based on the quantum state corresponding to the modular multiplication result.

Yet another embodiment of the present application provides a storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

Specifically, in this embodiment, the above storage medium may be configured to store a computer program for performing the following steps:

Obtain the variable modulo addition operator and the two data to be added described in the above embodiment;

Inputting the two data to be added into the variable modular addition operator, and running the variable modular addition operator to obtain a quantum state corresponding to a modular addition operation result of the two data to be added and the modulus;

The result of the modular addition operation is determined based on a quantum state corresponding to the result of the modular addition operation.

Specifically, in this embodiment, the above-mentioned storage medium may include but is not limited to: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, magnetic disk or optical disk and other media that can store computer programs.

Yet another embodiment of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

Specifically, the electronic device may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Specifically, in this embodiment, the processor may be configured to perform the following steps through a computer program:

Obtain the variable modulo addition operator and the two data to be added described in the above embodiment;

Inputting the two data to be added into the variable modular addition operator, and running the variable modular addition operator to obtain a quantum state corresponding to a modular addition operation result of the two data to be added and the modulus;

The result of the modular addition operation is determined based on a quantum state corresponding to the result of the modular addition operation.

The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.

Claims (29)

1. A variable modulo adder based on constant addition and subtraction, characterized in that the variable modulo adder includes a first adder, a first constant subtractor, a first CNOT gate and a first controlled constant adder which are cascaded in sequence, the constants in the first constant subtractor and the first controlled constant adder are both moduli, and the variable modulo adder is used to calculate the result of the modulo addition operation of two input data to be added and the moduli.
2. The variable modulo adder as claimed in claim 1, characterized in that the four input ends of the variable modulo adder are respectively connected to the three input ends of the first adder and one of the input ends of the first CNOT gate, and the four input ends of the variable modulo adder are used to input the quantum states corresponding to the two data to be added, the initial calculation auxiliary data and the initial comparison auxiliary data.
3. The variable modulo adder according to claim 2, characterized in that one of the output terminals of the first adder is connected to the input terminal of the first constant subtractor, the output terminal of the first constant subtractor is connected to the other input terminal of the first CNOT gate, and the two output terminals of the first CNOT gate are connected to the two input terminals of the first controlled constant adder.
4. The variable modulo adder according to claim 3 is characterized in that the output end of the first constant subtractor includes a data output end and a sign output end, one of the input ends of the first controlled constant adder includes a data input end and a sign input end, the sign output end of the first constant subtractor is connected to the other input end of the first CNOT gate, and one of the output ends of the first CNOT gate is connected to the sign input end of the first controlled constant adder.
5. The variable modular addition operator as described in claim 4 is characterized in that the two output ends of the first controlled constant adder are respectively used to output the quantum state corresponding to the modular addition operation result and the intermediate comparison auxiliary data, and the other two output ends of the first adder are used to output one of the quantum states corresponding to the data to be added and the intermediate calculation auxiliary data.
6. The variable modular adder according to any one of claims 1 to 5 is characterized in that the first adder, the first constant subtractor, the first CNOT gate and the first controlled constant adder are modular addition operation modules, and the modular addition operation module is used to calculate the modular addition operation result and the intermediate comparison auxiliary data based on the input initial comparison auxiliary data and two data to be added, and the variable modular adder also includes an auxiliary data reset module connected to the modular addition operation module, and the auxiliary data reset module is used to reset the intermediate comparison auxiliary data to the initial comparison auxiliary data.
7. The variable modulo addition operator as claimed in claim 6 is characterized in that the auxiliary data reset module includes a subtractor, a first NOT gate, a second CONT gate, a second NOT gate and a second adder cascaded in sequence, the four input ends of the auxiliary data reset module are respectively connected to the three input ends of the subtractor and one of the input ends of the second CNOT gate, the four output ends of the auxiliary data reset module are respectively connected to the three output ends of the second adder and one of the output ends of the second CONT gate, the three output ends of the second adder are used to output the modulo addition operation result, one of the data to be added and the quantum state corresponding to the initial calculation auxiliary data, and one of the output ends of the second CONT gate is used to output the quantum state corresponding to the initial comparison auxiliary data.
8. The variable modulo adder according to claim 7, characterized in that the three output ends of the subtractor are respectively connected to the input end of the first NOT gate and two of the input ends of the second adder, the output end of the first NOT gate is connected to the other input end of the second CNOT gate, and the other output end of the second CNOT gate is connected to the input end of the second NOT gate. The output end of the second NOT gate is connected to another input end of the second adder.
9. The variable modulo adder as described in claim 8 is characterized in that one of the output terminals of the subtractor includes a data output terminal and a sign output terminal, the other input terminal of the second adder includes a data input terminal and a sign input terminal, the sign output terminal of the subtractor is connected to the input terminal of the first NOT gate, and the output terminal of the second NOT gate is connected to the sign input terminal of the second adder.
10. The variable modulo adder as described in claim 5 is characterized in that the four output terminals of the variable modulo adder are respectively connected to the two output terminals of the first controlled constant adder and the other two output terminals of the first adder.
11. A variable double modular multiplication operator, characterized in that the variable double modular multiplication operator includes a double operation module and a modulus operation module cascaded in sequence, the constant in the modulus operation module includes a modulus, the double operation module is used to determine the double of the input data to be multiplied, and the modulus operation module is used to calculate the modulus operation result of the double of the data to be multiplied and the modulus.
12. The variable double modular multiplication operator as described in claim 11 is characterized in that the double operation module includes one of the following operations: an operation of staggered storage of data, an adder, and a SWAP gate.
13. The variable double modular multiplication operator as described in claim 11 or 12 is characterized in that one of the input ends of the variable double modular multiplication operator is connected to the input end of the double operation module, the output end of the double operation module is connected to one of the input ends of the modulus operation module, another input end of the variable double modular multiplication operator is connected to another input end of the modulus operation module, one of the input ends of the variable double modular multiplication operator is used to input the quantum state corresponding to the data to be multiplied, and the other input end of the variable double modular multiplication operator is used to input the quantum state corresponding to the initial auxiliary data.
14. The variable double modular multiplication operator as described in claim 13 is characterized in that the modular operation module includes a second constant subtractor, a third CNOT gate and a second controlled constant adder cascaded in sequence, and the constant in the second constant subtractor and the second controlled constant adder is the modulus.
15. The variable double modular multiplication operator as described in claim 13 is characterized in that the output end of the second constant subtractor includes a data output end and a sign output end, one of the input ends of the second controlled constant adder includes a data input end and a sign input end, the data output end of the second constant subtractor is connected to the data input end of the second controlled constant adder, the sign output end of the second constant subtractor is connected to one of the input ends of the third CNOT gate, and the two output ends of the third CNOT gate are respectively connected to the sign input end and the other input end of the second controlled constant adder.
16. The variable double modular multiplication operator as described in claim 15 is characterized in that the two output ends of the second controlled constant adder are respectively used to output the quantum state corresponding to the modular operation result of twice the data to be multiplied and the modulus and the quantum state corresponding to the intermediate auxiliary data.
17. The variable double modular multiplication operator as described in claim 16 is characterized in that the two output ends of the second controlled constant adder are respectively connected to the two output ends of the variable double modular multiplication operator.
18. The variable double modular multiplication operator as described in claim 17 is characterized in that the second constant subtractor, the third CNOT gate and the second controlled constant adder are a first operator module, and the modular operation module also includes a second operator module cascaded with the first operator module, and the second operator module is used to reset the intermediate auxiliary data to the initial auxiliary data.
19. The variable double modular multiplication operator as described in claim 18 is characterized in that the second sub-operation module includes a third NOT gate, a fourth CNOT gate and a fourth NOT gate cascaded in sequence, one of the output ends of the second controlled constant adder includes a low-order output end and a non-low-order output end, the low-order output end of the second controlled constant adder is connected to the input end of the third NOT gate, and the other output end of the second controlled constant adder is connected to one of the input ends of the fourth CNOT gate.
20. The variable double modular multiplication operator as described in claim 19 is characterized in that the output end of the third NOT gate is connected to the other input end of the fourth CNOT gate, and the other output end of the fourth CNOT gate is connected to the input end of the fourth NOT gate.
21. The variable double modular multiplication operator as described in claim 20 is characterized in that the output end of the fourth NOT gate and the non-low-order output end of the second controlled constant adder are used to output the quantum state corresponding to the modular operation result of twice the data to be multiplied and the modulus, and one of the output ends of the fourth CNOT gate is used to output the quantum state corresponding to the initial auxiliary data.
22. The variable double modular multiplication operator as described in claim 21 is characterized in that the output end of the fourth NOT gate and the non-low-order output end of the second controlled constant adder are connected to one of the output ends of the variable double modular multiplication operator, and one of the output ends of the fourth CNOT gate is connected to the other output end of the variable double modular multiplication operator.
23. A variable modular multiplication operator, characterized in that the variable modular multiplication operator includes n controlled variable modular addition operators as described in any one of the preceding claims 1-10 and n-1 variable double modular multiplication operators as described in any one of the preceding claims 11-22, which are alternately cascaded, the constants in the controlled variable modular addition operators and the variable double modular multiplication operators include modulos, and the variable modular multiplication operator is used to calculate the modular multiplication result of two input data to be multiplied and the modulus.
24. A variable modular addition operation method based on constant addition and subtraction, characterized in that the method comprises:

    Obtain the variable modular addition operator as described in any one of claims 1 to 10 and the two data to be added;

    Inputting the two data to be added into the variable modular addition operator, and running the variable modular addition operator to obtain a quantum state corresponding to a modular addition operation result of the two data to be added and the modulus;

    The result of the modular addition operation is determined based on a quantum state corresponding to the result of the modular addition operation.
25. A variable double modular multiplication operation method, characterized in that the method comprises:

    Obtain the variable double modular multiplication operator and the data to be multiplied as described in any one of claims 11 to 22;

    Inputting the data to be multiplied into the variable double modular multiplication operator, and running the variable double modular multiplication operator to obtain a quantum state corresponding to a modular operation result of twice the data to be multiplied and the modulus;

    The modulus operation result of twice the data to be multiplied and the modulus is determined based on the quantum state corresponding to the modulus operation result.
26. A variable modular multiplication operation method, characterized in that the method comprises:

    Obtain the variable modular multiplication operator as claimed in claim 23 and two data to be multiplied;

    Inputting the two data to be multiplied into the variable modular multiplication operator, and running the variable modular multiplication operator to obtain a quantum state corresponding to a modular multiplication operation result of the two data to be multiplied and the modulus;

    The modular multiplication result of the two data to be multiplied and the modulus is determined based on the quantum state corresponding to the modular multiplication result.
27. A variable modular addition operation device based on constant addition and subtraction, characterized in that the device comprises:

    An acquisition unit, used for acquiring the variable modular addition operator as claimed in any one of claims 1 to 10 and the two data to be added;

    A calculation unit, used for inputting the two data to be added into the variable modular addition operator, and running the variable modular addition operator to obtain a quantum state corresponding to a result of modular addition operation of the two data to be added and the modulus;

    A determination unit, configured to determine the result of the modular addition operation based on a quantum state corresponding to the result of the modular addition operation;

    The acquisition unit is further used to acquire the variable double modular multiplication operator and the data to be multiplied as described in any one of claims 11 to 22;

    The computing unit is further configured to input the data to be multiplied into the variable double modular multiplication operator, and to operate the variable double modular multiplication operator to obtain a quantum state corresponding to a modular operation result of twice the data to be multiplied and the modulus;

    The determining unit is further used to determine a modulus operation result of twice the data to be multiplied and the modulus based on the quantum state corresponding to the modulus operation result;

    The acquisition unit is further used to acquire the variable modular multiplication operator and two data to be multiplied as claimed in claim 23;

    The computing unit is further used to input the two data to be multiplied into the variable modular multiplication operator, and to run the variable modular multiplication operator to obtain a quantum state corresponding to a modular multiplication operation result of the two data to be multiplied and the modulus;

    The determining unit is further used to determine the modular multiplication result of the two data to be multiplied and the modulus based on the quantum state corresponding to the modular multiplication result.
28. A storage medium, characterized in that a computer program is stored in the storage medium, wherein the computer program is configured to execute the method described in any one of claims 24 to 26 when running.
29. An electronic device comprises a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in any one of claims 24 to 26.