WO2024109014A1

WO2024109014A1 - Bit-error test method and related device

Info

Publication number: WO2024109014A1
Application number: PCT/CN2023/102059
Authority: WO
Inventors: 李苏
Original assignee: 华为技术有限公司
Priority date: 2022-11-24
Filing date: 2023-06-25
Publication date: 2024-05-30
Also published as: CN118075066A

Abstract

Disclosed in the embodiments of the present application are a bit-error test method and a related device, which are used for reducing the probability of erroneous determination and reducing a bit error rate. The method in the embodiments of the present application comprises: acquiring a signal set, which comprises an initial EOB bit error signal; performing reverse bit error transmission starting from the initial EOB bit error signal, and determining an initial SOB bit error signal from the signal set, wherein in the signal set, the initial SOB bit error signal and signals between the initial SOB bit error signal and the initial EOB bit error signal are signals to be tested; respectively calculating a cumulative error from each signal to be tested to the initial EOB bit error signal, wherein the cumulative error is determined according to errors of any two adjacent signals between each signal to be tested and the initial EOB bit error signal; and according to the cumulative errors, determining whether there is a target SOB bit error signal among the signals to be tested.

Description

Error detection method and related equipment

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on November 24, 2022, with application number CN202211483137.8 and invention name “Error Detection Method and Related Equipment”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of communications, and in particular to a method for detecting bit errors and related equipment.

Background technique

In high-speed wired serial communication systems, as the data rate increases, the signal spectrum becomes wider and wider, but the channel bandwidth is limited, so the signal received by the receiver is not only affected by noise, but also by inter-symbol interference (ISI), which is not conducive to signal judgment and demodulation. How to eliminate inter-symbol interference has become an urgent problem to be solved.

After using decision feedback equalizer (DFE) + precoding, the burst error signal still has start of burst (SOB) error signal and end of burst (EOB) error signal. In the traditional method, when the EOB error signal is determined, the SOB error signal is determined based on the decision error of a single symbol.

In this method, the SOB error signal is determined based on the decision error of a single symbol. The determination basis is weak, resulting in a high probability of misjudgment.

Summary of the invention

The embodiment of the present application provides an error detection method and related equipment. In the error detection method, the initial EOB error signal is reversely transmitted. After the initial SOB error signal is determined, the cumulative error from each signal to be tested to the initial EOB error signal is calculated respectively, and the signal whose cumulative error meets the condition is determined from the signal to be tested as the target SOB error signal. The cumulative error of each signal to be tested is determined based on the error from the signal to be tested to any two adjacent signals in the initial EOB signal. That is to say, the technical solution of the present application is based on the sequence cumulative error, and the SOB error signal is determined, which enriches the determination basis, reduces the probability of misjudgment, and also reduces the bit error rate.

A first aspect of an embodiment of the present application provides a method for detecting a bit error, including:

A signal set is obtained, wherein the signal set includes an initial EOB error signal, and an initial SOB error signal can be determined according to the initial EOB error signal. The initial EOB error signal is used as a starting point, and reverse error transmission is performed to determine the initial SOB error signal from the signal set, and the initial SOB error signal is a possible SOB error signal. The signal set includes a signal to be tested, and the signal to be tested includes the initial SOB error signal and the signal between the initial SOB error signal and the initial EOB error signal. In other words, the signal from the initial SOB error signal to the previous signal of the initial EOB error signal is the signal to be tested. The cumulative error from each signal to be tested to the initial EOB error signal is calculated respectively, wherein the cumulative error is determined according to the error from each signal to be tested to any two adjacent signals in the initial EOB error signal. For example, there are 7 signals with sequence numbers 1 to 7, and signal No. 7 is the initial EOB error signal. After reverse error transmission, signal No. 2 is determined to be the initial SOB error signal, and then signals No. 2 to No. 6 are the signals to be tested. The cumulative error from signal No. 2 to the initial EOB error signal (signal No. 7) is the sum of the errors of any two adjacent signals from signal No. 2 to signal No. 7; the cumulative error from signal No. 3 to signal No. 7 is the sum of the errors of any two adjacent signals from signal No. 3 to signal No. 7. After the cumulative error of each signal to be tested is obtained, it is determined from the signal to be tested whether there is a target SOB error signal according to the cumulative error of each signal to be tested, and the target SOB error signal is a true SOB error signal.

It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

The initial EOB error signal is reversely transmitted. After the initial SOB error signal is determined, the cumulative error from each test signal to the initial EOB error signal is calculated respectively, and the signal whose cumulative error meets the condition is determined from the test signal as the target SOB error signal. The cumulative error of each test signal is determined based on the error between any two adjacent signals in the initial EOB signal from the test signal. That is to say, the technical solution of the present application is based on the sequence cumulative error to determine the SOB error signal, which enriches the determination basis, reduces the probability of misjudgment, and can reduce the error rate. At the same time, this method can also perform error detection on various types of channels, not limited to 1+D channels, and has good effects on other channels as well, which improves the generalization of the technical solution of the present application.

In a possible implementation of the first aspect, if there is a target test signal with the smallest cumulative error and less than a cumulative error threshold in the test signal, then the target test signal can be determined to be a target SOB error signal, where the cumulative error threshold is the error corresponding to the initial EOB error signal.

In the embodiment of the present application, the target SOB error signal is determined from the signal to be tested by comparing the accumulated error of the signal to be tested with the error threshold. It provides a basis for the implementation of the technical solution of this application and further improves the practicality and feasibility of the solution.

In a possible implementation of the first aspect, the accumulated error includes a reverse compensation error and a decision error. Error transmission may occur in the signal set during transmission. In the process of reverse error transmission starting from the initial EOB error signal, the error signal is compensated to make up for the error. In other words, the reverse compensation error is used to compensate the error signal. In addition, the decision error indicates the error before and after the signal decision.

In the embodiment of the present application, the cumulative error includes a reverse compensation error and a decision error, which can compensate and correct the error generated in the signal processing process, so that the calculation result of the cumulative error is more accurate, further improving the accuracy of error detection.

In a possible implementation of the first aspect, the specific process of determining the initial SOB error signal from the signal set includes: taking the initial EOB error signal as the starting point for reverse error transmission, when an abnormal level value appears, the next signal of the signal corresponding to the abnormal level value is considered to be the initial SOB error signal. Among them, the abnormal level value refers to a level value that will not appear in the normal signal transmission process (or, a level value greater than or less than the level extreme value). Exemplarily, taking 4-level pulse amplitude modulation (PAM-4) as an example, each symbol has 4 possible level values, such as {-3, -1, 1, 3}, then the level extreme value is ±3. In this case, a level value greater than +3 or less than -3 is an abnormal level value. Reverse error transmission of the PAM-4 signal specifically refers to taking a certain signal as the starting point and performing a +2, -2 or -2, +2 cyclic operation on the original decision result level. Assuming that signal No. 5 is the initial EOB error signal, reverse error transmission is carried out starting from signal No. 5, and an abnormal level value of -5 appears when it is transmitted to signal No. 1, then it can be determined that the next signal of signal No. 1 (i.e., signal No. 2) is the initial SOB error signal.

In the embodiment of the present application, the initial SOB error signal is determined by the abnormal level value appearing in the reverse error transmission process, which complies with the law of signal transmission, provides technical support for the implementation of the technical solution of the present application, and further improves the feasibility of the solution.

In a possible implementation manner of the first aspect, a first equalization result and a second equalization result may also be obtained. The first equalization result is obtained by equalizing a plurality of consecutive signals in a signal set based on a first equalization method, and the second equalization result is obtained by equalizing the plurality of consecutive signals based on a second equalization method, wherein the plurality of consecutive signals include a target signal. If the first equalization result is different from the second equalization result, it may be determined that the target signal is an initial EOB error signal.

In the embodiment of the present application, by combining the equalization results of multiple continuous signals with different equalization methods, a possible error signal is determined as an initial EOB error signal from the signal set, and as many EOB error signals as possible can be screened out. At the same time, by equalizing multiple continuous signals, the equalization result is more accurate compared to the method of only judging a single signal.

In a possible implementation manner of the first aspect, the multiple consecutive signals include a target signal and a signal preceding the target signal; or, a target signal and a signal following the target signal.

In the embodiments of the present application, there are multiple possibilities for equalizing continuous multiple signals using different equalization methods, which enriches the implementation methods and application scenarios of the technical solution of the present application, can be adapted to different needs, and improves the flexibility of the technical solution.

In a possible implementation of the first aspect, the initial EOB error signal may also be determined in other ways. A decision result and a decision error of a target signal in a signal set may be obtained. If the decision result is an extreme value corresponding to the signal set, and the absolute value of the decision error is greater than an error threshold, then the target signal may be determined to be an initial EOB error signal.

In the embodiment of the present application, whether the signal is an initial EOB error signal can be determined by the judgment result and judgment error of a single signal, and the process is simple and easy to implement. In addition, there are multiple ways to determine the initial EOB error signal, which further enriches the implementation method of the technical solution of the present application and improves the flexibility of the technical solution.

In a possible implementation of the first aspect, a decision error and a first decision result of a target signal in a signal set may be obtained. If the decision error is greater than or equal to the first threshold, the target signal is confirmed to be an initial EOB error signal; if the decision error is less than or equal to the second threshold, the target signal is confirmed not to be an initial EOB error signal; if the decision error is greater than the second threshold and less than the first threshold, a second stage determination is performed to confirm whether the target signal is an initial error signal. The second decision result of the target signal is determined according to the input signal and the equalization result corresponding to the next signal of the target signal. The third decision result and the fourth decision result of the previous signal of the target signal are obtained, the third decision result and the first decision result are based on the same decision method, and the second decision result and the fourth decision result are based on the same decision method. In the case where the decision error is greater than the second threshold and less than the first threshold, if the first decision result is the same as the second decision result, and the third decision result is different from the fourth decision result, the target signal is confirmed to be an initial EOB error signal; otherwise, the target signal is confirmed to be a non-initial EOB error signal.

In a possible implementation manner of the first aspect, if there is a target SOB error signal in the signal to be tested, then By determining that the initial EOB error signal is a correct EOB error signal, the target SOB error signal and the initial SOB error signal can be corrected.

In the embodiment of the present application, in addition to being able to perform bit error detection, the finally determined bit error signal can also be corrected, thereby ensuring the accuracy of signal transmission.

In a possible implementation of the first aspect, if the cumulative error corresponding to any one of the test signals is not less than the cumulative error threshold, that is, the error corresponding to the initial EOB error signal is the minimum error value, then it can be determined that there is no target SOB error signal in the test signal. Based on this, it is explained that the initial EOB error signal is a misjudgment, and the initial EOB error signal is actually a non-error signal.

In the embodiment of the present application, a signal that is misjudged as an EOB error signal can also be discovered, and the error can be corrected to avoid causing more errors, thereby further improving the accuracy of the technical solution of the present application.

A second aspect of an embodiment of the present application provides a method for detecting a bit error, including:

A first equalization result is obtained by equalizing a plurality of consecutive signals in the signal set based on a first equalization method, wherein the plurality of signals include a target signal. A second equalization result is obtained by equalizing the plurality of consecutive signals based on a second equalization method. If the first equalization result is different from the second equalization result, it is determined that the target signal is the initial EOB error signal.

In a possible implementation manner of the second aspect, the multiple consecutive signals include a target signal and a previous signal of the target signal; or, a target signal and a subsequent signal of the target signal.

A third aspect of an embodiment of the present application provides a bit error detection device, including:

The acquisition unit is used to perform the acquisition operation in the first aspect and any one of the implementations of the first aspect. The processing unit is used to perform operations other than the acquisition operation in the first aspect and any one of the implementations of the first aspect.

The beneficial effects shown in this aspect are similar to those in the first aspect and any implementation method of the first aspect, and will not be repeated here.

A fourth aspect of an embodiment of the present application provides a bit error detection device, including:

The acquisition unit is used to perform the acquisition operation in the second aspect and any one of the implementations of the second aspect. The processing unit is used to perform operations other than the acquisition operation in the second aspect and any one of the implementations of the second aspect.

The beneficial effects shown in this aspect are similar to those in the second aspect and any implementation method of the second aspect, and will not be repeated here.

In a fifth aspect, the present application provides a communication device, including a processor and a memory, wherein the processor stores instructions. When the instructions stored in the memory are executed on the processor, the method shown in the aforementioned first aspect and any possible implementation method of the first aspect or the aforementioned second aspect and any possible implementation method of the second aspect is implemented.

In a sixth aspect of the present application, a chip is provided, including a processing unit and a power supply circuit, the power supply circuit supplies power to the processing unit, and the processing unit is used to implement the method shown in the aforementioned first aspect and any possible implementation of the first aspect or the aforementioned second aspect and any possible implementation of the second aspect.

In the seventh aspect of the present application, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed on a processor, the method shown in the first aspect and any possible implementation of the first aspect or the second aspect and any possible implementation of the second aspect is implemented.

An eighth aspect of the present application provides a computer program product. When the computer program product is executed on a processor, it implements the method shown in the first aspect and any possible implementation of the first aspect or the second aspect and any possible implementation of the second aspect.

The beneficial effects shown in the fifth to eighth aspects are similar to the methods shown in the first aspect and any possible implementation of the first aspect or the aforementioned second aspect and any possible implementation of the second aspect, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing the effect of a precoding scheme;

FIG2 is a schematic diagram of a system architecture provided in an embodiment of the present application;

FIG3 is a schematic diagram of a flow chart of a method for detecting bit errors provided in an embodiment of the present application;

FIG4a is a signal processing block diagram of the error detection method provided in an embodiment of the present application;

FIG4b is a signal processing block diagram of the error detection method provided in an embodiment of the present application;

FIG5 is another schematic flow chart of the error detection method provided in an embodiment of the present application;

FIG6 is another signal processing block diagram of the error detection method provided in an embodiment of the present application;

FIG7 is another signal processing block diagram of the error detection method provided in an embodiment of the present application;

FIG8 is another signal processing block diagram of the error detection method provided in an embodiment of the present application;

FIG9 is another signal processing block diagram of the error detection method provided in an embodiment of the present application;

FIG10 is another signal processing block diagram of the error detection method provided in an embodiment of the present application;

FIG11 is a schematic diagram of a simulation result of the error detection method provided in an embodiment of the present application;

FIG12 is a schematic diagram of the structure of a bit error detection device provided in an embodiment of the present application;

FIG13 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application.

Detailed ways

The embodiments of the present application are described below in conjunction with the accompanying drawings. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged in appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attribute in the embodiments of the present application when describing. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment containing a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment. In addition, "at least one" refers to one or more, and "multiple" refers to two or more. "And/or", describes the association relationship of associated objects, indicating that three relationships can exist, for example, A and/or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, wherein A, B can be singular or plural. The character "/" generally represents that the associated objects before and after are a kind of "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or plural.

Inter-symbol interference (ISI) includes front-end ISI and back-end ISI. The feed-forward equalizer (FFE) can eliminate the front-end ISI and part of the back-end ISI, and the decision feedback equalizer (DFE) can eliminate the remaining back-end ISI. However, with the rapid development of high-speed wired serial communication links, the transmission rate is getting faster and faster, and the channel's ISI is getting bigger and bigger, which makes the DFE equalization coefficient larger. Correspondingly, the probability of error transmission is also getting bigger. In order to solve the error transmission problem of large coefficient DFE, the signal can be precoded, including 1/(1+D) encoding at the transmitter and 1/(1+D) decoding of the signal after DFE at the receiver.

After precoding, the burst errors caused by continuous DFE error transmission can be eliminated, but at the cost of adding a new error after the original error.

The following is an explanation with reference to a schematic diagram, and please refer to Figure 1, which is a schematic diagram of the effect of the precoding scheme. The precoding scheme refers to a DFE+precodingd scheme.

As shown in Figure 1, when the continuous error length of the signal after DFE processing is 1 (that is, no error transmission occurs), it will become two error signals after precoding. As shown in Figure 1, when the continuous error length of the signal after DFE processing is greater than 1 (that is, error transmission occurs), it will still become two error signals after precoding, and the number of errors is reduced. Generally, the first of a series of continuous burst errors is called the burst start bit SOB error signal, and the error signal added after precoding is called the burst end bit SOB error signal. EOB error signal.

The bit error detection method provided in the embodiment of the present application detects SOB and EOB on the basis of DFE+precoding and performs corrections to further reduce the bit error rate and improve the transmission efficiency.

Next, please refer to FIG. 2 , which is a schematic diagram of the system architecture provided in an embodiment of the present application.

The scenarios to which the embodiments of the present application are applied may include all high-speed wired serial links, acting on the communication equipment at the receiving end, and deployed in a serial interface chip (i.e., a SerDes chip). In some optional implementations, the error detection method provided by the implementation of the present application may act on a serializer/deserlizer (SerDes) chip at the receiving end. For example, as shown in Figure 2, any communication device A and communication device B are interconnected through a high-speed serial link via a serializer/deserializer.

It should be noted that, as a transmitting device, communication device A can be decoupled from the serial/deserializer as shown in FIG2, or coupled to the serial/deserializer, which is not limited here. The high-speed serial link used in the error detection method can be a link between chips or a link between a chip and an optical module. In addition, it can also be other types of high-speed serial links, such as a link between an optical module and a single board, which is not limited here.

Below, taking a serial interface chip coupled in a communication device and the communication device as an execution subject as an example, the error detection method provided in an embodiment of the present application is described in detail.

It is understandable that in the process of detecting the SOB error signal and the EOB error signal, the EOB error signal is usually detected first, and then the SOB error signal is determined according to the EOB error signal. For ease of description, the embodiments of the present application are also described in this order.

First, the process of detecting the EOB error signal is described. Please refer to Figure 3, which is a flow chart of the error detection method provided in the embodiment of the present application, including the following steps:

301. Obtain a first equalization result, where the first equalization result is obtained by equalizing a plurality of consecutive signals in a signal set based on a first equalization method, where the plurality of signals include a target signal.

The first equalization mode may be a normal adaptive DFE equalization mode, or a joint equalization mode, or other modes capable of equalizing a signal, which are not specifically limited here. The continuous multiple signals include a target signal and a signal before the target signal; or, a target signal and a signal after the target signal, which are not specifically limited here.

The first equalization result is obtained by processing a plurality of continuous signals in a first equalization mode. The equalization result can also be called a decision result. The so-called decision result refers to determining the level value corresponding to the signal as the standard level value closest to it. Taking the standard level value of PAM-4 as {-3, -1, 1, 3} as an example, if the level value of the current signal is 2.5, the level value of the signal will be determined as 3, which is closest to 2.5.

302. Obtain a second equalization result, where the second equalization result is obtained by equalizing a plurality of continuous signals based on a second equalization method.

The second equalization mode is different from the first equalization mode, and may also be a normal adaptive DFE equalization mode, or a joint equalization mode, or other modes capable of equalizing a signal, which are not specifically limited here.

303. If the first equalization result is different from the second equalization result, it is determined that the target signal is an initial EOB error signal.

If the first equalization result is different from the second equalization result, it can be considered that the target signal may be an EOB error signal, that is, the target signal is determined to be an initial EOB error signal. As for whether the initial EOB error signal is indeed an EOB error signal, it can be further confirmed in combination with the determination of the SOB error signal, which will be explained below.

It should be noted that the embodiment of the present application does not limit the order of step 301 and step 302. Step 301 may be performed first, or step 302 may be performed first, or step 301 and step 302 may be performed simultaneously. This is not limited here.

In the embodiment of the present application, by combining the equalization results of multiple continuous signals with different equalization methods, a possible error signal is determined as the initial EOB error signal from the signal set, and as many EOB error signals as possible can be screened out. At the same time, by equalizing multiple continuous signals, the equalization result is more accurate compared to the method of only judging a single signal. In addition, there are many possibilities for equalizing multiple continuous signals using different equalization methods, which enriches the implementation methods and application scenarios of the technical solution of the present application, can be applied to different needs, and improves the flexibility of the technical solution.

Exemplarily, taking the first equalization mode as a normal adaptive DFE equalization mode and the second equalization mode as a joint equalization mode as an example, and assuming that the signal acquired by the communication device is a PAM-4 signal and the standard level value is (-3, -1, 1, 3), and the consecutive multiple signals are the target signal and the previous signal of the target signal, the above process is further explained.

Please refer to FIG. 4 a , which is a signal processing block diagram of the error detection method provided in an embodiment of the present application.

As shown in Figure 4a, assuming that after a continuous time linear equalizer (CTLE) and After the equalization compensation of FFE, the residual ISI is only the first-order ISI (post-1 ISI). That is to say, in Figure 4a, y[n] represents the signal FFEout after FFE equalization, and FFEout has the first-order ISI. Then:
y[n]＝a[n]+h[1]a[n-1]+w[n]

Wherein, a[n] represents the precoded signal of the target signal x[n] sent by the transmitter, a[n-1] represents the precoded signal of the previous signal x[n-1] of the target signal, h[1] represents post-1 ISI, and w[n] represents Gaussian white noise.

In the signal processing block diagram shown in Figure 4a, the upper dotted box represents the processing circuit of the first-order DFE (1-tap DFE) equalization, and the lower dotted box represents the processing circuit of the joint decoding (JD) equalization, which are explained separately below.

As shown in the processing circuit of the first-order DFE equalization, the signal FFEout undergoes a conventional first-order DFE equalization to eliminate the post-1 ISI, and then the estimation result b[n] of the transmitted signal a[n] is obtained through judgment, that is, the Slicer _out signal in FIG4a.

The post-1 coefficient c of the DFE in the figure is adaptively and dynamically adjusted to the optimal value through the least mean square (LMS) algorithm. After a certain period of time, the coefficient c converges to the value of the post-1 ISI h[1], that is, c≈h[1]. Therefore, the input signal of the slicer-4 module can be expressed as:
y[n]-cb[n-1]＝a[n]+h[1]a[n-1]+w[n]-cb[n-1]
≈a[n]+c(a[n-1]-b[n-1])+w[n]

When the previous signal symbol is determined to be correct, that is, a[n-1]=b[n-1], y[n]-cb[n-1]=a[n]+w[n].

After the decision is made by the decision device, a[n] can be estimated correctly with a high probability.

When the previous signal symbol is judged to be wrong, that is, a[n-1]≠b[n-1], the error signal is represented by e[n]＝a[n-1]-b[n-1], then:
y[n]-cb[n-1]＝a[n]+ce[n]+w[n]

At this time, after the decision is made by the decision device, there is a high probability that an incorrect estimation result of a[n] will be obtained.

Because of the feedback mechanism of DFE, when continuous burst bit errors occur, the error signal e[n] always alternates between positive and negative. Therefore, when we add b[n] and b[n-1] together, the result different from a[n]+a[n-1] will appear only at SoB and EoB. This can be expressed by the following formula:

As shown in FIG4a , the output signal of the FFE (i.e., FFEout) also undergoes a joint decoding equalization process. Unlike the DFE decision on a[n], in the joint decoding, a[n]+a[n-1] is directly decided.

According to FIG4a, the output signal of the FFE (i.e., FFEout) is first delayed and superimposed, i.e.,
y[n]+(1-c)y[n-1]
=a[n]+h[1]a[n-1]+w[n]+(1-c)(a[n-1]+h[1]a[n-2]+w[n-1])
=a[n]+a[n-1]+c(1-c)a[n-2]+w[n]+(1-c)w[n-1]

Then subtract the a[n-2] off part from the delayed superimposed signal. The decision result of DFE is used here. therefore:

If the signal is directly subjected to a 7-level decision, the estimated result of the signal a[n]+a[n-1] can be obtained. The reason for using a 7-level decision device here is that, assuming that a[n] and a[n-1] are both PAM-4 signals, there are four level values (-3, -1, 1, 3). Then a[n]+a[n-1] has 7 possible level results (-6, -4, -2, 0, 2, 4, 6).

Because precoding is performed at the sending end, a[n] = (x[n] - a[n-1]) mod 4. After obtaining the estimated value of a[n] + a[n-1], only one more map & mod 4 operation (i.e. decoding operation) is required to obtain the estimated result of x[n], i.e.:

Therefore, the JD _out signal in FIG4 a is the restored result of the transmitting end signal x[n].

By comparing the estimation results of a[n]+a[n-1] of the two equalization methods, it is determined whether the signal x[n] corresponding to a[n] is the initial EoB error signal. Specifically, when the results obtained by the two equalization methods are the same, the current symbol (that is, the target signal x[n]) is determined not to be an EoB error signal, and EoBD signal = 0. When the results of the two equalization methods are different, the current symbol is determined to be a possible EoB error signal, that is, the initial EoB error signal.

Optionally, in the following description, it is set that when the joint decoding symbol level is smaller than the DFE equalization result symbol level, EoBD signal = -2, and when the joint decoding symbol level is larger than the DFE equalization result symbol level, EoBD signal = 2. EoBD signal is used to compensate for the level value in the reverse bit error transmission, which will be explained below and will not be repeated here.

It should be noted that the value of EoBD signal can also be opposite to the above definition, that is, when the joint decoding symbol level is smaller than the DFE equalization result symbol level, EoBD signal can be set to 2, and when the joint decoding symbol level is larger than the DFE equalization result symbol level, EoBD signal = -2. There is no specific limitation here. If the latter setting is adopted, the level value to be compensated needs to be adjusted accordingly when performing reverse bit error transmission.

As shown in the example in Table 1 below, through calculation, we can find that the result of normal DFE equalization and the result of joint decoding are different at the 7th symbol, so it can be determined that the signal corresponding to symbol 7 is the initial EOB error signal. The specific calculation results are shown in Table 1 below.

Table 1

It should be noted that the embodiment shown in FIG. 4 a is only an example of determining the initial EOB error signal based on two different equalization methods. In practical applications, the processing block diagram may also adopt other structures, which are not specifically limited here.

Exemplarily, as shown in Fig. 4b, based on the processing block diagram shown in Fig. 4a, a MOD4 module is added before the comparator, and the MOD4 module is used to perform a decoding operation. In this case, the output signals of the MOD4 module and the Map&MOD4 module are input to the comparator.

It should be noted that in the above description, PAM-4 is taken as an example. In practical applications, it can be widely applied to other types of signals, such as PAM-2, or PAM-6, etc., which are not specifically limited here. For example, assuming that a PAM-2 signal with a standard level value of (-1, +1) is processed, the Slicer-4 module in Figure 4a and Figure 4b needs to be modified to a Slicer-2 module, and the Slicer-7 module needs to be modified to a Slicer-3 module. This is because it is assumed that a[n] and a[n-1] are both PAM-2 signals with two level values (-1, 1). Then a[n]+a[n-1] has three possible level results (-2, 0, 2). Similarly, assuming that a PAM-6 signal with a standard level value of (±1, ±3, ±5) is processed, the Slicer-4 module in Figure 4a and Figure 4b needs to be modified to a Slicer-6 module, and the Slicer-7 module needs to be modified to a Slicer-11 module.

The above describes the process of determining the initial EOB bit error signal based on two different equalization methods. In practical applications, other methods may also be used to determine the initial EOB bit error signal.

In some optional implementations, the communication device may obtain a decision result and a decision error of a target signal in a signal set. If the decision result is an extreme value corresponding to the signal set and the absolute value of the decision error is greater than an error threshold, the target signal is determined to be an initial EOB error signal.

Among them, the extreme value refers to the limit level value corresponding to the signal set. If the decision result of the target signal is achieved by deciding a single signal, then the limit level value refers to the limit level value of the single signal, for example, the single limit level value corresponding to the PAM-4 signal with a standard level value of (±1, ±3) is ±3; if the decision result of the target signal is achieved by deciding multiple continuous signals, then the limit level value refers to the limit level values of multiple signals, for example, the limit level values of the two signals corresponding to the PAM-4 signal with a standard level value of (±1, ±3) are ±6.

Among them, the decision result of the target signal can be a result obtained according to the DFE equalization method (Slicer _out as shown in Figure 4a), or a decision result obtained based on other decision methods, such as a result obtained according to the joint coding equalization method (JD _out as shown in Figure 4a), which is not limited here.

The setting of the error threshold is related to the channel coefficient. Generally, the larger the channel coefficient, the larger the threshold. If the judgment error is greater than the error threshold, it means that the judgment error exceeds the error allowable range, and the signal is more likely to be an error signal. Since the judgment result is to determine the level value corresponding to the signal as the standard level value closest to it, after the error is transmitted to the extreme level value, the positive or negative direction offset caused by the error transmission will not affect the judgment result. In other words, the extreme level is the most likely EOB error signal. At the same time, the decision error is also combined to more accurately identify the EOB error signal.

In some optional implementations, the communication device may also determine the initial EOB error signal in the following manner. Taking the signal as PAM-4 as an example:

Assume that after equalization compensation by FFE, the remaining ISI is only first-order ISI (post-1 ISI). Let y[n] represent the signal input to FFE, then:
y[n]＝a[n]+h[1]a[n-1]+w[n]

After the conventional 1-Tap DFE equalizes y[n], we get:
y[n]-cb[n-1]＝a[n]+h[1]a[n-1]+w[n]-cb[n-1]
≈a[n]+c(a[n-1]-b[n-1])+w[n]

After the decision device, the decision result b[n]=slicer{y[n]-cb[n-1]} for a[n] is obtained.

The slicing error (Slicing Error) is: slicing error[n] = y[n]-cb[n-1]-b[n].

The first threshold (thershold ₁ ) and the second threshold (thershold ₂ ) are set and compared with the slicing error [n] to complete the first stage of determination. The first threshold is greater than the second threshold. The size of the threshold is related to the channel parameters. The thresholds of different channels can be the same or different, and are not limited here.

When slicing error[n]≥thershold ₁ , the nth symbol is determined as the initial EoB error signal.

When slicing error[n]≤thershold ₂ , the nth symbol is determined to be a non-initial EoB error signal.

When thershold ₂ ＜slicing error[n]＜thershold ₁ , a second stage determination is required to determine whether the nth symbol is an initial EOB error signal.

Specifically, for the signal y[n+1] received at the next moment and its conventional equalization result b[n+1], the following calculation can be performed:

After the decision maker, we can get another decision result b′[n] for a[n]:

The signal S[n] is defined as follows:

When thershold ₂ ＜slicing error[n]＜thershold ₁ , S[n-1] and S[n] are calculated. When S[n-1]＝0 and S[n]＝1, the nth symbol is determined to be an initial EoB error signal; otherwise, it is a non-initial EoB error signal.

Optionally, the definition of signal S[n] can be modified as follows:

Then, when thershold ₂ ＜slicing error[n]＜thershold ₁ , S[n-1] and S[n] are calculated, and when S[n-1]＝1 and S[n]＝0, the nth symbol is determined to be an initial EoB error signal; otherwise, it is a non-initial EoB error signal.

In general, when thershold ₂ < slicing error[n] < thershold ₁ , if b[n-1]≠b′[n-1] and b[n]=b′[n], the nth symbol can be determined to be an initial EOB error signal.

The process of detecting the SOB error signal is described below. Please refer to FIG5 , which is a flowchart of the error detection method provided in the embodiment of the present application, including the following steps:

501. Obtain a signal set, the signal set including an initial burst end bit (EOB) error signal.

The computing device can obtain a signal set, wherein the signal set includes an initial EOB error signal. The initial EOB error signal can be determined based on the method described above.

502. Perform reverse error transmission starting from the initial EOB error signal, determine the initial SOB error signal from the signal set, and the initial SOB error signal and the signal between the initial SOB error signal and the initial EOB error signal in the signal set are the signals to be tested.

The initial SOB error signal is used as the starting point for reverse error transmission to offset the error caused by the forward error transmission, and the initial SOB error signal is determined according to the level value after the directional error transmission. Specifically, the initial EOB error signal is used as the starting point for reverse error transmission. When an abnormal level value appears, the next signal of the signal corresponding to the abnormal level value is determined to be the initial SOB error signal. Among them, the abnormal level value refers to a level value that will not appear in the normal signal transmission process (or a level value greater than or less than the level extreme value). Exemplarily, taking the PAM-4 signal with a standard value of (-3, -1, 1, 3) as an example, the possible level value of each signal is one of the four types, and the level extreme value is ±3. In this case, a level value greater than +3 or less than -3 is an abnormal level value. Assuming that signal No. 5 is the initial EOB error signal, reverse error transmission is carried out starting from signal No. 5. When an abnormal level value -5 appears when it is transmitted to signal No. 1, the next signal of signal No. 1 (i.e., signal No. 2) can be determined as the initial SOB error signal.

The signal set includes the signal to be tested, and the signal to be tested includes the initial SOB error signal and the signal from the initial SOB error signal to the initial EOB error signal. In other words, starting from the initial SOB error signal to the signal before the initial EOB error signal, all are the signals to be tested. Exemplarily, assuming that there are 7 signals with sequence numbers 1 to 7, signal No. 7 is the initial EOB error signal, and after reverse error transmission, it is determined that signal No. 2 is the initial SOB error signal, then signals No. 2 to No. 6 are the signals to be tested.

503. Calculate the cumulative error from each signal to be tested to the initial EOB error signal respectively, where the cumulative error is determined based on the error between any two adjacent signals from each signal to be tested to the initial EOB error signal.

The accumulated error includes a reverse compensation error and a decision error. The reverse compensation error is used to compensate the error signal, and the decision error indicates the error before and after the decision signal.

Exemplarily, the cumulative error from signal No. 2 to the initial EOB error signal (signal No. 7) is the sum of the errors of any two adjacent signals from signal No. 2 to signal No. 7; the cumulative error from signal No. 3 to signal No. 7 is the sum of the errors of any two adjacent signals from signal No. 3 to signal No. 7.

504. According to the accumulated error, determine whether there is a target SOB error signal in the signal to be tested.

If there is a target test signal with the smallest cumulative error and less than the cumulative error threshold in the test signal, then it can be determined that the target test signal is a target SOB error signal. If the cumulative error corresponding to any test signal in the test signal is not less than the cumulative error threshold, then it can be determined that there is no target SOB error signal in the signal set. Among them, the cumulative error threshold is the error corresponding to the initial EOB error signal.

In the embodiment of the present application, by comparing the cumulative error of the signal to be tested with the error threshold, the target SOB error signal is determined from the signal to be tested, which provides an implementation basis for the technical solution of the present application and further improves the practicality and feasibility of the solution.

In some optional implementations, when it is determined that a target EOB error signal exists in the signal to be tested, the initial EOB error signal can be determined to be a correct EOB error signal, and the target EOB error signal and the initial SOB error signal can be corrected.

In some optional implementations, if the cumulative error corresponding to any of the test signals is not less than the cumulative error threshold, it means that the error corresponding to the initial EOB error signal is the minimum error value, and since a signal cannot be both an EOB error signal and an SOB error signal at the same time, it can be determined that there is no target SOB error signal in the test signal. Based on this, it is explained that the initial EOB error signal is a misjudgment, and the initial EOB error signal is actually a non-error signal.

In general, the embodiment of the present application performs reverse error transmission on the initial EOB error signal, and after determining the initial SOB error signal, the cumulative error from each signal to be tested to the initial EOB error signal is calculated respectively, and the signal whose cumulative error satisfies the condition is determined from the signal to be tested as the target SOB error signal. The cumulative error of each signal to be tested is determined based on the error from the signal to be tested to any two adjacent signals in the initial EOB signal, that is, the technical solution of the present application determines the SOB error signal based on the sequence cumulative error, enriches the determination basis, reduces the probability of misjudgment, and also reduces the error rate.

Next, the process of determining the target SOB error signal is further described in conjunction with the schematic diagram. Figures 6 to 10 are all signal processing block diagrams of the error detection method provided by the embodiments of the present application. Figures 6 to 10 are taken as an example that the signal is a PAM-4 signal and the standard level value is (-3, -1, 1, 3), and the ISI is considered to be a first-order ISI.

The output of the signal processing block diagram shown in FIG4a is used as the input of the signal processing block diagram shown in FIG6. After the initial EOB error signal is detected, as shown in FIG6, the judgment error sequence can be calculated according to the slicer _in and slicer _out signals and stored in the shift register. The SoB _init detection is completed according to the slicer _out and EoBD signals, and the reverse compensation error is generated according to the EoBD signal. The cumulative error of the short sequence is calculated, and then the target SOB error signal is determined based on the short sequence number with the smallest cumulative error, and the correction is performed. Among them, the SoB _init detection is to perform reverse error transmission.

As shown in FIG7 , the decision error sequence module calculates and uses a shift register to store the decision error. S[n] represents the decision error at the nth moment, and then:
S[n]＝silcer _in [n]-silcer _out [n]

The number of shift registers N can be selected as needed. When the probability of channel error transmission is high, N should be selected to obtain better performance; when the probability of channel error transmission is low, N can be selected to be small to save power. The register saves S _1:N [n] = {S[n], S[n]..., S[nN]} from left to right, a total of N moments of decision error values, which will be used to calculate the cumulative error later.

As shown in FIG8 , the SoB _init detection module first uses N shift registers to buffer the slicer _out signal, and detects whether there is an abnormal level value (i.e., +5 or -5 level) by reversely transmitting the bit error. If there is, the reverse transmission distance corresponding to the first +5 or -5 level is recorded as i ^* ; if not, let i ^* = N. SoB _init can be expressed as:
SoB _init =EOB-i ^* +1

For example, in the example in Table 1, after performing SoB _init detection, the results shown in Table 2 can be obtained. After 6 symbols are transmitted in the reverse direction, a -5 level is detected. That is, an abnormal level value is detected at symbol 1, and it can be determined that the initial EOB error signal is the signal corresponding to the next symbol of symbol 1 (i.e., symbol 2). Therefore, i ^* = 6, SoB _init = EOB-i ^* + 1 = 7-6+1 = 2. This shows that the real SoB error signal is between symbol 2 and symbol 6.

Table 2

As shown in FIG9 , the reverse compensation error generation module generates corresponding compensation signals e ₀ [n], e ₁ [n], e ₂ [n] according to the EoBD Signal and stores them in three registers.
e ₀ [n] = ES
e ₁ [n] = c × ES
_e2 [n]＝(1-c)×ES

As shown in FIG10 , the sequence cumulative error module needs to calculate the soft decision cumulative error based on the reverse compensation error e ₀ [n], e ₁ [n], e ₂ [n] and the decision error sequence S _1:N [n]. A total of i ^* cumulative errors need to be calculated, which are:

Where M _j [ni] is the sign after reverse transfer compensation and satisfies:

It should be noted that M _j [ni] is only used as an intermediate variable in theoretical derivation and is not required in actual implementation. Substituting M _j [ni] into ε _j [n], we can calculate:

For the case of j ≥ 3, we have:

It should be noted that, as shown in FIG10 , the signal e ₂ =e ₀ +e ₁ .

Then select the short sequence j ^* = _armminjεj [n] _with the minimum cumulative error, then SoB=EoB-j ^* , where SoB refers to the symbol number corresponding to the signal.

When j ^* ≥ 1, the corresponding SoB signal is corrected:

When j ^* ≥0, that is, the first short sequence has the smallest soft decision cumulative error, then SoB＝EoB. Then the initial EOB error signal is considered to be a misjudgment, and there is no EOB error signal in the signal set.

It should be noted that, in the embodiment shown in FIG. 6 , correction is performed on the signal corresponding to JD _out . In practical applications, JD _out may also be replaced by slicer _out , which is not limited here.

For example, assuming that the corresponding short sequence cumulative error calculation is performed on the examples in Table 1 and Table 2, the results shown in Table 3 below can be obtained. As shown in Table 3, since EoB = 7, and ε ₄ [7] is the smallest, then j ^* = 4, and SoB = 7-4 = 3. In other words, the signal corresponding to symbol 3 is determined to be the target SOB error signal. Then, JD _out [3] can be corrected to obtain the correct symbol x [3]:
JD _out [3] = [1-1] mod 4 = 0 = x [3]

table 3

Based on the implementations shown in FIG. 3 to FIG. 10 , FIG. 11 shows the simulation results of the bit error rate. The simulation model only considers the channel model of the first-order ISIh(1) and Gaussian white noise. The horizontal axis represents different channel ISI values, represented by alpha (the maximum value is 1). The vertical axis It represents the bit error rate (SER) of the PAM-4 symbol.

As shown in Figure 11, DFE means that only DFE is used for equalization, DFE+PreC means the result of DFE and Precoding, DFE+PreC+EoBD means the result of applying the existing EoBD after DFE and Precoding, and MLSE+Precoding is the result of applying MLSE equalization and then adding precoding. The results of the implementation methods shown in Figures 3 to 10 are expressed as SoBD SSE. The simulation results show that the implementation methods shown in Figures 3 to 10 can effectively reduce the bit error rate compared to EoBD. When the Alpha value is large, the bit error rate can be close to that of MLSE+Precoding. At the same time, the implementation complexity and power consumption of the implementation methods shown in Figures 3 to 10 are much smaller than MLSE+Precoding. In other words, the bit error detection method provided in the embodiments of the present application greatly improves the detection accuracy while reducing the complexity and power consumption.

Next, the related equipment provided in the embodiments of the present application is described.

Please refer to FIG. 12 , which is a schematic diagram of a bit error detection device provided in an embodiment of the present application.

As shown in FIG12 , the bit error detection device 1200 includes:

The acquisition unit 1201 is used to execute the acquisition operation performed by the communication device in the embodiments shown in Figures 2 to 8 above.

The processing unit 1202 is used to perform operations other than the acquisition operations performed by the communication device in the embodiments shown in Figures 2 to 8 above.

In some optional implementations, the acquisition unit 1201 is used to acquire a signal set, where the signal set includes an initial EOB error signal.

The processing unit 1202 is used to perform reverse error transmission starting from the initial EOB error signal, determine the initial SOB error signal from the signal set, and the initial SOB error signal and the signal between the initial SOB error signal and the initial EOB error signal in the signal set are the test signals. The cumulative error from each test signal to the initial EOB error signal is calculated respectively, and the cumulative error is determined based on the error from each test signal to any two adjacent signals in the initial EOB error signal. According to the cumulative error, it is determined whether there is a target SOB error signal from the test signal.

In some optional embodiments, the processing unit 1202 is specifically used to determine that the target test signal is a target SOB error signal if there is a target test signal with the smallest cumulative error and less than a cumulative error threshold in the test signal, and the cumulative error threshold is the error corresponding to the initial EOB error signal.

In some optional implementations, the accumulated error includes a reverse compensation error and a decision error, the reverse compensation error is used to compensate the error signal, and the decision error indicates the error before and after the decision of the signal.

In some optional implementations, the processing unit 1202 is specifically configured to perform reverse error transmission starting from the initial EOB error signal, and when an abnormal level value appears, determine that the next signal of the signal corresponding to the abnormal level value is the initial SOB error signal.

In some optional implementations, the acquisition unit 1201 is further configured to acquire a first equalization result, where the first equalization result is obtained by equalizing a plurality of consecutive signals in the signal set based on the first equalization method, where the plurality of signals include the target signal, and to acquire a second equalization result, where the second equalization result is obtained by equalizing a plurality of consecutive signals based on the second equalization method.

The processing unit 1202 is further configured to determine that the target signal is an initial EOB error signal if the first equalization result is different from the second equalization result.

In some optional implementations, the continuous plurality of signals include: a target signal and a signal preceding the target signal; or, a target signal and a signal following the target signal.

In some optional implementations, the acquisition unit 1201 is further configured to acquire a decision result and a decision error of a target signal in a signal set.

The processing unit 1202 is further configured to determine that the target signal is an initial EOB error signal if the judgment result is an extreme value corresponding to the signal set and the absolute value of the judgment error is greater than the error threshold.

In some optional implementations, the acquisition unit 1201 is further configured to acquire a decision error and a first decision result of a target signal in a signal set.

The processing unit 1202 is also used to confirm that the target signal is an initial EOB error signal if the decision error is greater than or equal to the first threshold; if the decision error is less than or equal to the second threshold, confirm that the target signal is not an initial EOB error signal; if the decision error is greater than the second threshold and less than the first threshold, then perform a second stage judgment to confirm whether the target signal is an initial error signal. Determine the second decision result of the target signal according to the input signal and the equalization result corresponding to the next signal of the target signal. Obtain the third decision result and the fourth decision result of the previous signal of the target signal, the third decision result and the first decision result are based on the same decision method, and the second decision result and the fourth decision result are based on the same decision method. In the case where the decision error is greater than the second threshold and less than the first threshold, if the first decision result is the same as the second decision result, and the third decision result is different from the fourth decision result, then confirm that the target signal is an initial EOB error signal; otherwise, confirm that the target signal is a non-initial EOB error signal.

In some optional implementations, the processing unit 1202 is further configured to correct the target SOB error signal if it is determined that the signal to be tested includes the target SOB error signal. Positive target SOB error signal and initial EOB error signal.

In some optional implementations, the processing unit 1202 is specifically configured to determine that there is no target SOB error signal in the test signal if the cumulative error corresponding to any test signal in the test signal is not less than the cumulative error threshold;

If the target SOB error signal does not exist in the signal to be tested, the initial EOB error signal is determined to be a non-error signal.

The bit error detection device 1200 can execute the operations executed by the communication device in the embodiments shown in the aforementioned FIG. 2 to FIG. 11 , which will not be described in detail here.

The communication device provided in the embodiment of the present application is described below, and please refer to Figure 13, which is a schematic diagram of the structure of the communication device provided in the embodiment of the present application. The communication device 1300 includes: a processor 1301 and a memory 1302, and the memory 1302 stores one or more applications or data.

Among them, the memory 1302 can be a volatile storage or a persistent storage. The program stored in the memory 1302 may include one or more modules, each of which can be used to execute a series of operations performed by the communication device 1300. Furthermore, the processor 1301 can communicate with the memory 1302 and execute a series of instruction operations in the memory 1302 on the communication device 1300. The processor 1301 can be a central processing unit (CPU) or a single-core processor. In addition, it can also be other types of processors, such as a dual-core processor, which is not limited here.

The communication device 1300 may further include one or more communication interfaces 1303, one or more operating systems, such as Windows Server ^™ , Mac OS X ^™ , Unix ^™ , Linux ^™ , FreeBSD ^™ , etc.

The communication device 1300 can execute the operations executed by the communication devices in the embodiments shown in the aforementioned FIG. 2 to FIG. 11 , which will not be described in detail here.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

Claims

A method for detecting a bit error, characterized by comprising:

Acquire a signal set, wherein the signal set includes an initial burst end bit (EOB) error signal;

Taking the initial EOB error signal as the starting point, reverse error transmission is performed, and an initial burst start bit SOB error signal is determined from the signal set, wherein the initial SOB error signal and the signal between the initial SOB error signal and the initial EOB error signal in the signal set are the signals to be tested;

Calculating respectively the cumulative error from each signal to be tested to the initial EOB error signal, wherein the cumulative error is determined according to the error from each signal to be tested to any two adjacent signals in the initial EOB error signal;

According to the accumulated error, it is determined whether a target SOB error signal exists in the signal to be tested.
The method according to claim 1, characterized in that the step of determining whether a target SOB error signal exists in the signal to be tested based on the accumulated error comprises:

If there is a target test signal with the smallest cumulative error and less than a cumulative error threshold among the test signals, the target test signal is determined to be the target SOB error signal, and the cumulative error threshold is the error corresponding to the initial EOB error signal.
The method according to claim 1 or 2 is characterized in that the accumulated error includes a reverse compensation error and a decision error, the reverse compensation error is used to compensate the error signal, and the decision error indicates the error before and after the decision signal.
The method according to any one of claims 1 to 3, characterized in that the reverse error transmission is performed with the initial EOB error signal as the starting point, and the initial SOB error signal is determined from the signal set, comprising:

Reverse error transmission is performed with the initial EOB error signal as a starting point. When an abnormal level value appears, the next signal of the signal corresponding to the abnormal level value is determined to be the initial SOB error signal.
The method according to any one of claims 1 to 4, characterized in that the method further comprises:

Acquire a first equalization result, where the first equalization result is obtained by equalizing a plurality of consecutive signals in the signal set based on a first equalization method, where the plurality of signals include a target signal;

Obtaining a second equalization result, where the second equalization result is obtained by equalizing the plurality of continuous signals in a second equalization manner;

If the first equalization result is different from the second equalization result, it is determined that the target signal is the initial EOB error signal.
The method according to claim 5, characterized in that the plurality of continuous signals comprises:

The target signal and a signal preceding the target signal; or,

The target signal and a signal subsequent to the target signal.
The method according to any one of claims 1 to 4, characterized in that the method further comprises:

Obtaining a decision result and a decision error of a target signal in the signal set;

If the decision result is an extreme value corresponding to the signal set, and the absolute value of the decision error is greater than an error threshold, it is determined that the target signal is the initial EOB error signal.
The method according to any one of claims 1 to 7, characterized in that the method further comprises:

If it is determined that the signal to be tested includes the target SOB bit error signal, the target SOB bit error signal and the initial EOB bit error signal are corrected.
The method according to any one of claims 1, 3 to 7, characterized in that the step of determining whether a target SOB error signal exists in the signal to be tested based on the accumulated error comprises:

If the cumulative error corresponding to any one of the signals to be tested is not less than the cumulative error threshold, it is determined that the target SOB error signal does not exist in the signal to be tested;

If the target SOB error signal does not exist in the signal to be tested, it is determined that the initial EOB error signal is a non-error signal.
A method for detecting a bit error, characterized in that the method further comprises:

Acquire a first equalization result, where the first equalization result is obtained by equalizing a plurality of consecutive signals in the signal set based on a first equalization method, where the plurality of signals include a target signal;

Obtaining a second equalization result, where the second equalization result is obtained by equalizing the plurality of continuous signals based on a second equalization method;

According to the first equalization result and the second equalization result, it is determined whether the target signal is the initial EOB error signal.
The method according to claim 10, characterized in that the plurality of continuous signals comprises:

The target signal and a signal preceding the target signal; or,

The target signal and a signal subsequent to the target signal.
A bit error detection device, characterized in that it comprises:

An acquisition unit, configured to perform an acquisition operation in the method according to any one of claims 1 to 9;

A processing unit, used to perform operations other than the acquisition operation in the method of any one of claims 1 to 9.
A bit error detection device, characterized in that it comprises:

An acquisition unit, configured to perform an acquisition operation in the method according to claim 10 or 11;

A processing unit, used to perform operations other than the acquisition operation in the method described in claim 10 or 11.
A communication device, comprising: a processor and a memory;

The processor stores instructions, and when the instructions are executed on the processor, the method according to any one of claims 1 to 11 is implemented.
A chip, characterized in that it comprises: a processing unit and a power supply circuit;

The power supply circuit supplies power to the processing unit, and the processing unit is used to execute the method according to any one of claims 1 to 11.
A computer-readable storage medium, characterized in that the computer-readable storage medium stores instructions, and when the instructions are executed on a processor, the method according to any one of claims 1 to 11 is implemented.
A computer program product, characterized in that when the computer program product is executed on a processor, the method according to any one of claims 1 to 11 is implemented.