WO2024108836A1 - Computing device, operating method, and machine-readable storage medium - Google Patents

Abstract

The present invention provides a computing device, an operating method therefor, and a machine-readable storage medium. The computing device comprises an execution unit (EU) circuit and an instruction scheduler (IS) circuit. The IS circuit may transmit an instruction to the EU circuit for execution. The IS circuit comprises a descriptor address register (DAR). The DAR is used for storing address information of a resource descriptor. When a current instruction processed by the IS circuit uses the resource descriptor, the IS circuit obtains the address information stored in the local DAR of the IS circuit, without triggering the EU circuit to read, to the IS circuit, the address information of the resource descriptor from a scalar register file external to the IS circuit. After obtaining the address information of the resource descriptor, the IS circuit transmits, on the basis of the address information, the current instruction using the resource descriptor to the EU circuit for execution.

Description

Computing device, operating method and machine-readable storage medium

This application claims priority to Chinese Patent Application No. 202211486231.9 filed on November 24, 2022. The contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as a part of this application.

Technical Field

Embodiments of the present disclosure relate to a computing device, an operating method, and a machine-readable storage medium.

Background technique

In general, a resource descriptor is used to describe information about a resource (e.g., image, texture, etc.) (e.g., size, etc.). Instructions can access resources in memory based on resource descriptors. Instructions may use one or more resource descriptors. For example, a load instruction, a store instruction, or an atomic instruction (i.e., the minimum operation instruction) uses one resource descriptor, while a texture instruction usually uses two resource descriptors. A bindless resource descriptor is usually not pre-bound to any on-chip addressable memory. A bindless resource descriptor is usually obtained dynamically by a resource access instruction. For example, a memory access instruction must obtain a resource descriptor before performing a memory access on a resource.

The scalar register file (SRF) pre-stores the 64-bit complete memory address of the resource descriptor (the address of the target resource in the memory) or the 32-bit offset of the resource descriptor in the descriptor set. When an instruction uses an unbound resource descriptor to access memory, the instruction scheduler (IS) obtains the complete memory address of the unbound resource descriptor from the SRF based on the address of the SRF provided by the instruction. In the first step of the process of obtaining the address/offset of the resource descriptor, the instruction scheduler issues an additional hidden instruction to the execution unit (EU) to read the value in the SRF (the address/offset of the resource descriptor). In the second step, the execution unit executes the hidden instruction issued by the instruction scheduler to read the address/offset of the resource descriptor from the SRF. In the third step In the example, the execution unit returns the value from the SRF (the address/offset of the resource descriptor) to the instruction scheduler. If the value returned to the instruction scheduler is the offset of the resource descriptor within the descriptor set, the instruction scheduler can use the identifier (ID) of the descriptor set (or the base memory address of the descriptor set) and the offset returned by the execution unit to calculate the complete memory address of the resource descriptor. Regardless of whether the instruction scheduler calculates the complete memory address of the resource descriptor or the execution unit directly returns the complete memory address of the resource descriptor to the instruction scheduler, after determining the complete memory address of the resource descriptor, based on the execution of the execution unit, the instruction can use the resource descriptor to access the memory.

The problem is that the instruction scheduler must issue additional hidden instructions to the execution unit, and hidden instructions cause pipeline latency in the execution unit. Hidden instructions are additional instructions dynamically generated by the instruction scheduler, and are not instructions in the instruction set. Hidden instructions are not in the program source code, so they cannot be optimized during the compilation of the program source code. Furthermore, hidden instructions are forced to be executed for each descriptor, which ignores the reuse of descriptors in the instruction scheduler and puts a burden on the hardware.

Summary of the invention

The present disclosure provides a computing device and an operating method thereof, and a machine-readable storage medium, so as to more efficiently obtain address information of a resource descriptor.

In an embodiment according to the present disclosure, the computing device includes an execution unit (EU) circuit and an instruction scheduler (IS) circuit. The instruction scheduler circuit is coupled to the execution unit circuit to send instructions to the execution unit circuit for execution. The instruction scheduler circuit includes a descriptor address register (DAR). The descriptor address register is used to store the first address information of the first resource descriptor. In the case where the current instruction processed by the instruction scheduler circuit uses the first resource descriptor, the instruction scheduler circuit uses the first address information of the descriptor address register stored locally in the instruction scheduler circuit without triggering the execution unit circuit to read the first address information of the first resource descriptor from the scalar register file (SRF) outside the instruction scheduler circuit to the instruction scheduler circuit. After obtaining the first address information of the first resource descriptor, the instruction scheduler circuit sends the current instruction using the first resource descriptor to the execution unit circuit for execution based on the first address information.

In an embodiment of the present disclosure, the operation method includes: storing first address information of a first resource descriptor in a descriptor address register of an instruction scheduler circuit of a computing device; When the current instruction processed by the instruction scheduler circuit uses the first resource descriptor, the first address information of the descriptor address register stored locally in the instruction scheduler circuit is retrieved without triggering the execution unit circuit of the computing device to read the first address information of the first resource descriptor from the scalar register stack outside the instruction scheduler circuit to the instruction scheduler circuit; and after obtaining the first address information of the first resource descriptor, the instruction scheduler circuit transmits the current instruction using the first resource descriptor to the execution unit circuit for execution based on the first address information.

In an embodiment of the present disclosure, the machine-readable storage medium is used to store non-transitory machine-readable instructions. When the non-transitory machine-readable instructions are executed by a computer, the operating method of the computing device can be implemented.

Based on the above, the instruction scheduler circuit is locally configured with a descriptor address register. The instruction scheduler circuit can directly access the address information stored in the local descriptor address register, so the address information of the resource descriptor can be obtained more efficiently. Based on the actual design and application scenario, in some embodiments, the address information may include the complete memory address of the resource descriptor or the offset of the resource descriptor in the descriptor set. Based on this, the instruction scheduler is exempted from issuing additional hidden instructions to the execution unit, thereby avoiding the pipeline latency of the execution unit caused by the hidden instructions. In the case where the address information of the second resource descriptor used by the next instruction is the same as the address information of the resource descriptor used by the current instruction, the instruction scheduler circuit can reuse the address information stored in the descriptor address register. Therefore, the instruction scheduler circuit can more efficiently utilize the address information of the descriptor address register stored locally in the instruction scheduler circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic diagram of a circuit block of a computing device according to an embodiment of the present disclosure.

FIG. 2 is a flowchart of an operating method of a computing device according to an embodiment of the present disclosure.

Description of Reference Numerals
100: Computing Device
110: Instruction Scheduler (IS) Circuit
111: Descriptor Address Register (DAR)
112: Base Address Register (BAR)
120: Execution Unit (EU) Circuit
130: Scalar register file
S210, S220, S230: Steps

Detailed ways

Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

The term "coupled (or connected)" used in the entire specification of this case (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of this case (including the claims) are used to name the components (element), and are not used to limit the upper or lower limit of the number of components, nor are they used to limit the order of components. In addition, wherever possible, components/components/steps with the same number in the drawings and embodiments represent the same or similar parts. Components/components/steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

FIG. 1 is a circuit block diagram of a computing device 100 according to an embodiment of the present disclosure. The computing device 100 shown in FIG. 1 includes an instruction scheduler (IS) circuit 110, an execution unit (EU) circuit 120, and a scalar register file (SRF) 130. The EU circuit 120 is coupled to the IS circuit 110 and the scalar register file 130. The IS circuit 110 can send instructions to the EU circuit 120 for execution. According to different design requirements, in some embodiments, the implementation of the IS circuit 110 and (or) the EU circuit 120 can be a hardware circuit. In other embodiments, the implementation of the IS circuit 110 and (or) the EU circuit 120 can be firmware, software (i.e., program) or a combination of the above two. In some other embodiments, the implementation of the IS circuit 110 and (or) the EU circuit 120 can be a combination of hardware, firmware, and software.

In terms of hardware, the IS circuit 110 and/or the EU circuit 120 may be implemented as a logic circuit on an integrated circuit. For example, the related functions of the IS circuit 110 and/or the EU circuit 120 may be implemented in one or more controllers, microcontrollers, or The various logic blocks, modules and circuits in a microcontroller, a microprocessor, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA) and/or other processing units. The related functions of the IS circuit 110 and/or the EU circuit 120 can be implemented as hardware circuits, such as various logic blocks, modules and circuits in an integrated circuit, using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

In terms of software and/or firmware, the related functions of the IS circuit 110 and/or the EU circuit 120 can be implemented as programming codes. For example, the IS circuit 110 and/or the EU circuit 120 can be implemented using general programming languages (such as C, C++ or assembly language) or other suitable programming languages. The programming code can be recorded/stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, a semiconductor memory and/or a storage device. The semiconductor memory includes a memory card, a read-only memory (ROM), a flash memory (FLASH memory), a programmable logic circuit or other semiconductor memory. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD) or other storage devices. An electronic device (such as a central processing unit (CPU), a controller, a microcontroller or a microprocessor) can read and execute the programming code from the machine-readable storage medium to implement the relevant functions of the IS circuit 110 and (or) the EU circuit 120. Alternatively, the programming code can be provided to the electronic device via any transmission medium (such as a communication network or broadcast waves, etc.). The communication network is, for example, the Internet, a wired communication network, a wireless communication network or other communication media.

Figure 2 is a flow chart of an operating method of a computing device according to an embodiment of the present disclosure. In some embodiments, the operating method of the computing device shown in Figure 2 can be implemented in firmware or software (i.e., a program). For example, the relevant operations of the operating method of the computing device shown in Figure 2 can be implemented as non-transitory machine-readable instructions (programming code or program), and the non-transitory machine-readable instructions can be stored in a machine-readable storage medium. When the non-transitory machine-readable instructions are executed by a computer, the operating method of the computing device shown in Figure 2 can be implemented. In other embodiments, the operating method of the computing device shown in Figure 2 can be implemented in hardware, for example, in the computing device 100 shown in Figure 1.

Please refer to FIG. 1 and FIG. 2. The IS circuit 110 includes a descriptor address register (DAR) 111 and a base address register (BAR) 112. The base address register 112 can store the base memory address (base memory address) of the descriptor set. The base memory address of the descriptor set can be, for example, 64 bits. Each descriptor set corresponds to a base address register 112. For example, when 4 or 8 descriptor sets are supported, 4 or 8 base address registers 112 are required respectively. The specific number of the base address register 112 can be determined according to the actual design. The descriptor set identifier (Descriptor set ID) is an immediate number embedded in the current instruction. The base address register 112 can be selected by the descriptor set identifier, thereby determining the base memory address of the descriptor set corresponding to the identifier. The number of identification numbers is determined by the current instruction. For example, when two resource descriptors are required, two corresponding identification numbers are provided in the current instruction. The descriptor address register 111 can store the address information of the resource descriptor. Based on the actual design and application scenario, in some embodiments, the address information may include the complete memory address of the resource descriptor, or the offset of the resource descriptor in the descriptor set. The complete memory address of the resource descriptor is the sum of the basic memory address of the descriptor set and the offset of the resource descriptor in the descriptor set. The specific number of descriptor address registers 111 can be determined according to the actual design. For example, the descriptor address register 111 can include a 32-bit register dar0 (not shown, or a register of other bit numbers) to store the offset of a resource descriptor in the descriptor set. Alternatively, the descriptor address register 111 can include two 32-bit registers dar0 and dar1 (not shown, or a register of other bit numbers). When the address information is an offset, the offset of the resource descriptor can be stored in register dar0. When the address information is the complete memory address of the resource descriptor, the complete memory address of the resource descriptor can be stored in registers dar0 and dar1. Alternatively, the descriptor address register 111 can include four 32-bit registers dar0, dar1, dar2 and dar3 (not shown, or registers of other bit numbers). When an instruction uses one resource descriptor, the offset of the resource descriptor can be stored in register dar0, or the complete memory address of the resource descriptor can be stored in registers dar0 and dar1. When an instruction uses two resource descriptors, the complete memory address (or offset) of one resource descriptor can be stored in registers dar0 and dar1, and the complete memory address (or offset) of the other resource descriptor can be stored in registers dar2 and dar3.

For example (but not limited to), a warp can have four 32-bit registers dar0, dar1, dar2 and dar3, and the IS circuit 110 can directly read the registers dar0~dar3 of the descriptor address register 111. Generally speaking, a thread group can include multiple warps, and a warp can also be called a thread bundle. A load instruction or a store instruction can use the registers dar0 and dar1 of the descriptor address register 111 to store the offset or address of the descriptor. A texture instruction can use the registers dar0 and dar1 of the descriptor address register 111 to store the offset or address of the texture descriptor, and use the registers dar2 and dar3 of the descriptor address register 111 to store the offset or address of the sampler descriptor.

It is assumed here that the descriptor address register 111 stores the first address information of the first resource descriptor (step S210). In the case where the current instruction processed by the IS circuit 110 uses the first resource descriptor, the IS circuit 110 can access the first address information of the descriptor address register 111 stored locally in the IS circuit 110 (step S220), without triggering the EU circuit 120 to read the first address information of the first resource descriptor from the scalar register file 130 outside the IS circuit 110 to the IS circuit 110. After obtaining the first address information of the first resource descriptor, the IS circuit 110 can send the current instruction using the first resource descriptor to the EU circuit 120 for execution based on the first address information (step S230).

In the case where the address information of the second resource descriptor used by the next instruction is the same as the first address information of the first resource descriptor used by the current instruction, that is, when the resource descriptor used by the next instruction is the same as the resource descriptor used by the current instruction, the IS circuit 110 can reuse the first address information stored in the descriptor address register 111 to access the resources in the memory (not shown) without triggering the EU circuit 120 to read the address information of the second resource descriptor from the scalar register file 130 to the IS circuit 110. After obtaining the address information of the second resource descriptor (that is, the first address information), the IS circuit 110 can transmit the current instruction using the second resource descriptor to the EU circuit 120 for execution based on the first address information (step S230).

Based on the actual design and application scenario, in some embodiments, the address information may include the complete memory address of the resource descriptor, or the offset of the resource descriptor in the descriptor set. If the address information includes the offset of the resource descriptor in the descriptor set, the IS circuit 110 may select the corresponding base address register 112 according to the identification number of the descriptor set carried in the current instruction, and then use the basic memory address of the descriptor set stored in the base address register 112 and the offset stored in the descriptor address register 111 to calculate the complete memory address of the first resource descriptor. The IS circuit 110 may transmit the complete memory address and the current instruction using the first resource descriptor to the EU circuit 120 for execution. If the address information includes the complete memory address of the first resource descriptor in the memory, the IS circuit 110 may transmit the complete memory address stored in the descriptor address register 111 and the current instruction using the first resource descriptor to the EU circuit 120 for execution.

In summary, the descriptor address register 111 can be added to the IS circuit 110. The IS circuit 110 can directly access the address information stored in the local descriptor address register 111, so that the address information of the resource descriptor (such as the complete memory address of the resource descriptor or the offset of the resource descriptor in the descriptor set) can be obtained more efficiently. Based on this, the IS circuit 110 is exempted from issuing additional hidden instructions to the EU circuit 120, thereby avoiding the pipeline latency of the EU circuit 120 caused by the hidden instructions, and reducing the burden on the hardware. In the case where the address information of the second resource descriptor used by the next instruction is the same as the first address information of the first resource descriptor used by the current instruction, the IS circuit 110 can reuse the address information stored in the descriptor address register 111. Therefore, the IS circuit 110 can more efficiently utilize the address information of the descriptor address register 111 stored locally in the IS circuit 110.

In contrast, the instruction scheduler of the prior art must issue an additional hidden instruction to the execution unit for each bindless resource descriptor to trigger the execution unit to read the value (address/offset of the resource descriptor) in the scalar register file. The problem is that the hidden instructions issued by the instruction scheduler of the prior art will cause pipeline delays in the execution unit. In addition, the hidden instructions are additional instructions dynamically generated by the instruction scheduler, rather than instructions in the instruction set. The hidden instructions are not in the program source code, so the hidden instructions cannot be optimized during the compilation of the program source code. Furthermore, the prior art forces the issuance/execution of hidden instructions for each descriptor, thereby ignoring the reuse of descriptors in the instruction scheduler and placing a burden on the hardware.

Please refer to the embodiment of the present disclosure shown in Figure 1. In this embodiment, a new move instruction SMOVD can be added to the instruction set to move a value (the complete memory address of the resource descriptor or the offset of the resource descriptor in the descriptor set) from the scalar register file 130 to the descriptor address register 111. For example, according to the actual operation scenario, the move instruction SMOVD can be the following pseudo code [1]. In the following pseudo code [1], dest represents the descriptor address register 111, and source can represent the scalar register file 130, a constant random access memory (RAM), a constant register or an immediate value. Programs or shaders can The descriptor address register 111 is updated using the move instruction SMOVD.

smovd dest,source;         Pseudocode[1]

The move instruction SMOVD is an instruction of the instruction set. The move instruction SMOVD is in the program source code, so the move instruction SMOVD can be optimized during the compilation of the program source code. When the second address information of the second resource descriptor used by the next instruction is different from the first address information of the first resource descriptor used by the current instruction, that is, when the resource descriptor used by the next instruction is not the resource descriptor used by the current instruction, the IS circuit 110 can transmit the move instruction SMOVD of the instruction set to the EU circuit 120. Based on the move instruction SMOVD, the EU circuit 120 can move the second address information of the second resource descriptor from the scalar register stack 130 outside the IS circuit 110 to the descriptor address register 111 local to the IS circuit 110. Therefore, when the IS circuit 110 processes the next instruction using the second resource descriptor, the IS circuit 110 can access the second address information stored in the descriptor address register 111. After obtaining the second address information of the second resource descriptor, the IS circuit 110 may transmit the next instruction using the second resource descriptor to the EU circuit 120 for execution based on the second address information.

In contrast, the instruction scheduler of the prior art issues an additional hidden instruction to the execution unit for each unbound resource descriptor to trigger the execution unit to read the value (address/offset of the resource descriptor) in the scalar register file. The problem is that the hidden instruction is an additional instruction dynamically generated by the instruction scheduler, not an instruction of the instruction set. The hidden instruction is not in the program source code, so the hidden instruction cannot be optimized during the compilation process of the program source code.

Please refer to the embodiment of the present disclosure shown in FIG. 1 . In some actual operation scenarios, the address information of the resource descriptor generated by the scalar operation can be directly stored in the descriptor address register 111 local to the IS circuit 110. In other actual operation scenarios, the address information of the resource descriptor generated by the scalar operation can be stored in a scalar register stack 130 outside the IS circuit 110 for use by the IS circuit 110.

For example, before the IS circuit 110 processes the current instruction, the IS circuit 110 processes the scalar operation instruction and generates the first address information of the first resource descriptor. At this time, when the IS circuit 110 needs to reuse the first address information, the IS circuit 110 can directly store the first address information in the local descriptor address register 111 of the IS circuit 110, without transmitting the first address information through the EU circuit. The first resource descriptor is stored in the scalar register file 130 outside the IS circuit 110 by the EU circuit 120. When the IS circuit 110 processes the current instruction using the first resource descriptor, the IS circuit 110 can access the first address information stored in the descriptor address register 111. Therefore, the IS circuit 110 can issue the current instruction using the first resource descriptor to the EU circuit 120 for execution based on the first address information. When the IS circuit 110 does not need to reuse the first address information, the IS circuit 110 can store the first address information in the scalar register file 130 outside the IS circuit 110 through the EU circuit 120.

For another example, when the second address information of the second resource descriptor used by the next instruction is different from the first address information of the first resource descriptor used by the current instruction, that is, when the resource descriptor used by the next instruction is not the resource descriptor used by the current instruction, the IS circuit 110 processes the scalar operation instruction and generates the second address information of the second resource descriptor. At this time, the IS circuit 110 can directly store the second address information in the descriptor address register 111 local to the IS circuit 110, instead of storing the second address information in the scalar register stack 130 outside the IS circuit 110 (for example, when the IS circuit 110 does not need to reuse the second address information). Therefore, when the IS circuit 110 processes the next instruction using the second resource descriptor, the IS circuit 110 can access the second address information stored in the descriptor address register 111. After obtaining the second address information of the second resource descriptor, the IS circuit 110 can transmit the next instruction using the second resource descriptor to the EU circuit 120 for execution based on the second address information.

For another example, after the scalar operation instruction processed by the IS circuit 110 generates the first address information of the first resource descriptor, the IS circuit 110 may store the first address information in the scalar register file 130 outside the IS circuit 110. Before the IS circuit 110 processes the current instruction using the first resource descriptor, the IS circuit 110 may send a move instruction SMOVD of the instruction set to the EU circuit 120 to move the first address information of the first resource descriptor from the scalar register file 130 to the descriptor address register 111 of the IS circuit 110. When the IS circuit 110 processes the current instruction using the first resource descriptor, the IS circuit 110 may access the first address information stored in the descriptor address register 111. Therefore, the IS circuit 110 may send the current instruction using the first resource descriptor to the EU circuit 120 for execution based on the first address information.

Based on actual design, in some embodiments, the descriptor address register 111 may be added to the address space of the scalar register file 130. The program or shader may update the descriptor address register 111 using the target address in the address space of the scalar register file 130. For example, the first interval of the address space may correspond to the scalar register file 130 outside the IS circuit 110, and the second interval of the address space may correspond to the scalar register file 130 outside the IS circuit 110. The second interval may correspond to the descriptor address register 111 local to the IS circuit 110. After the scalar operation instruction processed by the IS circuit 110 generates the first address information of the first resource descriptor, the IS circuit 110 may use the address space to selectively store the first address information in one of the scalar register file 130 and the descriptor address register 111. As a specific example of adding the descriptor address register 111 to the address space of the scalar register file 130, it is assumed that the address space of the scalar register file 130 is a 7-bit address space, wherein each address of addresses 0 to 63 (the first interval of the address space) may be used to represent a conventional scalar register in the scalar register file 130, and each address of addresses 64 to 67 (the second interval of the address space) may be used to represent one of the registers dar0 to dar3 in the descriptor address register 111. The IS circuit 110 may use the address space of the scalar register file 130 to specify that the result of the scalar operation is written to the descriptor address register 111.

In summary, the IS circuit 110 can directly access the descriptor address register 111 local to the IS circuit 110, so the IS circuit 110 can avoid hidden instructions that cause EU pipeline delays. Because the IS does not need to prepare and issue hidden instructions, the complexity of the IS circuit 110 is reduced. In the case where the address information of the second resource descriptor used by the next instruction is the same as the address information of the resource descriptor used by the current instruction, the IS circuit 110 can reuse the address information stored in the descriptor address register 111, that is, reuse the resource descriptor with the same offset (or address) (this is impossible in the prior art). Therefore, when a series of instructions use the same resource descriptor, the IS circuit 110 can achieve better performance.

Finally, it should be noted that the above embodiments are only used to illustrate the embodiments of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding embodiments from the scope of the embodiments of the present disclosure.

Claims (17)

1. A computing device, comprising:

   execution unit circuit; and

   An instruction scheduler circuit is coupled to the execution unit circuit and is configured to issue instructions to the execution unit circuit for execution, wherein the instruction scheduler circuit includes a descriptor address register, and the descriptor address register is configured to store first address information of a first resource descriptor.

   In a case where the current instruction processed by the instruction scheduler circuit uses the first resource descriptor, the instruction scheduler circuit uses the first address information of the descriptor address register stored locally in the instruction scheduler circuit without triggering the execution unit circuit to read the first address information of the first resource descriptor from a scalar register file external to the instruction scheduler circuit to the instruction scheduler circuit, and

   After obtaining the first address information of the first resource descriptor, the instruction scheduler circuit issues the current instruction using the first resource descriptor to the execution unit circuit for execution based on the first address information.
2. The computing device according to claim 1, wherein, when the address information of the second resource descriptor used by the next instruction is the same as the first address information of the first resource descriptor used by the current instruction, the instruction scheduler circuit reuses the first address information stored in the descriptor address register without triggering the execution unit circuit to read the first address information from the scalar register file to the instruction scheduler circuit.
3. The computing device according to claim 1 or 2, wherein:

   In a case where the second address information of the second resource descriptor used by the next instruction is not the first address information of the first resource descriptor used by the current instruction: the instruction scheduler circuit transmits a move instruction of an instruction set to the execution unit circuit to move the second address information of the second resource descriptor from the scalar register file outside the instruction scheduler circuit to the descriptor address register local to the instruction scheduler circuit, or the instruction scheduler circuit processes a scalar operation instruction to generate the second address information of the second resource descriptor, and the instruction scheduler circuit directly stores the second address information in the descriptor address register local to the instruction scheduler circuit, instead of storing the second address information in the scalar register file outside the instruction scheduler circuit;

   When the instruction scheduler circuit processes the next instruction using the second resource descriptor, the instruction scheduler circuit retrieves the second address information stored in the descriptor address register; and

   After obtaining the second address information of the second resource descriptor, the instruction scheduler circuit issues the next instruction using the second resource descriptor to the execution unit circuit for execution based on the second address information.
4. A computing device according to any one of claims 1-3, wherein, before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit processes a scalar operation instruction to generate the first address information of the first resource descriptor, and the instruction scheduler circuit directly stores the first address information in the descriptor address register local to the instruction scheduler circuit, instead of storing the first address information in the scalar register file outside the instruction scheduler circuit.
5. The computing device according to any one of claims 1 to 3, wherein:

   After the scalar operation instruction processed by the instruction scheduler circuit generates the first address information of the first resource descriptor, the instruction scheduler circuit stores the first address information in the scalar register file outside the instruction scheduler circuit; and

   Before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit issues a move instruction of an instruction set to the execution unit circuit to move the first address information of the first resource descriptor from the scalar register file to the descriptor address register of the instruction scheduler circuit.
6. A computing device according to any one of claims 1-3, wherein the descriptor address register is added to the address space of the scalar register stack, a first interval of the address space corresponds to the scalar register stack outside the instruction scheduler circuit, a second interval of the address space corresponds to the descriptor address register local to the instruction scheduler circuit, and after the scalar operation instruction processed by the instruction scheduler circuit generates the first address information of the first resource descriptor, the instruction scheduler circuit uses the address space to selectively store the first address information in one of the scalar register stack and the descriptor address register.
7. The computing device according to any one of claims 1 to 6, wherein the first address information comprises an offset of the first resource descriptor within a descriptor set, and the instruction scheduler circuit further comprises:

   a base address register configured to store a base memory address of the descriptor set,

   The instruction scheduler circuit uses the basic memory address stored in the base address register and the offset stored in the descriptor address register to calculate the complete memory address of the first resource descriptor, and the instruction scheduler circuit transmits the complete memory address and the current instruction using the first resource descriptor to the execution unit circuit for execution.
8. A computing device according to any one of claims 1-6, wherein the first address information includes a complete memory address of the first resource descriptor in a memory, and the instruction scheduler circuit transmits the complete memory address stored in the descriptor address register and the current instruction using the first resource descriptor to the execution unit circuit for execution.
9. A method for operating a computing device, comprising:

   The descriptor address register of the instruction scheduler circuit of the computing device stores first address information of the first resource descriptor;

   When the current instruction processed by the instruction scheduler circuit uses the first resource descriptor, fetch the first address information of the descriptor address register stored locally in the instruction scheduler circuit without triggering the execution unit circuit of the computing device to read the first address information of the first resource descriptor from a scalar register file external to the instruction scheduler circuit to the instruction scheduler circuit; and

   After obtaining the first address information of the first resource descriptor, the instruction scheduler circuit issues the current instruction using the first resource descriptor to the execution unit circuit for execution based on the first address information.
10. The operating method according to claim 9, further comprising:

    When the address information of the second resource descriptor used by the next instruction is the same as the first address information of the first resource descriptor used by the current instruction, the first address information stored in the descriptor address register is reused without triggering the execution unit circuit to read the first address information from the scalar register file to the instruction scheduler circuit.
11. The operating method according to claim 9 or 10, further comprising:

    In a case where the second address information of the second resource descriptor used by the next instruction is not the first address information of the first resource descriptor used by the current instruction: the instruction scheduler circuit issues a move instruction of the instruction set to the execution unit circuit to move the second address information of the second resource descriptor from the scalar register outside the instruction scheduler circuit to the scalar register outside the instruction scheduler circuit. The instruction scheduler circuit is configured to move the second address information of the second resource descriptor to the descriptor address register local to the instruction scheduler circuit, or the instruction scheduler circuit processes a scalar operation instruction to generate the second address information of the second resource descriptor, and the instruction scheduler circuit directly stores the second address information in the descriptor address register local to the instruction scheduler circuit, instead of storing the second address information in the scalar register stack outside the instruction scheduler circuit;

    When the instruction scheduler circuit processes the next instruction using the second resource descriptor, accessing the second address information stored in the descriptor address register; and

    After obtaining the second address information of the second resource descriptor, the instruction scheduler circuit issues the next instruction using the second resource descriptor to the execution unit circuit for execution based on the second address information.
12. The operating method according to any one of claims 9 to 11, further comprising:

    Before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit processes a scalar operation instruction to generate the first address information of the first resource descriptor; and

    The first address information is directly stored in the descriptor address register local to the instruction scheduler circuit, instead of being stored in the scalar register file outside the instruction scheduler circuit.
13. The operating method according to any one of claims 9 to 11, further comprising:

    After the scalar operation instruction processed by the instruction scheduler circuit generates the first address information of the first resource descriptor, storing the first address information in the scalar register file outside the instruction scheduler circuit; and

    Before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit issues a move instruction of an instruction set to the execution unit circuit to move the first address information of the first resource descriptor from the scalar register file to the descriptor address register of the instruction scheduler circuit.
14. The operating method according to any one of claims 9 to 11, wherein the descriptor address register is added to the address space of the scalar register file, a first interval of the address space corresponds to the scalar register file outside the instruction scheduler circuit, a second interval of the address space corresponds to the descriptor address register local to the instruction scheduler circuit, and the operating method further comprises:

    The scalar operation instruction processed by the instruction scheduler circuit generates the first resource descriptor After receiving the first address information, the address space is used to selectively store the first address information in one of the scalar register file and the descriptor address register.
15. The operating method according to any one of claims 9 to 14, wherein the first address information comprises an offset of the first resource descriptor within a descriptor set, and the operating method further comprises:

    The base address register of the instruction scheduler circuit stores the base memory address of the descriptor set;

    Using the base memory address stored in the base address register and the offset stored in the descriptor address register to calculate a complete memory address of the first resource descriptor; and

    The instruction scheduler circuit issues the complete memory address and the current instruction using the first resource descriptor to the execution unit circuit for execution.
16. The operating method according to any one of claims 9 to 14, wherein the first address information comprises a complete memory address of the first resource descriptor in a memory, and the operating method further comprises:

    The instruction scheduler circuit issues the complete memory address stored in the descriptor address register and the current instruction using the first resource descriptor to the execution unit circuit for execution.
17. A machine-readable storage medium for storing non-transitory machine-readable instructions, which, when executed by a computer, can implement the operating method of the computing device described in any one of claims 9 to 16.