WO2024108825A1

WO2024108825A1 - Memory backup acceleration method, apparatus and device, and non-volatile readable storage medium

Info

Publication number: WO2024108825A1
Application number: PCT/CN2023/081742
Authority: WO
Inventors: 刘伟; 宿栋栋; 沈艳梅
Original assignee: 浪潮(北京)电子信息产业有限公司
Priority date: 2022-11-21
Filing date: 2023-03-15
Publication date: 2024-05-30
Also published as: CN115756962A

Abstract

The present application relates to the technical field of servers, and discloses a memory backup acceleration method, comprising: when a host memory space of a local host is insufficient, determining whether there is an allocable space on an on-chip memory of a local FPGA; if there is an allocable space on the on-chip memory of the local FPGA, backing up target data into the on-chip memory of the local FPGA; and if there is no allocable space on the on-chip memory of the local FPGA, backing up the target data into a remote memory array device. The method uses the memory of the local FPGA on the local host and the memory of the remote memory array device as physical carriers for backing up data in the host memory of the local host, thereby effectively increasing the running speed of a system. The present application further discloses a memory backup acceleration apparatus and device, and a non-volatile readable storage medium, which all have the described technical effect.

Description

Memory backup acceleration method, device, equipment and non-volatile readable storage medium

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on November 21, 2022, with application number 202211458494.9, and application name “Memory backup acceleration method, device, equipment and computer-readable storage medium”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of server technology, and in particular to a memory backup acceleration method; and also to a memory backup acceleration device, equipment and a non-volatile readable storage medium.

Background technique

In early computers or embedded devices using 8-bit/16-bit MCUs (Microcontroller Units), programs run directly on physical memory. Running directly on physical memory means that all addresses accessed by the program during runtime are physical addresses. This method of running programs directly on physical memory is simple to implement, but it has defects such as insufficient physical memory, uncertain program running addresses, and low memory utilization. For this reason, virtual memory management technology is currently introduced. The basic idea of virtual memory management technology is that the total size of memory used by the program can exceed the size of physical memory, and the operating system puts part of the currently used data in the memory, and saves the other unused parts on the hard disk.

Although virtual memory management technology solves many defects of running programs directly on physical memory, there are still some problems. For example, during the running of the program, the operating system needs to spend time to maintain and update the page table (the memory management unit in the CPU (Central Processing Unit) converts virtual addresses to physical addresses by querying the page table), add and delete table entries, also known as establishing and deleting memory mapping. When the memory space required by the program is larger than the existing physical memory in the system, the operating system needs to frequently move data between the physical memory and the hard disk. The data transfer rate of the traditional hard disk (on the order of 0.1GB/s) is much slower than the memory access rate (on the order of 10GB/s), which seriously reduces the overall operation speed of the system.

In view of this, how to improve the operating speed of the system has become a technical problem that needs to be solved urgently by those skilled in the art.

Summary of the invention

The purpose of the present application is to provide a memory backup acceleration method that can improve the operating speed of the system. Another purpose of the present application is to provide a memory backup acceleration device, equipment and non-volatile readable storage medium, all of which have the above technical effects.

In order to solve the above technical problems, the present application provides a memory backup acceleration method, comprising:

When the host memory space of the local host is insufficient, it is determined whether there is allocatable space in the on-chip memory of the local FPGA;

If there is allocatable space in the on-chip memory of the local FPGA, the target data is backed up to the on-chip memory of the local FPGA;

If there is no allocatable space in the on-chip memory of the local FPGA, the target data is backed up to a remote memory array device.

In some embodiments, backing up the target data to a remote memory array device includes:

If there is allocatable space in the on-chip memory of the remote FPGA in the remote memory array device, the target data is transmitted to the remote FPGA, and the target data is stored in the on-chip memory of the remote FPGA;

If there is no allocatable space in the on-chip memory of the remote FPGA, the target data is transmitted to the remote FPGA, and the target data is stored in the remote memory of the remote memory array device via the remote FPGA.

In some embodiments, transmitting the target data to the remote FPGA includes:

The target data is transmitted to the remote FPGA through the RDMA transmission module of the local FPGA.

In some embodiments, it also includes:

When accessing data, if the data to be accessed is located in the host memory, the host memory is accessed;

If the data to be accessed is located in the on-chip memory of the local FPGA, the data to be accessed is copied from the on-chip memory of the local FPGA to the host memory, and the host memory is accessed;

If the data to be accessed is located in a remote memory array device, the data to be accessed is copied from the remote memory array device to the host memory, and the host memory is accessed.

In some embodiments, when the host memory space of the local host is insufficient, before determining whether there is allocatable space in the on-chip memory of the local FPGA, the method further includes:

Comparing the host memory space of the local host with a first preset threshold;

When the host memory space of the local host is less than or equal to the first preset threshold, it is determined that the host memory space of the local host is insufficient.

In some embodiments, if there is no allocatable space in the on-chip memory of the local FPGA, before backing up the target data to the remote memory array device, the method further includes:

When the remaining capacity of the local FPGA drops to a second preset threshold, it is determined that the on-chip memory of the local FPGA does not exist. Allocate space, or,

When the remaining capacity of the local FPGA is smaller than the size of the target data, it is determined that there is no allocatable space in the on-chip memory of the local FPGA.

In some embodiments, copying the to-be-accessed data from the remote memory array device to the host memory includes:

If the data to be accessed is located in the on-chip memory of the remote FPGA of the remote memory array device, copying the data to be accessed from the on-chip memory of the remote FPGA to the local memory;

If the data to be accessed is located in the remote memory of the remote memory array device, the data to be accessed is copied from the remote memory to the local memory.

In some embodiments, it also includes:

After the data to be accessed is copied from the on-chip memory of the local FPGA to the host memory, the space occupied by the data to be accessed in the on-chip memory of the local FPGA is released.

In some embodiments, it also includes:

After the data to be accessed is copied from the remote memory array device to the host memory, the space occupied by the data to be accessed in the remote memory array device is released.

In some embodiments, releasing the space occupied by the to-be-accessed data in the remote memory array device includes:

If the data to be accessed is copied from the on-chip memory of the remote FPGA to the local memory, the space occupied by the data to be accessed in the on-chip memory of the remote FPGA is released;

If the data to be accessed is copied from the remote memory to the local memory, the space occupied by the data to be accessed in the remote memory is released.

In some embodiments, it also includes:

After the target data is backed up to the on-chip memory of the local FPGA or the remote memory array device, the space of the local memory occupied by the target data is released.

In some embodiments, releasing the space of the local memory occupied by the target data includes:

Delete the memory mapping of the local memory occupied by the target data.

In some embodiments, it also includes:

When the host memory space of the local host is sufficient, host memory is allocated and a memory mapping is established.

In some embodiments, when the host memory space of the local host is sufficient, allocating host memory and establishing memory mapping further includes:

Determine whether the local host has established memory mapping;

If the local host does not have a memory mapping, determine whether the host memory space of the local host is sufficient;

If the host memory space of the local host is sufficient, the host memory is allocated and a memory mapping is established.

In some embodiments, establishing a memory map includes:

By creating page table entries, a mapping relationship between virtual addresses and physical addresses is established to obtain a memory mapping.

In some embodiments, it also includes:

Record the information of the device where the target data to be backed up is located and the address of the memory in the device where the target data is stored.

In some embodiments, recording information of the device where the target data to be backed up is located includes:

The local FPGA number of the target data and the remote memory array device number are determined as the information of the device where the target data is located and recorded, wherein the information of the device where the target data is located is used to copy the backed up target data back to the local memory when the target data is accessed.

In order to solve the above technical problems, the present application also provides a memory backup acceleration device, comprising:

A judgment module, used for judging whether there is allocatable space in the on-chip memory of the local FPGA when the host memory space of the local host is insufficient;

A first backup module, configured to back up the target data to the on-chip memory of the local FPGA if there is allocatable space in the on-chip memory of the local FPGA;

The second backup module is used to back up the target data to a remote memory array device if there is no allocatable space in the on-chip memory of the local FPGA.

In order to solve the above technical problems, the present application also provides a memory backup acceleration device, including:

Memory for storing computer programs;

A processor is used to implement the steps of any of the above-mentioned memory backup acceleration methods when executing the above-mentioned computer program.

In order to solve the above technical problems, the present application also provides a non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned memory backup acceleration methods are implemented.

The memory backup acceleration method provided in the present application includes: when the host memory space of the local host is insufficient, determining whether there is allocatable space in the on-chip memory of the local FPGA; if there is allocatable space in the on-chip memory of the local FPGA, backing up the target data to the on-chip memory of the local FPGA; if there is no allocatable space in the on-chip memory of the local FPGA, backing up the target data to a remote memory array device.

It can be seen that the memory backup acceleration method provided in the present application uses the memory of the local FPGA on the local host and the memory of the remote memory array device as the physical carrier for backing up the data in the host memory of the local host, replacing the traditional solution of using the hard disk as the data backup carrier, and can effectively improve the speed of system operation.

The memory backup acceleration device, equipment and non-volatile readable storage medium provided in this application all have the above technical effects. fruit.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the relevant technologies and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of an existing hardware architecture;

FIG2 is a schematic diagram of existing software logic;

FIG3 is a schematic diagram of a flow chart of a memory backup acceleration method provided in an embodiment of the present application;

FIG4 is a schematic diagram of a hardware architecture provided in an embodiment of the present application;

FIG5 is a schematic diagram of a software logic provided in an embodiment of the present application;

FIG6 is a schematic diagram of a memory backup acceleration device provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of a memory backup acceleration device provided in an embodiment of the present application.

Detailed ways

The core of this application is to provide a memory backup acceleration method, which can improve the operating speed of the system. Another core of this application is to provide a memory backup acceleration device, equipment and non-volatile readable storage medium, all of which have the above technical effects.

In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

Referring to Figures 1 and 2, the relevant technical solution is that when the application needs to access the memory, the operating system executes the processing logic shown in Figure 2, which is recorded as the swap processing logic. It mainly includes backing up the long-unused data from the local memory to the swap partition in the hard disk when the local memory of the host is insufficient, freeing up memory space for new data; if the data to be accessed this time is backed up to the swap partition, the data to be accessed is copied from the swap partition to the local memory before accessing the local memory. However, the use of the above technical solution will seriously reduce the overall operating speed of the system. For this reason, the present application provides a memory backup acceleration method, which aims to increase the operating speed of the system.

Please refer to FIG. 3 , which is a flow chart of a memory backup acceleration method provided in an embodiment of the present application. Referring to FIG. 3 , the method includes:

S101: When the host memory space of the local host is insufficient, determine whether there is allocatable space in the on-chip memory of the local FPGA (Field Programmable Gate Array);

S102: If there is allocatable space in the on-chip memory of the local FPGA, back up the target data to the on-chip memory of the local FPGA;

S103: If there is no allocatable space in the on-chip memory of the local FPGA, the target data is backed up to a remote memory array device.

As shown in Figure 4, the local host includes a local FPGA in addition to the CPU chip and local memory. The local FPGA is connected to the processor core through a PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) bridge, and the processor core can access the local FPGA through the address bus -> PCIe bridge. The local FPGA can access the local memory through the PCIe bridge -> address bus. The local FPGA can expose part of the on-chip memory for the processor core to access.

The remote memory array device may be a physical carrier specially set up to back up the data in the host memory of the local host, or may be another server.

When the remaining capacity of the local memory drops to a preset threshold, the local memory is considered insufficient. For example, when the remaining capacity of the local memory drops to 10%, the local memory is considered insufficient. The target data may be data that has not been used for a period of time. In order to obtain a faster access rate, this embodiment gives priority to the use of the on-chip memory of the local FPGA. When the local memory is insufficient, the on-chip memory of the local FPGA is used as the backup carrier of the target data, and the target data is backed up to the on-chip memory of the local FPGA. If there is no allocatable storage space in the local FPGA, that is, the on-chip memory space is insufficient, the memory of the remote memory array device is used as the backup carrier of the target data, and the target data is backed up to the memory of the remote memory array device. When the remaining capacity of the local FPGA drops to a preset threshold, it can be considered that the on-chip memory space of the local FPGA is insufficient. Or when the remaining capacity of the local FPGA is less than the size of the target data, it can be considered that the on-chip memory space of the local FPGA is insufficient.

The information of the device where the backed-up target data is located (for example, the number of the local FPGA, the number of the remote memory array device, etc.) and its memory address must be recorded so that when the program accesses the target data in the future, the backed-up target data can be copied back to the local memory.

The memory management module is responsible for the management of the on-chip memory of the local FPGA, the on-chip memory of the remote FPGA, and the remote memory, which mainly includes memory allocation, memory recycling, and judging whether there is enough memory available.

As shown in FIG4 , in this embodiment, the remote memory array device includes a remote memory and a remote FPGA. The remote memory and the remote FPGA may be connected via a PCIe bridge. Alternatively, for a remote FPGA that can directly access the remote memory, the remote FPGA and the remote memory may be directly connected without a PCIe bridge.

When the target data is to be backed up in the remote memory array device, the target data is preferentially backed up in the on-chip memory of the remote FPGA in the remote memory array device. If the on-chip memory space of the remote FPGA is insufficient, the target data is stored in the remote memory of the remote memory array device.

In order to improve the operating speed of the system, in some embodiments, transmitting the target data to the remote FPGA includes:

As shown in FIG. 4 , in this embodiment, both the local FPGA and the remote FPGA are provided with RDMA transmission modules, and the local host and the remote memory array device are connected to the RDMA network via the RDMA transmission module.

RDMA is the abbreviation of Remote Direct Memory Access, which means remote direct address access. Through RDMA, the local node can directly access the memory of the remote node. The so-called direct means that it can bypass the complex TCP/IP (TCP, Transmission Control Protocol) (IP, Internet Protocol) network protocol stack of traditional Ethernet to read and write the memory of the peer node just like accessing local memory. The CPU of the peer node does not participate in the reading and writing process, and most of the work of this reading and writing process is completed by hardware rather than software.

When the local memory and the on-chip memory space of the local FPGA are insufficient, the above target data is preferentially transferred to the remote FPGA through the RDMA module and stored in the on-chip memory of the remote FPGA. If the on-chip memory space of the remote FPGA is insufficient, the target data is transferred to the remote FPGA through the RDMA module, and the remote FPGA stores the target data in the remote memory through the PCIe bridge or directly.

Furthermore, in some embodiments, it also includes:

After backing up the target data to the on-chip memory of the local FPGA or the remote memory array device, the space of the local memory occupied by the target data is released.

Referring to FIG. 5 , after backing up the target data to the on-chip memory of the local FPGA or the remote memory array device, the memory mapping (page table entry) of the local memory occupied by the target data is deleted to release the space of the local memory occupied by the target data.

Furthermore, in some embodiments, it also includes:

If the data to be accessed is located in the on-chip memory of the local FPGA, copy the data to be accessed from the on-chip memory of the local FPGA to the host memory, and access the host memory;

If the data to be accessed is located in the remote memory array device, the data to be accessed is copied from the remote memory array device to the host memory, and the host memory is accessed.

In some embodiments, if the data to be accessed is located in the host memory, the data to be accessed in the host memory is directly accessed. If the data to be accessed is located in the on-chip memory of the local FPGA, the data to be accessed is first copied from the on-chip memory of the local FPGA to the host memory through the PCIe bridge, and then the data to be accessed copied from the host memory is accessed. If the data to be accessed is located in a remote memory array device, when the local host and the remote memory array device are connected to the RDMA network through an RDMA transmission module, the data to be accessed is first copied to the host memory through the RDMA transmission module, and then the data to be accessed copied from the host memory is accessed.

Wherein, corresponding to the embodiment in which the remote memory array device includes a remote FPGA and a remote memory, the copying of the to-be-accessed data from the remote memory array device to the host memory includes:

Furthermore, in some embodiments, it also includes:

After the to-be-accessed data is copied from the remote memory array device to the host memory, the space occupied by the to-be-accessed data in the remote memory array device is released.

As shown in FIG5 , after the data to be accessed is copied from the on-chip memory of the local FPGA to the host memory via the PCIe bridge, the space occupied by the data to be accessed in the on-chip memory of the local FPGA is released. After the data to be accessed is copied from the remote memory array device to the host memory via the RDMA module, the space occupied by the data to be accessed in the remote memory array is released.

The releasing of the space occupied by the to-be-accessed data in the remote memory array device comprises:

If the data to be accessed is copied from the remote memory to the local memory, the remote memory is released. The space occupied by the data to be accessed.

That is, if the data to be accessed is located in the on-chip memory of the remote FPGA, after the data to be accessed is copied from the on-chip memory of the remote FPGA to the host memory, the space occupied by the data to be accessed in the on-chip memory of the remote FPGA is released. If the data to be accessed is located in the remote memory, after the data to be accessed is copied from the remote memory to the host memory, the space occupied by the data to be accessed in the remote memory is released.

Furthermore, in some embodiments, it also includes:

When the host memory space of the local host is sufficient, host memory is allocated and memory mapping is established.

Wherein, when the host memory space of the local host is sufficient, the host memory is allocated, and before the memory mapping is established, the following steps are also included:

Determine whether the local host has established memory mapping;

If the local host does not establish a memory mapping, determining whether the host memory space of the local host is sufficient;

As shown in FIG5 , when the application starts to access the host memory, it first determines whether a memory mapping has been established. If so, the memory access instruction is executed to access the host memory. If the memory mapping has not been established, it is determined whether the host memory space of the local host is sufficient. If the host memory space of the local host is sufficient, the host memory is allocated and the memory mapping is established. If the host memory space of the local host is insufficient, steps S101 to S103 are executed. Establishing a memory mapping refers to establishing a mapping relationship between a virtual address and a physical address by creating a page table entry for the MMU (Memory Management Unit) in the CPU to query.

In applications, data writing (such as the operation of assigning a value to the address pointed to by a pointer in C language code) is an essential operation. The following takes the assignment operation as an example to explain an optional implementation method:

The application directly assigns a value to an address. This address is a virtual address and has not yet been assigned an actual physical address, so the CPU will generate a page fault exception.

*p＝A;

When the above statements are executed at the processor level, data assignment instructions are executed, such as "STRB WO, [<address>]".

After the CPU generates a page fault exception, the page fault processing part of the operating system finds that there are not enough local physical addresses for address mapping, so it executes the processing logic of steps S101 to S103, which is recorded as rdma_swap processing logic.

In the rdma_swap processing logic, when it is found that the on-chip memory of the local FPGA is insufficient, the data that has not been used for a long time in the local memory is backed up to the memory of the remote memory array device.

The optional process is:

1. Issue an RDMA_WRITE instruction to the RDMA transport module in the local FPGA.

rdma_sq_wr.opcode = IBV_WR_RDMA_WRITE; //RDMA operation instruction code

rdma_sgl.addr = local_addr; //The local memory address where the data not used for a long time is located

rdma_sq_wr.sg_list＝&rdma_sgl：

rdma_sq_wr.wr.rdma.remote_addr = remote_addr; //remote destination address

ibv_post_send(qp, &rdma_sq_wr, &bad_wr); //Post command to RDMA transmission module

2. Wait for the RDMA transmission module to complete processing.

ibv_poll_cq(cq,1,&wc);

After the RDMA transmission module completes the processing, it deletes the memory mapping of the data that has not been used for a long time, and releases the space for the address that is currently being accessed.

In practical applications, the existing swap processing logic in the operating system as shown in FIG. 2 can be replaced by the rdma_swap processing logic provided in this application. It is also possible to add new logic based on the swap processing logic, that is, to be compatible with the original swap processing logic. If new logic is added based on the swap processing logic, modifications can be made in the "swap processing logic". Before saving the data to the swap partition in the hard disk, first determine whether there is available on-chip memory of the local FPGA or available memory of a remote memory array device. If so, run the processing logic shown in FIG. 5; if not, run the original swap processing logic.

In summary, the memory backup acceleration method provided in the present application uses the memory of the local FPGA on the local host and the memory of the remote memory array device as the physical carrier for backing up the data in the host memory of the local host, replacing the traditional solution of using the hard disk as the data backup carrier, and can effectively improve the speed of system operation.

The present application also provides a memory backup acceleration device, and the device described below can be referred to in correspondence with the method described above. Please refer to Figure 6, which is a schematic diagram of a memory backup acceleration device provided in an embodiment of the present application. As shown in Figure 6, the device includes:

The judgment module 10 is used to judge whether there is allocatable space in the on-chip memory of the local FPGA when the host memory space of the local host is insufficient;

A first backup module 20, configured to back up the target data to the on-chip memory of the local FPGA if there is allocatable space in the on-chip memory of the local FPGA;

The second backup module 30 is used to back up the target data to a remote memory array device if there is no allocatable space in the on-chip memory of the local FPGA.

Based on the above embodiment, as an optional implementation, the second backup module 30 includes:

A first backup unit is configured to transmit the target data to the remote FPGA in the remote memory array device if there is allocatable space in the on-chip memory of the remote FPGA, and store the target data in the on-chip memory of the remote FPGA;

The second backup unit is used to transfer the target data to the remote FPGA if there is no allocatable space in the on-chip memory of the remote FPGA, and store the target data in the remote memory of the remote memory array device via the remote FPGA.

Based on the above embodiment, as an optional implementation manner, the first backup unit and the second backup unit may be used to:

Based on the above embodiment, as an optional implementation manner, it also includes:

A first access module, configured to access the host memory if the data to be accessed is located in the host memory;

A second access module is used for copying the data to be accessed from the on-chip memory of the local FPGA to the host memory and accessing the host memory if the data to be accessed is located in the on-chip memory of the local FPGA;

The third access module is used for copying the data to be accessed from the remote memory array device to the host memory and accessing the host memory if the data to be accessed is located in the remote memory array device.

Based on the above embodiment, as an optional implementation manner, the third access module includes:

A first copying unit, configured to copy the data to be accessed from the on-chip memory of the remote FPGA to the local memory if the data to be accessed is located in the on-chip memory of the remote FPGA of the remote memory array device;

The second copying unit is used for copying the data to be accessed from the remote memory to the local memory if the data to be accessed is located in the remote memory of the remote memory array device.

The first space release module is used to release the space occupied by the data to be accessed in the on-chip memory of the local FPGA after copying the data to be accessed from the on-chip memory of the local FPGA to the host memory.

The second space releasing module is used to release the space occupied by the data to be accessed in the remote memory array device after copying the data to be accessed from the remote memory array device to the host memory.

Based on the above embodiment, as an optional implementation manner, the second space release module includes:

A first releasing unit, configured to release the space occupied by the to-be-accessed data in the on-chip memory of the remote FPGA if the to-be-accessed data is copied from the on-chip memory of the remote FPGA to the local memory;

The second releasing unit is used for releasing the space occupied by the data to be accessed in the remote memory if the data to be accessed is copied from the remote memory to the local memory.

The third space releasing unit is used to release the space of the local memory occupied by the target data after backing up the target data to the on-chip memory of the local FPGA or the remote memory array device.

The memory mapping establishment module is used to allocate host memory and establish memory mapping when the host memory space of the local host is sufficient.

A first determination module is used to determine whether the local host has established a memory mapping;

A second determination module is used to determine whether the host memory space of the local host is sufficient if the local host does not establish a memory mapping;

If the host memory space of the local host is sufficient, the memory mapping establishment module allocates host memory and establishes a memory map.

The recording module is used to record the information of the device where the backed-up target data is located and the address of the memory in the device where the target data is stored.

The memory backup acceleration device provided in the present application uses the memory of the local FPGA on the local host and the memory of the remote memory array device as the physical carrier for backing up the data in the host memory of the local host, replacing the traditional solution of using the hard disk as the data backup carrier, and can effectively improve the speed of system operation.

The present application also provides a memory backup acceleration device, as shown in FIG. 7 , the device includes a memory 1 and a processor 2 .

Memory 1, used for storing computer programs;

Processor 2 is used to execute the computer program to implement the following steps:

When the host memory space of the local host is insufficient, determine whether there is allocatable space in the on-chip memory of the local FPGA; if there is allocatable space in the on-chip memory of the local FPGA, back up the target data to the on-chip memory of the local FPGA; if there is no allocatable space in the on-chip memory of the local FPGA, back up the target data to a remote memory array device.

The memory backup acceleration device provided in this application uses the memory of the local FPGA on the local host and the remote memory array The device's memory serves as a physical carrier for backing up data in the host memory of the local host, replacing the traditional solution of using a hard disk as a data backup carrier, which can effectively improve the speed of system operation.

For an introduction to the equipment provided in this application, please refer to the above method embodiments, and this application will not go into details here.

The present application also provides a non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

The non-volatile readable storage medium provided in the present application uses the memory of the local FPGA on the local host and the memory of the remote memory array device as the physical carrier for backing up the data in the host memory of the local host, replacing the traditional solution of using the hard disk as the data backup carrier, which can effectively improve the speed of system operation.

The non-volatile readable storage medium may include: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

For an introduction to the non-volatile readable storage medium provided in this application, please refer to the above method embodiment, and this application will not go into details here.

The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, and non-volatile readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

The steps of the methods or algorithms described in the embodiments disclosed herein may be implemented directly using hardware, software modules executed by a processor, or a combination of the two. The software modules may be placed in random access memory (RAM), internal memory, read-only storage, or other storage mediums. The memory may be stored in a memory device (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

The memory backup acceleration method, device, equipment and non-volatile readable storage medium provided by the present application are introduced in detail above. Optional examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

A memory backup acceleration method, characterized by comprising:

When the host memory space of the local host is insufficient, it is determined whether there is allocatable space in the on-chip memory of the local FPGA;

If there is allocatable space in the on-chip memory of the local FPGA, backing up the target data to the on-chip memory of the local FPGA;

If there is no allocatable space in the on-chip memory of the local FPGA, the target data is backed up to a remote memory array device.
The memory backup acceleration method according to claim 1, characterized in that backing up the target data to a remote memory array device comprises:

If there is allocatable space in the on-chip memory of the remote FPGA in the remote memory array device, the target data is transmitted to the remote FPGA, and the target data is stored in the on-chip memory of the remote FPGA;

If there is no allocatable space in the on-chip memory of the remote FPGA, the target data is transmitted to the remote FPGA, and the target data is stored in the remote memory of the remote memory array device via the remote FPGA.
The memory backup acceleration method according to claim 1, wherein transmitting the target data to the remote FPGA comprises:

The target data is transmitted to the remote FPGA through the RDMA transmission module of the local FPGA.
The memory backup acceleration method according to claim 1, further comprising:

When accessing data, if the data to be accessed is located in the host memory, accessing the host memory;

If the data to be accessed is located in the on-chip memory of the local FPGA, copying the data to be accessed from the on-chip memory of the local FPGA to the host memory, and accessing the host memory;

If the data to be accessed is located in the remote memory array device, the data to be accessed is copied from the remote memory array device to the host memory, and the host memory is accessed.
The memory backup acceleration method according to claim 1 is characterized in that, before determining whether there is allocatable space in the on-chip memory of the local FPGA when the host memory space of the local host is insufficient, the method further comprises:

Comparing the host memory space of the local host with a first preset threshold;

In a case where the host memory space of the local host is less than or equal to the first preset threshold, it is determined that the host memory space of the local host is insufficient.
The memory backup acceleration method according to claim 1, characterized in that before backing up the target data to the remote memory array device if there is no allocatable space in the on-chip memory of the local FPGA, the method further comprises:

When the remaining capacity of the local FPGA drops to a second preset threshold, it is determined that there is no allocatable space in the on-chip memory of the local FPGA, or,

When the remaining capacity of the local FPGA is smaller than the size of the target data, it is determined that no allocatable space exists in the on-chip memory of the local FPGA.
The memory backup acceleration method according to claim 4, characterized in that copying the to-be-accessed data from the remote memory array device to the host memory comprises:

If the data to be accessed is located in the on-chip memory of the remote FPGA of the remote memory array device, copying the data to be accessed from the on-chip memory of the remote FPGA to the local memory;

If the data to be accessed is located in the remote memory of the remote memory array device, the data to be accessed is copied from the remote memory to the local memory.
The memory backup acceleration method according to claim 7, further comprising:

After the to-be-accessed data is copied from the on-chip memory of the local FPGA to the host memory, the space occupied by the to-be-accessed data in the on-chip memory of the local FPGA is released.
The memory backup acceleration method according to claim 7, further comprising:

After the to-be-accessed data is copied from the remote memory array device to the host memory, the space occupied by the to-be-accessed data in the remote memory array device is released.
The memory backup acceleration method according to claim 9, wherein releasing the space occupied by the to-be-accessed data in the remote memory array device comprises:

If the data to be accessed is copied from the on-chip memory of the remote FPGA to the local memory, the space occupied by the data to be accessed in the on-chip memory of the remote FPGA is released;

If the data to be accessed is copied from the remote memory to the local memory, the space occupied by the data to be accessed in the remote memory is released.
The memory backup acceleration method according to claim 1, further comprising:

After backing up the target data to the on-chip memory of the local FPGA or the remote memory array device, the space of the local memory occupied by the target data is released.
The memory backup acceleration method according to claim 11, characterized in that the releasing of the space of the local memory occupied by the target data comprises:

Delete the memory mapping of the local memory occupied by the target data.
The memory backup acceleration method according to claim 1, further comprising:

When the host memory space of the local host is sufficient, host memory is allocated and memory mapping is established.
The memory backup acceleration method according to claim 13, characterized in that when the host memory space of the local host is sufficient, the host memory is allocated, and before the memory mapping is established, it also includes:

Determine whether the local host has established memory mapping;

If the local host does not establish a memory mapping, determining whether the host memory space of the local host is sufficient;

If the host memory space of the local host is sufficient, host memory is allocated and a memory mapping is established.
The memory backup acceleration method according to claim 14, wherein the establishing of the memory mapping comprises:

The mapping relationship between the virtual address and the physical address is established by creating a table entry of the page table to obtain the memory mapping.
The memory backup acceleration method according to claim 1, further comprising:

Record the information of the device where the backed-up target data is located and the address of the memory in the device that stores the target data.
The memory backup acceleration method according to claim 1, wherein the information of the device where the target data to be backed up is located includes:

The number of the local FPGA of the target data and the number of the remote memory array device are determined as the information of the device where the target data is located and recorded, wherein the information of the device where the target data is located is used to re-copy the backed-up target data to the local memory when the target data is accessed.
A memory backup acceleration device, characterized by comprising:

A judgment module, used for judging whether there is allocatable space in the on-chip memory of the local FPGA when the host memory space of the local host is insufficient;

A first backup module, configured to back up the target data to the on-chip memory of the local FPGA if there is allocatable space in the on-chip memory of the local FPGA;

The second backup module is used to back up the target data to a remote memory array device if there is no allocatable space in the on-chip memory of the local FPGA.
A memory backup acceleration device, comprising:

Memory for storing computer programs;

A processor, configured to implement the steps of the memory backup acceleration method as described in any one of claims 1 to 12 when executing the computer program.
A non-volatile readable storage medium, characterized in that a computer program is stored on the non-volatile readable storage medium, and when the computer program is executed by a processor, the steps of the memory backup acceleration method as described in any one of claims 1 to 12 are implemented.