WO2024105811A1 - Error factor analysis device and error factor analysis method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 217
- 238000000556 factor analysis Methods 0.000 title claims abstract description 12
- 230000008569 process Effects 0.000 claims abstract description 147
- 238000005259 measurement Methods 0.000 claims abstract description 114
- 230000005856 abnormality Effects 0.000 claims abstract description 67
- 238000007689 inspection Methods 0.000 claims abstract description 53
- 238000004364 calculation method Methods 0.000 claims abstract description 38
- 230000002159 abnormal effect Effects 0.000 claims abstract description 20
- 238000004458 analytical method Methods 0.000 claims description 53
- 238000012937 correction Methods 0.000 claims description 16
- 230000002596 correlated effect Effects 0.000 claims description 6
- 238000011144 upstream manufacturing Methods 0.000 claims description 6
- 239000000284 extract Substances 0.000 claims description 3
- 238000002372 labelling Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 44
- 238000003860 storage Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000001514 detection method Methods 0.000 description 9
- 238000013145 classification model Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 230000010365 information processing Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000013075 data extraction Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 238000010801 machine learning Methods 0.000 description 4
- 238000001878 scanning electron micrograph Methods 0.000 description 4
- 238000004422 calculation algorithm Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000001364 causal effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000003066 decision tree Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007637 random forest analysis Methods 0.000 description 1
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- the present invention relates to an error cause analysis device and an error cause analysis method that analyze the causes of errors that occur in inspection equipment, etc.
- Semiconductor inspection equipment and semiconductor measurement equipment perform inspections at each inspection point on the surface of a semiconductor wafer and measurements at each measurement point according to set parameters called recipes. However, if an insufficiently adjusted recipe is used or if the characteristics of the equipment change over time, errors may occur in the inspection or measurement, which is one of the factors that reduce the equipment's operating rate.
- equipment users often have to perform manual tasks such as checking each inspection value, each measurement value, and images captured by a scanning electron microscope (hereinafter referred to as SEM images), and analyzing the cause of the error takes a considerable amount of time.
- One of the challenges in error cause analysis is the need to accurately estimate the process that caused the error.
- Semiconductor inspection and measurement processes can be further broken down into multiple sub-processes, such as alignment, addressing, and length measurement.
- a matching score is calculated between a template image registered in advance in the recipe and an SEM image of the measurement point. If the matching score is equal to or greater than a threshold, it is determined that pattern detection was successful and the process moves on to the next sub-process.
- the board inspection system of Patent Document 1 is known as a conventional technology for estimating the sub-process in which an error or defect occurred.
- the analytical information storage unit 202 is provided with an analytical program database 221, an analytical program selection table 222, a cause-countermeasure table 223, a cause-basis table 224, a display image database 225, and the like.”
- Figures 12 to 14 of this document show examples of the configuration of each table, and Figure 15 discloses a process for identifying the cause of defects using each table.
- Patent Document 1 discloses a technology in which a table of the characteristics of the measured values for each process and the causal process is constructed in advance, and the causal process is estimated by referring to this table.
- Another method is to apply anomaly detection techniques and infer the causative process by determining whether or not there is an anomaly in each process based on the degree of deviation from pre-collected normal data.
- This requires the task of defining normal data for tens or hundreds of recipes that are frequently changed, which is difficult and requires knowledge and effort to distinguish normal data.
- the present invention aims to provide a technology that can estimate the process that caused a detected error and deduce the cause of the error by analyzing the data of the process that caused the error, without constructing a relationship table between measured values and the process that caused the error, or collecting and defining normal data.
- the error cause analysis device of the present invention is an error cause analysis device that, when a data set measured by an inspection device contains an error, estimates a sub-process causing an error from a plurality of sub-processes constituting an inspection process based on the data set, and is equipped with an error label assignment unit that estimates an error-related measurement point related to the measurement point where the error was detected from a measurement point of a sub-process other than the sub-process including the measurement point where the error was detected, and assigns an error label to the measurement point where the error was detected and the error-related measurement point, an error correlation calculation unit that estimates a feature value highly correlated with the occurrence of an error for each sub-process from the difference in data between the measurement point to which the error label is assigned and the measurement point to which the error label is not assigned, an abnormality degree calculation unit that calculates a feature-based abnormality degree for each sub-process according to the degree of statistical deviation between the data of the measurement point to which the error label is assigned and the measurement point to which the error
- the error cause analysis device and error cause analysis method of the present invention make it possible to estimate the process causing a detected error, even if the recipe for the product or measurement/inspection device is changed, without having to create various tables for each recipe or collect and define normal data.
- FIG. 1 is a schematic diagram showing a configuration example of an information processing system according to a first embodiment. An example of the inspection process of semiconductor inspection equipment.
- FIG. 2 is a functional block diagram of the error cause analysis device according to the first embodiment.
- 4 is a process flowchart of the error cause analysis device according to the first embodiment. An example of process-specific data with error labels added. An example of analysis results displayed on the device.
- FIG. 11 is a functional block diagram of an error cause analysis device according to a second embodiment.
- FIG. 11 is a schematic diagram for explaining a method for calculating a total abnormality degree according to the second embodiment.
- FIG. 11 is a functional block diagram of an error cause analysis device according to a third embodiment.
- FIG. 13 is a schematic diagram for explaining a method for calculating an error factor estimation result according to the third embodiment.
- the term "semiconductor inspection device” includes not only a device that measures the dimensions of a pattern formed on the surface of a semiconductor wafer, but also a device that inspects the presence or absence of defects in a pattern formed on the surface of a semiconductor wafer, a device that inspects the presence or absence of defects in a bare wafer on which no pattern is formed, and a composite device that combines these devices.
- “inspection” is also used to mean measurement
- “inspection operation” is also used to mean measurement operation.
- “inspection target” refers not only to a wafer that is the object of measurement or inspection, but also to a region on the wafer that is the object of measurement or inspection.
- "error” includes not only measurement problems and device failures, but also warning messages and other signs of errors.
- (Outline of the information processing system) 1 is a schematic diagram showing an example of the configuration of an information processing system 100 according to this embodiment.
- the information processing system 100 includes a semiconductor inspection device 1, a database 2, an error cause analysis device 3, a terminal 4, and a network N. Each of these will be described in turn below.
- the semiconductor inspection device 1 is a device that inspects the dimensions of patterns formed on the surface of a semiconductor wafer, and is connected to a database 2 and an error cause analysis device 3 via a network N.
- the database 2 is a recording device that records data sent from the semiconductor inspection device 1, such as device data, recipes, measurement results, and error results.
- the error cause analysis device 3 is a device for analyzing the cause of an error if an error occurs in the inspection process performed by the semiconductor inspection equipment 1, and is specifically a computer equipped with hardware such as a calculation device such as a CPU, a storage device such as a semiconductor memory, and a communication device.
- This error cause analysis device 3 may be on-premise operated within a facility managed by the user of the semiconductor inspection equipment 1, or it may be a cloud operated outside the facility.
- the functions of the error cause analysis device 3 may also be incorporated into the semiconductor inspection equipment 1.
- the terminal 4 is a device equipped with a display that functions as a GUI (Graphical User Interface) when presenting the analysis results of the error cause analysis device 3 to the user, and is connected to the error cause analysis device 3 so as to be able to communicate with it via a wired or wireless communication line.
- GUI Graphic User Interface
- Data recorded in database 2 The data transmitted from the semiconductor inspection equipment 1, recorded in the database 2, and further analyzed by the error cause analysis device 3 includes, for example, equipment data, recipes, measurement results, and error results. Each piece of data will be explained below in order.
- the equipment data includes equipment-specific parameters, equipment difference correction data, and observation condition parameters.
- the equipment-specific parameters are correction parameters used to operate the semiconductor inspection equipment 1 in accordance with the prescribed specifications.
- the equipment difference correction data are parameters used to correct the equipment differences between semiconductor inspection equipment.
- the observation condition parameters are parameters that specify the observation conditions of a scanning electron microscope (SEM), such as the accelerating voltage of the electron optical system, for example.
- the recipe includes a wafer map, various parameters (alignment parameters, addressing parameters, length measurement parameters), a template image, etc.
- the wafer map is a coordinate map (e.g., pattern coordinates) of the surface of the semiconductor wafer.
- the alignment parameters are, for example, parameters used to correct the misalignment between the coordinate system of the surface of the semiconductor wafer and the coordinate system inside the semiconductor inspection device 1.
- the addressing parameters are, for example, information that identifies a characteristic pattern that exists within the inspection target area among the patterns formed on the surface of the semiconductor wafer.
- the length measurement parameters are parameters that describe the conditions for measuring length, and are, for example, parameters that specify which part of the pattern is to be measured in length.
- the template image is a reference image for detecting measurement points by pattern matching.
- the recipe may include the number of measurement points, coordinate information of the measurement points (Evaluation Points: EP), imaging conditions for capturing images, etc.
- the recipe may also include the coordinates and imaging conditions of images captured in the preparation stage for measuring the measurement points in addition to the measurement points.
- the measurement results include length measurement results, image data, and an operation log.
- the length measurement results describe the results of measuring the length of the pattern on the surface of the semiconductor wafer.
- the image data is an observed image of the semiconductor wafer.
- the operation log is data describing the internal state of the semiconductor inspection device 1 in each operation process of alignment, addressing, and length measurement. For example, this includes the operating voltage of each component, the coordinates of the observation field, etc.
- the error result is a parameter that indicates in which operation process (alignment, addressing, or length measurement) the error occurred if an error occurred.
- step P1 shows an example of an inspection process of the semiconductor inspection device 1.
- the inspection process illustrated here is decomposed into five operation steps (sub-steps), from step P1 to step P5. That is, in step P1, the positional deviation between the measurement wafer and the stage of the semiconductor inspection device is corrected by alignment in the optical (OM) mode. Next, in step P2, the positional deviation between the measurement wafer and the stage is corrected by alignment in the electron beam (SEM) mode. After that, in steps P3 and P4, the field of view is moved to the measurement coordinates by addressing. Finally, in step P5, the dimensions of the pattern formed on the surface of the measurement wafer are measured.
- the semiconductor inspection device 1 inspects the semiconductor wafer.
- a matching score is calculated between the template image registered in the recipe and the SEM image captured of the measurement point, and if the matching score is equal to or greater than a threshold, the pattern detection is deemed successful and the process moves to the next operation step.
- this threshold is inappropriate, the process may slip through the error judgment and move on to the next operation step even if the pattern detection fails, for example, if a different position than intended is detected.
- the cause of the error is in the operation step where the slip-through occurred, which is different from the operation step where the error was actually detected.
- an error cause analysis device 3 is provided as follows so that even if an error is detected in a later operation process, the previous operation process that caused the error can be inferred and the cause of the error can be accurately analyzed based on the data acquired in the previous operation process.
- the error factor analysis device 3 includes a process-specific data extraction unit 31, an error label assignment unit 32, an error correlation calculation unit 33, an abnormality calculation unit 34, an abnormality storage unit 35, and an abnormal process estimation unit 36, and outputs an abnormal process estimation result D1 using these units.
- the error correlation calculation unit 33 includes a feature generation unit 33a, an error classification model learning unit 33b, and a model analysis unit 33c
- the abnormality calculation unit 34 includes a feature extraction unit 34a and a feature base calculation unit 34b.
- Each functional unit is realized by a calculation unit of the error factor analysis device 3, which is a general computer, executing a predetermined program loaded into a storage device.
- FIG. 4 is a processing flowchart of the error cause analysis device 3. Below, the details of the error cause analysis process by the error cause analysis device 3 will be explained with reference to FIG. 3 and FIG. 4 as appropriate.
- step S1 the process-specific data extraction unit 31 acquires from the database 2 a data set measured by the semiconductor inspection device 1 using a recipe for which an error cause is to be analyzed, and divides the data by operation process.
- an identification number is given to the data set collected in the database 2 to distinguish which operation process the data was measured in, so that the data set can be divided into measurement data by operation process using this identification number.
- Operation steps that may be related to this error can be, for example, data on the operation step where the error was detected and its upstream operation steps, a series of operation steps that repeat addressing and length measurement, operation steps with close measurement timing, etc.
- Step S2 the error label assignment unit 32 assigns an error label to the measurement point where an error was detected for the process data extracted in step S1, and also assigns error labels to related measurement points (error-related measurement points) that are estimated to affect the inspection performance of this measurement point.
- FIG. 5 is a diagram showing excerpts of process P1 data and process P5 data constituting a data set measured by the semiconductor inspection device 1.
- the "wafer INDEX" in the first column from the left is an identification number for distinguishing the semiconductor wafer.
- the "measurement No.” in the second column from the left is a serial number indicating which measurement point on the same semiconductor wafer it is.
- the method of estimating the error-related measurement point is, for example, if an error is detected in the measurement item with "measurement No.” "12" of a semiconductor wafer with "wafer INDEX” "XXX001" in the process P5 data, the measurement point with the same "wafer INDEX” as the semiconductor wafer and a younger "measurement No.” (for example, the measurement point with "wafer INDEX” "XXX001” and “measurement No.” "0” or "1” in the process P1 data) is estimated to be the error-related measurement point.
- the error label assignment unit 32 then assigns the error label "1" to the error-related measurement point thus estimated and the error detection measurement point that is its origin, as shown in the figure.
- step S3 the error correlation calculation unit 33 selects one of the process-specific data extracted in step S1 for which the anomaly degree calculation has not been completed (the process P1 data or the process P5 data in the example of FIG. 5) as the target for processing in step S4 and thereafter.
- Step S4 the error correlation calculation unit 33 generates features suitable for input to a machine learning model from the data selected in step S3 (for example, the process P1 data in FIG. 5). To this end, the following process is specifically executed.
- the feature generator 33a calculates the correlation of each feature with respect to the occurrence of an error from the difference in data between measurement points with and without the error labels added in step S2.
- the feature generator 33a uses the process-specific data to be processed to generate features suitable for input to a machine learning model that distinguishes between data with and without error labels.
- the generation of features can use, for example, scaling and statistical processing of measurement data, encoding of categorical variables, creation of composite features by combining multiple data such as interaction features, etc.
- the error classification model learning unit 33b uses as input the features generated by the feature generation unit 33a and the error labels assigned in step S2, and learns an error classification model that classifies data from measurement points with error labels based on the difference in tendency between data from measurement points without error labels.
- This error classification model may be generated using any machine learning algorithm, such as a decision tree-based algorithm such as Random Forest or XGBoost, or a Neural Network.
- the model analysis unit 33c calculates the degree of correlation of the error classification model learned by the error classification model learning unit 33b, indicating the degree to which each input feature quantity influenced the error prediction result, which is the model output. For example, when the error detection model is constructed using an algorithm based on a decision tree, this correlation can be evaluated by the feature importance, which is calculated based on the number of times each feature quantity appears in a branch in the model and the improvement value of the objective function, or the SHAP (Shapley Additive exPlanations) value, which calculates the degree of correlation of the value of each feature quantity with the model output.
- the feature importance which is calculated based on the number of times each feature quantity appears in a branch in the model and the improvement value of the objective function
- SHAP Shape Additive exPlanations
- Step S5 the feature extraction unit 34a extracts the feature having the high correlation calculated in step S4.
- the extraction method may be a method of extracting the top N feature amounts in descending order of correlation, or a method of extracting feature amounts having a correlation equal to or greater than a preset threshold.
- Step S6 the feature-based calculation unit 34b calculates the degree of deviation between the data of the measurement point to which the error label of the feature highly correlated with the error extracted in step S5 is assigned and the data of the measurement point without the error label as the degree of abnormality of the operation process.
- the degree of deviation for example, the Euclidean distance or the Mahalanobis distance can be used.
- Step S7 the abnormality degree storage unit 35 stores the abnormality degree for each operation process calculated in step S6.
- step S8 it is determined whether the processes from step S3 to step S7 have been performed for all the operation process data extracted in step S1. If the requirements are met, the process proceeds to step S9, and if the requirements are not met, the processes from step S3 to step S7 are repeated until the degree of anomaly is calculated for all the operation process data.
- step S9 the abnormal process estimation unit 36 estimates the operation process that caused the error by using the degree of abnormality for each operation process stored in step S7.
- the method for estimating the error causing process can be, for example, the operation process with the highest degree of abnormality, the most upstream operation process with a degree of abnormality equal to or higher than a preset threshold, or an operation process estimated using a machine learning model that has learned the relationship between the feature amount highly correlated with the error correlation, the degree of abnormality for each process, and the causing process.
- the estimation result of the process causing the error in this step is output as abnormal process estimation result D1.
- the abnormal process estimation result D1 is an error analysis result including the degree of abnormality for each operation process stored in the abnormality degree storage unit 35 and the process causing the error estimated by the abnormal process estimation unit 36. These error analysis results are presented to the user via terminal 4, which is a GUI.
- Figure 6 shows an example of how to present the error analysis results to the user.
- the level of abnormality for each operation process is indicated by the length of the bar, and process P2, which is presumed to be the cause of the error by the processing in the flowchart of Figure 4, is shown in a different color (darker color) from the other processes.
- process P5 which is presumed to be the cause of the error by the processing in the flowchart of Figure 4
- process P5 which is presumed to be the cause of the error by the processing in the flowchart of Figure 4
- the error information generated is used as is to estimate the error-related measurement points contained in the data of each preceding operation process.Then, the error-related measurement points are regarded as error data, and the deviation between the error data and other data is calculated as the degree of anomaly for each process.
- the error factor analysis device 3 of the second embodiment is obtained by adding a matching score-based anomaly degree calculation unit 37 and a total anomaly degree calculation unit 38 to the error factor analysis device 3 of the first embodiment. The details of these will be explained below.
- the matching score-based anomaly calculation unit 37 calculates the degree of anomaly between the data of a measurement point to which an error label of the matching score is assigned and the data of a measurement point without an error label for each process data that may be the cause of an error extracted by the process data extraction unit 31.
- This degree of anomaly can be a Z score based on the average value or standard deviation of the original data.
- the matching score-based anomaly degree for each process is stored in the anomaly storage unit 35.
- the overall abnormality degree calculation unit 38 calculates an overall degree of abnormality from each degree of abnormality stored in the abnormality degree storage unit 35.
- a schematic diagram of this overall abnormality degree calculation is shown in Fig. 8.
- the overall abnormality degree for each process is calculated from the feature-based abnormality degree and the matching score-based abnormality degree.
- This calculation method can be, for example, a method of simply adding up both the abnormality degrees for each process, a method of taking the maximum value of both, a method of multiplying each by a preset weight and then adding them up, etc.
- the abnormal process estimation unit 36 uses the overall abnormality degree for each process calculated by the overall abnormality degree calculation unit 38 to estimate the process that caused the error based on the level of the abnormality and a threshold value, as in the first embodiment.
- the terminal 4 which is a GUI, may display only the final overall abnormality degree, or may display both the feature-based abnormality degree and the matching score-based abnormality degree, which are the basis for calculating the overall abnormality degree, together with the overall abnormality degree.
- the process estimated by the abnormal process estimation unit 36 to be the cause of the error is shown in a different color (darker color) from the other processes.
- the estimation method of the error process employed by the abnormal process estimation unit 36 is, for example, to estimate the most upstream process whose abnormality degree exceeds a threshold as the process causing the error, then as in the example of FIG. 8, the most upstream process P1 whose abnormality degree exceeds a threshold may be estimated to be the cause of the error, rather than process P2 whose abnormality degree is the highest.
- the error factor analysis device 3 of the third embodiment is different from that of the first embodiment in that it includes a process-specific error factor estimation unit 39, an error dictionary 3A, and an error factor probability correction unit 3B. The details of these will be explained below in order.
- the process-specific error factor estimation unit 39 searches the error dictionary 3A for items with high similarity using the feature amount, its value, correlation degree, etc. that are highly correlated with the error calculated by the error correlation calculation unit 33, and obtains one or more searched error factors and their similarities for each process as error factor probabilities D2. For example, estimation by collaborative filtering or rank learning can be used as a method for calculating this similarity.
- the error dictionary 3A stores combinations of feature quantities, their values, and correlation degrees, and their error causes in association with each other.
- the method of storing the error features and their causes may be systematized in a table format based on past know-how, or past error data and their error causes may be stored.
- the error factor probability correction unit 3B corrects the process-specific error factor probability D2 calculated by the process-specific error factor estimation unit 39, using the process-specific abnormality degree stored in the abnormality degree storage unit 35.
- a schematic diagram of this correction method is shown in FIG.
- the top three error factors and their error probabilities calculated by the process-specific error factor estimation unit 39 are obtained for each process. These error probabilities are corrected by the degree of abnormality for each process stored in the degree of abnormality storage unit 35, and the error probability with the highest degree of error after correction is obtained together with the process number as the error factor estimation result D3.
- the degree of abnormality value may be normalized by [0.0-1.0] and multiplied by the error probability, or a coefficient may be calculated so that processes with an abnormality degree above a threshold are increased and processes with an abnormality degree above the threshold are decreased, and the coefficient may be multiplied by the error probability.
- the error factor estimation result D3 obtained in this way is presented to the user via terminal 4.
- the estimated probability of the error factor obtained for each process is corrected by the abnormality degree for each process, so that the error factor according to the abnormality degree for each process can be estimated.
- the error factor for each process can be extracted and presented to the user.
- the present disclosure is not limited to the above-described embodiments, and includes various modified examples.
- the above-described embodiments have been described in detail to clearly explain the present disclosure, and it is not necessary to include all of the configurations described.
- a part of an embodiment can be replaced with a configuration of another embodiment.
- a configuration of another embodiment can be added to a configuration of an embodiment.
- a part of the configuration of each embodiment can be added to, deleted from, or replaced with a part of the configuration of another embodiment.
- two methods for calculating the degree of anomaly for each process are used: a feature-based degree of anomaly and a matching score-based degree of anomaly.
- three or more other methods for calculating the degree of anomaly may be used.
- Example 3 a process-specific error factor estimation unit 39, an error dictionary 3A, and an error factor probability correction unit 3B are added to the configuration of Example 1, but these may also be added to the configuration of Example 2.
- the information stored in the error dictionary 3A may include recipe modification suggestions, and the error cause and the recipe modification suggestions may be presented together as information presented to the user in the error cause estimation result D3.
- 100 Information processing system
- 1 Semiconductor inspection device
- 2 Database
- 3 Error factor analysis device
- 31 Process-specific data extraction unit
- 32 Error label assignment unit
- 33 Error correlation calculation unit
- 33a Feature generation unit
- 33b Error classification model learning unit
- 33c Model analysis unit
- 34 Anomaly calculation unit
- 34a Feature extraction unit
- 34b Anomaly calculation unit
- 35 Anomaly storage unit
- 36 Abnormal process estimation unit
- 37 Matching score-based anomaly calculation unit
- 38 Overall anomaly calculation unit
- 39 Process-specific error factor estimation unit
- 3A Error dictionary
- 3B Error factor probability correction unit
- 4 Terminal
- D1 Abnormal process estimation result
- D2 Error factor probability
- D3 Error factor estimation result
- N Network
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Abstract
This error factor analysis device estimates a sub-process that is an error cause from a plurality of sub-processes constituting an inspection process on the basis of a data set measured by an inspection device, and comprises: an error label affixing unit that estimates, from measurement points of sub-processes different from a sub-process including a measurement point where an error is detected, an error-related measurement point related to the measurement point where the error is detected, and affixes an error label to the measurement point where the error is detected and the error-related measurement point; an error correlation calculation unit that estimates a feature quantity having a high correlation to the occurrence of the error in each sub-process from a difference in data between the measurement points to which the error label is affixed and the measurement points to which the error label is not affixed; an abnormality degree calculation unit that, with respect to the feature quantity having a high correlation, calculates the feature quantity-based abnormality degree in each sub-process in accordance with the degree of statistical divergence of data between the measurement points to which the error label is affixed and the measurement points to which the error label is not affixed; and an abnormal process estimation unit that, on the basis of the abnormality degree in each sub-process, estimates the sub-process that is the error cause.
Description
本発明は、検査装置等で発生したエラーの要因を解析するエラー要因解析装置、および、エラー要因解析方法に関する。
The present invention relates to an error cause analysis device and an error cause analysis method that analyze the causes of errors that occur in inspection equipment, etc.
半導体検査装置や半導体計測装置は、レシピと呼ばれる設定パラメータに従って、半導体ウエハの表面における検査点毎に検査を実施したり、測定点毎に計測を実施したりする。しかし、調整不十分なレシピを使用する場合や、経時変化によって装置の特性が変わった場合などには、検査や計測にエラーが生じる可能性があり、装置の稼働率を低下させる一因となっている。この種のエラーの要因を解析する場合、装置のユーザは、各検査値・各測定値や、走査型電子顕微鏡の撮像画像(以下、SEM画像と称する)を確認するなどのマニュアル作業を実施しなければならないことが多く、エラー要因の解析に相当の時間を要していた。
Semiconductor inspection equipment and semiconductor measurement equipment perform inspections at each inspection point on the surface of a semiconductor wafer and measurements at each measurement point according to set parameters called recipes. However, if an insufficiently adjusted recipe is used or if the characteristics of the equipment change over time, errors may occur in the inspection or measurement, which is one of the factors that reduce the equipment's operating rate. When analyzing the causes of this type of error, equipment users often have to perform manual tasks such as checking each inspection value, each measurement value, and images captured by a scanning electron microscope (hereinafter referred to as SEM images), and analyzing the cause of the error takes a considerable amount of time.
エラー要因解析における課題の一つとして、エラーの原因工程を正確に推定しなければならないことがある。半導体の検査工程や計測工程は、更に、アライメント、アドレッシング、測長などの複数の小工程に分解でき、各小工程では予めレシピに登録されたテンプレート画像と測定点を撮像したSEM画像のマッチングスコアを算出し、マッチングスコアが閾値以上であるとパターン検出成功と判断して次の小工程に移行している。
One of the challenges in error cause analysis is the need to accurately estimate the process that caused the error. Semiconductor inspection and measurement processes can be further broken down into multiple sub-processes, such as alignment, addressing, and length measurement. In each sub-process, a matching score is calculated between a template image registered in advance in the recipe and an SEM image of the measurement point. If the matching score is equal to or greater than a threshold, it is determined that pattern detection was successful and the process moves on to the next sub-process.
しかしながら、この閾値の設定が不適切であれば、本来はパターン検出に失敗したと判定すべき小工程であるにもかかわらず、エラー判定をすり抜けて次の小工程に移行してしまい、実際にはエラーのない後段の小工程にエラー原因があると誤った推定をすることがある。このため、エラー要因を正確に解析するには、エラーの発生した小工程を正確に推定することが重要となる。
However, if this threshold is set inappropriately, a sub-process that should have been determined to have failed pattern detection may slip through the error detection and move on to the next sub-process, resulting in the erroneous assumption that the cause of the error is in a subsequent sub-process that is actually error-free. For this reason, to accurately analyze the cause of the error, it is important to accurately estimate the sub-process in which the error occurred.
ここで、エラーや不具合が発生した小工程を推定する従来技術として、特許文献1の基板検査システムが知られている。例えば、同文献の要約書には「熟練者でなくとも、不良の原因を容易に認識できるようにする。」と記載されており、段落0056には「分析用情報記憶部202には、分析用プログラムデータベース221、分析用プログラム選択テーブル222、原因-対策テーブル223、原因-根拠テーブル224、表示用画像データベース225などが設けられる。」と記載されている。また、同文献の図12から図14には、各テーブルの構成が例示されており、図15には各テーブルを用いた不良原因の特定処理が開示されている。
Here, the board inspection system of Patent Document 1 is known as a conventional technology for estimating the sub-process in which an error or defect occurred. For example, the abstract of this document states, "The system enables even non-experts to easily recognize the cause of defects," and paragraph 0056 states, "The analytical information storage unit 202 is provided with an analytical program database 221, an analytical program selection table 222, a cause-countermeasure table 223, a cause-basis table 224, a display image database 225, and the like." Additionally, Figures 12 to 14 of this document show examples of the configuration of each table, and Figure 15 discloses a process for identifying the cause of defects using each table.
このように、特許文献1には、各工程の測定値の特徴と原因工程のテーブルを予め構築しておき、このテーブルを参照することで原因工程を推定する技術が開示されている。
In this way, Patent Document 1 discloses a technology in which a table of the characteristics of the measured values for each process and the causal process is constructed in advance, and the causal process is estimated by referring to this table.
ここで、半導体検査装置や半導体計測装置で用いる検査・計測レシピを変更すると、エラー発生のメカニズムも変化するため、特許文献1の不良原因特定処理を利用するには、レシピ毎に各種テーブルを構築する必要がある。多量少品種の半導体製品を製造する生産工程であれば、同じレシピを長期間使用できるため、レシピの切り替えの毎に各種テーブルを構築しても、その労力はさほど大きくない。しかしながら、少量多品種の半導体製品を製造する生産工程であれば、レシピを頻繁に切り替える必要があるため、レシピの切り替えの毎に各種テーブルを構築するのは、現実的ではない。
Here, when the inspection and measurement recipes used in the semiconductor inspection equipment or semiconductor measurement equipment are changed, the mechanism by which errors occur also changes, so in order to use the defect cause identification process of Patent Document 1, it is necessary to build various tables for each recipe. In a production process that manufactures a small variety of semiconductor products in large quantities, the same recipe can be used for a long period of time, so the effort required to build various tables each time the recipe is changed is not that great. However, in a production process that manufactures a large variety of semiconductor products in small quantities, recipes must be changed frequently, so it is not realistic to build various tables each time the recipe is changed.
また、別の手法として異常検知の手法を応用し、予め収集した正常データとの乖離度から各工程の異常の有無を判定することで原因工程を推定する方法が考えられる。しかしながら、この場合は、頻繁に切り替わる数十、数百のレシピごとに正常データを定義する作業が必要となるため、正常データを見分ける知識や工数が必要であり困難である。
Another method is to apply anomaly detection techniques and infer the causative process by determining whether or not there is an anomaly in each process based on the degree of deviation from pre-collected normal data. However, this requires the task of defining normal data for tens or hundreds of recipes that are frequently changed, which is difficult and requires knowledge and effort to distinguish normal data.
そこで、本発明は、測定値とエラー原因工程の関係テーブルを構築したり、正常データの収集や定義をしたりすることなく、検知されたエラーの原因工程を推定し、このエラー原因工程のデータを解析することでエラー要因を推定可能な技術を提供することを目的とする。
The present invention aims to provide a technology that can estimate the process that caused a detected error and deduce the cause of the error by analyzing the data of the process that caused the error, without constructing a relationship table between measured values and the process that caused the error, or collecting and defining normal data.
上記課題を解決するために、本発明にエラー要因解析装置は、検査装置で計測したデータセットがエラーを含む場合、前記データセットに基づいて、検査工程を構成する複数の小工程からエラー原因の小工程を推定するエラー要因解析装置であって、エラーが検知された測定点を含む小工程とは異なる小工程の測定点から、エラーが検知された測定点に関連するエラー関連測定点を推定すると共に、前記エラーが検知された測定点および前記エラー関連測定点にエラーラベルを付与するエラーラベル付与部と、前記エラーラベルが付与された測定点と付与されない測定点のデータの違いから、エラー発生に相関の大きい特徴量を小工程毎に推定するエラー相関計算部と、前記相関の大きい特徴量について、エラーラベルが付与された測定点と付与されない測定点のデータの統計的な乖離の度合いに応じて、特徴量ベースの異常度を小工程毎に計算する異常度計算部と、小工程毎の異常度に基づきエラー原因の小工程を推定する異常工程推定部と、を備えるものとした。
In order to solve the above problem, the error cause analysis device of the present invention is an error cause analysis device that, when a data set measured by an inspection device contains an error, estimates a sub-process causing an error from a plurality of sub-processes constituting an inspection process based on the data set, and is equipped with an error label assignment unit that estimates an error-related measurement point related to the measurement point where the error was detected from a measurement point of a sub-process other than the sub-process including the measurement point where the error was detected, and assigns an error label to the measurement point where the error was detected and the error-related measurement point, an error correlation calculation unit that estimates a feature value highly correlated with the occurrence of an error for each sub-process from the difference in data between the measurement point to which the error label is assigned and the measurement point to which the error label is not assigned, an abnormality degree calculation unit that calculates a feature-based abnormality degree for each sub-process according to the degree of statistical deviation between the data of the measurement point to which the error label is assigned and the measurement point to which the error label is not assigned, for the feature value with high correlation, and an abnormality process estimation unit that estimates the sub-process causing the error based on the abnormality degree for each sub-process.
本発明のエラー要因解析装置、および、エラー要因解析方法によれば、製品や計測・検査装置のレシピが変更になった場合においても、レシピ毎に各種テーブルを構築したり、正常データの収集や定義をしたりすることなく、検知されたエラーの原因工程を推定することが可能となる。
The error cause analysis device and error cause analysis method of the present invention make it possible to estimate the process causing a detected error, even if the recipe for the product or measurement/inspection device is changed, without having to create various tables for each recipe or collect and define normal data.
上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。
Problems, configurations and advantages other than those mentioned above will become clear from the description of the embodiments below.
以下、図面を用いて、本発明のエラー要因解析装置、および、エラー要因解析方法の実施例を説明する。なお、以下において、「半導体検査装置」とは、半導体ウエハの表面に形成されたパターンの寸法を計測する装置だけでなく、半導体ウエハの表面に形成されたパターンの欠陥の有無を検査する装置、パターンが形成されていないベアウエハの欠陥の有無を検査する装置、及び、これらの装置を組合せた複合装置を含むものである。また、「検査」とは、計測の意味でも用いるものとし、「検査動作」とは、計測動作の意味でも用いるものとする。さらに、「検査対象」とは、計測対象または検査対象となるウエハだけでなく、当該ウエハにおける計測対象領域または検査対象領域も指すものとする。また、以下において、「エラー」とは、測定不具合や装置故障のほか、アラートや警告メッセージなどのエラーの予兆も含むものとする。
Below, an embodiment of the error cause analysis device and error cause analysis method of the present invention will be described with reference to the drawings. In the following, the term "semiconductor inspection device" includes not only a device that measures the dimensions of a pattern formed on the surface of a semiconductor wafer, but also a device that inspects the presence or absence of defects in a pattern formed on the surface of a semiconductor wafer, a device that inspects the presence or absence of defects in a bare wafer on which no pattern is formed, and a composite device that combines these devices. In addition, "inspection" is also used to mean measurement, and "inspection operation" is also used to mean measurement operation. Furthermore, "inspection target" refers not only to a wafer that is the object of measurement or inspection, but also to a region on the wafer that is the object of measurement or inspection. In the following, "error" includes not only measurement problems and device failures, but also warning messages and other signs of errors.
まず、図1から図7を用いて、本発明の実施例1に係るエラー要因解析装置を説明する。
First, the error cause analysis device according to the first embodiment of the present invention will be described with reference to Figures 1 to 7.
(情報処理システムの概要)
図1は、本実施例の情報処理システム100の構成例を示す概略図である。本図に示すように、情報処理システム100は、半導体検査装置1と、データベース2と、エラー要因解析装置3と、端末4と、ネットワークNを有している。以下、各々を順次説明する。 (Outline of the information processing system)
1 is a schematic diagram showing an example of the configuration of aninformation processing system 100 according to this embodiment. As shown in the figure, the information processing system 100 includes a semiconductor inspection device 1, a database 2, an error cause analysis device 3, a terminal 4, and a network N. Each of these will be described in turn below.
図1は、本実施例の情報処理システム100の構成例を示す概略図である。本図に示すように、情報処理システム100は、半導体検査装置1と、データベース2と、エラー要因解析装置3と、端末4と、ネットワークNを有している。以下、各々を順次説明する。 (Outline of the information processing system)
1 is a schematic diagram showing an example of the configuration of an
半導体検査装置1は、半導体ウエハの表面に形成されたパターンの寸法を検査する装置等であり、ネットワークNを介して、データベース2やエラー要因解析装置3と接続される。
The semiconductor inspection device 1 is a device that inspects the dimensions of patterns formed on the surface of a semiconductor wafer, and is connected to a database 2 and an error cause analysis device 3 via a network N.
データベース2は、半導体検査装置1から送られた、装置データ、レシピ、計測結果、エラー結果などのデータを記録する記録装置である。
The database 2 is a recording device that records data sent from the semiconductor inspection device 1, such as device data, recipes, measurement results, and error results.
エラー要因解析装置3は、半導体検査装置1で実施した検査工程にエラーがある場合、そのエラー要因を解析するための装置であり、具体的には、CPU等の演算装置、半導体メモリ等の記憶装置、および、通信装置などのハードウェアを備えたコンピュータである。このエラー要因解析装置3は、半導体検査装置1のユーザが管理する施設内で運用されるオンプレミスであっても良いし、同施設外で運用されるクラウドであっても良い。また、半導体検査装置1にエラー要因解析装置3の機能を組み込んでも良い。
The error cause analysis device 3 is a device for analyzing the cause of an error if an error occurs in the inspection process performed by the semiconductor inspection equipment 1, and is specifically a computer equipped with hardware such as a calculation device such as a CPU, a storage device such as a semiconductor memory, and a communication device. This error cause analysis device 3 may be on-premise operated within a facility managed by the user of the semiconductor inspection equipment 1, or it may be a cloud operated outside the facility. The functions of the error cause analysis device 3 may also be incorporated into the semiconductor inspection equipment 1.
端末4は、エラー要因解析装置3の解析結果を、ユーザに提示する際のGUI(Graphical User Interface)として機能するディスプレイを備えた装置であり、有線または無線の通信回線を介して、エラー要因解析装置3と通信可能に接続されている。
The terminal 4 is a device equipped with a display that functions as a GUI (Graphical User Interface) when presenting the analysis results of the error cause analysis device 3 to the user, and is connected to the error cause analysis device 3 so as to be able to communicate with it via a wired or wireless communication line.
(データベース2に記録されるデータ)
半導体検査装置1から送信され、データベース2に記録され、さらに、エラー要因解析装置3で解析されるデータには、例えば、装置データ、レシピ、計測結果、エラー結果が含まれる。以下、各データを順次説明する。 (Data recorded in database 2)
The data transmitted from thesemiconductor inspection equipment 1, recorded in the database 2, and further analyzed by the error cause analysis device 3 includes, for example, equipment data, recipes, measurement results, and error results. Each piece of data will be explained below in order.
半導体検査装置1から送信され、データベース2に記録され、さらに、エラー要因解析装置3で解析されるデータには、例えば、装置データ、レシピ、計測結果、エラー結果が含まれる。以下、各データを順次説明する。 (Data recorded in database 2)
The data transmitted from the
装置データは、装置固有パラメータ、装置機差補正データ、及び、観察条件パラメータを含む。装置固有パラメータは、半導体検査装置1を規定仕様どおりに動作させるために用いる補正パラメータである。装置機差補正データは、半導体検査装置間の機差を補正するために用いるパラメータである。観察条件パラメータは、例えば、電子光学系の加速電圧等の走査型電子顕微鏡(SEM)の観察条件を規定するパラメータである。
The equipment data includes equipment-specific parameters, equipment difference correction data, and observation condition parameters. The equipment-specific parameters are correction parameters used to operate the semiconductor inspection equipment 1 in accordance with the prescribed specifications. The equipment difference correction data are parameters used to correct the equipment differences between semiconductor inspection equipment. The observation condition parameters are parameters that specify the observation conditions of a scanning electron microscope (SEM), such as the accelerating voltage of the electron optical system, for example.
レシピは、ウエハマップ、各種パラメータ(アライメントパラメータ、アドレッシングパラメータ、測長パラメータ)、テンプレート画像などを含む。ウエハマップは、半導体ウエハの表面の座標マップ(例えばパターンの座標)である。アライメントパラメータは、例えば、半導体ウエハの表面の座標系と半導体検査装置1内部の座標系との間のずれを補正するために用いるパラメータである。アドレッシングパラメータは、例えば、半導体ウエハの表面に形成されているパターンのうち、検査対象領域内に存在する特徴的なパターンを特定する情報である。測長パラメータは、長さを測定する条件を記述したパラメータであり、例えばパターンのうちどの部位の長さを測定するかを指定するパラメータである。テンプレート画像は、測定点をパターンマッチングで検出するための基準画像である。
The recipe includes a wafer map, various parameters (alignment parameters, addressing parameters, length measurement parameters), a template image, etc. The wafer map is a coordinate map (e.g., pattern coordinates) of the surface of the semiconductor wafer. The alignment parameters are, for example, parameters used to correct the misalignment between the coordinate system of the surface of the semiconductor wafer and the coordinate system inside the semiconductor inspection device 1. The addressing parameters are, for example, information that identifies a characteristic pattern that exists within the inspection target area among the patterns formed on the surface of the semiconductor wafer. The length measurement parameters are parameters that describe the conditions for measuring length, and are, for example, parameters that specify which part of the pattern is to be measured in length. The template image is a reference image for detecting measurement points by pattern matching.
なお、レシピには、測定点数、測定点(Evaluation Point:EP)の座標情報、画像を撮像する際の撮像条件等が含まれていてもよい。また、レシピには、測定点に併せて測定点を計測するための準備段階で取得される画像の座標や撮像条件等が含まれていてもよい。
The recipe may include the number of measurement points, coordinate information of the measurement points (Evaluation Points: EP), imaging conditions for capturing images, etc. The recipe may also include the coordinates and imaging conditions of images captured in the preparation stage for measuring the measurement points in addition to the measurement points.
計測結果は、測長結果、画像データ及び動作ログを含む。測長結果は、半導体ウエハの表面のパターンの長さを測定した結果を記述したものである。画像データは、半導体ウエハの観察画像である。動作ログは、アライメント、アドレッシング及び測長の各動作工程における半導体検査装置1の内部状態を記述したデータである。例えば、各部品の動作電圧、観察視野の座標等が挙げられる。
The measurement results include length measurement results, image data, and an operation log. The length measurement results describe the results of measuring the length of the pattern on the surface of the semiconductor wafer. The image data is an observed image of the semiconductor wafer. The operation log is data describing the internal state of the semiconductor inspection device 1 in each operation process of alignment, addressing, and length measurement. For example, this includes the operating voltage of each component, the coordinates of the observation field, etc.
エラー結果は、エラーが発生した場合に、アライメント、アドレッシング及び測長の各動作工程のいずれで発生したエラーであるかを示すパラメータである。
The error result is a parameter that indicates in which operation process (alignment, addressing, or length measurement) the error occurred if an error occurred.
(検査工程の概要)
図2は、半導体検査装置1の検査工程の一例を示したものである。ここに例示する検査工程は、工程P1から工程P5の5つの動作工程(小工程)に分解される。すなわち、工程P1では、光学(OM)モードのアライメントにより、測定ウエハと半導体検査装置のステージの位置ずれを補正する。次に、工程P2では、電子線(SEM)モードのアライメントにより、測定ウエハとステージの位置ずれを補正する。その後、工程P3,P4では、アドレッシングにより測長座標へ視野移動する。最後に、工程P5では、測定ウエハの表面に形成されたパターンの寸法を測長する。以上の検査工程により、半導体検査装置1は、半導体ウエハを検査する。 (Overview of the inspection process)
2 shows an example of an inspection process of thesemiconductor inspection device 1. The inspection process illustrated here is decomposed into five operation steps (sub-steps), from step P1 to step P5. That is, in step P1, the positional deviation between the measurement wafer and the stage of the semiconductor inspection device is corrected by alignment in the optical (OM) mode. Next, in step P2, the positional deviation between the measurement wafer and the stage is corrected by alignment in the electron beam (SEM) mode. After that, in steps P3 and P4, the field of view is moved to the measurement coordinates by addressing. Finally, in step P5, the dimensions of the pattern formed on the surface of the measurement wafer are measured. Through the above inspection steps, the semiconductor inspection device 1 inspects the semiconductor wafer.
図2は、半導体検査装置1の検査工程の一例を示したものである。ここに例示する検査工程は、工程P1から工程P5の5つの動作工程(小工程)に分解される。すなわち、工程P1では、光学(OM)モードのアライメントにより、測定ウエハと半導体検査装置のステージの位置ずれを補正する。次に、工程P2では、電子線(SEM)モードのアライメントにより、測定ウエハとステージの位置ずれを補正する。その後、工程P3,P4では、アドレッシングにより測長座標へ視野移動する。最後に、工程P5では、測定ウエハの表面に形成されたパターンの寸法を測長する。以上の検査工程により、半導体検査装置1は、半導体ウエハを検査する。 (Overview of the inspection process)
2 shows an example of an inspection process of the
ここで、各動作工程では、レシピに登録されたテンプレート画像と測定点を撮像したSEM画像のマッチングスコアを算出し、マッチングスコアが閾値以上であれば、パターン検出成功として次の動作工程に移行する。しかし、この閾値が不適切であれば、本来とは別の位置を検出したなどのパターン検出に失敗しているにもかかわらずエラー判定をすり抜けて次の動作工程に移行することがある。この場合、実際にエラーが検知された動作工程とは別の、すり抜けがあった動作工程にエラー原因があることになる。
Here, in each operation step, a matching score is calculated between the template image registered in the recipe and the SEM image captured of the measurement point, and if the matching score is equal to or greater than a threshold, the pattern detection is deemed successful and the process moves to the next operation step. However, if this threshold is inappropriate, the process may slip through the error judgment and move on to the next operation step even if the pattern detection fails, for example, if a different position than intended is detected. In this case, the cause of the error is in the operation step where the slip-through occurred, which is different from the operation step where the error was actually detected.
そこで、本実施例では、後の動作工程でエラーが検知された場合であっても、エラー原因となった前の動作工程を推定し、その前の動作工程で取得したデータに基づいてエラー要因を正確に解析できるように、次のようなエラー要因解析装置3を設けた。
In this embodiment, therefore, an error cause analysis device 3 is provided as follows so that even if an error is detected in a later operation process, the previous operation process that caused the error can be inferred and the cause of the error can be accurately analyzed based on the data acquired in the previous operation process.
(エラー要因解析装置の構成および処理内容)
図3は、本実施例のエラー要因解析装置3の詳細構成を示したものである。ここに示すように、エラー要因解析装置3は、工程別データ抽出部31、エラーラベル付与部32、エラー相関計算部33、異常度計算部34、異常度記憶部35、異常工程推定部36を備えており、これらを用いて異常工程推定結果D1を出力する。また、エラー相関計算部33は、特徴量生成部33aと、エラー分類モデル学習部33bと、モデル解析部33cを備えており、異常度計算部34は、特徴量抽出部34aと、特徴量ベース計算部34bを備えている。なお、各機能部は、一般的なコンピュータであるエラー要因解析装置3の演算装置が、記憶装置に読み込んだ所定のプログラムを実行することで実現されたものである。 (Configuration and processing contents of the error cause analysis device)
3 shows a detailed configuration of the errorfactor analysis device 3 of this embodiment. As shown in the figure, the error factor analysis device 3 includes a process-specific data extraction unit 31, an error label assignment unit 32, an error correlation calculation unit 33, an abnormality calculation unit 34, an abnormality storage unit 35, and an abnormal process estimation unit 36, and outputs an abnormal process estimation result D1 using these units. The error correlation calculation unit 33 includes a feature generation unit 33a, an error classification model learning unit 33b, and a model analysis unit 33c, and the abnormality calculation unit 34 includes a feature extraction unit 34a and a feature base calculation unit 34b. Each functional unit is realized by a calculation unit of the error factor analysis device 3, which is a general computer, executing a predetermined program loaded into a storage device.
図3は、本実施例のエラー要因解析装置3の詳細構成を示したものである。ここに示すように、エラー要因解析装置3は、工程別データ抽出部31、エラーラベル付与部32、エラー相関計算部33、異常度計算部34、異常度記憶部35、異常工程推定部36を備えており、これらを用いて異常工程推定結果D1を出力する。また、エラー相関計算部33は、特徴量生成部33aと、エラー分類モデル学習部33bと、モデル解析部33cを備えており、異常度計算部34は、特徴量抽出部34aと、特徴量ベース計算部34bを備えている。なお、各機能部は、一般的なコンピュータであるエラー要因解析装置3の演算装置が、記憶装置に読み込んだ所定のプログラムを実行することで実現されたものである。 (Configuration and processing contents of the error cause analysis device)
3 shows a detailed configuration of the error
図4は、エラー要因解析装置3の処理フローチャートである。以下では、図3と図4を適宜参照しながら、エラー要因解析装置3によるエラー要因解析処理の詳細を説明する。
FIG. 4 is a processing flowchart of the error cause analysis device 3. Below, the details of the error cause analysis process by the error cause analysis device 3 will be explained with reference to FIG. 3 and FIG. 4 as appropriate.
((ステップS1))
まず、ステップS1では、工程別データ抽出部31は、エラー要因を解析したいレシピを用いて半導体検査装置1が計測したデータセットをデータベース2から取得し、動作工程別にデータを分割する。一般的に、データベース2に収集されたデータセットには、どの動作工程で計測されたものであるかを区別するための識別番号が付与されているため、この識別番号を用いてデータセットを動作工程別の計測データに分割できる。 ((Step S1))
First, in step S1, the process-specificdata extraction unit 31 acquires from the database 2 a data set measured by the semiconductor inspection device 1 using a recipe for which an error cause is to be analyzed, and divides the data by operation process. In general, an identification number is given to the data set collected in the database 2 to distinguish which operation process the data was measured in, so that the data set can be divided into measurement data by operation process using this identification number.
まず、ステップS1では、工程別データ抽出部31は、エラー要因を解析したいレシピを用いて半導体検査装置1が計測したデータセットをデータベース2から取得し、動作工程別にデータを分割する。一般的に、データベース2に収集されたデータセットには、どの動作工程で計測されたものであるかを区別するための識別番号が付与されているため、この識別番号を用いてデータセットを動作工程別の計測データに分割できる。 ((Step S1))
First, in step S1, the process-specific
そして、この分割した計測データから、検出されたエラーに関係のある可能性ある動作工程の計測データを抽出する。このエラーに関係のある可能性ある動作工程は、例えばエラーが検知された動作工程とその上流の動作工程や、アドレッシング-測長の繰り返し動作の一連の動作工程や、計測タイミングの近い動作工程などのデータとすることができる。
Then, from this divided measurement data, measurement data of operation steps that may be related to the detected error is extracted. Operation steps that may be related to this error can be, for example, data on the operation step where the error was detected and its upstream operation steps, a series of operation steps that repeat addressing and length measurement, operation steps with close measurement timing, etc.
((ステップS2))
次に、ステップS2では、エラーラベル付与部32は、ステップS1で抽出した工程データについて、エラーが検知された測定点にエラーラベルを与えるとともに、この測定点の検査性能に影響を与えると推定した関連測定点(エラー関連測定点)にもエラーラベルを与える。 (Step S2)
Next, in step S2, the errorlabel assignment unit 32 assigns an error label to the measurement point where an error was detected for the process data extracted in step S1, and also assigns error labels to related measurement points (error-related measurement points) that are estimated to affect the inspection performance of this measurement point.
次に、ステップS2では、エラーラベル付与部32は、ステップS1で抽出した工程データについて、エラーが検知された測定点にエラーラベルを与えるとともに、この測定点の検査性能に影響を与えると推定した関連測定点(エラー関連測定点)にもエラーラベルを与える。 (Step S2)
Next, in step S2, the error
このようにしてエラーラベルを付与した工程別データの一例を、図5に示す。図5は、半導体検査装置1が計測したデータセットを構成する、工程P1データと、工程P5データを抜粋して表示した図である。各工程別データにおいて、左から1列目の「ウエハINDEX」は半導体ウエハを区別するための識別番号である。また、左から2列目の「測定No」は同じ半導体ウエハでの何番目の測定点であるかを示す通し番号である。本ステップにおけるエラー関連測定点の推定方法は、例えば、工程P5データ内の、「ウエハINDEX」が「XXX001」の半導体ウエハの「測定No」が「12」の測定項目でエラーを検知した場合であれば、当該半導体ウエハと同じ「ウエハINDEX」であり、より若い「測定No」の測定点(例えば、工程P1データ内の「ウエハINDEX」が「XXX001」、「測定No」が「0」または「1」の測定点)を、エラー関連測定点と推定する。その後、エラーラベル付与部32は、このように推定したエラー関連測定点と、その起点となったエラー検出測定点に、図示するように、エラーラベル「1」を付与する。
An example of process data to which an error label has been added in this manner is shown in FIG. 5. FIG. 5 is a diagram showing excerpts of process P1 data and process P5 data constituting a data set measured by the semiconductor inspection device 1. In each process data, the "wafer INDEX" in the first column from the left is an identification number for distinguishing the semiconductor wafer. Also, the "measurement No." in the second column from the left is a serial number indicating which measurement point on the same semiconductor wafer it is. In this step, the method of estimating the error-related measurement point is, for example, if an error is detected in the measurement item with "measurement No." "12" of a semiconductor wafer with "wafer INDEX" "XXX001" in the process P5 data, the measurement point with the same "wafer INDEX" as the semiconductor wafer and a younger "measurement No." (for example, the measurement point with "wafer INDEX" "XXX001" and "measurement No." "0" or "1" in the process P1 data) is estimated to be the error-related measurement point. The error label assignment unit 32 then assigns the error label "1" to the error-related measurement point thus estimated and the error detection measurement point that is its origin, as shown in the figure.
((ステップS3))
ステップS3では、エラー相関計算部33は、ステップS1で抽出した工程別データの中から異常度計算が未完了の1つ(図5の例における、工程P1データ、または、工程P5データ)を、ステップS4以降の処理の対象として選定する。 (Step S3)
In step S3, the errorcorrelation calculation unit 33 selects one of the process-specific data extracted in step S1 for which the anomaly degree calculation has not been completed (the process P1 data or the process P5 data in the example of FIG. 5) as the target for processing in step S4 and thereafter.
ステップS3では、エラー相関計算部33は、ステップS1で抽出した工程別データの中から異常度計算が未完了の1つ(図5の例における、工程P1データ、または、工程P5データ)を、ステップS4以降の処理の対象として選定する。 (Step S3)
In step S3, the error
((ステップS4))
ステップS4では、エラー相関計算部33は、ステップS3で選定したデータ(例えば、図5の工程P1データ)から機械学習モデルの入力に適した特徴量を生成する。そのため、具体的には次の処理を実行する。 (Step S4)
In step S4, the errorcorrelation calculation unit 33 generates features suitable for input to a machine learning model from the data selected in step S3 (for example, the process P1 data in FIG. 5). To this end, the following process is specifically executed.
ステップS4では、エラー相関計算部33は、ステップS3で選定したデータ(例えば、図5の工程P1データ)から機械学習モデルの入力に適した特徴量を生成する。そのため、具体的には次の処理を実行する。 (Step S4)
In step S4, the error
まず、特徴量生成部33aは、ステップS2で付与したエラーラベルのある測定点とない測定点のデータの違いから、各特徴量のエラー発生に対する相関度を計算する。次に、特徴量生成部33aは、エラーラベルのあるデータとないデータを見分ける機械学習モデルの入力に適した特徴量を、処理対象の工程別データを用いて生成する。ここで、特徴量の生成は、例えば測定データのスケーリングや統計処理、カテゴリカル変数のエンコーディング、交互作用特徴量等の複数のデータを組み合わせた複合的な特徴量作成等を用いることができる。
First, the feature generator 33a calculates the correlation of each feature with respect to the occurrence of an error from the difference in data between measurement points with and without the error labels added in step S2. Next, the feature generator 33a uses the process-specific data to be processed to generate features suitable for input to a machine learning model that distinguishes between data with and without error labels. Here, the generation of features can use, for example, scaling and statistical processing of measurement data, encoding of categorical variables, creation of composite features by combining multiple data such as interaction features, etc.
次に、エラー分類モデル学習部33bは、特徴量生成部33aで生成した特徴量や、ステップS2で付与したエラーラベルを入力として、エラーラベルのある測定点のデータと、ない測定点のデータの傾向の違いに基づき、これらを分類するエラー分類モデルを学習する。このエラー分類モデルはRandom ForestやXGBoostなどの決定木をベースとしたアルゴリズムや、Neural Networkなど、どのような機械学習アルゴリズムを用いて生成するとしてもよい。
Next, the error classification model learning unit 33b uses as input the features generated by the feature generation unit 33a and the error labels assigned in step S2, and learns an error classification model that classifies data from measurement points with error labels based on the difference in tendency between data from measurement points without error labels. This error classification model may be generated using any machine learning algorithm, such as a decision tree-based algorithm such as Random Forest or XGBoost, or a Neural Network.
更に、モデル解析部33cは、エラー分類モデル学習部33bで学習されたエラー分類モデルについて、入力された各特徴量がモデル出力であるエラー予測結果に対してどの程度影響したかの相関度を計算する。この相関度は、例えば、エラー検出モデルが決定木をベースとしたアルゴリズムで構築される場合、各特徴量がモデル内の分岐に出現する個数や目的関数の改善値等に基づき計算される変数重要度(Feature Importance)や、各特徴量の値のモデル出力への相関度を計算するSHAP(Shapley Additive exPlanations)値によって評価することができる。
Furthermore, the model analysis unit 33c calculates the degree of correlation of the error classification model learned by the error classification model learning unit 33b, indicating the degree to which each input feature quantity influenced the error prediction result, which is the model output. For example, when the error detection model is constructed using an algorithm based on a decision tree, this correlation can be evaluated by the feature importance, which is calculated based on the number of times each feature quantity appears in a branch in the model and the improvement value of the objective function, or the SHAP (Shapley Additive exPlanations) value, which calculates the degree of correlation of the value of each feature quantity with the model output.
((ステップS5))
ステップS5では、特徴量抽出部34aは、ステップS4で計算した相関度の高い特徴量を抽出する。この抽出方法としては、例えば相関度の高い順から上位N個の特徴量を抽出する方法や、予め設定された閾値以上の相関度を持つ特徴量を抽出する方法を用いることができる。 (Step S5)
In step S5, thefeature extraction unit 34a extracts the feature having the high correlation calculated in step S4. For example, the extraction method may be a method of extracting the top N feature amounts in descending order of correlation, or a method of extracting feature amounts having a correlation equal to or greater than a preset threshold.
ステップS5では、特徴量抽出部34aは、ステップS4で計算した相関度の高い特徴量を抽出する。この抽出方法としては、例えば相関度の高い順から上位N個の特徴量を抽出する方法や、予め設定された閾値以上の相関度を持つ特徴量を抽出する方法を用いることができる。 (Step S5)
In step S5, the
((ステップS6))
ステップS6では、特徴量ベース計算部34bは、ステップS5で抽出したエラーに相関の高い特徴量のエラーラベルが付与された測定点と、エラーラベルのない測定点のデータの乖離度を、その動作工程の異常度として計算する。この乖離度は、例えばユークリッド距離やマハラノビス距離を用いることができる。 (Step S6)
In step S6, the feature-basedcalculation unit 34b calculates the degree of deviation between the data of the measurement point to which the error label of the feature highly correlated with the error extracted in step S5 is assigned and the data of the measurement point without the error label as the degree of abnormality of the operation process. For this deviation, for example, the Euclidean distance or the Mahalanobis distance can be used.
ステップS6では、特徴量ベース計算部34bは、ステップS5で抽出したエラーに相関の高い特徴量のエラーラベルが付与された測定点と、エラーラベルのない測定点のデータの乖離度を、その動作工程の異常度として計算する。この乖離度は、例えばユークリッド距離やマハラノビス距離を用いることができる。 (Step S6)
In step S6, the feature-based
((ステップS7))
ステップS7では、異常度記憶部35は、ステップS6で計算した動作工程毎の異常度を記憶する。 (Step S7)
In step S7, the abnormalitydegree storage unit 35 stores the abnormality degree for each operation process calculated in step S6.
ステップS7では、異常度記憶部35は、ステップS6で計算した動作工程毎の異常度を記憶する。 (Step S7)
In step S7, the abnormality
((ステップS8))
ステップS8では、ステップS3からステップS7までの処理を、ステップS1で抽出した全動作工程データについて実施したかを判定する。そして、要件を満たす場合は、ステップS9に進み、要件を満たさない場合は、全動作工程データについて異常度を計算し終えるまで、ステップS3からステップS7までの処理を繰り返す。 ((Step S8))
In step S8, it is determined whether the processes from step S3 to step S7 have been performed for all the operation process data extracted in step S1. If the requirements are met, the process proceeds to step S9, and if the requirements are not met, the processes from step S3 to step S7 are repeated until the degree of anomaly is calculated for all the operation process data.
ステップS8では、ステップS3からステップS7までの処理を、ステップS1で抽出した全動作工程データについて実施したかを判定する。そして、要件を満たす場合は、ステップS9に進み、要件を満たさない場合は、全動作工程データについて異常度を計算し終えるまで、ステップS3からステップS7までの処理を繰り返す。 ((Step S8))
In step S8, it is determined whether the processes from step S3 to step S7 have been performed for all the operation process data extracted in step S1. If the requirements are met, the process proceeds to step S9, and if the requirements are not met, the processes from step S3 to step S7 are repeated until the degree of anomaly is calculated for all the operation process data.
((ステップS9))
ステップS9では、異常工程推定部36は、ステップS7で記憶した動作工程別の異常度を用いて、エラー原因となった動作工程を推定する。ここでのエラー原因工程の推定方法としては、例えば異常度が最も高い動作工程や、異常度が予め設定された閾値以上の最上流の動作工程や、エラー相関に相関の高い特徴量と工程別の異常度と原因工程の関係を学習した機械学習モデルを用いて推定した動作工程などとすることができる。 (Step S9)
In step S9, the abnormalprocess estimation unit 36 estimates the operation process that caused the error by using the degree of abnormality for each operation process stored in step S7. The method for estimating the error causing process here can be, for example, the operation process with the highest degree of abnormality, the most upstream operation process with a degree of abnormality equal to or higher than a preset threshold, or an operation process estimated using a machine learning model that has learned the relationship between the feature amount highly correlated with the error correlation, the degree of abnormality for each process, and the causing process.
ステップS9では、異常工程推定部36は、ステップS7で記憶した動作工程別の異常度を用いて、エラー原因となった動作工程を推定する。ここでのエラー原因工程の推定方法としては、例えば異常度が最も高い動作工程や、異常度が予め設定された閾値以上の最上流の動作工程や、エラー相関に相関の高い特徴量と工程別の異常度と原因工程の関係を学習した機械学習モデルを用いて推定した動作工程などとすることができる。 (Step S9)
In step S9, the abnormal
本ステップでのエラー原因工程の推定結果は、異常工程推定結果D1として出力される。異常工程推定結果D1は、異常度記憶部35に記憶された動作工程毎の異常度や、異常工程推定部36で推定されたエラー原因工程などを含むエラー解析結果である。これらエラー解析結果を、GUIである端末4を介してユーザに提示する。
The estimation result of the process causing the error in this step is output as abnormal process estimation result D1. The abnormal process estimation result D1 is an error analysis result including the degree of abnormality for each operation process stored in the abnormality degree storage unit 35 and the process causing the error estimated by the abnormal process estimation unit 36. These error analysis results are presented to the user via terminal 4, which is a GUI.
エラー解析結果のユーザへの提示方法の一例を図6に示す。この例では、動作工程毎の異常度の大きさをバーの長さで示しており、かつ、図4のフローチャートの処理によってエラー原因と推定された工程P2を他の工程と異なる色(濃色)で示している。このようにして、仮に工程P5でエラーが検知された場合であっても、そのエラーの原因がエラーの検知されなかった工程P2で発生していたことをユーザに報知することができる。
Figure 6 shows an example of how to present the error analysis results to the user. In this example, the level of abnormality for each operation process is indicated by the length of the bar, and process P2, which is presumed to be the cause of the error by the processing in the flowchart of Figure 4, is shown in a different color (darker color) from the other processes. In this way, even if an error is detected in process P5, the user can be notified that the cause of the error occurred in process P2, where no error was detected.
(実施例1の効果)
以上で説明した本実施例では、レシピ毎にテーブルや定義を用意しなければならない従来の異常検知方法とは異なり、発生したエラー情報をそのまま用いて、先行する各動作工程のデータに含まれるエラー関連測定点を推定する。そして、このエラー関連測定点をエラーデータと見なし、エラーデータとそれ以外のデータの乖離度を各工程の異常度として計算する。 (Effects of Example 1)
In the present embodiment described above, unlike the conventional anomaly detection method in which a table and definition must be prepared for each recipe, the error information generated is used as is to estimate the error-related measurement points contained in the data of each preceding operation process.Then, the error-related measurement points are regarded as error data, and the deviation between the error data and other data is calculated as the degree of anomaly for each process.
以上で説明した本実施例では、レシピ毎にテーブルや定義を用意しなければならない従来の異常検知方法とは異なり、発生したエラー情報をそのまま用いて、先行する各動作工程のデータに含まれるエラー関連測定点を推定する。そして、このエラー関連測定点をエラーデータと見なし、エラーデータとそれ以外のデータの乖離度を各工程の異常度として計算する。 (Effects of Example 1)
In the present embodiment described above, unlike the conventional anomaly detection method in which a table and definition must be prepared for each recipe, the error information generated is used as is to estimate the error-related measurement points contained in the data of each preceding operation process.Then, the error-related measurement points are regarded as error data, and the deviation between the error data and other data is calculated as the degree of anomaly for each process.
これにより、事前に準備した、測定値とエラー原因工程の関係テーブルや、正常データの収集・定義を用いることなく、エラー原因工程の推定が可能となる。従って、本実施例によれば、少量多品種の半導体製品を製造するために、レシピを頻繁に更新する場合であっても、各レシピに対応したエラー原因推定を容易に行うことができる。
This makes it possible to estimate the process causing the error without using a previously prepared relationship table between measured values and the process causing the error, or without collecting and defining normal data. Therefore, according to this embodiment, even if recipes are frequently updated to manufacture a wide variety of semiconductor products in small quantities, it is possible to easily estimate the cause of the error corresponding to each recipe.
次に、図7及び図8を参照して、実施例2のエラー要因解析装置3を説明する。なお、実施例1との共通点は重複説明を省略する。
Next, the error cause analysis device 3 of the second embodiment will be described with reference to Figures 7 and 8. Note that a duplicated description of the points in common with the first embodiment will be omitted.
図3と図7の比較から自明なように、実施例2のエラー要因解析装置3は、実施例1のエラー要因解析装置3に、マッチングスコアベースの異常度計算部37と、総合異常度計算部38を付加したものである。以下、これらの詳細を順次説明する。
As is obvious from a comparison of FIG. 3 and FIG. 7, the error factor analysis device 3 of the second embodiment is obtained by adding a matching score-based anomaly degree calculation unit 37 and a total anomaly degree calculation unit 38 to the error factor analysis device 3 of the first embodiment. The details of these will be explained below.
(マッチングスコアベースの異常度計算部37)
データベース2には一般的に、予めレシピに登録されたテンプレート画像と、測定点を撮像したSEM画像のマッチングスコアが記録されている。マッチングスコアベースの異常度計算部37では、工程別データ抽出部31で抽出されたエラー原因の可能性のある工程別のデータについて、このマッチングスコアのエラーラベルが付与された測定点とエラーラベルのない測定点のデータの乖離度を異常度として計算する。この乖離度は、元のデータの平均値や標準偏差に基づくZスコアなどを用いることができる。このマッチングスコアベースの工程別の異常度を異常度記憶部35に記憶する。 (Matching score-based abnormality calculation unit 37)
In general, thedatabase 2 records matching scores between a template image registered in advance in a recipe and an SEM image of a measurement point. The matching score-based anomaly calculation unit 37 calculates the degree of anomaly between the data of a measurement point to which an error label of the matching score is assigned and the data of a measurement point without an error label for each process data that may be the cause of an error extracted by the process data extraction unit 31. This degree of anomaly can be a Z score based on the average value or standard deviation of the original data. The matching score-based anomaly degree for each process is stored in the anomaly storage unit 35.
データベース2には一般的に、予めレシピに登録されたテンプレート画像と、測定点を撮像したSEM画像のマッチングスコアが記録されている。マッチングスコアベースの異常度計算部37では、工程別データ抽出部31で抽出されたエラー原因の可能性のある工程別のデータについて、このマッチングスコアのエラーラベルが付与された測定点とエラーラベルのない測定点のデータの乖離度を異常度として計算する。この乖離度は、元のデータの平均値や標準偏差に基づくZスコアなどを用いることができる。このマッチングスコアベースの工程別の異常度を異常度記憶部35に記憶する。 (Matching score-based abnormality calculation unit 37)
In general, the
(総合異常度計算部38)
総合異常度計算部38では、異常度記憶部35に記憶された各異常度から総合的な異常度を計算する。この総合異常度計算の模式図を図8に示す。特徴量ベースの異常度およびマッチングスコアベースの異常度から、工程別の総合異常度を計算する。この計算方法としては、例えば単純に両者の異常度を工程別に足し合わせる方法や、両者の最大値をとる方法や、予め設定された重みをそれぞれに乗算してから足し合わせる方法などとすることができる。 (Total Abnormality Level Calculation Unit 38)
The overall abnormalitydegree calculation unit 38 calculates an overall degree of abnormality from each degree of abnormality stored in the abnormality degree storage unit 35. A schematic diagram of this overall abnormality degree calculation is shown in Fig. 8. The overall abnormality degree for each process is calculated from the feature-based abnormality degree and the matching score-based abnormality degree. This calculation method can be, for example, a method of simply adding up both the abnormality degrees for each process, a method of taking the maximum value of both, a method of multiplying each by a preset weight and then adding them up, etc.
総合異常度計算部38では、異常度記憶部35に記憶された各異常度から総合的な異常度を計算する。この総合異常度計算の模式図を図8に示す。特徴量ベースの異常度およびマッチングスコアベースの異常度から、工程別の総合異常度を計算する。この計算方法としては、例えば単純に両者の異常度を工程別に足し合わせる方法や、両者の最大値をとる方法や、予め設定された重みをそれぞれに乗算してから足し合わせる方法などとすることができる。 (Total Abnormality Level Calculation Unit 38)
The overall abnormality
(異常工程推定部36)
異常工程推定部36では、総合異常度計算部38で計算された工程別の総合異常度を用いて、実施例1と同様に異常度の高さや閾値に基づきエラー原因となった工程を推定する。 (Abnormal process estimation unit 36)
The abnormalprocess estimation unit 36 uses the overall abnormality degree for each process calculated by the overall abnormality degree calculation unit 38 to estimate the process that caused the error based on the level of the abnormality and a threshold value, as in the first embodiment.
異常工程推定部36では、総合異常度計算部38で計算された工程別の総合異常度を用いて、実施例1と同様に異常度の高さや閾値に基づきエラー原因となった工程を推定する。 (Abnormal process estimation unit 36)
The abnormal
本実施例のように総合異常度を計算する場合、GUIである端末4には、最終的な総合異常度のみを表示することとしても良いし、総合異常度を計算する根拠となった、特徴量ベースの異常度と、マッチングスコアベースの異常度の双方を、総合異常度と共に表示しても良い。なお、図8においても、図6と同様に、異常工程推定部36によってエラー原因と推定された工程を他の工程と異なる色(濃色)で示しているが、異常工程推定部36で採用されるエラー工程の推定方法が、例えば、異常度の大きさが閾値を超えた最上流の工程をエラー原因の工程として推定する場合であれば、図8の例のように、異常度が最大の工程P2ではなく、異常度が閾値を超える最上流の工程P1がエラー原因と推定されることもある。
When calculating the overall abnormality degree as in this embodiment, the terminal 4, which is a GUI, may display only the final overall abnormality degree, or may display both the feature-based abnormality degree and the matching score-based abnormality degree, which are the basis for calculating the overall abnormality degree, together with the overall abnormality degree. Note that in FIG. 8 as in FIG. 6, the process estimated by the abnormal process estimation unit 36 to be the cause of the error is shown in a different color (darker color) from the other processes. However, if the estimation method of the error process employed by the abnormal process estimation unit 36 is, for example, to estimate the most upstream process whose abnormality degree exceeds a threshold as the process causing the error, then as in the example of FIG. 8, the most upstream process P1 whose abnormality degree exceeds a threshold may be estimated to be the cause of the error, rather than process P2 whose abnormality degree is the highest.
(実施例2の効果)
実施例2では、工程別の異常度を算出する手段を複数持ち、それらを複合した異常度を計算する。これにより、エラー原因工程の推定に多角的な情報を用いることが可能となり、エラーの特徴の見逃しが減ることで推定精度を向上することができる。 (Effects of Example 2)
In the second embodiment, multiple means for calculating the degree of anomaly for each process are provided, and the degree of anomaly is calculated by combining these means. This makes it possible to use multifaceted information to estimate the process causing the error, and reduces overlooking of the characteristics of the error, thereby improving the accuracy of the estimation.
実施例2では、工程別の異常度を算出する手段を複数持ち、それらを複合した異常度を計算する。これにより、エラー原因工程の推定に多角的な情報を用いることが可能となり、エラーの特徴の見逃しが減ることで推定精度を向上することができる。 (Effects of Example 2)
In the second embodiment, multiple means for calculating the degree of anomaly for each process are provided, and the degree of anomaly is calculated by combining these means. This makes it possible to use multifaceted information to estimate the process causing the error, and reduces overlooking of the characteristics of the error, thereby improving the accuracy of the estimation.
次に、図9及び図10を参照して、実施例3のエラー要因解析装置3を説明する。なお、実施例1との共通点は重複説明を省略する。
Next, an error cause analysis device 3 according to the third embodiment will be described with reference to Figures 9 and 10. Note that a duplicated description of the points in common with the first embodiment will be omitted.
図3と図9の比較から分かるように、実施例3のエラー要因解析装置3は、実施例1と異なり工程別エラー要因推定部39、エラー辞書3A、エラー要因確率修正部3Bを備える。以下、これらの詳細を順次説明する。
As can be seen from a comparison between FIG. 3 and FIG. 9, the error factor analysis device 3 of the third embodiment is different from that of the first embodiment in that it includes a process-specific error factor estimation unit 39, an error dictionary 3A, and an error factor probability correction unit 3B. The details of these will be explained below in order.
(工程別エラー要因推定部39)
工程別エラー要因推定部39は、エラー相関計算部33で計算されたエラーと相関度の高い特徴量やその値、相関度などを用いて、エラー辞書3Aから類似度の高い項目を検索し、検索されたエラー要因やその類似度をエラー要因確率D2として工程別に1つ以上取得する。この類似度の計算方法としては、例えば協調フィルタリングやランク学習による推定を用いることができる。 (Process-specific error factor estimation unit 39)
The process-specific errorfactor estimation unit 39 searches the error dictionary 3A for items with high similarity using the feature amount, its value, correlation degree, etc. that are highly correlated with the error calculated by the error correlation calculation unit 33, and obtains one or more searched error factors and their similarities for each process as error factor probabilities D2. For example, estimation by collaborative filtering or rank learning can be used as a method for calculating this similarity.
工程別エラー要因推定部39は、エラー相関計算部33で計算されたエラーと相関度の高い特徴量やその値、相関度などを用いて、エラー辞書3Aから類似度の高い項目を検索し、検索されたエラー要因やその類似度をエラー要因確率D2として工程別に1つ以上取得する。この類似度の計算方法としては、例えば協調フィルタリングやランク学習による推定を用いることができる。 (Process-specific error factor estimation unit 39)
The process-specific error
(エラー情報蓄積部3A)
エラー辞書3Aは、特徴量やその値、相関度の組合せと、そのエラー要因が紐づけられて蓄積されている。この蓄積方法としては、エラーの特徴とその要因を過去のノウハウに基づきテーブル形式などで体系化してもよいし、過去のエラーデータとそのエラー要因を保存しておくものでもよい。 (Error Information Accumulation Unit 3A)
The error dictionary 3A stores combinations of feature quantities, their values, and correlation degrees, and their error causes in association with each other. The method of storing the error features and their causes may be systematized in a table format based on past know-how, or past error data and their error causes may be stored.
エラー辞書3Aは、特徴量やその値、相関度の組合せと、そのエラー要因が紐づけられて蓄積されている。この蓄積方法としては、エラーの特徴とその要因を過去のノウハウに基づきテーブル形式などで体系化してもよいし、過去のエラーデータとそのエラー要因を保存しておくものでもよい。 (Error Information Accumulation Unit 3A)
The error dictionary 3A stores combinations of feature quantities, their values, and correlation degrees, and their error causes in association with each other. The method of storing the error features and their causes may be systematized in a table format based on past know-how, or past error data and their error causes may be stored.
(エラー要因確率修正部3B)
エラー要因確率修正部3Bでは、工程別エラー要因推定部39で計算された工程別のエラー要因確率D2を、異常度記憶部35で記憶された工程別の異常度を用いて補正する。この補正方法の模式図を図10に示す。 (Error factorprobability correction unit 3B)
The error factorprobability correction unit 3B corrects the process-specific error factor probability D2 calculated by the process-specific error factor estimation unit 39, using the process-specific abnormality degree stored in the abnormality degree storage unit 35. A schematic diagram of this correction method is shown in FIG.
エラー要因確率修正部3Bでは、工程別エラー要因推定部39で計算された工程別のエラー要因確率D2を、異常度記憶部35で記憶された工程別の異常度を用いて補正する。この補正方法の模式図を図10に示す。 (Error factor
The error factor
図10において、工程別エラー要因推定部39で計算されたエラー要因とそのエラー確率が上位3つまで工程別に取得されている。このエラー確率を、異常度記憶部35で記憶された工程別の異常度で補正し、補正後のエラー確率が上位のものを工程番号とともにエラー要因推定結果D3として取得する。この補正方法としては、例えば異常度の値を[0.0-1.0]で正規化してエラー確率に乗算するとしてもよいし、異常度が閾値以上の工程を高く閾値以上の工程が低くなるような係数を算出してエラー確率に乗算するなどとしてもよい。こうして得られたエラー要因推定結果D3を、端末4を介してユーザに提示する。
In FIG. 10, the top three error factors and their error probabilities calculated by the process-specific error factor estimation unit 39 are obtained for each process. These error probabilities are corrected by the degree of abnormality for each process stored in the degree of abnormality storage unit 35, and the error probability with the highest degree of error after correction is obtained together with the process number as the error factor estimation result D3. As a method of this correction, for example, the degree of abnormality value may be normalized by [0.0-1.0] and multiplied by the error probability, or a coefficient may be calculated so that processes with an abnormality degree above a threshold are increased and processes with an abnormality degree above the threshold are decreased, and the coefficient may be multiplied by the error probability. The error factor estimation result D3 obtained in this way is presented to the user via terminal 4.
(実施例3の効果)
実施例3では、工程ごとに求めたエラー要因の推定確率を、工程ごとの異常度で補正することで、工程ごとの異常度に応じたエラー要因を推定することができる。これにより、複数の工程の相互作用によりエラーが発生したケースにおいても、それぞれの工程におけるエラー要因を抽出してユーザに提示することができる。 (Effects of Example 3)
In the third embodiment, the estimated probability of the error factor obtained for each process is corrected by the abnormality degree for each process, so that the error factor according to the abnormality degree for each process can be estimated. As a result, even in a case where an error occurs due to the interaction of multiple processes, the error factor for each process can be extracted and presented to the user.
実施例3では、工程ごとに求めたエラー要因の推定確率を、工程ごとの異常度で補正することで、工程ごとの異常度に応じたエラー要因を推定することができる。これにより、複数の工程の相互作用によりエラーが発生したケースにおいても、それぞれの工程におけるエラー要因を抽出してユーザに提示することができる。 (Effects of Example 3)
In the third embodiment, the estimated probability of the error factor obtained for each process is corrected by the abnormality degree for each process, so that the error factor according to the abnormality degree for each process can be estimated. As a result, even in a case where an error occurs due to the interaction of multiple processes, the error factor for each process can be extracted and presented to the user.
(変形例)
本開示は、上述した実施形態に限定されるものでなく、様々な変形例を含んでいる。例えば、上述した実施形態は、本開示を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備える必要はない。また、ある実施形態の一部を他の実施形態の構成に置き換えることができる。また、ある実施形態の構成に他の実施形態の構成を加えることもできる。また、各実施形態の構成の一部について、他の実施形態の構成の一部を追加、削除又は置換することもできる。 (Modification)
The present disclosure is not limited to the above-described embodiments, and includes various modified examples. For example, the above-described embodiments have been described in detail to clearly explain the present disclosure, and it is not necessary to include all of the configurations described. In addition, a part of an embodiment can be replaced with a configuration of another embodiment. In addition, a configuration of another embodiment can be added to a configuration of an embodiment. In addition, a part of the configuration of each embodiment can be added to, deleted from, or replaced with a part of the configuration of another embodiment.
本開示は、上述した実施形態に限定されるものでなく、様々な変形例を含んでいる。例えば、上述した実施形態は、本開示を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備える必要はない。また、ある実施形態の一部を他の実施形態の構成に置き換えることができる。また、ある実施形態の構成に他の実施形態の構成を加えることもできる。また、各実施形態の構成の一部について、他の実施形態の構成の一部を追加、削除又は置換することもできる。 (Modification)
The present disclosure is not limited to the above-described embodiments, and includes various modified examples. For example, the above-described embodiments have been described in detail to clearly explain the present disclosure, and it is not necessary to include all of the configurations described. In addition, a part of an embodiment can be replaced with a configuration of another embodiment. In addition, a configuration of another embodiment can be added to a configuration of an embodiment. In addition, a part of the configuration of each embodiment can be added to, deleted from, or replaced with a part of the configuration of another embodiment.
例えば、上記した実施例1~3では、半導体検査装置1のエラー要因を推定する例について説明したが、半導体検査装置1以外の機器で発生するエラーのエラー要因を推定することも可能である。
For example, in the above-mentioned Examples 1 to 3, an example of estimating the error cause of the semiconductor inspection device 1 has been described, but it is also possible to estimate the error cause of an error that occurs in a device other than the semiconductor inspection device 1.
また、上記した実施例2では、工程別の異常度の計算手段として特徴量ベースの異常度とマッチングスコアベースの異常度の2つを用いたが、この2つ以外の3つ以上の異常度の計算手段を用いるとしてもよい。
In addition, in the above-mentioned second embodiment, two methods for calculating the degree of anomaly for each process are used: a feature-based degree of anomaly and a matching score-based degree of anomaly. However, three or more other methods for calculating the degree of anomaly may be used.
また、上記した実施例3では、実施例1の形態に工程別エラー要因推定部39、エラー辞書3A、エラー要因確率修正部3Bを付加した構成としたが、実施例2の形態にこれらを付加した構成としてもよい。
In addition, in the above-mentioned Example 3, a process-specific error factor estimation unit 39, an error dictionary 3A, and an error factor probability correction unit 3B are added to the configuration of Example 1, but these may also be added to the configuration of Example 2.
また、上記した実施例3において、エラー辞書3Aに蓄積される情報にレシピ修正案を含み、エラー要因推定結果D3でユーザに提示される情報として、エラー要因とレシピ修正案をあわせて提示するとしてもよい。
In addition, in the above-described third embodiment, the information stored in the error dictionary 3A may include recipe modification suggestions, and the error cause and the recipe modification suggestions may be presented together as information presented to the user in the error cause estimation result D3.
100:情報処理システム、1:半導体検査装置、2:データベース、3:エラー要因解析装置、31:工程別データ抽出部、32:エラーラベル付与部、33:エラー相関計算部、33a:特徴量生成部、33b:エラー分類モデル学習部、33c:モデル解析部、34:異常度計算部、34a:特徴量抽出部、34b:異常度計算部、35:異常度記憶部、36:異常工程推定部、37:マッチングスコアベースの異常度計算部、38:総合異常度計算部、39:工程別エラー要因推定部、3A:エラー辞書、3B:エラー要因確率修正部、4:端末、D1:異常工程推定結果、D2:エラー要因確率、D3:エラー要因推定結果、N:ネットワーク
100: Information processing system, 1: Semiconductor inspection device, 2: Database, 3: Error factor analysis device, 31: Process-specific data extraction unit, 32: Error label assignment unit, 33: Error correlation calculation unit, 33a: Feature generation unit, 33b: Error classification model learning unit, 33c: Model analysis unit, 34: Anomaly calculation unit, 34a: Feature extraction unit, 34b: Anomaly calculation unit, 35: Anomaly storage unit, 36: Abnormal process estimation unit, 37: Matching score-based anomaly calculation unit, 38: Overall anomaly calculation unit, 39: Process-specific error factor estimation unit, 3A: Error dictionary, 3B: Error factor probability correction unit, 4: Terminal, D1: Abnormal process estimation result, D2: Error factor probability, D3: Error factor estimation result, N: Network
Claims (10)
- 検査装置で計測したデータセットがエラーを含む場合、前記データセットに基づいて、検査工程を構成する複数の小工程からエラー原因の小工程を推定するエラー要因解析装置であって、
エラーが検知された測定点を含む小工程とは異なる小工程の測定点から、エラーが検知された測定点に関連するエラー関連測定点を推定すると共に、前記エラーが検知された測定点および前記エラー関連測定点にエラーラベルを付与するエラーラベル付与部と、
前記エラーラベルが付与された測定点と付与されない測定点のデータの違いから、エラー発生に相関の大きい特徴量を小工程毎に推定するエラー相関計算部と、
前記相関の大きい特徴量について、エラーラベルが付与された測定点と付与されない測定点のデータの統計的な乖離の度合いに応じて、特徴量ベースの異常度を小工程毎に計算する異常度計算部と、
小工程毎の異常度に基づきエラー原因の小工程を推定する異常工程推定部と、
を備えることを特徴とするエラー要因解析装置。 An error cause analysis device that, when a data set measured by an inspection device includes an error, estimates a sub-process causing an error from among a plurality of sub-processes constituting an inspection process based on the data set, comprising:
an error label assigning unit that estimates an error-related measurement point related to the measurement point where the error is detected from a measurement point of a sub-process other than the sub-process including the measurement point where the error is detected, and assigns an error label to the measurement point where the error is detected and the error-related measurement point;
an error correlation calculation unit that estimates a feature quantity that is highly correlated with error occurrence for each small process from a difference between data of a measurement point to which the error label is assigned and data of a measurement point to which the error label is not assigned;
an anomaly degree calculation unit that calculates a feature-based anomaly degree for each small process in accordance with a degree of statistical deviation between data of a measurement point to which an error label is assigned and data of a measurement point to which an error label is not assigned, for the feature values having a high correlation;
an abnormal process estimation unit that estimates a sub-process causing an error based on the degree of abnormality of each sub-process;
An error cause analysis device comprising: - 請求項1に記載のエラー要因解析装置において、
更に、測定点のテンプレート画像と、測定点の撮像画像のマッチングスコアを推定し、エラーラベルが付与された測定点と付与されない測定点のマッチングスコアの統計的な乖離の度合いに応じてマッチングスコアベースの異常度を計算する第2の異常度計算部と、
前記異常度計算部で計算した小工程毎の異常度と、前記第2の異常度計算部で計算した小工程毎の異常度とに基づいて、小工程毎の総合異常度を計算する総合異常度計算部と、
を備え、
前記異常工程推定部は、小工程毎の総合異常度に基づきエラー原因の小工程を推定することを特徴とするエラー要因解析装置。 2. The error cause analysis device according to claim 1,
a second anomaly degree calculation unit that estimates a matching score between a template image of the measurement point and a captured image of the measurement point, and calculates a matching score-based anomaly degree according to a degree of statistical deviation between the matching scores of a measurement point to which an error label is assigned and a measurement point to which no error label is assigned;
a total abnormality degree calculation unit that calculates a total abnormality degree for each sub-process based on the abnormality degree for each sub-process calculated by the abnormality degree calculation unit and the abnormality degree for each sub-process calculated by the second abnormality degree calculation unit;
Equipped with
The error cause analysis device is characterized in that the abnormal process estimation unit estimates the sub-process causing the error based on the overall abnormality degree for each sub-process. - 請求項1または請求項2に記載のエラー要因解析装置において、
更に、エラーの特徴とそのエラー要因やパラメータ修正案の関連を蓄積したエラー辞書と、
前記相関の大きい特徴量や測定結果の統計情報のエラー特徴の組合せと類似する項目を前記エラー辞書の中から検索して、エラー要因やパラメータ修正案の候補を小工程毎に抽出する工程別エラー要因推定部と、
を備えることを特徴とするエラー要因解析装置。 3. The error cause analysis device according to claim 1,
In addition, an error dictionary that stores the relationship between the characteristics of errors, their causes, and parameter correction proposals;
a process-specific error factor estimating unit that searches the error dictionary for items similar to a combination of the highly correlated feature quantities and error features of statistical information of the measurement results, and extracts error factors and candidates for parameter correction proposals for each sub-process;
An error cause analysis device comprising: - 請求項3に記載のエラー要因解析装置において、
前記小工程毎のエラー要因やパラメータ修正案の類似度を、前記小工程毎の異常度に応じて補正し、各小工程のエラー要因やパラメータ修正案の中から補正後の類似度が高い上位のものを抽出してユーザに提示することを特徴とするエラー要因解析装置。 4. The error cause analysis device according to claim 3,
an error factor analysis device that corrects the similarity between the error factors and parameter correction proposals for each sub-process in accordance with the degree of abnormality for each sub-process, extracts the error factors and parameter correction proposals for each sub-process that have the highest similarity after correction, and presents them to a user. - 請求項4に記載のエラー要因解析装置において、
エラー発生のなかった測定点の数に対して、エラーが検知された測定点の確率が閾値以下である場合に、前記抽出された補正後の類似度のうち一部の項目の類似度を低めることを特徴とするエラー要因解析装置。 5. The error factor analysis device according to claim 4,
An error cause analysis device characterized in that, when the probability of measurement points at which an error is detected relative to the number of measurement points at which no error occurred is equal to or less than a threshold, the similarity of some items among the extracted corrected similarities is reduced. - 請求項1に記載のエラー要因解析装置において、
前記異常工程推定部は、小工程毎の前記異常度が閾値以上で、かつ、最も上流の工程をエラー原因の小工程と推定することを特徴とするエラー要因解析装置。 2. The error cause analysis device according to claim 1,
The error cause analysis device is characterized in that the abnormal process estimation unit estimates that the sub-process causing the error is the process that is the most upstream process and has the degree of abnormality for each sub-process equal to or greater than a threshold value. - 請求項2に記載のエラー要因解析装置において、
前記異常工程推定部は、小工程毎の前記総合異常度が閾値以上で、かつ、最も上流の工程をエラー原因の小工程と推定することを特徴とするエラー要因解析装置。 3. The error cause analysis device according to claim 2,
The error cause analysis device is characterized in that the abnormal process estimation unit estimates that the sub-process causing the error is the process that is most upstream and has the overall abnormality degree for each sub-process equal to or greater than a threshold value. - 請求項1に記載のエラー要因解析装置において、
前記異常工程推定部は、小工程毎の前記異常度、前記相関の大きい特徴量の項目やその相関度と、エラー原因工程の関係を学習したモデルを構築し、前記モデルで推定された工程をエラー原因工程とすることを特徴とするエラー要因解析装置。 2. The error cause analysis device according to claim 1,
the abnormal process estimation unit constructs a model that learns the relationship between the degree of abnormality for each sub-process, the feature items with high correlation and their correlations, and the process causing the error, and determines the process estimated by the model as the process causing the error. - 請求項2に記載のエラー要因解析装置において、
前記異常工程推定部は、小工程毎の前記総合異常度、前記相関の大きい特徴量の項目やその相関度と、エラー原因工程の関係を学習したモデルを構築し、前記モデルで推定された工程をエラー原因工程とすることを特徴とするエラー要因解析装置。 3. The error cause analysis device according to claim 2,
the abnormal process estimation unit constructs a model that learns the relationship between the overall abnormality degree for each sub-process, the feature items with high correlations and their correlations, and the error cause process, and determines the process estimated by the model as the error cause process. - 検査装置で計測したデータセットがエラーを含む場合、前記データセットに基づいて、検査工程を構成する複数の小工程からエラー原因の小工程を推定するエラー要因解析方法であって、
エラーが検知された測定点を含む小工程とは異なる小工程の測定点から、エラーが検知された測定点に関連するエラー関連測定点を推定すると共に、前記エラーが検知された測定点および前記エラー関連測定点にエラーラベルを付与するエラーラベル付与ステップと、
前記エラーラベルが付与された測定点と付与されない測定点のデータの違いから、エラー発生に相関の大きい特徴量を小工程毎に推定するエラー相関計算ステップと、
前記相関の大きい特徴量について、エラーラベルが付与された測定点と付与されない測定点のデータの統計的な乖離の度合いに応じて、特徴量ベースの異常度を小工程毎に計算する異常度計算ステップと、
小工程毎の異常度に基づきエラー原因の小工程を推定する異常工程推定ステップと、
を備えることを特徴とするエラー要因解析方法。 1. An error cause analysis method for estimating a sub-process causing an error from among a plurality of sub-processes constituting an inspection process based on a data set measured by an inspection device when the data set contains an error, comprising:
an error labeling step of estimating an error-related measurement point related to the measurement point where the error is detected from a measurement point of a sub-process other than the sub-process including the measurement point where the error is detected, and assigning an error label to the measurement point where the error is detected and the error-related measurement point;
an error correlation calculation step of estimating a feature quantity having a high correlation with error occurrence for each small process from a difference between data of a measurement point to which an error label is assigned and data of a measurement point to which an error label is not assigned;
an anomaly calculation step of calculating a feature-based anomaly level for each sub-process in accordance with a degree of statistical deviation between data of a measurement point to which an error label is assigned and data of a measurement point to which an error label is not assigned for the feature having a high correlation;
an abnormal process estimation step of estimating a sub-process causing an error based on the degree of abnormality for each sub-process;
13. An error cause analysis method comprising:
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