WO2024095639A1 - Light receiving element and electronic device - Google Patents

Light receiving element and electronic device Download PDF

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Publication number
WO2024095639A1
WO2024095639A1 PCT/JP2023/034818 JP2023034818W WO2024095639A1 WO 2024095639 A1 WO2024095639 A1 WO 2024095639A1 JP 2023034818 W JP2023034818 W JP 2023034818W WO 2024095639 A1 WO2024095639 A1 WO 2024095639A1
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transistor
region
amplifier transistor
insulating film
pixel
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PCT/JP2023/034818
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French (fr)
Japanese (ja)
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光児 布村
千広 荒井
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024095639A1 publication Critical patent/WO2024095639A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • This disclosure relates to a light receiving element and an electronic device.
  • CMOS image sensors include a type in which pixel signals photoelectrically converted by photodiodes are read out to a source follower circuit for all pixels simultaneously. Reading out pixel signals from all pixels simultaneously, as in this type of CMOS image sensor, results in high power consumption. On the other hand, if you try to drive the amplifier transistor of the source follower circuit in a lower current range than before in order to reduce power consumption, it is expected that random noise (RN) will worsen. Thermal noise in the source follower circuit has a large impact on this deterioration of random noise.
  • the present disclosure therefore provides a light receiving element and electronic device capable of reducing random noise.
  • the light receiving element includes a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light, and a source follower circuit including an amplifier transistor that amplifies the pixel signal.
  • a source follower circuit including an amplifier transistor that amplifies the pixel signal.
  • an insulating film is formed directly below each of the drain region and source region of the amplifier transistor.
  • the impurity concentration of the semiconductor well region between the drain region and the source region may be a concentration that is depleted to the same depth as the bottom ends of the drain region and the source region, or to a position deeper than the bottom ends while the amplifier transistor is operating.
  • the impurity concentration may be 10 times or more lower than 4e17 (cm ⁇ 3 ).
  • the semiconductor well region may also be an epitaxially grown layer of silicon.
  • the semiconductor well region may also have a silicon germanium layer directly below a channel region formed between the drain region and the source region while the amplifier transistor is in operation.
  • the thickness of the insulating film may also be at least deeper than the depletion layer that is generated while the amplifier transistor is in operation.
  • the thickness of the insulating film may be within 10% of the thickness of the semiconductor substrate on which the amplifier transistor is formed.
  • the insulating film may also surround the amplifier transistor.
  • each of the drain region and the source region may be a polysilicon film.
  • the insulating film may also be formed directly below a channel region that is formed between the drain region and the source region while the amplifier transistor is in operation.
  • the channel region may also be formed on a Si(110) surface.
  • the amplifier transistor may also be a Fin-type MOS transistor.
  • the amplifier transistor may also be disposed on the same semiconductor substrate as the photoelectric conversion circuit.
  • the amplifier transistor may also be disposed on a different semiconductor substrate from the photoelectric conversion circuit.
  • An electronic device includes a light receiving element including a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light, and a source follower circuit including an amplifier transistor that amplifies the pixel signal.
  • a light receiving element including a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light
  • a source follower circuit including an amplifier transistor that amplifies the pixel signal.
  • an insulating film is formed directly below each of the drain region and source region of the amplifier transistor.
  • FIG. 1 is a block diagram showing an example of the configuration of a CMOS image sensor according to a first embodiment
  • FIG. 2 is a diagram showing a circuit configuration of a pixel in a pixel array portion.
  • 1 is a diagram showing an example of a stacked structure of a CMOS image sensor according to a first embodiment
  • 11 is a plan view showing an example of the layout of an upper pixel array unit.
  • FIG. 5 is a cross-sectional view taken along the line AA shown in FIG. 4.
  • 1A to 1C are cross-sectional views showing a step of forming a silicon oxide film on a semiconductor substrate.
  • 1A to 1C are cross-sectional views showing a step of forming an insulating film in a semiconductor substrate.
  • FIG. 11A to 11C are cross-sectional views showing a step of etching a part of an insulating film.
  • FIG. 2 is a cross-sectional view showing a selective epitaxial growth process.
  • FIG. 2 is a cross-sectional view showing a non-selective epitaxial growth step.
  • FIG. 11 is a cross-sectional view showing a planarization process.
  • 1A to 1C are cross-sectional views showing a step of forming a gate electrode, a drain region, and a source region.
  • 10A to 10C are cross-sectional views showing another example of a process for forming a silicon oxide film on a semiconductor substrate.
  • 10A to 10C are cross-sectional views showing another example of a process for forming an insulating film in a semiconductor substrate.
  • 11A to 11C are cross-sectional views showing a step of dividing an insulating film.
  • 10A to 10C are cross-sectional views showing another example of a step of etching a part of an insulating film.
  • FIG. 2 is a cross-sectional view showing a selective epitaxial growth process.
  • FIG. 2 is a cross-sectional view showing a non-selective epitaxial growth step.
  • FIG. 11 is a cross-sectional view showing a planarization process.
  • 1A to 1C are cross-sectional views showing a step of forming a gate electrode, a drain region, and a source region.
  • FIG. 11 is a cross-sectional view showing a structure of a first amplifier transistor according to a second embodiment.
  • FIG. 1 is a perspective view showing a structure of a general Fin-type MOS transistor.
  • FIG. 11 is a cross-sectional view showing a structure of a first amplifier transistor according to a third embodiment.
  • 1A to 1C are cross-sectional views showing a process for forming a semiconductor substrate.
  • 1A to 1C are cross-sectional views showing a step of forming a stopper film in a semiconductor substrate.
  • 1A to 1C are cross-sectional views showing a process of forming a trench for an ESS.
  • 1A to 1C are cross-sectional views showing a process of forming an ESS.
  • FIG. 11A to 11C are cross-sectional views showing a step of forming an insulating film in the trench and the ESS.
  • FIG. 11 is a cross-sectional view showing a planarization process.
  • 1A to 1C are cross-sectional views showing a step of forming a gate electrode, a drain region, and a source region.
  • FIG. 13 is a diagram showing a circuit configuration of a pixel according to a first modified example.
  • FIG. 13 is a diagram showing a circuit configuration of a pixel according to a second modified example.
  • FIG. 13 is a diagram showing a circuit configuration of a pixel according to a third modified example.
  • FIG. 13 is a diagram showing a circuit configuration of a pixel according to a fourth modified example.
  • FIG. 13 is a diagram showing a circuit configuration of a pixel according to a first modified example.
  • FIG. 13 is a diagram showing a circuit configuration of a pixel according to a second modified example.
  • FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a fourth modified example.
  • 17 is a cross-sectional view taken along the line BB shown in FIG. 16.
  • 17 is a cross-sectional view of the periphery of a transfer transistor and a first selection transistor in the layout shown in FIG. 16.
  • 13 is a cross-sectional view in which a Fin-type MOS transistor is applied to a first amplifier transistor according to a fourth modified example.
  • FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a fifth modified example.
  • FIG. 13 is a diagram showing a circuit configuration of a pixel according to a sixth modified example.
  • FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a sixth modified example.
  • FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a seventh modified example.
  • FIG. 13 is a diagram showing a configuration of a CMOS image sensor according to a fourth embodiment.
  • FIG. 11 is a cross-sectional view of a part of a CMOS image sensor according to a fourth embodiment, cut in the vertical direction.
  • FIG. 13 is a block diagram showing an example of the configuration of an electronic device according to a fifth embodiment.
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit;
  • First Embodiment Fig. 1 is a block diagram showing an example of the configuration of a CMOS image sensor according to the first embodiment.
  • the CMOS image sensor 1 shown in Fig. 1 includes a pixel array section 10, a vertical drive section 20, a column processing section 30, a horizontal drive section 40, a system control section 50, a signal processing section 60, and a memory section 70.
  • the pixel array section 10 has a plurality of pixels arranged two-dimensionally in a matrix. Each pixel has a photoelectric conversion element that generates and internally accumulates an electric charge whose amount corresponds to the amount of incident light. The circuit configuration of the pixel will be described later.
  • pixel array section 10 has pixel drive lines 80 connected to each pixel row, and vertical signal lines 90 connected to each pixel column.
  • the vertical drive unit 20 is composed of a shift register, an address decoder, etc., and drives each pixel of the pixel array unit 10 on a row basis, etc.
  • One end of a pixel drive line 80 is connected to the output terminal of the vertical drive unit 20 corresponding to each pixel row.
  • the column processing unit 30 has a signal processing circuit for each pixel column of the pixel array unit 10. Each signal processing circuit of the column processing unit 30 performs signal processing such as noise removal processing such as CDS (Correlated Double Sampling) processing and A/D (Analog/Digital) conversion processing on the pixel signals output from each pixel of the selected row through the vertical signal line 90.
  • the column processing unit 30 temporarily holds the pixel signals after signal processing.
  • the horizontal drive unit 40 is composed of a shift register, an address decoder, etc., and sequentially selects the signal processing circuits of the column processing unit 30. Through selective scanning by this horizontal drive unit 40, pixel signals that have been signal-processed by each signal processing circuit of the column processing unit 30 are output in sequence to the signal processing unit 60.
  • the system control unit 50 is composed of a timing generator that generates various timing signals, and controls the vertical drive unit 20, column processing unit 30, and horizontal drive unit 40 based on the various timing signals generated by the timing generator.
  • the signal processing unit 60 has at least an addition processing function.
  • the signal processing unit 60 performs various signal processing such as addition processing on the pixel signals output from the column processing unit 30. At this time, the signal processing unit 60 stores intermediate results of the signal processing in the memory unit 70 as necessary, and refers to them at the required timing.
  • the signal processing unit 60 outputs the pixel signals after signal processing.
  • the memory unit 70 is composed of DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), etc.
  • FIG. 2 is a diagram showing the circuit configuration of a pixel in the pixel array section 10.
  • the pixel 11 shown in FIG. 2 has a photoelectric conversion circuit 110, a first source follower circuit 120, a signal retention selection circuit 130, and a second source follower circuit 140. Each circuit will be described below.
  • the photoelectric conversion circuit 110 has a photodiode 111, a transfer transistor 112, a first reset transistor 113, and a discharge transistor 114.
  • the transfer transistor 112, the first reset transistor 113, and the discharge transistor 114 are configured, for example, with an N-channel MOS transistor.
  • the photodiode 111 converts incident light into electricity to generate an electric charge.
  • the anode of the photodiode 111 is connected to a ground having a reference potential.
  • the cathode of the photodiode 111 is connected to the transfer transistor 112 and the discharge transistor 114.
  • the transfer transistor 112 transfers charge from the photodiode 111 to the FD (Floating Diffusion) in accordance with a transfer signal TRG input to its gate from the vertical drive unit 20 through the pixel drive line 80.
  • the FD accumulates the charge and generates a pixel signal represented by a voltage according to the amount of charge.
  • the drain of the transfer transistor 112 is connected to the cathode of the photodiode 111, and the source is connected to the FD.
  • the first reset transistor 113 extracts charge from the FD to perform initialization in accordance with a first reset signal RST input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the drain of the first reset transistor 113 is connected to a power supply line having a potential of the power supply voltage VDD, and the source is connected to the FD.
  • the discharge transistor 114 discharges and initializes the charge accumulated in the photodiode 111 in accordance with a discharge signal OFG input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the drain of the discharge transistor 114 is connected to the cathode of the photodiode 111 and the drain of the transfer transistor 112.
  • the source of the discharge transistor 114 is connected to the power supply line.
  • the first source follower circuit 120 has a first amplifier transistor 121, a first selection transistor 122, a bias cut transistor 123, and a load transistor 124. Each transistor is connected in series between a power supply line having a potential of the power supply voltage VDD and ground, and is composed of, for example, an N-channel MOS transistor.
  • the first amplifier transistor 121 amplifies the voltage level of the pixel signal generated by the FD to a voltage V1 and outputs it to the signal holding and selection circuit 130.
  • the gate of the first amplifier transistor 121 is connected to the FD.
  • the drain is connected to the power supply line.
  • the source is connected to the drain of the first selection transistor 122.
  • the first selection transistor 122 switches whether or not to transmit the pixel signal amplified by the first amplifier transistor 121 to the signal holding selection circuit 130 according to a switching signal SW input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the drain of the first selection transistor 122 is connected to the source of the first amplifier transistor 121, and the source is connected to the drain of the signal holding selection circuit 130 and the bias cut transistor 123.
  • the bias cut transistor 123 switches whether or not to supply current from the load transistor 124 according to a bias cut signal PC input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the source of the bias cut transistor 123 is connected to the drain of the load transistor 124.
  • the load transistor 124 supplies a predetermined current into the first source follower circuit 120 according to the bias signal VB input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the source of the load transistor 124 is connected to ground.
  • the signal retention selection circuit 130 has a first capacitive element 131, a second capacitive element 132, a first sampling transistor 133, a second sampling transistor 134, and a second reset transistor 135.
  • Each transistor is, for example, an N-channel MOS transistor.
  • each of the first capacitive element 131 and the second capacitive element 132 is commonly connected to the output terminal of the first source follower circuit 120 (the source of the first selection transistor 122).
  • the other end of the first capacitive element 131 is connected to the drain of the first sampling transistor 133.
  • the other end of the second capacitive element 132 is connected to the drain of the second sampling transistor 134.
  • the first sampling transistor 133 switches whether or not to output the pixel signal held in the first capacitance element 131 to the output node 136 according to the first sampling signal SR input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the source of the first sampling transistor 133 is connected to the output node 136.
  • the second sampling transistor 134 switches whether or not to output the pixel signal held in the second capacitance element 132 to the output node 136 according to the second sampling signal SD input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the source of the second sampling transistor 134 is also connected to the output node 136 in common with the source of the first sampling transistor 133.
  • the second reset transistor 135 initializes the voltage V2 of the output node 136 to a predetermined voltage VREG according to a second reset signal RB input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the voltage VREG is set to a potential lower than the power supply voltage VDD.
  • the drain of the second reset transistor 135 is connected to a voltage wiring having a potential of the voltage VREG, and the source is connected to the output node 136.
  • the second source follower circuit 140 is a circuit that selectively reads out and amplifies a signal from the signal holding and selection circuit 130, and has a second amplifier transistor 141, a second selection transistor 142, and a current source 143.
  • the second amplifier transistor 141 and the second selection transistor 142 are connected in series with each other and are composed of, for example, N-channel MOS transistors.
  • the gate of the second amplifier transistor 141 is connected to the output node 136 of the signal holding selection circuit 130.
  • the drain is connected to a power supply line having a potential of the power supply voltage VDD.
  • the source is connected to the drain of the second selection transistor 142.
  • the second selection transistor 142 switches whether or not to output the pixel signal amplified by the second amplifier transistor 141 to the signal line VSL according to the second selection signal SEL input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the source of the second selection transistor 142 is connected to the signal line VSL and the current source 143.
  • the current source 143 is connected in series to the second selection transistor 142.
  • the current source 143 supplies a constant current to the second amplifier transistor 141 and the second selection transistor 142 in accordance with a control signal input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the vertical drive unit 20 supplies a high-level first reset signal RST and a transfer signal TRG to all pixels 11 at the start of exposure. This initializes the photodiodes 111.
  • the vertical drive unit 20 sets the second reset signal RB and the first sampling signal SR to high level for all pixels 11, and supplies a high-level first reset signal RST for the pulse period. This initializes the FD, and a pixel signal corresponding to the voltage level of the FD at that time is held in the first capacitance element 131.
  • the vertical drive unit 20 sets the second reset signal RB and the second sampling signal SD to high level for all pixels 11, and supplies a high-level transfer signal TRG for the pulse period.
  • a signal charge according to the amount of exposure is transferred to the FD, and a pixel signal according to the level of the FD at that time is held in the second capacitance element 132.
  • This type of exposure control in which exposure starts and ends simultaneously for all pixels 11, is called a global shutter method.
  • the photoelectric conversion circuits 110 of all pixels 11 generate pixel signals of the reset level and data level in sequence.
  • the pixel signal of the reset level is held in the first capacitance element 131, and the pixel signal of the data level is held in the second capacitance element 132.
  • the vertical drive unit 20 selects rows in sequence and outputs pixel signals of the reset level and data level for that row in sequence.
  • the vertical drive unit 20 sets the first reset signal RST and second selection signal SEL of the selected row to a high level, while supplying a high-level first sampling signal SR for a predetermined period of time. This connects the first capacitance element 131 to the output node 136, and the reset level is read out.
  • the vertical drive unit 20 After reading out the reset level, the vertical drive unit 20 supplies a high-level second reset signal RB for the pulse period while keeping the first reset signal RST and second selection signal SEL of the selected row at a high level. This initializes the voltage level of the output node 136. At this time, the first sampling transistor 133 and the second sampling transistor 134 are both in the off state, so the first capacitance element 131 and the second capacitance element 132 are disconnected from the output node 136.
  • the vertical drive unit 20 After initializing the output node 136, the vertical drive unit 20 supplies a high-level second sampling signal SD for a predetermined period of time while keeping the first reset signal RST and the second selection signal SEL of the selected row at a high level. This connects the second capacitance element 132 to the output node 136, and a pixel signal at a data level is read out.
  • FIG. 3 is a diagram showing an example of the stacked structure of the CMOS image sensor 1 according to the first embodiment.
  • the CMOS image sensor 1 according to this embodiment has a sensor chip 201 (first chip) and a logic chip 202 (second chip) stacked below the sensor chip 201.
  • the sensor chip 201 and logic chip 202 are electrically connected by, for example, so-called Cu-Cu bonding, which bonds Cu pads formed on each chip. Note that these chips can also be connected by vias or bumps in addition to Cu-Cu bonding.
  • the upper pixel array section 10a is arranged on the sensor chip 201.
  • the lower pixel array section 10b and the column processing section 30 are arranged on the logic chip 202.
  • the photoelectric conversion circuit 110, and the first amplifier transistor 121 and the first selection transistor 122 of the first source follower circuit 120 are arranged on the upper pixel array section 10a.
  • the bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120, the signal holding selection circuit 130, and the second source follower circuit 140 are arranged on the lower pixel array section 10b.
  • the layout of the sensor chip 201 and the logic chip 202 is not limited to the above layout.
  • all elements of the first source follower circuit 120 may be arranged on the logic chip 202. That is, the first source follower circuit 120 may be formed on a semiconductor substrate different from the semiconductor substrate on which the photoelectric conversion circuit 110 is formed. In this case, the arrangement space of the photodiode 111 in the sensor chip 201 is expanded, thereby improving the sensitivity.
  • the logic chip 202 also includes a vertical drive unit 20, a horizontal drive unit 40, a system control unit 50, a signal processing unit 60, and a memory unit 70, but these are not shown in FIG. 3.
  • FIG. 4 is a plan view showing an example of the layout of the upper pixel array section 10a.
  • an insulating film 115 is formed at the boundary between the area in which the FD, transfer transistor 112, and discharge transistor 114 are arranged and the area in which the first reset transistor 113 is arranged.
  • the insulating film 115 is an element isolation film formed as STI (Shallow Trench Isolation).
  • An insulating film 115 is also formed at the boundary between the area in which the first reset transistor 113 is arranged and the area in which the first selection transistor 122 is arranged. Furthermore, an insulating film 115 is also formed at the boundary between the area in which the first selection transistor 122 is arranged and the area in which the first amplifier transistor 121 is arranged. In particular, this insulating film 115 is formed so as to surround the first amplifier transistor 121.
  • this insulating film 115 is formed so as to surround the first amplifier transistor 121.
  • FIG. 5 is a cross-sectional view taken along the line A-A shown in FIG. 4.
  • the sensor chip 201 includes a semiconductor substrate 210.
  • This semiconductor substrate 210 is composed of an N-type base layer 211 and a P-type epitaxial growth layer 212 formed on the base layer 211.
  • a gate insulating film 112b of the transfer transistor 112 is formed on the epitaxial growth layer 212.
  • a gate electrode 112a of the transfer transistor 112 is formed on the gate insulating film 112b.
  • a sidewall insulating film 112c is formed on the side surface of the gate electrode 112a.
  • the gate electrode 112a can be formed using, for example, polysilicon.
  • the gate insulating film 112b and the sidewall insulating film 112c can be formed using, for example, silicon oxide (SiO 2 ).
  • An FD is formed in the drain region of the transfer transistor 112.
  • a photodiode 111 is formed in the source region of the transfer transistor 112.
  • a gate insulating film 121b of the first amplifier transistor 121 is also formed on the epitaxial growth layer 212.
  • a gate electrode 121a of the first amplifier transistor 121 is formed on the gate insulating film 121b.
  • a sidewall insulating film 121c is formed on a side surface of the gate electrode 121a.
  • the gate electrode 121a can be formed using, for example, polysilicon.
  • the gate insulating film 121b and the sidewall insulating film 121c can be formed using, for example, silicon oxide (SiO 2 ).
  • the drain region 121d and source region 121e of the first amplifier transistor 121 are formed in the epitaxial growth layer 212.
  • An insulating film 115 is formed directly below the drain region 121d and the source region 121e.
  • the CMOS image sensor 1 has two source follower circuits, the first source follower circuit 120 and the second source follower circuit 140, and therefore tends to consume large amounts of power. If an attempt is made to drive each transistor in each source follower circuit in a current range of nA order, which is lower than the conventional current range of ⁇ A order, in order to suppress this power consumption, it is expected that random noise will worsen.
  • the thermal noise of the first source follower circuit 120 in particular has a large effect on the deterioration of random noise.
  • V NSH V/sqrtHz
  • C Total capacity of V1 node (F)
  • ⁇ n1 A dimensionless parameter that depends on the bias, called the noise factor.
  • ⁇ n2 A dimensionless parameter that depends on the bias, called the noise factor.
  • the thermal noise V 2 NSH of the first source follower circuit 120 is determined by the ratio between gm1 of the first amplifier transistor 121 and gm2 of the load transistor 124, as shown in the following formula (2).
  • gm1 and gm2 are defined by the following equation (3).
  • gm1 and gm2 are electrical characteristics indicating how much current Ids can flow between the drain and source for each gate voltage Vg of the first amplifier transistor 121 and the load transistor 124.
  • the thermal noise V 2 NSH is improved by improving gm1 of the first amplifier transistor 121.
  • the relationship expressed by the following formula (4) holds among gm1, the capacitance C Dep of the depletion layer formed between the drain region 121d and the source region 121e, and the capacitance C ox of the gate insulating film 121b.
  • the drain-source current Ids of the first amplifier transistor 121 can be expressed by the following equations (5) and (6) when the Taur-Ning current equation is used in the subthreshold region.
  • ⁇ eff Effective mobility [cm 2 /V ⁇ s]
  • W Channel width [cm]
  • L Channel length [cm]
  • ⁇ Si Dielectric constant of silicon
  • q Elementary charge
  • Na Acceptor density (cm -3 )
  • ⁇ B Difference between Fermi potential and intrinsic potential [V]
  • k Boltzmann constant
  • T Absolute temperature [K]
  • Vg Gate voltage [V]
  • Vt Threshold voltage based on the definition of 2 ⁇ B [V]
  • m Body effect coefficient of MOSFET
  • Vds Source-drain voltage [V]
  • the body effect coefficient m can be expressed by the following equation (8).
  • the capacitance C Deep of the depletion layer can be reduced by increasing the width xd of the depletion layer.
  • This width xd can be expressed by the following formula (10).
  • ⁇ 0 Dielectric constant of vacuum
  • ⁇ B Surface potential
  • q Elementary charge
  • N A Impurity concentration of semiconductor well region
  • the depletion layer of the first amplifier transistor 121 can be expanded.
  • the insulating film 115 is formed immediately below the drain region 121d and the source region 121e. This makes it possible to increase the width xd of the depletion layer while suppressing the short channel effect even if the impurity concentration N A of the semiconductor well region is reduced.
  • the width xd of the depletion layer is estimated to be about 93 nm.
  • the capacitance C Dep of the depletion layer is about 1.97 (fF/ ⁇ m 2 ).
  • the width xd of the depletion layer is assumed to be about 565 nm.
  • the capacitance C Dep of the depletion layer is about 0.18 (fF/ ⁇ m 2 ).
  • the thickness t (see FIG. 5 ) of the insulating film 115 from the surface of the epitaxial growth layer 212 be within 10% of the thickness of the semiconductor substrate 210. For example, when the thickness of the semiconductor substrate 210 is about 6 ⁇ m, the thickness t of the insulating film 115 is about 510 nm.
  • the above values of the impurity concentration N A and the thickness t of the insulating film 115 are merely examples and are not limited to these values.
  • the impurity concentration N A may be a concentration that depletes the drain region 121d and the source region 121e to the same depth as the bottom ends of the drain region 121d and the source region 121e while the first amplifier transistor 121 is in operation, or to a position deeper than the bottom ends.
  • the insulating film 115 may be formed so that its thickness t is at least deeper than the depletion layer generated while the first amplifier transistor 121 is in operation.
  • the impurity concentration of the semiconductor well region may be different between the first amplifier transistor 121 and other pixel transistors such as the transfer transistor 112 and the first reset transistor 113. In other words, only the impurity concentration of the first amplifier transistor 121 may be lower than the impurity concentration of the other pixel transistors.
  • a silicon oxide film 213 is formed on the epitaxial growth layer 212 of the semiconductor substrate 210.
  • the silicon oxide film 213 can be formed by a commonly used film formation method such as thermal oxidation.
  • an insulating film 115 is formed in the epitaxial growth layer 212.
  • the insulating film 115 can be formed, for example, by filling a hole formed by etching a part of the epitaxial growth layer 212 with silicon oxide.
  • the silicon oxide can be filled using, for example, the ALD (Atomic Layer Deposition) method.
  • a portion of the insulating film 115 is etched using, for example, a mask.
  • the area to be etched is the area where the drain region 121d and source region 121e of the first amplifier transistor 121 are formed.
  • the epitaxial growth layer 212 between the insulating films 115 is selectively epitaxially grown to form the channel region 212a of the first amplifier transistor 121.
  • the epitaxial growth layer 212 is selectively epitaxially grown, for example, by a single-wafer thermal CVD (Chemical Vapor Deposition Method).
  • a single-wafer thermal CVD Chemical Vapor Deposition Method
  • nucleation is controlled by the effect of an etchant gas such as hydrogen chloride (HCl).
  • the above region is epitaxially grown at a film formation speed that increases the difference in film formation time with the silicon oxide film 213, so that the channel region 212a is formed only in the region of the epitaxial growth layer 212 exposed between the insulating films 115.
  • a polysilicon film 214 is formed on the silicon oxide film 213 by non-selective epitaxial growth, and the channel region 212a is further epitaxially grown.
  • epitaxial growth is also performed by a single-wafer thermal CVD (Chemical Vapor Deposition Method).
  • the etchant gas used in this non-selective epitaxial growth process is changed from the etchant gas used in the selective epitaxial growth process. In other words, an etchant gas that does not suppress nucleation is used.
  • epitaxial growth is performed at a film growth rate that reduces the difference in film growth time between the silicon oxide film 213 and the channel region 212a.
  • the film growth temperature (substrate temperature) in this non-selective epitaxial growth process is set to a temperature higher than the film growth temperature (substrate temperature) in the selective epitaxial growth process.
  • a planarization process is performed by CMP (Chemical Mechanical Polishing). This removes the silicon oxide film 213, part of the polysilicon film 214, and part of the channel region 212a. As a result, the polysilicon film 214 remains in the regions that will become the drain region 121d and the source region 121e on the silicon oxide film 213, and the channel region 212a remains between the remaining polysilicon film 214.
  • CMP Chemical Mechanical Polishing
  • a gate insulating film 121b, a gate electrode 121a, and a sidewall insulating film 121c are formed on the channel region 212a. Since these can be formed by a commonly used manufacturing process, detailed description is omitted.
  • an N-type impurity is implanted into the polysilicon film 214 remaining after the planarization process to form the drain region 121d and the source region 121e.
  • the concentration of this impurity is, for example, about 1e 20 cm ⁇ 3 .
  • the drain region 121d and the source region 121e it is not necessary to diffuse the impurity into the entire region, and it is sufficient that at least the portion in contact with the channel region 212a is a diffusion film. That is, the inside of the drain region 121d and the source region 121e may be a diffusion film, and the outside may be a polysilicon film. In this embodiment, the concentration of the P-type semiconductor well region including the channel region 212a is extremely low. Therefore, this semiconductor well region is a non-doped region formed by epitaxial growth rather than ion implantation.
  • the above-described method for manufacturing the first amplifier transistor 121 is an example, and is not limited to this.
  • Figures 7A to 7H another example of the method for manufacturing the first amplifier transistor 121 according to this embodiment will be described. Note that in this example, redundant descriptions of manufacturing steps similar to those described using Figures 6A to 6G will be omitted.
  • a silicon oxide film 213 is formed on a base layer 211 of a semiconductor substrate 210.
  • the insulating film 115 is formed.
  • the insulating film 115 can be formed, for example, by filling a hole formed by etching a part of the base layer 211 with silicon oxide using an ALD method or the like.
  • the insulating film 115 is formed in the formation region of the drain region 121d and the source region 121e of the first amplifier transistor 121 as shown in FIG. 6B.
  • the insulating film 115 is formed over the entire formation region of the first amplifier transistor 121.
  • the insulating film 115 is divided.
  • the division is at a portion that will become the channel region 212a of the first amplifier transistor 121.
  • the insulating film 115 can be divided by etching using, for example, an RIE (Reactive Ion Etching) device.
  • a portion of the insulating film 115 is etched using, for example, a mask.
  • the area to be etched is the area where the drain region 121d and source region 121e of the first amplifier transistor 121 are formed.
  • the etched portions of the insulating film 115 are selectively epitaxially grown to form a channel region 212a, which is a P-type epitaxial growth layer.
  • a polysilicon film 214 is formed on the silicon oxide film 213 by non-selective epitaxial growth, and the channel region 212a is further epitaxially grown.
  • a planarization process is performed by CMP. This removes the silicon oxide film 213, part of the polysilicon film 214, and part of the channel region 212a. As a result, the polysilicon film 214 remains in the regions that will become the drain region 121d and the source region 121e on the silicon oxide film 213, and the channel region 212a remains between the remaining polysilicon film 214.
  • an epitaxial growth layer 212 is formed on the upper part of the base layer 211, and a gate insulating film 121b, a gate electrode 121a, and a sidewall insulating film 121c are formed on the channel region 212a.
  • an N-type impurity is implanted into the polysilicon film 214 remaining after the planarization process to form the drain region 121d and the source region 121e.
  • the concentration of this impurity is, for example, about 1e 20 cm ⁇ 3 .
  • the drain region 121d and the source region 121e it is not necessary to diffuse the impurity into the entire region, and it is sufficient that at least the part in contact with the channel region 212a is a diffusion film. That is, the inside of the drain region 121d and the source region 121e may be a diffusion film, and the outside may be a polysilicon film. In this example, the concentration of the P-type semiconductor well region including the channel region 212a is extremely low. Therefore, this semiconductor well region is a non-doped region formed by epitaxial growth rather than ion implantation.
  • the insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120 even when the first amplifier transistor 121 is driven with a low current. Therefore, the CMOS image sensor 1 according to this embodiment makes it possible to reduce random noise while suppressing power consumption.
  • the second embodiment will be described below.
  • the structure of the first amplifier transistor 121 is different from that of the first embodiment. Therefore, only the structure of the first amplifier transistor 121 will be described here, and other descriptions will be omitted.
  • FIG. 8 is a cross-sectional view showing the structure of the first amplifier transistor 121 according to the second embodiment.
  • the same components as those in the first embodiment are given the same reference numerals.
  • a SiGe (silicon germanium) layer 215 is formed directly below the channel region 212a. That is, the epitaxial growth layer 212 of the first amplifier transistor 121 has a three-layer structure of a first silicon layer which is the channel region 212a, a SiGe layer 215, and a second silicon layer stacked on the SiGe layer 215.
  • the SiGe layer 215 can be formed during the selective epitaxial growth process shown in FIG. 6D or FIG. 7E.
  • the etchant gas introduced into the thermal CVD apparatus is switched from a first etchant gas for forming the SiGe layer 215 in the film formation apparatus to a second etchant gas for forming the channel region 212a. This allows the SiGe layer 215 and the channel region 212a to be selectively formed between the insulating films 115.
  • the interatomic distance of the SiGe layer 215 formed as described above is larger than the interatomic distance of silicon in the channel region 212a. Therefore, tensile stress is generated in the channel region 212a in the channel length direction (see the arrow in FIG. 8). This improves the electron mobility in the channel region 212a, and gm1 of the first amplifier transistor 121 increases. As a result, as shown in the formula (1) described in the first embodiment, the thermal noise V 2 NSH of the first source follower circuit 120 can be further reduced. Therefore, according to this embodiment, it is possible to further reduce random noise.
  • the third embodiment will be described.
  • the structure of the first amplifier transistor 121 is different from that of the first embodiment. Therefore, here too, only the structure of the first amplifier transistor 121 will be described, and other descriptions will be omitted.
  • the crystal plane of the channel region 212a will be arranged on the Si(111) surface, which has relatively many defects. In this case, there is a concern that the electrical characteristics may deteriorate.
  • the structure of a Fin-type MOS transistor is applied to the first amplifier transistor 121.
  • the structure of a general Fin-type MOS transistor will be described with reference to FIG. 9.
  • FIG. 9 is a perspective view showing the structure of a typical Fin-type MOS transistor.
  • a silicon oxide film 1150 is formed on a silicon substrate 2120.
  • a gate electrode 1210a having a so-called double gate structure is formed in the silicon oxide film 1150.
  • a drain region 1210d and a source region 1210e are arranged opposite each other with the gate electrode 1210a in between.
  • FIG. 10 is a cross-sectional view showing the structure of the first amplifier transistor 121 according to the third embodiment. Since FIG. 10 is a cross-sectional view, the drain region 121d and the source region 121e are omitted. However, similar to the Fin-type MOS transistor 1210, the drain region 121d is formed on the rear side of the gate electrode 121a, and the source region 121e is formed on the front side of the gate electrode 121a. Also, an insulating film 115 is formed directly below the drain region 121d and the source region 121e, similar to the other embodiments described above.
  • a semiconductor substrate 210 is formed, which is made of a base layer 211 on which an epitaxial growth layer 212 is not formed.
  • a part of the insulating film 115 is formed in the base layer 211.
  • This insulating film 115 can be formed, for example, by filling holes formed in the base layer 211 by etching or the like with silicon oxide using the ALD method or the like.
  • This insulating film 115 functions as a stopper film for ESS (Empty Space in Silicon), which will be described later.
  • a silicon nitride (SiN) film 216 is formed on the base layer 211. Then, a silicon oxide (SiO 2 ) film 217 is formed on the silicon nitride film 216. Then, a trench 218 for ESS, which will be described later, is formed. The trench 218 penetrates the silicon nitride film 216 and the silicon oxide film 217, and terminates at the base layer 211. In the base layer 211, the trench 218 is formed on the inside of the stopper film (insulating film 115). The depth of the trench 218 is shallower than the stopper film.
  • ESS 219 is formed in base layer 211.
  • ESS 219 can be formed by, for example, flowing an alkaline etching solution through trench 218 to highly selectively etch the Si(110) surface relative to the Si(111) surface. This etching stops at insulating film 115. This completes ESS 219 extending in the direction of the Si(110) surface.
  • the insulating film 115 is completed by filling the trench 218 and the ESS 219 with silicon oxide using the ALD method. As a result, a pseudo FD-SOI (Fully Depleted Silicon On Insulator) structure is formed.
  • a planarization process is performed by CMP. This removes the silicon nitride film 216 and the silicon oxide film 217.
  • an epitaxial growth layer 212 is formed on the upper part of the base layer 211, and a gate electrode 121a and a sidewall insulating film 121c of a double gate structure are formed. In this process, a drain region 121d and a source region 121e are also formed.
  • the epitaxial growth layer 212 i.e., the P-type semiconductor well region including the channel region 212a, has an extremely low concentration. Therefore, this semiconductor well region is a non-doped region formed by epitaxial growth rather than ion implantation.
  • the channel region 212a can be formed on the Si(110) surface, which has relatively few crystal defects. This makes it possible to improve the electrical characteristics of the first amplifier transistor 121.
  • an insulating film 115 is formed directly below the drain region 121d and the source region 121e. This makes it possible to make the impurity concentration of the channel region 212a extremely low while suppressing the short channel effect. This makes it possible to reduce random noise even when the first amplifier transistor 121 is driven in a low current region. Note that in this embodiment, the insulating film 115 is formed not only directly below the drain region 121d and the source region 121e, but also directly below the channel region 212a.
  • FIG. 12 is a diagram showing a circuit configuration of a pixel according to a first modified example.
  • the pixel 11a shown in Fig. 12 has a photoelectric conversion circuit 110a, a first source follower circuit 120a, a signal holding selection circuit 130a, and a second source follower circuit 140a.
  • the photoelectric conversion circuit 110a has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
  • the first source follower circuit 120a has a first amplifier transistor 121 and a bias cut transistor 123. These circuit elements are also described in the first embodiment, so detailed description will be omitted.
  • the signal holding selection circuit 130a has a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, and a second sampling transistor 134.
  • one end of each of the first capacitance element 131 and the second capacitance element 132 is connected to a power supply line having a potential of the power supply voltage VDD.
  • the other end of the first capacitance element 131 is connected to the source of the first sampling transistor 133.
  • the other end of the second capacitance element 132 is connected to the source of the second sampling transistor 134.
  • the first sampling transistor 133 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitance element 131 according to the first sampling signal SR input to its gate from the vertical drive unit 20 through the pixel drive line 80.
  • the second sampling transistor 134 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the second capacitance element 132 according to the second sampling signal SD input to its gate from the vertical drive unit 20 through the pixel drive line 80.
  • the drains of the sampling transistors are commonly connected to the output terminal of the first source follower circuit 120a.
  • the second source follower circuit 140a has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. In the second source follower circuit 140a, these circuit elements are connected to the first capacitance element 131 and the second capacitance element 132, respectively, to form a pair.
  • the photoelectric conversion circuit 110a and the first amplifier transistor 121 of the first source follower circuit 120a are arranged on the sensor chip 201.
  • the bias cut transistor 123 of the first source follower circuit 120a, the signal hold selection circuit 130a, and the second source follower circuit 140a are arranged on the logic chip 202.
  • the arrangement of the sensor chip 201 and the pixels 11a in the sensor chip 201 is not limited to the arrangement described above.
  • an insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120a even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
  • Fig. 13 is a diagram showing a circuit configuration of a pixel according to a second modified example.
  • the pixel 11b shown in Fig. 13 has a photoelectric conversion circuit 110b, a first source follower circuit 120b, a signal holding selection circuit 130b, and a second source follower circuit 140b.
  • the photoelectric conversion circuit 110b has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
  • the first source follower circuit 120b has a first amplifier transistor 121 and a bias cut transistor 123. These circuit elements are also described in the first embodiment, so detailed description will be omitted.
  • the signal holding selection circuit 130b has a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, and a second sampling transistor 134.
  • one end of the first capacitance element 131 is connected to a power supply line having a potential of the power supply voltage VDD.
  • the other end of the first capacitance element 131 is connected to the source of the first sampling transistor 133 and one end of the second capacitance element 132.
  • the other end of the second capacitance element 132 is connected to the output node 136.
  • the first sampling transistor 133 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitance element 131 and the second capacitance element 132 according to the first sampling signal SR input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the drain of the first sampling transistor 133 is commonly connected to the output terminal of the first source follower circuit 120a.
  • the second sampling transistor 134 resets the potential of the output node 136 according to the second sampling signal SD input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the drain of the second sampling transistor 134 is connected to the power supply line, and the source is connected to the output node 136.
  • the second source follower circuit 140b has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
  • the photoelectric conversion circuit 110b and the first amplifier transistor 121 of the first source follower circuit 120b are arranged on the sensor chip 201.
  • the bias cut transistor 123, signal hold selection circuit 130b, and second source follower circuit 140b of the first source follower circuit 120b are arranged on the logic chip 202.
  • the arrangement of the sensor chip 201 and the pixel 11b in the sensor chip 201 is not limited to the arrangement described above.
  • an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120b even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
  • Fig. 14 is a diagram showing a circuit configuration of a pixel according to a third modified example.
  • the pixel 11c shown in Fig. 14 has a photoelectric conversion circuit 110c, a first source follower circuit 120c, a signal holding selection circuit 130c, and a second source follower circuit 140c.
  • the photoelectric conversion circuit 110c has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
  • the first source follower circuit 120c has a first amplifier transistor 121, a bias cut transistor 123, and a load transistor 124. These circuit elements are also described in the first embodiment, so detailed description will be omitted.
  • the signal holding selection circuit 130c has a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, a second sampling transistor 134, and a switching transistor 137.
  • one end of each of the first capacitance element 131 and the second capacitance element 132 is connected to a power supply line having a potential of the power supply voltage VDD.
  • the other end of the first capacitance element 131 is connected to the drain of the first sampling transistor 133.
  • the other end of the second capacitance element 132 is connected to the drain of the second sampling transistor 134.
  • the first sampling transistor 133 switches whether or not to output the pixel signal held in the first capacitance element 131 to the second source follower circuit 140c according to the first sampling signal SR input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the source of the first sampling transistor 133 is connected to the source of the switching transistor 137 and the output node 136.
  • the second sampling transistor 134 switches whether or not to output the pixel signal held in the second capacitance element 132 to the second source follower circuit 140c according to the second sampling signal SD input to the gate from the vertical drive unit 20 through the pixel drive line 80.
  • the source of the second sampling transistor 134 is connected to the source of the switching transistor 137 and the output node 136.
  • the switching transistor 137 is composed of an N-channel MOS transistor.
  • a switching signal SH is input to the gate of the switching transistor 137 from the vertical drive unit 20 through the pixel drive line 80.
  • the switching transistor 137 is turned on based on the switching signal SH, the signal amplified by the first source follower circuit 120c is held in the first capacitance element 131 or the second capacitance element 132.
  • the second source follower circuit 140c has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
  • the photoelectric conversion circuit 110c and the first amplifier transistor 121 of the first source follower circuit 120c are arranged on the sensor chip 201.
  • the bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120c, the signal hold selection circuit 130b, and the second source follower circuit 140b are arranged on the logic chip 202.
  • the arrangement of the sensor chip 201 and the pixel 11c in the sensor chip 201 is not limited to the arrangement described above.
  • an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
  • FIG. 15 is a diagram showing a circuit configuration of a pixel according to a fourth modified example.
  • the pixel 11d shown in Fig. 15 has a photoelectric conversion circuit 110d, a first source follower circuit 120d, a signal holding selection circuit 130d, and a second source follower circuit 140d.
  • the photoelectric conversion circuit 110d has a photodiode 111, a transfer transistor 112, a first reset transistor 113, a switching transistor 116, and a capacitance element 117.
  • the switching transistor 116 is configured as an N-channel MOS transistor and is disposed between the first reset transistor 113 and the FD.
  • One end of the capacitance element 117 is connected to the drain of the switching transistor 116, and the other end is grounded.
  • a drive signal FDG is input from the vertical drive unit 20 to the gate of the switching transistor 116. When the switching transistor 116 is turned on based on the drive signal FDG, the charge held in the capacitance element 117 is transferred to the FD.
  • the circuit configurations of the first source follower circuit 120d, the signal holding selection circuit 130d, and the second source follower circuit 140d are the same as those in the first embodiment, and therefore will not be described.
  • the second reset transistor 135 of the signal holding selection circuit 130d and the second source follower circuit 140d are shared by four pixels 11d.
  • FIG. 16 is a plan view showing an example of the layout of a sensor chip 201 according to the fourth modified example. Also, FIG. 17 is a cross-sectional view taken along the cutting line B-B shown in FIG. 16.
  • the first amplifier transistor 121 and the first selection transistor 122 of the photoelectric conversion circuit 110d and the first source follower circuit 120d of the pixel 11d are arranged on the sensor chip 201.
  • the remaining circuit elements of the pixel 11d are arranged on the logic chip 202.
  • the first selection transistor 122 arranged on the sensor chip 201 is electrically connected to the bias cut transistor 123 arranged on the logic chip 202, for example, via a wiring that passes through the sensor chip 201 or a pad provided on the upper surface of the sensor chip 201.
  • a plurality of pixels 11d arranged on the sensor chip 201 are separated by an isolation film 220.
  • the isolation film 220 is, for example, a front full trench isolation (FFTI) type isolation film formed in a trench penetrating the semiconductor substrate 210.
  • a sidewall film made of, for example, silicon oxide is formed in the isolation film 220, and a filler made of polysilicon is embedded inside the sidewall film.
  • the filler in the FFTI is not limited to polysilicon.
  • an insulating film such as an oxide film may be formed in a single layer or multiple layers in the FFTI.
  • at least one type of conductive material such as a metal material or polysilicon may be formed in the FFTI.
  • an isolation film 220 is formed directly below the insulating film 115a in contact with the source region 121e, while an isolation film 200 is not formed directly below the insulating film 115b in contact with the drain region 121d. Furthermore, the thickness of the insulating film 115b from the surface of the semiconductor substrate 210 is thicker than that of the insulating film 115a.
  • FIG. 18 is a cross-sectional view of the transfer transistor 112 and the first selection transistor 122 in the layout shown in FIG. 16.
  • the isolation film 220 shown in FIG. 18 is also formed penetrating the semiconductor substrate 210.
  • a light-shielding film 221 that prevents light from leaking to adjacent pixels is formed on the back side (lower side of the drawing) of the isolation film 220.
  • the light-shielding film 221 is made of a metal material such as tungsten.
  • An OCL (on-chip lens) 222 that focuses incident light on the photodiode 111 is formed on the back side of the semiconductor substrate 210.
  • a trench 223 is opened on the surface side (upper side of the drawing) of the semiconductor substrate 210.
  • a transfer transistor 112 is provided in the trench 223.
  • An active region (Pwell) 224 is formed in the upper part of the semiconductor substrate 210.
  • An element isolation region 225 is formed in the active region 224.
  • the transfer transistor 112 may be of a recessed type in which the gate is formed in the trench 223, or may be of a planar type in which the gate is formed on the semiconductor substrate 210.
  • a P-type solid-phase diffusion layer 226 and an N-type solid-phase diffusion layer 227 are formed in this order from the isolation film 220 side toward the photodiode 111.
  • the photodiode 111 is composed of N-type regions. Photoelectric conversion takes place in some or all of these N-type regions.
  • a sidewall film 228 is formed on the inner wall of the separation film 220.
  • a filler material 229 is embedded inside the sidewall film 228.
  • silicon oxide or silicon nitride may be used for the sidewall film 228.
  • polysilicon or doped polysilicon may be used for the filler material 229. Note that the filler material 229 is not limited to these polysilicon materials.
  • the P-type solid-phase diffusion layer 226 is formed up to the rear surface silicon interface 240.
  • the N-type solid-phase diffusion layer 227 does not contact the rear surface silicon interface 240.
  • a gap is provided between the N-type solid-phase diffusion layer 227 and the rear surface silicon interface 240.
  • a P-type region 241 is provided between the photodiode 111 and the N-type solid-phase diffusion layer 227 and the back silicon interface 240, i.e., in the region of the semiconductor substrate 210 where the photodiode 111 and the like are not formed.
  • the pinning near the back silicon interface 240 is not weakened, so that it is possible to prevent the occurrence of a situation in which the generated charge flows into the photodiode 111 and the dark characteristics deteriorate.
  • the insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. As a result, even if the first amplifier transistor 121 is driven with a low current, the increase in thermal noise of the first source follower circuit 120c can be suppressed. Therefore, in this modified example, it is possible to reduce random noise while suppressing power consumption.
  • the thickness of the insulating film 115b not in contact with the isolation film 220 is made thicker than the thickness of the insulating film 115a in contact with the isolation film 220, so that the area of the low-concentration channel region 212a can be sufficiently secured.
  • the first amplifier transistor 121 may have a SiGe (silicon germanium) layer 215 formed directly under the channel region 212a, as described in the second embodiment. In this case, it is possible to further reduce random noise. Also, the first amplifier transistor 121 may be a Fin-type MOS transistor as described in the third embodiment.
  • FIG. 19 is a cross-sectional view of the fourth modified example in which a Fin-type MOS transistor is applied to the first amplifier transistor 121.
  • a Fin-type MOS transistor is applied to the first amplifier transistor 121, the thickness of the insulating film 115a in contact with the isolation film 220 is equal to the thickness of the insulating film 115b that is not in contact with the isolation film 220.
  • (Fifth Modification) 20 is a plan view showing an example of the layout of a sensor chip 201 according to the fifth modification.
  • the size of the sensor chip 201 according to this modification is the same as that of the fourth modification.
  • the circuit configurations of the pixels 11e arranged on the sensor chip 201 and the logic chip 202 are also the same as those of the fourth modification.
  • the multiple pixels 11e arranged on the sensor chip 201 are separated by an isolation layer 230.
  • the circuit elements of each pixel 11e are also separated by the isolation layer 230.
  • the isolation layer 230 is formed, for example, by injecting P-type impurities into the semiconductor substrate 210. Therefore, the isolation layer 230 is not provided under the insulating film 115 that contacts the drain region 121d and the source region 121e of the first amplifier transistor 121.
  • an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
  • FIG. 21 is a diagram showing a circuit configuration of a pixel according to a sixth modified example.
  • the pixel 11f shown in Fig. 21 has a photoelectric conversion circuit 110f, a first source follower circuit 120f, a signal holding selection circuit 130f, and a second source follower circuit 140f.
  • the photoelectric conversion circuit 110f has a photodiode 111, a transfer transistor 112, a first reset transistor 113, a discharge transistor 114, a switching transistor 116, and a capacitance element 117. That is, the photoelectric conversion circuit 110f according to this modification has a discharge transistor 114 in addition to the circuit elements of the photoelectric conversion circuit 110d according to the fourth modification.
  • the discharge transistor 114 is the same as in the first embodiment, so a description thereof will be omitted.
  • the circuit configurations of the first source follower circuit 120f, the signal holding selection circuit 130f, and the second source follower circuit 140f are also similar to those in the first embodiment, and therefore will not be described.
  • the second reset transistor 135 of the signal holding selection circuit 130f and the second source follower circuit 140f are shared by four pixels 11d, as in the fourth and fifth modifications.
  • FIG. 22 is a plan view showing an example of the layout of the sensor chip 201 according to the sixth modified example.
  • the size of the sensor chip 201 according to this modified example is larger than the size of the sensor chip 201 according to the fourth modified example.
  • the circuit configuration of the pixels 11e arranged on the sensor chip 201 and the logic chip 202 is also similar to that of the fourth modified example.
  • the emission transistor 114 is arranged on the sensor chip 201.
  • the multiple pixels 11f arranged on the sensor chip 201 are separated by an isolation film 220. Therefore, in the first amplifier transistor 121, the isolation film 220 is formed directly below the insulating film 115a in contact with the source region 121e, while the isolation film 200 is not formed directly below the insulating film 115b in contact with the drain region 121d. Furthermore, the thickness of the insulating film 115b from the surface of the semiconductor substrate 210 is thicker than that of the insulating film 115a.
  • the insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modified example as well, it is possible to reduce random noise while suppressing power consumption.
  • the thickness of the insulating film 115b not in contact with the isolation film 220 is made thicker than the thickness of the insulating film 115a in contact with the isolation film 220, so that the low concentration channel region 212a can be sufficiently secured.
  • the first amplifier transistor 121 may have a SiGe (silicon germanium) layer 215 formed directly under the channel region 212a as described in the second embodiment. In this case, it is possible to further reduce random noise.
  • the first amplifier transistor 121 may have a structure having the SiGe (silicon germanium) layer 215 described in the second embodiment, or may have a structure of a Fin-type MOS transistor described in the third embodiment.
  • (Seventh Modification) 23 is a plan view showing an example of the layout of the sensor chip 201 according to the seventh modification.
  • the size of the sensor chip 201 according to this modification is the same as that of the sixth modification.
  • the circuit configurations of the pixels 11f arranged on the sensor chip 201 and the logic chip 202 are also the same as those of the sixth modification.
  • the multiple pixels 11f arranged on the sensor chip 201 are separated by the separation layer 230, as in the fifth modification described above.
  • the circuit elements of each pixel 11f are also separated by the separation layer 230.
  • an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
  • the CMOS image sensor 4 includes a first chip 401, a second chip 402, and a third chip 403. The first chip 401, the second chip 402, and the third chip 403 are stacked.
  • the first chip 401 is provided with a first pixel array section 401a.
  • a plurality of sensor pixels 401b are arranged two-dimensionally in a matrix.
  • the photodiode 111, the transfer transistor 112, the FD, the first reset transistor 113, and the discharge transistor 114 of the photoelectric conversion circuit 110 are arranged.
  • the first amplifier transistor 121 and the first selection transistor 122 of the first source follower circuit 120 are also arranged.
  • the second chip 402 is provided with a second pixel array section 402a.
  • the bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120 are arranged in the second pixel array section 402a.
  • the signal retention selection circuit 130 and the second source follower circuit 140 are also arranged in the second pixel array section 402a.
  • the pixel drive lines 80 extend in the row direction
  • the vertical signal lines 90 extend in the column direction.
  • the third chip 403 is provided with a logic circuit 431.
  • the logic circuit 431 includes a vertical drive unit 20, a column processing unit 30, a horizontal drive unit 40, and a system control unit 50.
  • FIG. 25 is a vertical cross-sectional view of a portion of the CMOS image sensor 4 according to the fourth embodiment.
  • a first chip 401, a second chip 402, and a third chip 403 are stacked in this order.
  • a color filter 500 and a light receiving lens 600 are provided on the back side (light incident surface side) of the first chip 401.
  • one color filter 500 and one light receiving lens 600 are each provided for each sensor pixel 401b.
  • the CMOS image sensor 4 is a back-illuminated type.
  • the first chip 401 is constructed by laminating an insulating layer 46 on a first semiconductor substrate 410.
  • the first chip 401 has the insulating layer 46 as part of an interlayer insulating film 51.
  • the insulating layer 46 is provided in the gap between the first semiconductor substrate 410 and a second semiconductor substrate 420, which will be described later.
  • the first semiconductor substrate 410 is made of a silicon substrate.
  • the first semiconductor substrate 410 has a p-well layer 42, for example, in a part of the surface and in its vicinity, and has a photodiode 111 of a different conductivity type from the p-well layer 42 in the other region (region deeper than the p-well layer 42).
  • the p-well layer 42 is made of a p-type semiconductor region.
  • the photodiode 111 is made of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.
  • the first semiconductor substrate 410 has an FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.
  • the first chip 401 has a configuration in which a transfer transistor 112 and an FD are provided on the front side (the side opposite the light incident surface, the second chip 402 side) of the first semiconductor substrate 410.
  • the first chip 401 has an element isolation section 43 that isolates each sensor pixel 401b.
  • the element isolation portion 43 is formed extending in the normal direction of the first semiconductor substrate 410 (direction perpendicular to the surface of the first semiconductor substrate 410).
  • the element isolation portion 43 is provided between two adjacent sensor pixels 401b.
  • the element isolation portion 43 electrically isolates the adjacent sensor pixels 401b.
  • the element isolation portion 43 is made of, for example, silicon oxide.
  • the element isolation portion 43 penetrates, for example, the first semiconductor substrate 410.
  • the first chip 401 further has, for example, a p-well layer 44 that is a side surface of the element isolation section 43 and is in contact with the surface on the photodiode 111 side.
  • the p-well layer 44 is composed of a semiconductor region of a different conductivity type (specifically, p-type) from the photodiode 111.
  • the first chip 401 further has, for example, a fixed charge film 45 in contact with the back surface of the first semiconductor substrate 410.
  • the fixed charge film 45 is negatively charged in order to suppress the generation of dark current due to the interface state on the light-receiving surface side of the first semiconductor substrate 410.
  • the fixed charge film 45 is formed, for example, by an insulating film having a negative fixed charge. Examples of materials for such insulating films include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.
  • a hole accumulation layer is formed at the interface on the light-receiving surface side of the first semiconductor substrate 410 due to the electric field induced by the fixed charge film 45. This hole accumulation layer suppresses the generation of electrons from the interface.
  • the color filter 500 is provided on the back surface side of the first semiconductor substrate 410.
  • the color filter 500 is provided, for example, in contact with the fixed charge film 45 and is provided at a position facing the sensor pixel 401b via the fixed charge film 45.
  • the light receiving lens 600 is provided, for example, in contact with the color filter 500 and is provided in a position facing the sensor pixel 401b via the color filter 500 and the fixed charge film 45.
  • the second chip 402 is configured by laminating an insulating layer 52 on the second semiconductor substrate 420.
  • the second chip 402 has the insulating layer 52 as a part of the interlayer insulating film 51.
  • the insulating layer 52 is provided in the gap between the second semiconductor substrate 420 and the third semiconductor substrate 430.
  • the second semiconductor substrate 420 is configured of a silicon substrate.
  • the second chip 402 is configured such that a second pixel array section 402a is provided on the surface side (third chip 403 side) of the second semiconductor substrate 420.
  • the second chip 402 is bonded to the first chip 401 with the back surface of the second semiconductor substrate 420 facing the surface side of the first semiconductor substrate 410. In other words, the second chip 402 is bonded to the first chip 401 face-to-back.
  • the second chip 402 further has an insulating layer 53 penetrating the second semiconductor substrate 420 in the same layer as the second semiconductor substrate 420.
  • the second chip 402 has an insulating layer 53 as part of the interlayer insulating film 51.
  • the insulating layer 53 is provided to cover the side of the through wiring 54 described below.
  • the stack consisting of the first chip 401 and the second chip 402 has an interlayer insulating film 51 and through-wires 54 provided within the interlayer insulating film 51.
  • the stack has one through-wire 54 for each sensor pixel 401b.
  • the through-wires 54 extend in the normal direction of the second semiconductor substrate 420 and are provided penetrating a portion of the interlayer insulating film 51 that includes the insulating layer 53.
  • the first chip 401 and the second chip 402 are electrically connected to each other by the through-wires 54.
  • the through-wires 54 are electrically connected to the FD and the connection wires 55 described below.
  • the second chip 402 has, for example, a plurality of connection parts 59 in the insulating layer 52 that are electrically connected to the second pixel array part 402a and the second semiconductor substrate 420.
  • the second chip 402 further has, for example, a wiring layer 56 on the insulating layer 52.
  • the wiring layer 56 has, for example, an insulating layer 57, and a plurality of pixel drive lines 80 and a plurality of vertical signal lines 90 provided in the insulating layer 57.
  • the wiring layer 56 further has, for example, a plurality of connection wires 55 in the insulating layer 57, one for each of the four sensor pixels 401b.
  • connection wiring 55 electrically connects each of the through wirings 54 electrically connected to the FDs included in the four sensor pixels 401b that share the second pixel array unit 402a.
  • the total number of through wirings 54 is greater than the total number of sensor pixels 401b included in the first chip 401, and is twice the total number of sensor pixels 401b included in the first chip 401.
  • the total number of through wirings 54 is greater than the total number of sensor pixels 401b included in the first chip 401, and is three times the total number of sensor pixels 401b included in the first chip 401.
  • the wiring layer 56 further has, for example, a plurality of pad electrodes 58 in the insulating layer 57.
  • Each pad electrode 58 is formed of a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56.
  • Each pad electrode 58 is used for electrical connection between the second chip 402 and the third chip 403, and for bonding the second chip 402 and the third chip 403 together.
  • the multiple pad electrodes 58 are provided, for example, one for each pixel drive line 80 and vertical signal line 90.
  • the total number of pad electrodes 58 is less than the total number of sensor pixels 401b included in the first chip 401.
  • the third chip 403 is configured, for example, by laminating an interlayer insulating film 61 on a third semiconductor substrate 430.
  • the third semiconductor substrate 430 is configured as a silicon substrate.
  • the third chip 403 is configured such that a logic circuit 431 is provided on the surface side portion of the third semiconductor substrate 430.
  • the third chip 403 further has, for example, a wiring layer 62 on the interlayer insulating film 61.
  • the wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63.
  • the plurality of pad electrodes 64 are electrically connected to the logic circuit 431.
  • Each pad electrode 64 is formed of, for example, Cu (copper).
  • Each pad electrode 64 is exposed on the surface of the wiring layer 62.
  • Each pad electrode 64 is used for electrically connecting the second chip 402 and the third chip 403 and for bonding the second chip 402 and the third chip 403 together.
  • the number of pad electrodes 64 does not necessarily have to be multiple, and even one pad electrode 64 can be electrically connected to the logic circuit 431.
  • the second chip 402 and the third chip 403 are electrically connected to each other by bonding the pad electrodes 58, 64. That is, the gate of the transfer transistor 112 is electrically connected to the logic circuit 431 via the through-wire 54 and the pad electrodes 58, 64.
  • the third chip 403 is bonded to the second chip 402 with the surface of the third semiconductor substrate 430 facing the surface side of the second semiconductor substrate 420. That is, the third chip 403 is bonded to the second chip 402 face-to-face.
  • the first amplifier transistor 121 is provided in the second pixel array section 402a of the second chip 402.
  • an insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121, as in the first embodiment described above. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect.
  • the first amplifier transistor 121 is driven with a low current, the increase in thermal noise of the first source follower circuit 120c can be suppressed. Therefore, in this embodiment as well, it is possible to reduce random noise while suppressing power consumption.
  • the bonding form between the second chip 402 and the third chip is Cu-Cu bonding, which is bonding between pad electrodes
  • the bonding form between the first chip 401 and the second chip 402 is TSV (Through-Silicon Via) bonding, which is bonding between through-hole wiring.
  • TSV Through-Silicon Via
  • FIG. 26 is a block diagram showing an example of the configuration of an electronic device according to the fifth embodiment.
  • the electronic device 1000 shown in FIG. 26 is a video camera, a digital still camera, or the like.
  • the electronic device 1000 includes a lens group 1001, a solid-state CMOS image sensor 4002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008.
  • the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are interconnected via a bus line 1009.
  • the lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state CMOS image sensor 4002.
  • the solid-state CMOS image sensor 4002 is any one of the CMOS image sensors of each of the above-mentioned embodiments.
  • the solid-state CMOS image sensor 4002 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1003.
  • the DSP circuit 1003 performs a predetermined image processing on the pixel signals supplied from the solid-state CMOS image sensor 4002, and supplies the processed image signals to the frame memory 1004 on a frame-by-frame basis for temporary storage.
  • the display unit 1005 is, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on pixel signals on a frame-by-frame basis that are temporarily stored in the frame memory 1004.
  • a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on pixel signals on a frame-by-frame basis that are temporarily stored in the frame memory 1004.
  • the recording unit 1006 is composed of a DVD (Digital Versatile Disk), flash memory, etc., and reads out and records the pixel signals on a frame-by-frame basis that are temporarily stored in the frame memory 1004.
  • DVD Digital Versatile Disk
  • flash memory etc.
  • the operation unit 1007 issues operation commands for various functions of the electronic device 1000 under the operation of a user.
  • the power supply unit 1008 supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.
  • Electronic devices to which this technology can be applied include any device that uses a CMOS image sensor in its image capture section (photoelectric conversion section), such as the electronic device 1000, a portable terminal device with an imaging function, and a copying machine that uses a CMOS image sensor in its image reading section.
  • any one of the CMOS image sensors according to the above-mentioned embodiments is mounted as the solid-state CMOS image sensor 4002. Therefore, the solid-state CMOS image sensor 4002 has a low random noise function, which makes it possible to improve imaging performance.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 27 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 28 shows an example of the installation position of the imaging unit 12031.
  • the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 28 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering to avoid a collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology disclosed herein can be applied to, for example, the imaging unit 12031.
  • the imaging unit 12031 can be equipped with the above-mentioned CMOS image sensor.
  • the present technology can be configured as follows. (1) a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light; a source follower circuit including an amplifier transistor that amplifies the pixel signal; an insulating film is formed directly below each of the drain region and the source region of the amplifier transistor; (2) The photodiode according to (1), wherein the impurity concentration of the semiconductor well region between the drain region and the source region is a concentration that depletes the semiconductor well region to the same depth as the bottom ends of the drain region and the source region or to a position deeper than the bottom ends while the amplifier transistor is operating. (3) The light-receiving element according to (2), wherein the impurity concentration is 10 times or more lower than 4e17 (cm ⁇ 3 ).
  • the amplifier transistor is a Fin-type MOS transistor.
  • An electronic device including a light receiving element including a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light, and a source follower circuit including an amplifier transistor that amplifies the pixel signal, an insulating film is formed directly below each of the drain region and the source region of the amplifier transistor.
  • CMOS image sensor 110 photoelectric conversion circuit 115: insulating film 120: first source follower circuit 121: first amplifier transistor 121d: drain region 121e: source region 212: epitaxial growth layer 212a: channel region 214: polysilicon film 215: SiGe layer 1000: electronic device

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Abstract

[Problem] To provide a light receiving element in which random noise is reduced. [Solution] A light receiving element according to an aspect of the present disclosure comprises a photoelectric conversion circuit that outputs a pixel signal obtained by performing photoelectric conversion on input light, and a source follower circuit that includes an amplification transistor for amplifying the pixel signal. In the light receiving element, an insulating film is formed under each of a drain region and a source region of the amplification transistor.

Description

受光素子および電子機器Photodetector and electronic device
　本開示は、受光素子および電子機器に関する。 This disclosure relates to a light receiving element and an electronic device.
　ＣＭＯＳイメージセンサには、フォトダイオードで光電変換された画素信号を全画素同時にソースフォロワ回路に読み出すタイプがある。このタイプのＣＭＯＳイメージセンサのように全画素同時に画素信号を読み出すと消費電力が大きくなる。その一方で、消費電力を抑制するために従来よりも低い電流領域でソースフォロワ回路のアンプトランジスタを駆動しようとすると、ランダムノイズ（ＲＮ）が悪化することが想定される。このランダムノイズの悪化には、ソースフォロワ回路の熱雑音の影響が大きい。 CMOS image sensors include a type in which pixel signals photoelectrically converted by photodiodes are read out to a source follower circuit for all pixels simultaneously. Reading out pixel signals from all pixels simultaneously, as in this type of CMOS image sensor, results in high power consumption. On the other hand, if you try to drive the amplifier transistor of the source follower circuit in a lower current range than before in order to reduce power consumption, it is expected that random noise (RN) will worsen. Thermal noise in the source follower circuit has a large impact on this deterioration of random noise.
特開２０１６－４２５５７号公報JP 2016-42557 A
　そこで、本開示は、ランダムノイズを低減することが可能な受光素子および電子機器を提供する。 The present disclosure therefore provides a light receiving element and electronic device capable of reducing random noise.
　本開示の一態様に係る受光素子は、入射光を光電変換した画素信号を出力する光電変換回路と、画素信号を増幅するアンプトランジスタを含むソースフォロワ回路と、を備える。この受光素子では、アンプトランジスタのドレイン領域およびソース領域の各々の直下に、絶縁膜が形成されている。 The light receiving element according to one embodiment of the present disclosure includes a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light, and a source follower circuit including an amplifier transistor that amplifies the pixel signal. In this light receiving element, an insulating film is formed directly below each of the drain region and source region of the amplifier transistor.
　また、前記ドレイン領域と前記ソース領域との間における半導体ウェル領域の不純物濃度が、前記アンプトランジスタの駆動中に前記ドレイン領域および前記ソース領域の各々の下端部と同じ深さか、または前記下端部よりも深い位置まで空乏化する濃度であってもよい。 In addition, the impurity concentration of the semiconductor well region between the drain region and the source region may be a concentration that is depleted to the same depth as the bottom ends of the drain region and the source region, or to a position deeper than the bottom ends while the amplifier transistor is operating.
　また、前記不純物濃度が、４ｅ１７（ｃｍ－３）よりも１０倍以上低くてもよい。 The impurity concentration may be 10 times or more lower than 4e17 (cm −3 ).
　また、前記半導体ウェル領域は、シリコンのエピタキシャル成長層であってもよい。 The semiconductor well region may also be an epitaxially grown layer of silicon.
　また、前記半導体ウェル領域は、前記アンプトランジスタの駆動中に前記ドレイン領域と前記ソース領域との間に形成されるチャネル領域の直下にシリコンゲルマニウム層を有していてもよい。 The semiconductor well region may also have a silicon germanium layer directly below a channel region formed between the drain region and the source region while the amplifier transistor is in operation.
　また、前記絶縁膜の厚さが、前記アンプトランジスタの駆動中に生成される空乏層より少なくとも深くてもよい。 The thickness of the insulating film may also be at least deeper than the depletion layer that is generated while the amplifier transistor is in operation.
　また、前記絶縁膜の厚さが、前記アンプトランジスタを形成する半導体基板の厚さに対して１０％以内であってもよい。 The thickness of the insulating film may be within 10% of the thickness of the semiconductor substrate on which the amplifier transistor is formed.
　また、前記絶縁膜が、前記アンプトランジスタを囲んでいてもよい。 The insulating film may also surround the amplifier transistor.
　また、前記ドレイン領域および前記ソース領域の各々一部が、ポリシリコン膜であってもよい。 Furthermore, a portion of each of the drain region and the source region may be a polysilicon film.
　また、前記アンプトランジスタの駆動中に前記ドレイン領域と前記ソース領域との間に形成されるチャネル領域の直下にも前記絶縁膜が形成されていてもよい。 The insulating film may also be formed directly below a channel region that is formed between the drain region and the source region while the amplifier transistor is in operation.
　また、前記チャネル領域が、Ｓｉ（１１０）面に形成されていてもよい。 The channel region may also be formed on a Si(110) surface.
　また、前記アンプトランジスタが、Ｆｉｎ型ＭＯＳトランジスタであってもよい。 The amplifier transistor may also be a Fin-type MOS transistor.
　また、前記アンプトランジスタが、前記光電変換回路と同じ半導体基板に配置されていてもよい。 The amplifier transistor may also be disposed on the same semiconductor substrate as the photoelectric conversion circuit.
　また、前記アンプトランジスタが、前記光電変換回路と異なる半導体基板に配置されていてもよい。 The amplifier transistor may also be disposed on a different semiconductor substrate from the photoelectric conversion circuit.
　本開示の一態様に係る電子機器は、入射光を光電変換した画素信号を出力する光電変換回路と、前記画素信号を増幅するアンプトランジスタを含むソースフォロワ回路と、を含む受光素子を備える。この電子機器では、前記アンプトランジスタのドレイン領域およびソース領域の各々の直下に、絶縁膜が形成されている。 An electronic device according to one aspect of the present disclosure includes a light receiving element including a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light, and a source follower circuit including an amplifier transistor that amplifies the pixel signal. In this electronic device, an insulating film is formed directly below each of the drain region and source region of the amplifier transistor.
第１実施形態に係るＣＭＯＳイメージセンサの構成例を示すブロック図である。1 is a block diagram showing an example of the configuration of a CMOS image sensor according to a first embodiment; 画素アレイ部の画素の回路構成を示す図である。FIG. 2 is a diagram showing a circuit configuration of a pixel in a pixel array portion. 第１実施形態に係るＣＭＯＳイメージセンサの積層構造の一例を示す図である。1 is a diagram showing an example of a stacked structure of a CMOS image sensor according to a first embodiment; 上側画素アレイ部のレイアウトの一例を示す平面図である。11 is a plan view showing an example of the layout of an upper pixel array unit. FIG. 図４に示す切断線Ａ－Ａに沿った断面図である。5 is a cross-sectional view taken along the line AA shown in FIG. 4. 半導体基板上に酸化シリコン膜を形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a step of forming a silicon oxide film on a semiconductor substrate. 半導体基板内に絶縁膜を形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a step of forming an insulating film in a semiconductor substrate. 絶縁膜の一部をエッチングする工程を示す断面図である。11A to 11C are cross-sectional views showing a step of etching a part of an insulating film. 選択的エピタキシャル成長工程を示す断面図である。FIG. 2 is a cross-sectional view showing a selective epitaxial growth process. 非選択エピタキシャル成長工程を示す断面図である。FIG. 2 is a cross-sectional view showing a non-selective epitaxial growth step. 平坦化処理工程を示す断面図である。FIG. 11 is a cross-sectional view showing a planarization process. ゲート電極、ドレイン領域、およびソース領域を形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a step of forming a gate electrode, a drain region, and a source region. 半導体基板上に酸化シリコン膜を形成する工程の別例を示す断面図である。10A to 10C are cross-sectional views showing another example of a process for forming a silicon oxide film on a semiconductor substrate. 半導体基板内に絶縁膜を形成する工程の別例を示す断面図である。10A to 10C are cross-sectional views showing another example of a process for forming an insulating film in a semiconductor substrate. 絶縁膜を分断する工程を示す断面図である。11A to 11C are cross-sectional views showing a step of dividing an insulating film. 絶縁膜の一部をエッチングする工程の別例を示す断面図である。10A to 10C are cross-sectional views showing another example of a step of etching a part of an insulating film. 選択的エピタキシャル成長工程を示す断面図である。FIG. 2 is a cross-sectional view showing a selective epitaxial growth process. 非選択エピタキシャル成長工程を示す断面図である。FIG. 2 is a cross-sectional view showing a non-selective epitaxial growth step. 平坦化処理工程を示す断面図である。FIG. 11 is a cross-sectional view showing a planarization process. ゲート電極、ドレイン領域、およびソース領域を形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a step of forming a gate electrode, a drain region, and a source region. 第２実施形態に係る第１アンプトランジスタの構造を示す断面図である。11 is a cross-sectional view showing a structure of a first amplifier transistor according to a second embodiment. 一般的なＦｉｎ型ＭＯＳトランジスタの構造を示す斜視図である。FIG. 1 is a perspective view showing a structure of a general Fin-type MOS transistor. 第３実施形態に係る第１アンプトランジスタの構造を示す断面図である。FIG. 11 is a cross-sectional view showing a structure of a first amplifier transistor according to a third embodiment. 半導体基板を形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a process for forming a semiconductor substrate. 半導体基板内にストッパー膜を形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a step of forming a stopper film in a semiconductor substrate. ＥＳＳ用のトレンチを形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a process of forming a trench for an ESS. ＥＳＳを形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a process of forming an ESS. トレンチおよびＥＳＳに絶縁膜を形成する工程を示す断面図である。11A to 11C are cross-sectional views showing a step of forming an insulating film in the trench and the ESS. 平坦化処理工程を示す断面図である。FIG. 11 is a cross-sectional view showing a planarization process. ゲート電極、ドレイン領域、およびソース領域を形成する工程を示す断面図である。1A to 1C are cross-sectional views showing a step of forming a gate electrode, a drain region, and a source region. 第１変形例に係る画素の回路構成を示す図である。FIG. 13 is a diagram showing a circuit configuration of a pixel according to a first modified example. 第２変形例に係る画素の回路構成を示す図である。FIG. 13 is a diagram showing a circuit configuration of a pixel according to a second modified example. 第３変形例に係る画素の回路構成を示す図である。FIG. 13 is a diagram showing a circuit configuration of a pixel according to a third modified example. は、第４変形例に係る画素の回路構成を示す図である。FIG. 13 is a diagram showing a circuit configuration of a pixel according to a fourth modified example. 第４変形例に係るセンサチップのレイアウトの一例を示す平面図である。FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a fourth modified example. 図１６に示す切断線Ｂ－Ｂに沿った断面図である。17 is a cross-sectional view taken along the line BB shown in FIG. 16. 図１６に示すレイアウトにおいて、転送トランジスタおよび第１選択トランジスタ周辺の断面図である。17 is a cross-sectional view of the periphery of a transfer transistor and a first selection transistor in the layout shown in FIG. 16. 第４変形例に係る第１アンプトランジスタにＦｉｎ型ＭＯＳトランジスタを適用した断面図である。13 is a cross-sectional view in which a Fin-type MOS transistor is applied to a first amplifier transistor according to a fourth modified example. 第５変形例に係るセンサチップのレイアウトの一例を示す平面図である。FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a fifth modified example. 第６変形例に係る画素の回路構成を示す図である。FIG. 13 is a diagram showing a circuit configuration of a pixel according to a sixth modified example. 第６変形例に係るセンサチップのレイアウトの一例を示す平面図である。FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a sixth modified example. 第７変形例に係るセンサチップのレイアウトの一例を示す平面図である。FIG. 13 is a plan view showing an example of a layout of a sensor chip according to a seventh modified example. 第４実施形態に係るＣＭＯＳイメージセンサの構成を示す図である。FIG. 13 is a diagram showing a configuration of a CMOS image sensor according to a fourth embodiment. 第４実施形態に係るＣＭＯＳイメージセンサの一部を垂直方向に切断した断面図である。FIG. 11 is a cross-sectional view of a part of a CMOS image sensor according to a fourth embodiment, cut in the vertical direction. 第５実施形態に係る電子機器の構成例を示すブロック図である。FIG. 13 is a block diagram showing an example of the configuration of an electronic device according to a fifth embodiment. 車両制御システムの概略的な構成の一例を示すブロック図である。1 is a block diagram showing an example of a schematic configuration of a vehicle control system; 車外情報検出部及び撮像部の設置位置の一例を示す説明図である。4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG.
　以下に添付図面を参照しながら、本開示の好適な実施形態について詳細に説明する。下記の実施形態では、本開示に係る受光素子を、被写体の画像を撮像して各画素の画素信号を出力するＣＭＯＳイメージセンサに適用した例について説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。 Below, a preferred embodiment of the present disclosure will be described in detail with reference to the attached drawings. In the following embodiment, an example will be described in which a light receiving element according to the present disclosure is applied to a CMOS image sensor that captures an image of a subject and outputs a pixel signal for each pixel. Note that in this specification and drawings, components that have substantially the same functional configuration will be assigned the same reference numerals to avoid redundant description.
　（第１実施形態）
　図１は、第１実施形態に係るＣＭＯＳイメージセンサの構成例を示すブロック図である。図１に示すＣＭＯＳイメージセンサ１は、画素アレイ部１０、垂直駆動部２０、カラム処理部３０、水平駆動部４０、システム制御部５０、信号処理部６０、およびメモリ部７０を備える。 First Embodiment
Fig. 1 is a block diagram showing an example of the configuration of a CMOS image sensor according to the first embodiment. The CMOS image sensor 1 shown in Fig. 1 includes a pixel array section 10, a vertical drive section 20, a column processing section 30, a horizontal drive section 40, a system control section 50, a signal processing section 60, and a memory section 70.
　画素アレイ部１０には、複数の画素が行列状に２次元配置されている。各画素は、入射光の光量に応じた電荷量の電荷を発生して内部に蓄積する光電変換素子を有する。画素の回路構成については、後述する。また、画素アレイ部１０には、画素行ごとに画素駆動線８０が接続され、画素列ごとに垂直信号線９０が接続されている。 The pixel array section 10 has a plurality of pixels arranged two-dimensionally in a matrix. Each pixel has a photoelectric conversion element that generates and internally accumulates an electric charge whose amount corresponds to the amount of incident light. The circuit configuration of the pixel will be described later. In addition, pixel array section 10 has pixel drive lines 80 connected to each pixel row, and vertical signal lines 90 connected to each pixel column.
　垂直駆動部２０は、シフトレジスタやアドレスデコーダなどによって構成され、画素アレイ部１０の各画素を行単位等で駆動する。垂直駆動部２０の各画素行に対応した出力端には、画素駆動線８０の一端が接続されている。 The vertical drive unit 20 is composed of a shift register, an address decoder, etc., and drives each pixel of the pixel array unit 10 on a row basis, etc. One end of a pixel drive line 80 is connected to the output terminal of the vertical drive unit 20 corresponding to each pixel row.
　カラム処理部３０は、画素アレイ部１０の画素列ごとに信号処理回路を有する。カラム処理部３０の各信号処理回路は、選択行の各画素から垂直信号線９０を通じて出力される画素信号に対して、ＣＤＳ（Correlated Double Sampling）処理等のノイズ除去処理、Ａ／Ｄ（Analog/Digital）変換処理等の信号処理を行う。カラム処理部３０は、信号処理後の画素信号を一時的に保持する。 The column processing unit 30 has a signal processing circuit for each pixel column of the pixel array unit 10. Each signal processing circuit of the column processing unit 30 performs signal processing such as noise removal processing such as CDS (Correlated Double Sampling) processing and A/D (Analog/Digital) conversion processing on the pixel signals output from each pixel of the selected row through the vertical signal line 90. The column processing unit 30 temporarily holds the pixel signals after signal processing.
　水平駆動部４０は、シフトレジスタやアドレスデコーダなどによって構成され、カラム処理部３０の信号処理回路を順番に選択する。この水平駆動部４０による選択走査により、カラム処理部３０の各信号処理回路で信号処理された画素信号が順番に信号処理部６０に出力される。 The horizontal drive unit 40 is composed of a shift register, an address decoder, etc., and sequentially selects the signal processing circuits of the column processing unit 30. Through selective scanning by this horizontal drive unit 40, pixel signals that have been signal-processed by each signal processing circuit of the column processing unit 30 are output in sequence to the signal processing unit 60.
　システム制御部５０は、各種のタイミング信号を生成するタイミングジェネレータ等によって構成され、タイミングジェネレータで生成された各種のタイミング信号を基に垂直駆動部２０、カラム処理部３０、および水平駆動部４０を制御する。 The system control unit 50 is composed of a timing generator that generates various timing signals, and controls the vertical drive unit 20, column processing unit 30, and horizontal drive unit 40 based on the various timing signals generated by the timing generator.
　信号処理部６０は、少なくとも加算処理機能を有する。信号処理部６０は、カラム処理部３０から出力される画素信号に対して加算処理等の種々の信号処理を行う。このとき、信号処理部６０は、必要に応じて、信号処理の途中結果などをメモリ部７０に格納し、必要なタイミングで参照する。信号処理部６０は、信号処理後の画素信号を出力する。 The signal processing unit 60 has at least an addition processing function. The signal processing unit 60 performs various signal processing such as addition processing on the pixel signals output from the column processing unit 30. At this time, the signal processing unit 60 stores intermediate results of the signal processing in the memory unit 70 as necessary, and refers to them at the required timing. The signal processing unit 60 outputs the pixel signals after signal processing.
　メモリ部７０は、ＤＲＡＭ（Dynamic Random Access Memory)やSRAM( Static Random Access Memory）などにより構成される。 The memory unit 70 is composed of DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), etc.
　図２は、画素アレイ部１０の画素の回路構成を示す図である。図２に示す画素１１は、光電変換回路１１０と、第１ソースフォロワ回路１２０と、信号保持選択回路１３０と、第２ソースフォロワ回路１４０と、を有する。以下、各回路について説明する。 FIG. 2 is a diagram showing the circuit configuration of a pixel in the pixel array section 10. The pixel 11 shown in FIG. 2 has a photoelectric conversion circuit 110, a first source follower circuit 120, a signal retention selection circuit 130, and a second source follower circuit 140. Each circuit will be described below.
　光電変換回路１１０は、フォトダイオード１１１、転送トランジスタ１１２、第１リセットトランジスタ１１３、および排出トランジスタ１１４を有する。転送トランジスタ１１２、第１リセットトランジスタ１１３、および排出トランジスタ１１４は、例えばＮチャネル型のＭＯＳトランジスタで構成されている。 The photoelectric conversion circuit 110 has a photodiode 111, a transfer transistor 112, a first reset transistor 113, and a discharge transistor 114. The transfer transistor 112, the first reset transistor 113, and the discharge transistor 114 are configured, for example, with an N-channel MOS transistor.
　フォトダイオード１１１は、入射光を光電変換して電荷を生成する。フォトダイオード１１１のアノードは、基準電位を有するグランドに接地されている。フォトダイオード１１１のカソードは、転送トランジスタ１１２および排出トランジスタ１１４に接続されている。 The photodiode 111 converts incident light into electricity to generate an electric charge. The anode of the photodiode 111 is connected to a ground having a reference potential. The cathode of the photodiode 111 is connected to the transfer transistor 112 and the discharge transistor 114.
　転送トランジスタ１１２は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された転送信号ＴＲＧに従って、フォトダイオード１１１からＦＤ（Floating Diffusion）へ電荷を転送する。ＦＤは、電荷を蓄積し、電荷量に応じた電圧で示される画素信号を生成する。転送トランジスタ１１２のドレインは、フォトダイオード１１１のカソードに接続され、ソースは、ＦＤに接続されている。 The transfer transistor 112 transfers charge from the photodiode 111 to the FD (Floating Diffusion) in accordance with a transfer signal TRG input to its gate from the vertical drive unit 20 through the pixel drive line 80. The FD accumulates the charge and generates a pixel signal represented by a voltage according to the amount of charge. The drain of the transfer transistor 112 is connected to the cathode of the photodiode 111, and the source is connected to the FD.
　第１リセットトランジスタ１１３は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第１リセット信号ＲＳＴに従って、ＦＤから電荷を引き抜いて初期化する。第１リセットトランジスタ１１３のドレインは、電源電圧ＶＤＤの電位を有する電源線に接続され、ソースは、ＦＤに接続されている。 The first reset transistor 113 extracts charge from the FD to perform initialization in accordance with a first reset signal RST input to the gate from the vertical drive unit 20 through the pixel drive line 80. The drain of the first reset transistor 113 is connected to a power supply line having a potential of the power supply voltage VDD, and the source is connected to the FD.
　排出トランジスタ１１４は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された排出信号ＯＦＧに従って、フォトダイオード１１１に蓄積された電荷を排出して初期化する。排出トランジスタ１１４のドレインは、フォトダイオード１１１のカソードおよび転送トランジスタ１１２のドレインに接続されている。排出トランジスタ１１４のソースは、上記電源線に接続されている。 The discharge transistor 114 discharges and initializes the charge accumulated in the photodiode 111 in accordance with a discharge signal OFG input to the gate from the vertical drive unit 20 through the pixel drive line 80. The drain of the discharge transistor 114 is connected to the cathode of the photodiode 111 and the drain of the transfer transistor 112. The source of the discharge transistor 114 is connected to the power supply line.
　第１ソースフォロワ回路１２０は、第１アンプトランジスタ１２１、第１選択トランジスタ１２２、バイアスカットトランジスタ１２３、および負荷トランジスタ１２４を有する。各トランジスタは、電源電圧ＶＤＤの電位を有する電源線とグランドとの間で直列に接続され、例えばＮチャネル型のＭＯＳトランジスタで構成されている。 The first source follower circuit 120 has a first amplifier transistor 121, a first selection transistor 122, a bias cut transistor 123, and a load transistor 124. Each transistor is connected in series between a power supply line having a potential of the power supply voltage VDD and ground, and is composed of, for example, an N-channel MOS transistor.
　第１アンプトランジスタ１２１は、ＦＤで生成された画素信号の電圧レベルを電圧Ｖ１に増幅して信号保持選択回路１３０に出力する。第１アンプトランジスタ１２１のゲートは、ＦＤに接続されている。ドレインは、上記電源線に接続されている。ソースは、第１選択トランジスタ１２２のドレインに接続されている。 The first amplifier transistor 121 amplifies the voltage level of the pixel signal generated by the FD to a voltage V1 and outputs it to the signal holding and selection circuit 130. The gate of the first amplifier transistor 121 is connected to the FD. The drain is connected to the power supply line. The source is connected to the drain of the first selection transistor 122.
　第１選択トランジスタ１２２は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された切替信号ＳＷに従って、第１アンプトランジスタ１２１で増幅された画素信号を信号保持選択回路１３０に伝送するか否かを切り替える。第１選択トランジスタ１２２のドレインは、第１アンプトランジスタ１２１のソースに接続され、ソースは、信号保持選択回路１３０およびバイアスカットトランジスタ１２３のドレインに接続されている。 The first selection transistor 122 switches whether or not to transmit the pixel signal amplified by the first amplifier transistor 121 to the signal holding selection circuit 130 according to a switching signal SW input to the gate from the vertical drive unit 20 through the pixel drive line 80. The drain of the first selection transistor 122 is connected to the source of the first amplifier transistor 121, and the source is connected to the drain of the signal holding selection circuit 130 and the bias cut transistor 123.
　バイアスカットトランジスタ１２３は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力されたバイアスカット信号ＰＣに従って、負荷トランジスタ１２４からの電流供給を行うか否かを切り替える。バイアスカットトランジスタ１２３のソースは、負荷トランジスタ１２４のドレインに接続されている。 The bias cut transistor 123 switches whether or not to supply current from the load transistor 124 according to a bias cut signal PC input to the gate from the vertical drive unit 20 through the pixel drive line 80. The source of the bias cut transistor 123 is connected to the drain of the load transistor 124.
　負荷トランジスタ１２４は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力されたバイアス信号ＶＢに従って、所定の電流を第１ソースフォロワ回路１２０内に供給する。負荷トランジスタ１２４のソースはグランドに接地されている。 The load transistor 124 supplies a predetermined current into the first source follower circuit 120 according to the bias signal VB input to the gate from the vertical drive unit 20 through the pixel drive line 80. The source of the load transistor 124 is connected to ground.
　信号保持選択回路１３０は、第１容量素子１３１、第２容量素子１３２、第１サンプリングトランジスタ１３３、第２サンプリングトランジスタ１３４、および第２リセットトランジスタ１３５を有する。各トランジスタは、例えばＮチャネル型のＭＯＳトランジスタで構成されている。 The signal retention selection circuit 130 has a first capacitive element 131, a second capacitive element 132, a first sampling transistor 133, a second sampling transistor 134, and a second reset transistor 135. Each transistor is, for example, an N-channel MOS transistor.
　第１容量素子１３１および第２容量素子１３２のそれぞれの一端は、第１ソースフォロワ回路１２０の出力端子（第１選択トランジスタ１２２のソース）に共通に接続されている第１容量素子１３１の他端は、第１サンプリングトランジスタ１３３のドレインに接続されている。第２容量素子１３２の他端は、第２サンプリングトランジスタ１３４のドレインに接続されている。 One end of each of the first capacitive element 131 and the second capacitive element 132 is commonly connected to the output terminal of the first source follower circuit 120 (the source of the first selection transistor 122). The other end of the first capacitive element 131 is connected to the drain of the first sampling transistor 133. The other end of the second capacitive element 132 is connected to the drain of the second sampling transistor 134.
　第１サンプリングトランジスタ１３３は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第１サンプリング信号ＳＲに従って、第１容量素子１３１に保持された画素信号を出力ノード１３６へ出力するか否かを切り替える。第１サンプリングトランジスタ１３３のソースは、出力ノード１３６に接続されている。 The first sampling transistor 133 switches whether or not to output the pixel signal held in the first capacitance element 131 to the output node 136 according to the first sampling signal SR input to the gate from the vertical drive unit 20 through the pixel drive line 80. The source of the first sampling transistor 133 is connected to the output node 136.
　第２サンプリングトランジスタ１３４は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第２サンプリング信号ＳＤに従って、第２容量素子１３２に保持された画素信号を出力ノード１３６へ出力するか否かを切り替える。第２サンプリングトランジスタ１３４のソースも、第１サンプリングトランジスタ１３３のソースと共通に出力ノード１３６に接続されている。 The second sampling transistor 134 switches whether or not to output the pixel signal held in the second capacitance element 132 to the output node 136 according to the second sampling signal SD input to the gate from the vertical drive unit 20 through the pixel drive line 80. The source of the second sampling transistor 134 is also connected to the output node 136 in common with the source of the first sampling transistor 133.
　第２リセットトランジスタ１３５は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第２リセット信号ＲＢに従って、出力ノード１３６の電圧Ｖ２を所定の電圧ＶＲＥＧに初期化する。電圧ＶＲＥＧは、電源電圧ＶＤＤよりも低い電位に設定されている。第２リセットトランジスタ１３５のドレインは、電圧ＶＲＥＧの電位を有する電圧配線に接続され、ソースは出力ノード１３６に接続されている。 The second reset transistor 135 initializes the voltage V2 of the output node 136 to a predetermined voltage VREG according to a second reset signal RB input to the gate from the vertical drive unit 20 through the pixel drive line 80. The voltage VREG is set to a potential lower than the power supply voltage VDD. The drain of the second reset transistor 135 is connected to a voltage wiring having a potential of the voltage VREG, and the source is connected to the output node 136.
　第２ソースフォロワ回路１４０は、信号保持選択回路１３０から信号を選択的に読み出して増幅する回路であり、第２アンプトランジスタ１４１と、第２選択トランジスタ１４２と、電流源１４３と、を有する。互いに直列に接続されている第２アンプトランジスタ１４１および第２選択トランジスタ１４２は、例えばＮチャネル型のＭＯＳトランジスタで構成されている。 The second source follower circuit 140 is a circuit that selectively reads out and amplifies a signal from the signal holding and selection circuit 130, and has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. The second amplifier transistor 141 and the second selection transistor 142 are connected in series with each other and are composed of, for example, N-channel MOS transistors.
　第２アンプトランジスタ１４１のゲートは信号保持選択回路１３０の出力ノード１３６に接続されている。また、ドレインは電源電圧ＶＤＤの電位を有する電源線に接続されている。さらに、ソースは、第２選択トランジスタ１４２のドレインに接続されている。 The gate of the second amplifier transistor 141 is connected to the output node 136 of the signal holding selection circuit 130. In addition, the drain is connected to a power supply line having a potential of the power supply voltage VDD. Furthermore, the source is connected to the drain of the second selection transistor 142.
　第２選択トランジスタ１４２は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第２選択信号ＳＥＬに従って、第２アンプトランジスタ１４１で増幅された画素信号を信号線ＶＳＬに出力するか否かを切り替える。第２選択トランジスタ１４２のソースは、信号線ＶＳｌおよび電流源１４３に接続されている。 The second selection transistor 142 switches whether or not to output the pixel signal amplified by the second amplifier transistor 141 to the signal line VSL according to the second selection signal SEL input to the gate from the vertical drive unit 20 through the pixel drive line 80. The source of the second selection transistor 142 is connected to the signal line VSL and the current source 143.
　電流源１４３は、第２選択トランジスタ１４２に直列に接続されている。電流源１４３は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された制御信号に従って、第２アンプトランジスタ１４１および第２選択トランジスタ１４２に一定の電流を供給する。 The current source 143 is connected in series to the second selection transistor 142. The current source 143 supplies a constant current to the second amplifier transistor 141 and the second selection transistor 142 in accordance with a control signal input to the gate from the vertical drive unit 20 through the pixel drive line 80.
　上記のように構成されたＣＭＯＳイメージセンサ１では、垂直駆動部２０は、露光開始時に全画素１１へハイレベルの第１リセット信号ＲＳＴおよび転送信号ＴＲＧを供給する。これにより、フォトダイオード１１１が初期化される。 In the CMOS image sensor 1 configured as described above, the vertical drive unit 20 supplies a high-level first reset signal RST and a transfer signal TRG to all pixels 11 at the start of exposure. This initializes the photodiodes 111.
　続いて、垂直駆動部２０は、露光終了の直前に、全画素１１について第２リセット信号ＲＢおよび第１サンプリング信号ＳＲをハイレベルにしつつ、パルス期間に亘ってハイレベルの第１リセット信号ＲＳＴを供給する。これにより、ＦＤが初期化され、そのときのＦＤの電圧レベルに応じた画素信号が第１容量素子１３１に保持される。 Next, just before the end of exposure, the vertical drive unit 20 sets the second reset signal RB and the first sampling signal SR to high level for all pixels 11, and supplies a high-level first reset signal RST for the pulse period. This initializes the FD, and a pixel signal corresponding to the voltage level of the FD at that time is held in the first capacitance element 131.
　その後、垂直駆動部２０は、露光終了時に、全画素１１について第２リセット信号ＲＢおよび第２サンプリング信号ＳＤをハイレベルにしつつ、パルス期間に亘ってハイレベルの転送信号ＴＲＧを供給する。これにより、露光量に応じた信号電荷がＦＤへ転送され、そのときのＦＤのレベルに応じた画素信号が第２容量素子１３２に保持される。 After that, when the exposure is completed, the vertical drive unit 20 sets the second reset signal RB and the second sampling signal SD to high level for all pixels 11, and supplies a high-level transfer signal TRG for the pulse period. As a result, a signal charge according to the amount of exposure is transferred to the FD, and a pixel signal according to the level of the FD at that time is held in the second capacitance element 132.
　このように全画素１１について同時に露光を開始し、終了する露光制御は、グローバルシャッター方式と呼ばれる。この露光制御により、全画素１１の光電変換回路１１０は、リセットレベルおよびデータレベルの画素信号を順に生成する。リセットレベルの画素信号は、第１容量素子１３１に保持され、データレベルの画素信号は、第２容量素子１３２に保持される。 This type of exposure control, in which exposure starts and ends simultaneously for all pixels 11, is called a global shutter method. With this exposure control, the photoelectric conversion circuits 110 of all pixels 11 generate pixel signals of the reset level and data level in sequence. The pixel signal of the reset level is held in the first capacitance element 131, and the pixel signal of the data level is held in the second capacitance element 132.
　露光終了後に垂直駆動部２０は、行を順に選択して、その行のリセットレベルおよびデータレベルの画素信号を順に出力させる。リセットレベルの画素信号を出力させる際に、垂直駆動部２０は、選択した行の第１リセット信号ＲＳＴおよび第２選択信号ＳＥＬをハイレベルにしつつ、ハイレベルの第１サンプリング信号ＳＲを所定期間に亘って供給する。これにより、第１容量素子１３１が出力ノード１３６に接続され、リセットレベルが読み出される。 After exposure is complete, the vertical drive unit 20 selects rows in sequence and outputs pixel signals of the reset level and data level for that row in sequence. When outputting a pixel signal of the reset level, the vertical drive unit 20 sets the first reset signal RST and second selection signal SEL of the selected row to a high level, while supplying a high-level first sampling signal SR for a predetermined period of time. This connects the first capacitance element 131 to the output node 136, and the reset level is read out.
　リセットレベルの読出し後に垂直駆動部２０は、選択した行の第１リセット信号ＲＳＴおよび第２選択信号ＳＥＬをハイレベルにしたままで、ハイレベルの第２リセット信号ＲＢをパルス期間に亘って供給する。これにより、出力ノード１３６の電圧レベルが初期化される。このとき、第１サンプリングトランジスタ１３３および第２サンプリングトランジスタ１３４は両方ともオフ状態であるため、第１容量素子１３１および第２容量素子１３２は、出力ノード１３６から切り離される。 After reading out the reset level, the vertical drive unit 20 supplies a high-level second reset signal RB for the pulse period while keeping the first reset signal RST and second selection signal SEL of the selected row at a high level. This initializes the voltage level of the output node 136. At this time, the first sampling transistor 133 and the second sampling transistor 134 are both in the off state, so the first capacitance element 131 and the second capacitance element 132 are disconnected from the output node 136.
　出力ノード１３６の初期化後に、垂直駆動部２０は、選択した行の第１リセット信号ＲＳＴおよび第２選択信号ＳＥＬをハイレベルにしたままで、ハイレベルの第２サンプリング信号ＳＤを所定期間に亘って供給する。これにより、第２容量素子１３２が出力ノード１３６に接続され、データレベルの画素信号が読み出される。 After initializing the output node 136, the vertical drive unit 20 supplies a high-level second sampling signal SD for a predetermined period of time while keeping the first reset signal RST and the second selection signal SEL of the selected row at a high level. This connects the second capacitance element 132 to the output node 136, and a pixel signal at a data level is read out.
　図３は、第１実施形態に係るＣＭＯＳイメージセンサ１の積層構造の一例を示す図である。本実施形態に係るＣＭＯＳイメージセンサ１は、センサチップ２０１（第１チップ）と、センサチップ２０１の下側に積層されるロジックチップ２０２（第２チップ）と、を有する。センサチップ２０１およびロジックチップ２０２は、例えば、各チップに形成されたＣｕパッド同士を接合する、いわゆるＣｕ－Ｃｕ接合により電気的に接続される。なお、これらのチップは、Ｃｕ－Ｃｕ接合の他、ビアやバンプにより接続することもできる。 FIG. 3 is a diagram showing an example of the stacked structure of the CMOS image sensor 1 according to the first embodiment. The CMOS image sensor 1 according to this embodiment has a sensor chip 201 (first chip) and a logic chip 202 (second chip) stacked below the sensor chip 201. The sensor chip 201 and logic chip 202 are electrically connected by, for example, so-called Cu-Cu bonding, which bonds Cu pads formed on each chip. Note that these chips can also be connected by vias or bumps in addition to Cu-Cu bonding.
　センサチップ２０１には、上側画素アレイ部１０ａが配置される。ロジックチップ２０２には、下側画素アレイ部１０ｂとカラム処理部３０とが配置される。画素アレイ部１０内の画素１１ごとに、その一部が、上側画素アレイ部１０ａに配置され、残りが下側画素アレイ部１０ｂに配置される。例えば、上側画素アレイ部１０ａには、光電変換回路１１０と、第１ソースフォロワ回路１２０の第１アンプトランジスタ１２１および第１選択トランジスタ１２２とが配置されている。この場合、第１ソースフォロワ回路１２０のバイアスカットトランジスタ１２３および負荷トランジスタ１２４と、信号保持選択回路１３０、および第２ソースフォロワ回路１４０が、下側画素アレイ部１０ｂに配置される。 The upper pixel array section 10a is arranged on the sensor chip 201. The lower pixel array section 10b and the column processing section 30 are arranged on the logic chip 202. For each pixel 11 in the pixel array section 10, a part of it is arranged on the upper pixel array section 10a, and the rest is arranged on the lower pixel array section 10b. For example, the photoelectric conversion circuit 110, and the first amplifier transistor 121 and the first selection transistor 122 of the first source follower circuit 120 are arranged on the upper pixel array section 10a. In this case, the bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120, the signal holding selection circuit 130, and the second source follower circuit 140 are arranged on the lower pixel array section 10b.
　なお、センサチップ２０１およびロジックチップ２０２のレイアウトは、上記レイアウトに限定されない。例えば、第１ソースフォロワ回路１２０の全素子が、ロジックチップ２０２に配置されていてもよい。すなわち、第１ソースフォロワ回路１２０は、光電変換回路１１０が形成された半導体基板とは、異なる半導体基板に形成されていてもよい。この場合、センサチップ２０１におけるフォトダイオード１１１の配置スペースが広がるため、感度を向上させることができる。 The layout of the sensor chip 201 and the logic chip 202 is not limited to the above layout. For example, all elements of the first source follower circuit 120 may be arranged on the logic chip 202. That is, the first source follower circuit 120 may be formed on a semiconductor substrate different from the semiconductor substrate on which the photoelectric conversion circuit 110 is formed. In this case, the arrangement space of the photodiode 111 in the sensor chip 201 is expanded, thereby improving the sensitivity.
　また、ロジックチップ２０２には、カラム処理部３０に加えて、垂直駆動部２０、水平駆動部４０、システム制御部５０、信号処理部６０、およびメモリ部７０も配置されるが、これらは、図３において記載を省略している。 In addition to the column processing unit 30, the logic chip 202 also includes a vertical drive unit 20, a horizontal drive unit 40, a system control unit 50, a signal processing unit 60, and a memory unit 70, but these are not shown in FIG. 3.
　図４は、上側画素アレイ部１０ａのレイアウトの一例を示す平面図である。図４に示すように、上側画素アレイ部１０ａでは、ＦＤ、転送トランジスタ１１２、および排出トランジスタ１１４が配置されたエリアと、第１リセットトランジスタ１１３が配置されたエリアとの境界には、絶縁膜１１５が形成されている。絶縁膜１１５は、ＳＴＩ（Shallow Trench Isolation）として形成される素子分離膜である。 FIG. 4 is a plan view showing an example of the layout of the upper pixel array section 10a. As shown in FIG. 4, in the upper pixel array section 10a, an insulating film 115 is formed at the boundary between the area in which the FD, transfer transistor 112, and discharge transistor 114 are arranged and the area in which the first reset transistor 113 is arranged. The insulating film 115 is an element isolation film formed as STI (Shallow Trench Isolation).
　また、第１リセットトランジスタ１１３が配置されたエリアと、第１選択トランジスタ１２２が配置されたエリアの境界部分にも絶縁膜１１５が形成されている。さらに、第１選択トランジスタ１２２が配置されたエリアと、第１アンプトランジスタ１２１が配置されたエリアとの境界にも絶縁膜１１５が形成されている。特に、この絶縁膜１１５は、第１アンプトランジスタ１２１を囲むように形成されている。ここで、図５を参照して、センサチップ２０１の一部の断面構造について説明する。 An insulating film 115 is also formed at the boundary between the area in which the first reset transistor 113 is arranged and the area in which the first selection transistor 122 is arranged. Furthermore, an insulating film 115 is also formed at the boundary between the area in which the first selection transistor 122 is arranged and the area in which the first amplifier transistor 121 is arranged. In particular, this insulating film 115 is formed so as to surround the first amplifier transistor 121. Here, the cross-sectional structure of a portion of the sensor chip 201 will be described with reference to FIG. 5.
　図５は、図４に示す切断線Ａ－Ａに沿った断面図である。図５に示すように、センサチップ２０１は、半導体基板２１０を含む。この半導体基板２１０は、Ｎ型の基層２１１と、基層２１１上に形成されたＰ型のエピタキシャル成長層２１２と、で構成されている。 FIG. 5 is a cross-sectional view taken along the line A-A shown in FIG. 4. As shown in FIG. 5, the sensor chip 201 includes a semiconductor substrate 210. This semiconductor substrate 210 is composed of an N-type base layer 211 and a P-type epitaxial growth layer 212 formed on the base layer 211.
　エピタキシャル成長層２１２上には、転送トランジスタ１１２のゲート絶縁膜１１２ｂが形成されている。ゲート絶縁膜１１２ｂ上には、転送トランジスタ１１２のゲート電極１１２ａが形成されている。ゲート電極１１２ａの側面には、サイドウォール絶縁膜１１２ｃが形成されている。ゲート電極１１２ａは、例えばポリシリコンを用いて形成することができる。また、ゲート絶縁膜１１２ｂおよびサイドウォール絶縁膜１１２ｃは、例えば酸化シリコン（ＳｉＯ２）を用いて形成することができる。転送トランジスタ１１２のドレイン領域には、ＦＤが形成されている。また、転送トランジスタ１１２のソース領域には、フォトダイオード１１１が形成されている。 A gate insulating film 112b of the transfer transistor 112 is formed on the epitaxial growth layer 212. A gate electrode 112a of the transfer transistor 112 is formed on the gate insulating film 112b. A sidewall insulating film 112c is formed on the side surface of the gate electrode 112a. The gate electrode 112a can be formed using, for example, polysilicon. Furthermore, the gate insulating film 112b and the sidewall insulating film 112c can be formed using, for example, silicon oxide (SiO 2 ). An FD is formed in the drain region of the transfer transistor 112. Furthermore, a photodiode 111 is formed in the source region of the transfer transistor 112.
　また、エピタキシャル成長層２１２上には、第１アンプトランジスタ１２１のゲート絶縁膜１２１ｂも形成されている。ゲート絶縁膜１２１ｂ上には、第１アンプトランジスタ１２１のゲート電極１２１ａが形成されている。ゲート電極１２１ａの側面には、サイドウォール絶縁膜１２１ｃが形成されている。ゲート電極１２１ａは、例えばポリシリコンを用いて形成することができる。また、ゲート絶縁膜１２１ｂおよびサイドウォール絶縁膜１２１ｃは、例えば酸化シリコン（ＳｉＯ２）を用いて形成することができる。 In addition, a gate insulating film 121b of the first amplifier transistor 121 is also formed on the epitaxial growth layer 212. A gate electrode 121a of the first amplifier transistor 121 is formed on the gate insulating film 121b. A sidewall insulating film 121c is formed on a side surface of the gate electrode 121a. The gate electrode 121a can be formed using, for example, polysilicon. In addition, the gate insulating film 121b and the sidewall insulating film 121c can be formed using, for example, silicon oxide (SiO 2 ).
　エピタキシャル成長層２１２内には、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅが形成されている。ドレイン領域１２１ｄおよびソース領域１２１ｅの直下には、絶縁膜１１５が形成されている。 The drain region 121d and source region 121e of the first amplifier transistor 121 are formed in the epitaxial growth layer 212. An insulating film 115 is formed directly below the drain region 121d and the source region 121e.
　本実施形態に係るＣＭＯＳイメージセンサ１には、上述したように、第１ソースフォロワ回路１２０および第２ソースフォロワ回路１４０という２つのソースフォロワ回路が設けられているため、消費電力が大きくなる傾向にある。この消費電力を抑制するために、各ソースフォロワ回路の各トランジスタを従来のμＡオーダの電流領域よりも低いｎＡオーダの電流領域で駆動しようとすると、ランダムノイズの悪化が想定される。ランダムノイズの悪化には、特に第１ソースフォロワ回路１２０の熱雑音の影響が大きい。 As described above, the CMOS image sensor 1 according to this embodiment has two source follower circuits, the first source follower circuit 120 and the second source follower circuit 140, and therefore tends to consume large amounts of power. If an attempt is made to drive each transistor in each source follower circuit in a current range of nA order, which is lower than the conventional current range of μA order, in order to suppress this power consumption, it is expected that random noise will worsen. The thermal noise of the first source follower circuit 120 in particular has a large effect on the deterioration of random noise.
　一般的なソースフォロワ回路のノイズＶＮＳＨ（V/sqrtHz）は、下記の式（１）で表すことができる。
Figure JPOXMLDOC01-appb-M000001
 ここで、
Ｋ：ボルツマン定数(=1.38×10-23J/K)
Ｃ：V1ノードの全容量(F)
γｎ１：ノイズ因子（noise factor）と呼ばれるバイアスに依存する無次元のパラメータ
γｎ2：ノイズ因子（noise factor）と呼ばれるバイアスに依存する無次元のパラメータ The noise V NSH (V/sqrtHz) of a typical source follower circuit can be expressed by the following formula (1).
Figure JPOXMLDOC01-appb-M000001
 here,
K: Boltzmann constant (=1.38× 10-23 J/K)
C: Total capacity of V1 node (F)
γ n1 : A dimensionless parameter that depends on the bias, called the noise factor. γ n2 : A dimensionless parameter that depends on the bias, called the noise factor.
　上記式（１）に基づいて、第１ソースフォロワ回路１２０の熱雑音Ｖ２ ＮＳＨは、下記の式（２）に示すように、第１アンプトランジスタ１２１のｇｍ１と負荷トランジスタ１２４のｇｍ２との比率で決まる。
Figure JPOXMLDOC01-appb-M000002
 Based on the above formula (1), the thermal noise V 2 NSH of the first source follower circuit 120 is determined by the ratio between gm1 of the first amplifier transistor 121 and gm2 of the load transistor 124, as shown in the following formula (2).
Figure JPOXMLDOC01-appb-M000002
　ここで、ｇｍ１およびｇｍ２は、下記の式（３）で定義される。
Figure JPOXMLDOC01-appb-M000003
 Here, gm1 and gm2 are defined by the following equation (3).
Figure JPOXMLDOC01-appb-M000003
　式（３）に示すように、ｇｍ１およびｇｍ２は、第１アンプトランジスタ１２１と負荷トランジスタ１２４の各ゲート電圧Ｖｇに対してドレイン－ソース間にどの程度電流Ｉｄｓを流すことができるかを示す電気的特性である。本実施形態では、第１アンプトランジスタ１２１のｇｍ１を向上させることによって、熱雑音Ｖ２ ＮＳＨを改善する。 As shown in formula (3), gm1 and gm2 are electrical characteristics indicating how much current Ids can flow between the drain and source for each gate voltage Vg of the first amplifier transistor 121 and the load transistor 124. In this embodiment, the thermal noise V 2 NSH is improved by improving gm1 of the first amplifier transistor 121.
　第１アンプトランジスタ１２１において、ｇｍ１と、ドレイン領域１２１ｄおよびソース領域１２１ｅとの間に形成される空乏層の容量ＣＤｅｐと、ゲート絶縁膜１２１ｂの容量Ｃｏｘとの間には、下記の式（４）で表される関係が成り立つ。
Figure JPOXMLDOC01-appb-M000004
 In the first amplifier transistor 121, the relationship expressed by the following formula (4) holds among gm1, the capacitance C Dep of the depletion layer formed between the drain region 121d and the source region 121e, and the capacitance C ox of the gate insulating film 121b.
Figure JPOXMLDOC01-appb-M000004
　第１アンプトランジスタ１２１のドレイン－ソース間の電流Ｉｄｓは、サブスレッショルド領域にＴａｕｒ－Ｎｉｎｇによる電流式を使うと、下記の式（５）および（６）で表すことができる。
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000006
 ここで、
μeff：実効移動度[cm2/V・s]
Ｗ：チャネル幅[cm]
Ｌ：チャネル長[cm]
εSi：シリコンの誘電率
ｑ：素電荷量
Ｎａ：アクセプタ密度(cm-3)
ΨB：フェルミ・ポテンシャルと真性ポテンシャルの差[V]
ｋ：ボルツマン定数
Ｔ：絶対温度[K]
Ｖｇ：ゲート電圧[V]
Ｖｔ：２ΨBの定義に基づく閾値電圧[V]
ｍ：ＭＯＳＦＥＴのボディ効果係数
Ｖds：ソース・ドレイン電圧[V] The drain-source current Ids of the first amplifier transistor 121 can be expressed by the following equations (5) and (6) when the Taur-Ning current equation is used in the subthreshold region.
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000006
 here,
μ eff : Effective mobility [cm 2 /V·s]
W: Channel width [cm]
L: Channel length [cm]
ε Si : Dielectric constant of silicon q: Elementary charge Na: Acceptor density (cm -3 )
Ψ B : Difference between Fermi potential and intrinsic potential [V]
k: Boltzmann constant T: Absolute temperature [K]
Vg: Gate voltage [V]
Vt: Threshold voltage based on the definition of 2Ψ B [V]
m: Body effect coefficient of MOSFET Vds: Source-drain voltage [V]
　ここで、ｇｍをその定義に従って計算すると、下記の式（７）で表すことができる。
Figure JPOXMLDOC01-appb-M000007
 Here, when gm is calculated according to its definition, it can be expressed by the following equation (7).
Figure JPOXMLDOC01-appb-M000007
　式（７）において、ボディ効果係数ｍは、以下の式（８）で表すことができる。
Figure JPOXMLDOC01-appb-M000008
 In equation (7), the body effect coefficient m can be expressed by the following equation (8).
Figure JPOXMLDOC01-appb-M000008
上記式（８）を上記式（７）に代入すると、上記式（４）の関係を導出することができる。式（４）に示すように、第１アンプトランジスタ１２１の空乏層の容量ＣＤｅｐを低減すると、ｇｍ１が向上する。この容量ＣＤｅｐと、シリコンの誘電率εＳｉと、空乏層の深さ方向の長さである幅ｘｄ（図５参照）との間には、下記の式（９）で表される関係が成り立つ。
Figure JPOXMLDOC01-appb-M000009
 By substituting the above formula (8) into the above formula (7), the relationship of the above formula (4) can be derived. As shown in formula (4), reducing the capacitance C Dep of the depletion layer of the first amplifier transistor 121 improves gm1. The relationship expressed by the following formula (9) holds between this capacitance C Dep , the dielectric constant ε Si of silicon, and the width xd (see FIG. 5), which is the length in the depth direction of the depletion layer.
Figure JPOXMLDOC01-appb-M000009
　式（９）に示すように、空乏層の幅ｘｄを大きくすると、空乏層の容量ＣＤｅｐを低減することができる。この幅ｘｄは、下記の式（１０）で表すことができる。
Figure JPOXMLDOC01-appb-M000010
 ここで、
ε０：真空の誘電率
φＢ：表面ポテンシャル
ｑ：素電荷量
ＮＡ：半導体ウェル領域の不純物濃度 As shown in formula (9), the capacitance C Deep of the depletion layer can be reduced by increasing the width xd of the depletion layer. This width xd can be expressed by the following formula (10).
Figure JPOXMLDOC01-appb-M000010
 here,
ε 0 : Dielectric constant of vacuum φ B : Surface potential q : Elementary charge N A : Impurity concentration of semiconductor well region
　式（１０）に示すように、エピタキシャル成長層２１２におけるドレイン領域１２１ｄおよびソース領域１２１ｅとの間に位置する半導体ウェル領域の不純物濃度ＮＡを低くすると、第１アンプトランジスタ１２１の空乏層を広げることができる。 As shown in formula (10), by lowering the impurity concentration N A of the semiconductor well region located between the drain region 121 d and the source region 121 e in the epitaxial growth layer 212 , the depletion layer of the first amplifier transistor 121 can be expanded.
　しかし、単に半導体ウェル領域の不純物濃度ＮＡを低くすると、ゲート絶縁膜１２１ｂ直下のチャネル領域の空乏層だけでなく、ドレイン領域１２１ｄおよびソース領域１２１ｅの直下の空乏層も広がってしまう。その結果、短チャネル効果で第１アンプトランジスタ１２１の電気的性能が低下してしまう。 However, simply lowering the impurity concentration N A of the semiconductor well region causes the depletion layer in the channel region directly below the gate insulating film 121 b to expand, as well as the depletion layers directly below the drain region 121 d and the source region 121 e, resulting in a short channel effect that degrades the electrical performance of the first amplifier transistor 121.
　そこで、本実施形態では、ドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５を形成する。これにより、半導体ウェル領域の不純物濃度ＮＡを低くしても、短チャネル効果を抑制しつつ、空乏層の幅ｘｄを大きくすることができる。 Therefore, in this embodiment, the insulating film 115 is formed immediately below the drain region 121d and the source region 121e. This makes it possible to increase the width xd of the depletion layer while suppressing the short channel effect even if the impurity concentration N A of the semiconductor well region is reduced.
　ドレイン領域およびソース領域の直下に絶縁膜が形成されていない従来のアンプトランジスタにおいて、例えば、半導体ウェル領域の不純物濃度ＮＡが４ｅ１７（ｃｍ－３）であり、ゲート電圧Ｖｇ＝２．９Ｖ、ドレイン電圧Ｖｄ＝２．９Ｖ、およびソース電圧Ｖｓ＝１．８Ｖの電圧設定で駆動する場合、空乏層の幅ｘｄは約９３ｎｍと想定される。その結果、空乏層の容量ＣＤｅｐは約１．９７（ｆＦ／μｍ２）となる。 In a conventional amplifier transistor in which no insulating film is formed directly below the drain and source regions, for example, when the impurity concentration N A of the semiconductor well region is 4e 17 (cm -3 ) and the device is driven with voltage settings of gate voltage Vg = 2.9 V, drain voltage Vd = 2.9 V, and source voltage Vs = 1.8 V, the width xd of the depletion layer is estimated to be about 93 nm. As a result, the capacitance C Dep of the depletion layer is about 1.97 (fF/μm 2 ).
　これに対し、本実施形態の第１アンプトランジスタ１２１において、半導体ウェル領域の不純物濃度ＮＡが、４ｅ１７（ｃｍ－３）よりも１０倍以上低い１ｅ１６（ｃｍ－３）であり、上記と同じ電圧設定で駆動する場合、空乏層の幅ｘｄは約５６５ｎｍと想定される。その結果、空乏層の容量ＣＤｅｐは約０．１８（ｆＦ／μｍ２）となる。このような空乏層の幅ｘｄの広がりに対応するために、エピタキシャル成長層２１２表面からの絶縁膜１１５の厚さｔ（図５参照）は、半導体基板２１０の厚さに対して１０％以内であることが望ましい。例えば、半導体基板２１０の厚さが６μｍ程度である場合、絶縁膜１１５の厚さｔは、５１０ｎｍ程度である。 In contrast, in the first amplifier transistor 121 of this embodiment, when the impurity concentration N A of the semiconductor well region is 1e 16 (cm −3 ), which is 10 times lower than 4e 17 (cm −3 ), and the transistor is driven with the same voltage setting as above, the width xd of the depletion layer is assumed to be about 565 nm. As a result, the capacitance C Dep of the depletion layer is about 0.18 (fF/μm 2 ). In order to accommodate the expansion of the width xd of the depletion layer, it is desirable that the thickness t (see FIG. 5 ) of the insulating film 115 from the surface of the epitaxial growth layer 212 be within 10% of the thickness of the semiconductor substrate 210. For example, when the thickness of the semiconductor substrate 210 is about 6 μm, the thickness t of the insulating film 115 is about 510 nm.
　なお、上記の不純物濃度ＮＡの値や、絶縁膜１１５の厚さｔの値は、一例であり、これらの値に限定されるものではない。不純物濃度ＮＡは、第１アンプトランジスタ１２１の駆動中にドレイン領域１２１ｄおよびソース領域１２１ｅの各々の下端部と同じ深さか、または下端部よりも深い位置まで空乏化する濃度であればよい。また、絶縁膜１１５は、その厚さｔが、第１アンプトランジスタ１２１の駆動中に生成される空乏層より少なくとも深くなるように形成されていればよい。 The above values of the impurity concentration N A and the thickness t of the insulating film 115 are merely examples and are not limited to these values. The impurity concentration N A may be a concentration that depletes the drain region 121d and the source region 121e to the same depth as the bottom ends of the drain region 121d and the source region 121e while the first amplifier transistor 121 is in operation, or to a position deeper than the bottom ends. The insulating film 115 may be formed so that its thickness t is at least deeper than the depletion layer generated while the first amplifier transistor 121 is in operation.
　また、第１アンプトランジスタ１２１と、転送トランジスタ１１２や第１リセットトランジスタ１１３等の他の画素トランジスタとの間で、半導体ウェル領域の不純物濃度が異なっていてもよい。すなわち、第１アンプトランジスタ１２１の不純物濃度のみが、他の画素トランジスタの不純物濃度よりも低くてもよい。 In addition, the impurity concentration of the semiconductor well region may be different between the first amplifier transistor 121 and other pixel transistors such as the transfer transistor 112 and the first reset transistor 113. In other words, only the impurity concentration of the first amplifier transistor 121 may be lower than the impurity concentration of the other pixel transistors.
　以下、図６Ａ～図６Ｇを参照して、本実施形態に係る第１アンプトランジスタ１２１の製造方法の一例について説明する。 Below, an example of a method for manufacturing the first amplifier transistor 121 according to this embodiment will be described with reference to Figures 6A to 6G.
　まず、図６Ａに示すように、半導体基板２１０のエピタキシャル成長層２１２上に酸化シリコン膜２１３を成膜する。酸化シリコン膜２１３は、例えば熱酸化等の通常用いられる成膜方法で形成することができる。 First, as shown in FIG. 6A, a silicon oxide film 213 is formed on the epitaxial growth layer 212 of the semiconductor substrate 210. The silicon oxide film 213 can be formed by a commonly used film formation method such as thermal oxidation.
　次に、図６Ｂに示すように、エピタキシャル成長層２１２内に絶縁膜１１５を形成する。絶縁膜１１５は、例えば、エピタキシャル成長層２１２の一部をエッチングして形成されたホール内にシリコン酸化物を埋め込むことによって、形成することができる。なお、シリコン酸化物は、例えばＡＬＤ（Atomic Layer Deposition）法を用いて埋め込むことができる。 Next, as shown in FIG. 6B, an insulating film 115 is formed in the epitaxial growth layer 212. The insulating film 115 can be formed, for example, by filling a hole formed by etching a part of the epitaxial growth layer 212 with silicon oxide. The silicon oxide can be filled using, for example, the ALD (Atomic Layer Deposition) method.
　次に、図６Ｃに示すように、例えばマスク等を用いて絶縁膜１１５の一部をエッチングする。エッチングされる箇所は、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの形成領域である。 Next, as shown in FIG. 6C, a portion of the insulating film 115 is etched using, for example, a mask. The area to be etched is the area where the drain region 121d and source region 121e of the first amplifier transistor 121 are formed.
　次に、図６Ｄに示すように、絶縁膜１１５間のエピタキシャル成長層２１２を選択的にエピタキシャル成長させることによって、第１アンプトランジスタ１２１のチャネル領域２１２ａを形成する。この工程では、例えば枚葉方式の熱ＣＶＤ（Chemical Vapor Deposition Method）方式でエピタキシャル成長層２１２を選択的にエピタキシャル成長させる。この熱ＣＶＤ方式では、例えば塩化水素（ＨＣｌ）などのエッチャントガスの効果で核生成を制御する。このとき、絶縁膜１１５間で露出しているエピタキシャル成長層２１２の領域のみにチャネル領域２１２ａが成膜されるように、酸化シリコン膜２１３との成膜時間の差が大きくなる成膜速度で上記領域をエピタキシャル成長させる。 Next, as shown in FIG. 6D, the epitaxial growth layer 212 between the insulating films 115 is selectively epitaxially grown to form the channel region 212a of the first amplifier transistor 121. In this process, the epitaxial growth layer 212 is selectively epitaxially grown, for example, by a single-wafer thermal CVD (Chemical Vapor Deposition Method). In this thermal CVD method, nucleation is controlled by the effect of an etchant gas such as hydrogen chloride (HCl). At this time, the above region is epitaxially grown at a film formation speed that increases the difference in film formation time with the silicon oxide film 213, so that the channel region 212a is formed only in the region of the epitaxial growth layer 212 exposed between the insulating films 115.
　次に、図６Ｅに示すように、非選択エピタキシャル成長によって、酸化シリコン膜２１３上にポリシリコン膜２１４を形成するとともに、チャネル領域２１２ａをさらにエピタキシャル成長させる。この工程でも、枚葉方式の熱ＣＶＤ（Chemical Vapor Deposition Method）方式でエピタキシャル成長を行う。ただし、この非選択エピタキシャル成長工程で用いるエッチャントガスは、上記選択エピタキシャル成長工程で用いるエッチャントガスから変更される。すなわち、核生成を抑制しないエッチャントガスが用いられる。また、この非選択エピタキシャル成長工程では、酸化シリコン膜２１３とチャネル領域２１２ａとの間で成膜時間の差が小さくなるような成膜速度でエピタキシャル成長を行う。さらに、この非選択エピタキシャル成長工程の成膜温度（基板温度）は、上記選択エピタキシャル成長工程の成膜温度（基板温度）よりも高い温度に設定される。 Next, as shown in FIG. 6E, a polysilicon film 214 is formed on the silicon oxide film 213 by non-selective epitaxial growth, and the channel region 212a is further epitaxially grown. In this process, epitaxial growth is also performed by a single-wafer thermal CVD (Chemical Vapor Deposition Method). However, the etchant gas used in this non-selective epitaxial growth process is changed from the etchant gas used in the selective epitaxial growth process. In other words, an etchant gas that does not suppress nucleation is used. In addition, in this non-selective epitaxial growth process, epitaxial growth is performed at a film growth rate that reduces the difference in film growth time between the silicon oxide film 213 and the channel region 212a. Furthermore, the film growth temperature (substrate temperature) in this non-selective epitaxial growth process is set to a temperature higher than the film growth temperature (substrate temperature) in the selective epitaxial growth process.
　次に、図６Ｆに示すように、ＣＭＰ（Chemical Mechanical Polishing）によって、平坦化処理を行う。これにより、酸化シリコン膜２１３、ポリシリコン膜２１４の一部、およびチャネル領域２１２ａの一部が除去される。その結果、酸化シリコン膜２１３上におけるドレイン領域１２１ｄおよびソース領域１２１ｅになる領域にポリシリコン膜２１４が残り、残ったポリシリコン膜２１４間にチャネル領域２１２ａが残る。 Next, as shown in FIG. 6F, a planarization process is performed by CMP (Chemical Mechanical Polishing). This removes the silicon oxide film 213, part of the polysilicon film 214, and part of the channel region 212a. As a result, the polysilicon film 214 remains in the regions that will become the drain region 121d and the source region 121e on the silicon oxide film 213, and the channel region 212a remains between the remaining polysilicon film 214.
　最後に、図６Ｇに示すように、チャネル領域２１２ａ上にゲート絶縁膜１２１ｂ、ゲート電極１２１ａ、およびサイドウォール絶縁膜１２１ｃを形成する。なお、これらは、通常用いられる製造プロセスで形成することができるため、詳細な説明を省略する。また、この工程では、上記平坦化処理で残ったポリシリコン膜２１４にＮ型の不純物を注入してドレイン領域１２１ｄおよびソース領域１２１ｅを形成する。この不純物の濃度は、例えば１ｅ２０ｃｍ－３程度である。ただし、ドレイン領域１２１ｄおよびソース領域１２１ｅでは、不純物を全領域に拡散させる必要はなく、少なくともチャネル領域２１２ａに接する部分が拡散膜であればよい。すなわち、ドレイン領域１２１ｄおよびソース領域１２１ｅの内側が拡散膜で、外側がポリシリコン膜であってもよい。なお、本実施形態では、チャネル領域２１２ａを含むＰ型の半導体ウェル領域は、その濃度が極低濃度である。そのため、この半導体ウェル領域は、イオン注入ではなくエピタキシャル成長によって形成されたノンドープ型の領域である。 Finally, as shown in FIG. 6G, a gate insulating film 121b, a gate electrode 121a, and a sidewall insulating film 121c are formed on the channel region 212a. Since these can be formed by a commonly used manufacturing process, detailed description is omitted. In this process, an N-type impurity is implanted into the polysilicon film 214 remaining after the planarization process to form the drain region 121d and the source region 121e. The concentration of this impurity is, for example, about 1e 20 cm −3 . However, in the drain region 121d and the source region 121e, it is not necessary to diffuse the impurity into the entire region, and it is sufficient that at least the portion in contact with the channel region 212a is a diffusion film. That is, the inside of the drain region 121d and the source region 121e may be a diffusion film, and the outside may be a polysilicon film. In this embodiment, the concentration of the P-type semiconductor well region including the channel region 212a is extremely low. Therefore, this semiconductor well region is a non-doped region formed by epitaxial growth rather than ion implantation.
　上述した第１アンプトランジスタ１２１の製造方法は、一例であり、これに限定されない。ここで、図７Ａ～図７Ｈを参照して、本実施形態に係る第１アンプトランジスタ１２１の製造方法の別例について説明する。なお、本例では、図６Ａ～図６Ｇを用いて製造工程と同様の製造工程については、重複する説明を省略する。 The above-described method for manufacturing the first amplifier transistor 121 is an example, and is not limited to this. Here, with reference to Figures 7A to 7H, another example of the method for manufacturing the first amplifier transistor 121 according to this embodiment will be described. Note that in this example, redundant descriptions of manufacturing steps similar to those described using Figures 6A to 6G will be omitted.
　本例では、図７Ａに示すように、半導体基板２１０の基層２１１上に、酸化シリコン膜２１３を成膜する。 In this example, as shown in FIG. 7A, a silicon oxide film 213 is formed on a base layer 211 of a semiconductor substrate 210.
　次に、図７Ｂに示すように、絶縁膜１１５を成膜する。絶縁膜１１５は、例えば、基層２１１の一部をエッチングして形成されたホール内にＡＬＤ法等を用いてシリコン酸化物で埋め込むことによって、形成することができる。上述した例では、絶縁膜１１５は、図６Ｂにしめすように第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの形成領域に形成されている。一方、本例では、絶縁膜１１５は、第１アンプトランジスタ１２１の形成領域全体に形成されている。 Next, as shown in FIG. 7B, the insulating film 115 is formed. The insulating film 115 can be formed, for example, by filling a hole formed by etching a part of the base layer 211 with silicon oxide using an ALD method or the like. In the above example, the insulating film 115 is formed in the formation region of the drain region 121d and the source region 121e of the first amplifier transistor 121 as shown in FIG. 6B. On the other hand, in this example, the insulating film 115 is formed over the entire formation region of the first amplifier transistor 121.
　次に、図７Ｃに示すように、絶縁膜１１５を分断する。分断箇所は、第１アンプトランジスタ１２１のチャネル領域２１２ａとなる部分である。絶縁膜１１５は、例えばＲＩＥ（Reactive Ion Etching）装置等を用いたエッチングによって分断することができる。 Next, as shown in FIG. 7C, the insulating film 115 is divided. The division is at a portion that will become the channel region 212a of the first amplifier transistor 121. The insulating film 115 can be divided by etching using, for example, an RIE (Reactive Ion Etching) device.
　次に、図７Ｄに示すように、例えばマスク等を用いて絶縁膜１１５の一部をエッチングする。エッチングされる箇所は、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの形成領域である。 Next, as shown in FIG. 7D, a portion of the insulating film 115 is etched using, for example, a mask. The area to be etched is the area where the drain region 121d and source region 121e of the first amplifier transistor 121 are formed.
　次に、図７Ｅに示すように、絶縁膜１１５のエッチング箇所を選択的にエピタキシャル成長させることによって、Ｐ型のエピタキシャル成長層であるチャネル領域２１２ａを形成する。 Next, as shown in FIG. 7E, the etched portions of the insulating film 115 are selectively epitaxially grown to form a channel region 212a, which is a P-type epitaxial growth layer.
　次に、図７Ｆに示すように、非選択エピタキシャル成長によって、酸化シリコン膜２１３上にポリシリコン膜２１４を形成するとともに、チャネル領域２１２ａをさらにエピタキシャル成長させる。 Next, as shown in FIG. 7F, a polysilicon film 214 is formed on the silicon oxide film 213 by non-selective epitaxial growth, and the channel region 212a is further epitaxially grown.
　次に、図７Ｇに示すように、ＣＭＰによって、平坦化処理を行う。これにより、酸化シリコン膜２１３、ポリシリコン膜２１４の一部、およびチャネル領域２１２ａの一部が除去される。その結果、酸化シリコン膜２１３上におけるドレイン領域１２１ｄおよびソース領域１２１ｅになる領域にポリシリコン膜２１４が残り、残ったポリシリコン膜２１４間にチャネル領域２１２ａが残る。 Next, as shown in FIG. 7G, a planarization process is performed by CMP. This removes the silicon oxide film 213, part of the polysilicon film 214, and part of the channel region 212a. As a result, the polysilicon film 214 remains in the regions that will become the drain region 121d and the source region 121e on the silicon oxide film 213, and the channel region 212a remains between the remaining polysilicon film 214.
　最後に、図７Ｈに示すように、基層２１１の上部にエピタキシャル成長層２１２を形成するとともに、チャネル領域２１２ａ上にゲート絶縁膜１２１ｂ、ゲート電極１２１ａ、およびサイドウォール絶縁膜１２１ｃを形成する。また、この工程では、上記平坦化処理で残ったポリシリコン膜２１４にＮ型の不純物を注入してドレイン領域１２１ｄおよびソース領域１２１ｅも形成する。この不純物の濃度は、例えば１ｅ２０ｃｍ－３程度である。ただし、ドレイン領域１２１ｄおよびソース領域１２１ｅでは、不純物を全領域に拡散させる必要はなく、少なくともチャネル領域２１２ａに接する部分が拡散膜であればよい。すなわち、ドレイン領域１２１ｄおよびソース領域１２１ｅの内側が拡散膜で、外側がポリシリコン膜であってもよい。なお、本例でも、チャネル領域２１２ａを含むＰ型の半導体ウェル領域は、その濃度が極低濃度である。そのため、この半導体ウェル領域は、イオン注入ではなくエピタキシャル成長によって形成されたノンドープ型の領域である。 Finally, as shown in FIG. 7H, an epitaxial growth layer 212 is formed on the upper part of the base layer 211, and a gate insulating film 121b, a gate electrode 121a, and a sidewall insulating film 121c are formed on the channel region 212a. In this process, an N-type impurity is implanted into the polysilicon film 214 remaining after the planarization process to form the drain region 121d and the source region 121e. The concentration of this impurity is, for example, about 1e 20 cm −3 . However, in the drain region 121d and the source region 121e, it is not necessary to diffuse the impurity into the entire region, and it is sufficient that at least the part in contact with the channel region 212a is a diffusion film. That is, the inside of the drain region 121d and the source region 121e may be a diffusion film, and the outside may be a polysilicon film. In this example, the concentration of the P-type semiconductor well region including the channel region 212a is extremely low. Therefore, this semiconductor well region is a non-doped region formed by epitaxial growth rather than ion implantation.
　上述した本実施形態では、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０の熱雑音の増大を抑制することができる。したがって、本実施形態に係るＣＭＯＳイメージセンサ１によれば、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In the above-described embodiment, the insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120 even when the first amplifier transistor 121 is driven with a low current. Therefore, the CMOS image sensor 1 according to this embodiment makes it possible to reduce random noise while suppressing power consumption.
　（第２実施形態）
　以下、第２実施形態について説明する。本実施形態に係るＣＭＯＳイメージセンサでは、第１アンプトランジスタ１２１の構造が第１実施形態と異なる。そのため、ここでは、第１アンプトランジスタ１２１の構造についてのみ説明し、その他の説明は省略する。 Second Embodiment
The second embodiment will be described below. In the CMOS image sensor according to this embodiment, the structure of the first amplifier transistor 121 is different from that of the first embodiment. Therefore, only the structure of the first amplifier transistor 121 will be described here, and other descriptions will be omitted.
　図８は、第２実施形態に係る第１アンプトランジスタ１２１の構造を示す断面図である。図８では、第１実施形態と同様の構成要素には同じ符号を付している。本実施形態に係る第１アンプトランジスタ１２１では、ＳｉＧｅ（シリコンゲルマニウム）層２１５がチャネル領域２１２ａの直下に形成されている。すなわち、第１アンプトランジスタ１２１のエピタキシャル成長層２１２は、チャネル領域２１２ａである第１シリコン層、ＳｉＧｅ層２１５、ＳｉＧｅ層２１５に積層されている第２シリコン層の３層構造となっている。 FIG. 8 is a cross-sectional view showing the structure of the first amplifier transistor 121 according to the second embodiment. In FIG. 8, the same components as those in the first embodiment are given the same reference numerals. In the first amplifier transistor 121 according to this embodiment, a SiGe (silicon germanium) layer 215 is formed directly below the channel region 212a. That is, the epitaxial growth layer 212 of the first amplifier transistor 121 has a three-layer structure of a first silicon layer which is the channel region 212a, a SiGe layer 215, and a second silicon layer stacked on the SiGe layer 215.
　ＳｉＧｅ層２１５は、図６Ｄまたは図７Ｅに示す選択エピタキシャル成長工程時に、形成することができる。この工程では、例えば熱ＣＶＤ装置に内に導入するエッチャントガスを、成膜装置内にＳｉＧｅ層２１５を形成するための第１エッチャントガスからチャネル領域２１２ａを形成するための第２エッチャントガスに切り替えている。これにより、絶縁膜１１５間にＳｉＧｅ層２１５およびチャネル領域２１２ａを選択的に形成することができる。 The SiGe layer 215 can be formed during the selective epitaxial growth process shown in FIG. 6D or FIG. 7E. In this process, for example, the etchant gas introduced into the thermal CVD apparatus is switched from a first etchant gas for forming the SiGe layer 215 in the film formation apparatus to a second etchant gas for forming the channel region 212a. This allows the SiGe layer 215 and the channel region 212a to be selectively formed between the insulating films 115.
　上記のように形成されたＳｉＧｅ層２１５の原子間距離は、チャネル領域２１２ａのシリコンの原子間距離よりも大きい。そのため、チャネル領域２１２ａ内では、チャネル長方向に引っ張り応力が生じる（図８の矢印参照）。これにより、チャネル領域２１２ａ内における電子移動度が向上するので、第１アンプトランジスタ１２１のｇｍ１が大きくなる。その結果、第１実施形態で説明した式（１）に示すように、第１ソースフォロワ回路１２０の熱雑音Ｖ２ ＮＳＨをさらに低減することができる。よって、本実施形態によれば、ランダムノイズをより一層低減することが可能となる。 The interatomic distance of the SiGe layer 215 formed as described above is larger than the interatomic distance of silicon in the channel region 212a. Therefore, tensile stress is generated in the channel region 212a in the channel length direction (see the arrow in FIG. 8). This improves the electron mobility in the channel region 212a, and gm1 of the first amplifier transistor 121 increases. As a result, as shown in the formula (1) described in the first embodiment, the thermal noise V 2 NSH of the first source follower circuit 120 can be further reduced. Therefore, according to this embodiment, it is possible to further reduce random noise.
　（第３実施形態）
　以下、第３実施形態について説明する。本実施形態に係るＣＭＯＳイメージセンサでは、第１アンプトランジスタ１２１の構造が第１実施形態と異なる。そのため、ここでも、第１アンプトランジスタ１２１の構造についてのみ説明し、その他の説明は省略する。 Third Embodiment
Hereinafter, the third embodiment will be described. In the CMOS image sensor according to this embodiment, the structure of the first amplifier transistor 121 is different from that of the first embodiment. Therefore, here too, only the structure of the first amplifier transistor 121 will be described, and other descriptions will be omitted.
　第１アンプトランジスタ１２１をＳｉ（１１１）面に配置する場合、チャネル領域２１２ａの結晶面が、比較的欠陥の多いＳｉ（１１１）面に配置される。この場合、電気的特性の悪化が懸念される。 If the first amplifier transistor 121 is arranged on the Si(111) surface, the crystal plane of the channel region 212a will be arranged on the Si(111) surface, which has relatively many defects. In this case, there is a concern that the electrical characteristics may deteriorate.
　そこで、本実施形態では、Ｆｉｎ型ＭＯＳトランジスタの構造を第１アンプトランジスタ１２１に適用する。ここで、まず、図９を参照して一般的なＦｉｎ型ＭＯＳトランジスタの構造を説明する。 Therefore, in this embodiment, the structure of a Fin-type MOS transistor is applied to the first amplifier transistor 121. First, the structure of a general Fin-type MOS transistor will be described with reference to FIG. 9.
　図９は、一般的なＦｉｎ型ＭＯＳトランジスタの構造を示す斜視図である。図９に示すＦｉｎ型ＭＯＳトランジスタ１２１０では、シリコン基板２１２０の上に酸化シリコン膜１１５０が形成されている。酸化シリコン膜１１５０内には、いわゆるダブルゲート構造のゲート電極１２１０ａが形成されている。また、酸化シリコン膜１１５０内では、ドレイン領域１２１０ｄおよびソース領域１２１０ｅが、ゲート電極１２１０ａを挟んで対向配置されている。 FIG. 9 is a perspective view showing the structure of a typical Fin-type MOS transistor. In the Fin-type MOS transistor 1210 shown in FIG. 9, a silicon oxide film 1150 is formed on a silicon substrate 2120. A gate electrode 1210a having a so-called double gate structure is formed in the silicon oxide film 1150. Also, in the silicon oxide film 1150, a drain region 1210d and a source region 1210e are arranged opposite each other with the gate electrode 1210a in between.
　上記のような構造を有するＦｉｎ型ＭＯＳトランジスタ１２１０では、ゲート電極１２１０ａに駆動電圧が印加されると、チャネル領域は、Ｓｉ（１１１）面よりも欠陥の少ないＳｉ（１１０）面に生じる。そのため、電気的特性の悪化を回避することができる。 In the Fin-type MOS transistor 1210 having the above structure, when a drive voltage is applied to the gate electrode 1210a, a channel region is generated on the Si(110) surface, which has fewer defects than the Si(111) surface. This makes it possible to avoid deterioration of electrical characteristics.
　以上説明したＦｉｎ型ＭＯＳトランジスタ１２１０に続いて、本実施形態に係る第１アンプトランジスタ１２１の構造を説明する。 Following the above-described Fin-type MOS transistor 1210, the structure of the first amplifier transistor 121 according to this embodiment will now be described.
　図１０は、第３実施形態に係る第１アンプトランジスタ１２１の構造を示す断面図である。なお、図１０は、断面図であるため、ドレイン領域１２１ｄおよびソース領域１２１ｅの記載を省略している。ただし、Ｆｉｎ型ＭＯＳトランジスタ１２１０と同様に、ドレイン領域１２１ｄはゲート電極１２１ａの奥側に形成され、ソース領域１２１ｅはゲート電極１２１ａの手前側に形成されている。また、ドレイン領域１２１ｄおよびソース領域１２１ｅの直下には、上述した他の実施形態と同様に絶縁膜１１５が形成されている。 FIG. 10 is a cross-sectional view showing the structure of the first amplifier transistor 121 according to the third embodiment. Since FIG. 10 is a cross-sectional view, the drain region 121d and the source region 121e are omitted. However, similar to the Fin-type MOS transistor 1210, the drain region 121d is formed on the rear side of the gate electrode 121a, and the source region 121e is formed on the front side of the gate electrode 121a. Also, an insulating film 115 is formed directly below the drain region 121d and the source region 121e, similar to the other embodiments described above.
　上記のように構成された第１アンプトランジスタ１２１でも、ゲート電極１２１０ａに駆動電圧が印加されると、チャネル領域２１２ａがＳｉ（１１０）面に生じる。そのため、電気的特性の悪化を回避することができる。また、ドレイン領域１２１ｄおよびソース領域１２１ｅの直下には、絶縁膜１１５が形成されているため、空乏層の広がりを抑制することができる。 Even in the first amplifier transistor 121 configured as described above, when a drive voltage is applied to the gate electrode 1210a, a channel region 212a is generated on the Si(110) surface. This makes it possible to avoid deterioration of electrical characteristics. In addition, since an insulating film 115 is formed directly below the drain region 121d and the source region 121e, the expansion of the depletion layer can be suppressed.
　以下、図１１Ａ～図１１Ｇを参照して、本実施形態に係る第１アンプトランジスタ１２１の製造方法の一例について説明する。 Below, an example of a method for manufacturing the first amplifier transistor 121 according to this embodiment will be described with reference to Figures 11A to 11G.
　まず、図１１Ａに示すように、エピタキシャル成長層２１２が形成されていない基層２１１から成る半導体基板２１０を形成する。 First, as shown in FIG. 11A, a semiconductor substrate 210 is formed, which is made of a base layer 211 on which an epitaxial growth layer 212 is not formed.
　次に、図１１Ｂに示すように、基層２１１内に絶縁膜１１５の一部を形成する。この絶縁膜１１５は、例えば、基層２１１にエッチング等により形成されたホール内にＡＬＤ法等を用いてシリコン酸化物を埋め込むことによって、形成することができる。この絶縁膜１１５は、後述するＥＳＳ(Empty Space in Silicon)のストッパー膜として機能する。 Next, as shown in FIG. 11B, a part of the insulating film 115 is formed in the base layer 211. This insulating film 115 can be formed, for example, by filling holes formed in the base layer 211 by etching or the like with silicon oxide using the ALD method or the like. This insulating film 115 functions as a stopper film for ESS (Empty Space in Silicon), which will be described later.
　次に、図１１Ｃに示すように、基層２１１上に窒化シリコン（ＳｉＮ）膜２１６を形成する。続いて、窒化シリコン膜２１６上に酸化シリコン（ＳｉＯ２）膜２１７を形成する。続いて、後述するＥＳＳ用のトレンチ２１８を形成する。トレンチ２１８は、窒化シリコン膜２１６および酸化シリコン膜２１７を貫通し、基層２１１で終端する。基層２１１内において、トレンチ２１８は、ストッパー膜（絶縁膜１１５）の内側に形成されている。また、トレンチ２１８の深さは、上記ストッパー膜よりも浅い。 11C, a silicon nitride (SiN) film 216 is formed on the base layer 211. Then, a silicon oxide (SiO 2 ) film 217 is formed on the silicon nitride film 216. Then, a trench 218 for ESS, which will be described later, is formed. The trench 218 penetrates the silicon nitride film 216 and the silicon oxide film 217, and terminates at the base layer 211. In the base layer 211, the trench 218 is formed on the inside of the stopper film (insulating film 115). The depth of the trench 218 is shallower than the stopper film.
　次に、図１１Ｄに示すように、基層２１１内にＥＳＳ２１９を形成する。ＥＳＳ２１９は、例えばアルカリ性のエッチング液をトレンチ２１８から流入させることによって、Ｓｉ（１１１）面に対してＳｉ（１１０）面を高選択にエッチングすることによって形成することができる。このエッチングは、上記絶縁膜１１５でストップする。これにより、Ｓｉ（１１０）面方向に延びるＥＳＳ２１９が完成する。 Next, as shown in FIG. 11D, ESS 219 is formed in base layer 211. ESS 219 can be formed by, for example, flowing an alkaline etching solution through trench 218 to highly selectively etch the Si(110) surface relative to the Si(111) surface. This etching stops at insulating film 115. This completes ESS 219 extending in the direction of the Si(110) surface.
　次に、図１１Ｅに示すように、ＡＬＤ法を用いてシリコン酸化物をトレンチ２１８およびＥＳＳ２１９に埋め込むことによって、絶縁膜１１５が完成する。その結果、疑似的なＦＤ－ＳＯＩ（Fully Depleted Silicon On Insulator）構造が形成される。 Next, as shown in FIG. 11E, the insulating film 115 is completed by filling the trench 218 and the ESS 219 with silicon oxide using the ALD method. As a result, a pseudo FD-SOI (Fully Depleted Silicon On Insulator) structure is formed.
　次に、図１１Ｆに示すように、ＣＭＰによって平坦化処理を行う。これにより、窒化シリコン膜２１６および酸化シリコン膜２１７が除去される。 Next, as shown in FIG. 11F, a planarization process is performed by CMP. This removes the silicon nitride film 216 and the silicon oxide film 217.
　最後に、図１１Ｇに示すように、基層２１１の上部にエピタキシャル成長層２１２を形成するとともに、ダブルゲート構造のゲート電極１２１ａおよびサイドウォール絶縁膜１２１ｃを形成する。また、この工程では、ドレイン領域１２１ｄおよびソース領域１２１ｅも形成する。本実施形態でも、エピタキシャル成長層２１２、すなわち、チャネル領域２１２ａを含むＰ型の半導体ウェル領域は、その濃度が極低濃度である。そのため、この半導体ウェル領域は、イオン注入ではなくエピタキシャル成長によって形成されたノンドープ型の領域である。 Finally, as shown in FIG. 11G, an epitaxial growth layer 212 is formed on the upper part of the base layer 211, and a gate electrode 121a and a sidewall insulating film 121c of a double gate structure are formed. In this process, a drain region 121d and a source region 121e are also formed. In this embodiment, too, the epitaxial growth layer 212, i.e., the P-type semiconductor well region including the channel region 212a, has an extremely low concentration. Therefore, this semiconductor well region is a non-doped region formed by epitaxial growth rather than ion implantation.
　以上説明した本実施形態によれば、第１アンプトランジスタ１２１がＦｉｎ型ＭＯＳトランジスタであるため、チャネル領域２１２ａを、比較的結晶欠陥の少ないＳｉ（１１０）面に形成することができる。そのため、第１アンプトランジスタ１２１の電気的特性を改善することが可能となる。 In the present embodiment described above, since the first amplifier transistor 121 is a Fin-type MOS transistor, the channel region 212a can be formed on the Si(110) surface, which has relatively few crystal defects. This makes it possible to improve the electrical characteristics of the first amplifier transistor 121.
　また、本実施形態でも、他の実施形態と同様に、ドレイン領域１２１ｄおよびソース領域１２１ｅの直下には、絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつチャネル領域２１２ａの不純物濃度を極低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流領域で駆動しても、ランダムノイズを低減することが可能となる。なお、本実施形態では、絶縁膜１１５は、ドレイン領域１２１ｄおよびソース領域１２１ｅの直下だけでなく、チャネル領域２１２ａの直下にも形成されている。 In this embodiment, as in the other embodiments, an insulating film 115 is formed directly below the drain region 121d and the source region 121e. This makes it possible to make the impurity concentration of the channel region 212a extremely low while suppressing the short channel effect. This makes it possible to reduce random noise even when the first amplifier transistor 121 is driven in a low current region. Note that in this embodiment, the insulating film 115 is formed not only directly below the drain region 121d and the source region 121e, but also directly below the channel region 212a.
　（第１変形例）
　図１２は、第１変形例に係る画素の回路構成を示す図である。なお、図１２では、上述した第１実施形態に係る画素１１と同様の回路素子には、同じ符号を付す。図１２に示す画素１１ａは、光電変換回路１１０ａと、第１ソースフォロワ回路１２０ａと、信号保持選択回路１３０ａと、第２ソースフォロワ回路１４０ａと、を有する。 (First Modification)
Fig. 12 is a diagram showing a circuit configuration of a pixel according to a first modified example. In Fig. 12, the same circuit elements as those of the pixel 11 according to the first embodiment described above are denoted by the same reference numerals. The pixel 11a shown in Fig. 12 has a photoelectric conversion circuit 110a, a first source follower circuit 120a, a signal holding selection circuit 130a, and a second source follower circuit 140a.
　光電変換回路１１０ａは、フォトダイオード１１１、転送トランジスタ１１２、および第１リセットトランジスタ１１３を有する。これらの回路素子については、第１実施形態で説明しているため、詳細な説明を省略する。 The photoelectric conversion circuit 110a has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
　第１ソースフォロワ回路１２０ａは、第１アンプトランジスタ１２１およびバイアスカットトランジスタ１２３を有する。これらの回路素子についても、第１実施形態で説明しているため、詳細な説明を省略する。 The first source follower circuit 120a has a first amplifier transistor 121 and a bias cut transistor 123. These circuit elements are also described in the first embodiment, so detailed description will be omitted.
　信号保持選択回路１３０ａは、第１容量素子１３１、第２容量素子１３２、第１サンプリングトランジスタ１３３、および第２サンプリングトランジスタ１３４を有する。信号保持選択回路１３０ａでは、第１容量素子１３１および第２容量素子１３２のそれぞれの一端は、電源電圧ＶＤＤの電位を有する電源線に接続されている。第１容量素子１３１の他端は、第１サンプリングトランジスタ１３３のソースに接続されている。第２容量素子１３２の他端は、第２サンプリングトランジスタ１３４のソースに接続されている。 The signal holding selection circuit 130a has a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, and a second sampling transistor 134. In the signal holding selection circuit 130a, one end of each of the first capacitance element 131 and the second capacitance element 132 is connected to a power supply line having a potential of the power supply voltage VDD. The other end of the first capacitance element 131 is connected to the source of the first sampling transistor 133. The other end of the second capacitance element 132 is connected to the source of the second sampling transistor 134.
　第１サンプリングトランジスタ１３３は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第１サンプリング信号ＳＲに従って、第１ソースフォロワ回路１２０ａで増幅された画素信号を第１容量素子１３１に保持するか否かを切り替える。一方、第２サンプリングトランジスタ１３４は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第２サンプリング信号ＳＤに従って、第１ソースフォロワ回路１２０ａで増幅された画素信号を第２容量素子１３２に保持するか否かを切り替える。各サンプリングトランジスタのドレインは、第１ソースフォロワ回路１２０ａの出力端子に共通に接続されている。 The first sampling transistor 133 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitance element 131 according to the first sampling signal SR input to its gate from the vertical drive unit 20 through the pixel drive line 80. Meanwhile, the second sampling transistor 134 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the second capacitance element 132 according to the second sampling signal SD input to its gate from the vertical drive unit 20 through the pixel drive line 80. The drains of the sampling transistors are commonly connected to the output terminal of the first source follower circuit 120a.
　第２ソースフォロワ回路１４０ａは、第２アンプトランジスタ１４１と、第２選択トランジスタ１４２と、電流源１４３と、を有する。第２ソースフォロワ回路１４０ａでは、これらの回路素子が、第１容量素子１３１および第２容量素子１３２にそれぞれ接続されて一対となっている。 The second source follower circuit 140a has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. In the second source follower circuit 140a, these circuit elements are connected to the first capacitance element 131 and the second capacitance element 132, respectively, to form a pair.
　上記のように構成された画素１１ａでは、例えば、光電変換回路１１０ａおよび第１ソースフォロワ回路１２０ａの第１アンプトランジスタ１２１が、センサチップ２０１に配置されている。また、第１ソースフォロワ回路１２０ａのバイアスカットトランジスタ１２３、信号保持選択回路１３０ａおよび第２ソースフォロワ回路１４０ａがロジックチップ２０２に配置されている。ただし、センサチップ２０１およびセンサチップ２０１における画素１１ａの配置構成は、上記の配置構成に限定されない。 In the pixel 11a configured as described above, for example, the photoelectric conversion circuit 110a and the first amplifier transistor 121 of the first source follower circuit 120a are arranged on the sensor chip 201. Also, the bias cut transistor 123 of the first source follower circuit 120a, the signal hold selection circuit 130a, and the second source follower circuit 140a are arranged on the logic chip 202. However, the arrangement of the sensor chip 201 and the pixels 11a in the sensor chip 201 is not limited to the arrangement described above.
　本変形例においても、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ａの熱雑音の増大を抑制することができる。したがって、本変形例においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In this modification, as in the first embodiment described above, an insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120a even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
　（第２変形例）
　図１３は、第２変形例に係る画素の回路構成を示す図である。なお、図１３でも、上述した第１実施形態に係る画素１１と同様の回路素子には、同じ符号を付す。図１３に示す画素１１ｂは、光電変換回路１１０ｂと、第１ソースフォロワ回路１２０ｂと、信号保持選択回路１３０ｂと、第２ソースフォロワ回路１４０ｂと、を有する。 (Second Modification)
Fig. 13 is a diagram showing a circuit configuration of a pixel according to a second modified example. In Fig. 13, the same circuit elements as those of the pixel 11 according to the first embodiment described above are denoted by the same reference numerals. The pixel 11b shown in Fig. 13 has a photoelectric conversion circuit 110b, a first source follower circuit 120b, a signal holding selection circuit 130b, and a second source follower circuit 140b.
　光電変換回路１１０ｂは、フォトダイオード１１１、転送トランジスタ１１２、および第１リセットトランジスタ１１３を有する。これらの回路素子については、第１実施形態で説明しているため、詳細な説明を省略する。 The photoelectric conversion circuit 110b has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
　第１ソースフォロワ回路１２０ｂは、第１アンプトランジスタ１２１およびバイアスカットトランジスタ１２３を有する。これらの回路素子についても、第１実施形態で説明しているため、詳細な説明を省略する。 The first source follower circuit 120b has a first amplifier transistor 121 and a bias cut transistor 123. These circuit elements are also described in the first embodiment, so detailed description will be omitted.
　信号保持選択回路１３０ｂは、第１容量素子１３１、第２容量素子１３２、第１サンプリングトランジスタ１３３、および第２サンプリングトランジスタ１３４を有する。信号保持選択回路１３０ｂでは、第１容量素子１３１の一端は、電源電圧ＶＤＤの電位を有する電源線に接続されている。第１容量素子１３１の他端は、第１サンプリングトランジスタ１３３のソースと第２容量素子１３２の一端に接続されている。第２容量素子１３２の他端は、出力ノード１３６に接続されている。 The signal holding selection circuit 130b has a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, and a second sampling transistor 134. In the signal holding selection circuit 130b, one end of the first capacitance element 131 is connected to a power supply line having a potential of the power supply voltage VDD. The other end of the first capacitance element 131 is connected to the source of the first sampling transistor 133 and one end of the second capacitance element 132. The other end of the second capacitance element 132 is connected to the output node 136.
　第１サンプリングトランジスタ１３３は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第１サンプリング信号ＳＲに従って、第１ソースフォロワ回路１２０ａで増幅された画素信号を第１容量素子１３１および第２容量素子１３２に保持するか否かを切り替える。第１サンプリングトランジスタ１３３のドレインは、第１ソースフォロワ回路１２０ａの出力端子に共通に接続されている。 The first sampling transistor 133 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitance element 131 and the second capacitance element 132 according to the first sampling signal SR input to the gate from the vertical drive unit 20 through the pixel drive line 80. The drain of the first sampling transistor 133 is commonly connected to the output terminal of the first source follower circuit 120a.
　第２サンプリングトランジスタ１３４は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第２サンプリング信号ＳＤに従って、出力ノード１３６の電位をリセットする。第２サンプリングトランジスタ１３４のドレインは、上記電源線に接続され、ソースは、出力ノード１３６に接続されている。 The second sampling transistor 134 resets the potential of the output node 136 according to the second sampling signal SD input to the gate from the vertical drive unit 20 through the pixel drive line 80. The drain of the second sampling transistor 134 is connected to the power supply line, and the source is connected to the output node 136.
　第２ソースフォロワ回路１４０ｂは、第２アンプトランジスタ１４１と、第２選択トランジスタ１４２と、電流源１４３と、を有する。これらの回路素子については、第１実施形態で説明しているため、詳細な説明を省略する。 The second source follower circuit 140b has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
　上記のように構成された画素１１ｂでは、例えば、光電変換回路１１０ｂおよび第１ソースフォロワ回路１２０ｂの第１アンプトランジスタ１２１が、センサチップ２０１に配置されている。また、第１ソースフォロワ回路１２０ｂのバイアスカットトランジスタ１２３、信号保持選択回路１３０ｂおよび第２ソースフォロワ回路１４０ｂがロジックチップ２０２に配置されている。ただし、センサチップ２０１およびセンサチップ２０１における画素１１ｂの配置構成は、上記の配置構成に限定されない。 In the pixel 11b configured as described above, for example, the photoelectric conversion circuit 110b and the first amplifier transistor 121 of the first source follower circuit 120b are arranged on the sensor chip 201. Also, the bias cut transistor 123, signal hold selection circuit 130b, and second source follower circuit 140b of the first source follower circuit 120b are arranged on the logic chip 202. However, the arrangement of the sensor chip 201 and the pixel 11b in the sensor chip 201 is not limited to the arrangement described above.
　本変形例においても、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ｂの熱雑音の増大を抑制することができる。したがって、本変形例においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In this modification, as in the first embodiment described above, an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120b even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
　（第３変形例）
　図１４は、第３変形例に係る画素の回路構成を示す図である。なお、図１４でも、上述した第１実施形態に係る画素１１と同様の回路素子には、同じ符号を付す。図１４に示す画素１１ｃは、光電変換回路１１０ｃと、第１ソースフォロワ回路１２０ｃと、信号保持選択回路１３０ｃと、第２ソースフォロワ回路１４０ｃと、を有する。 (Third Modification)
Fig. 14 is a diagram showing a circuit configuration of a pixel according to a third modified example. In Fig. 14, the same circuit elements as those of the pixel 11 according to the first embodiment described above are denoted by the same reference numerals. The pixel 11c shown in Fig. 14 has a photoelectric conversion circuit 110c, a first source follower circuit 120c, a signal holding selection circuit 130c, and a second source follower circuit 140c.
　光電変換回路１１０ｃは、フォトダイオード１１１、転送トランジスタ１１２、および第１リセットトランジスタ１１３を有する。これらの回路素子については、第１実施形態で説明しているため、詳細な説明を省略する。 The photoelectric conversion circuit 110c has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
　第１ソースフォロワ回路１２０ｃは、第１アンプトランジスタ１２１、バイアスカットトランジスタ１２３、および負荷トランジスタ１２４を有する。これらの回路素子についても、第１実施形態で説明しているため、詳細な説明を省略する。 The first source follower circuit 120c has a first amplifier transistor 121, a bias cut transistor 123, and a load transistor 124. These circuit elements are also described in the first embodiment, so detailed description will be omitted.
　信号保持選択回路１３０ｃは、第１容量素子１３１、第２容量素子１３２、第１サンプリングトランジスタ１３３、第２サンプリングトランジスタ１３４、および切替トランジスタ１３７を有する。信号保持選択回路１３０ｃでは、第１容量素子１３１および第２容量素子１３２のそれぞれの一端は、電源電圧ＶＤＤの電位を有する電源線に接続されている。第１容量素子１３１の他端は、第１サンプリングトランジスタ１３３のドレインに接続されている。第２容量素子１３２の他端は、第２サンプリングトランジスタ１３４のドレインに接続されている。 The signal holding selection circuit 130c has a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, a second sampling transistor 134, and a switching transistor 137. In the signal holding selection circuit 130c, one end of each of the first capacitance element 131 and the second capacitance element 132 is connected to a power supply line having a potential of the power supply voltage VDD. The other end of the first capacitance element 131 is connected to the drain of the first sampling transistor 133. The other end of the second capacitance element 132 is connected to the drain of the second sampling transistor 134.
　第１サンプリングトランジスタ１３３は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第１サンプリング信号ＳＲに従って、第１容量素子１３１に保持された画素信号を第２ソースフォロワ回路１４０ｃに出力するか否かを切り替える。第１サンプリングトランジスタ１３３のソースは、切替トランジスタ１３７のソースおよび出力ノード１３６に接続されている。 The first sampling transistor 133 switches whether or not to output the pixel signal held in the first capacitance element 131 to the second source follower circuit 140c according to the first sampling signal SR input to the gate from the vertical drive unit 20 through the pixel drive line 80. The source of the first sampling transistor 133 is connected to the source of the switching transistor 137 and the output node 136.
　第２サンプリングトランジスタ１３４は、垂直駆動部２０から画素駆動線８０を通じてゲートに入力された第２サンプリング信号ＳＤに従って、第２容量素子１３２に保持された画素信号を第２ソースフォロワ回路１４０ｃに出力するか否かを切り替える。第２サンプリングトランジスタ１３４のソースは、切替トランジスタ１３７のソースおよび出力ノード１３６に接続されている。 The second sampling transistor 134 switches whether or not to output the pixel signal held in the second capacitance element 132 to the second source follower circuit 140c according to the second sampling signal SD input to the gate from the vertical drive unit 20 through the pixel drive line 80. The source of the second sampling transistor 134 is connected to the source of the switching transistor 137 and the output node 136.
　切替トランジスタ１３７は、Ｎチャネル型のＭＯＳトランジスタで構成されている。切替トランジスタ１３７のゲートには、垂直駆動部２０から画素駆動線８０を通じて切替信号ＳＨが入力される。切替トランジスタ１３７が、切替信号ＳＨに基づいてオンすると、第１ソースフォロワ回路１２０ｃで増幅された信号が、第１容量素子１３１または第２容量素子１３２に保持される。 The switching transistor 137 is composed of an N-channel MOS transistor. A switching signal SH is input to the gate of the switching transistor 137 from the vertical drive unit 20 through the pixel drive line 80. When the switching transistor 137 is turned on based on the switching signal SH, the signal amplified by the first source follower circuit 120c is held in the first capacitance element 131 or the second capacitance element 132.
　第２ソースフォロワ回路１４０ｃは、第２アンプトランジスタ１４１と、第２選択トランジスタ１４２と、電流源１４３と、を有する。これらの回路素子については、第１実施形態で説明しているため、詳細な説明を省略する。 The second source follower circuit 140c has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. These circuit elements have been described in the first embodiment, so detailed description will be omitted.
　上記のように構成された画素１１ｃでは、例えば、光電変換回路１１０ｃおよび第１ソースフォロワ回路１２０ｃの第１アンプトランジスタ１２１が、センサチップ２０１に配置されている。また、第１ソースフォロワ回路１２０ｃのバイアスカットトランジスタ１２３および負荷トランジスタ１２４、信号保持選択回路１３０ｂ、並びに第２ソースフォロワ回路１４０ｂがロジックチップ２０２に配置されている。ただし、センサチップ２０１およびセンサチップ２０１における画素１１ｃの配置構成は、上記の配置構成に限定されない。 In the pixel 11c configured as described above, for example, the photoelectric conversion circuit 110c and the first amplifier transistor 121 of the first source follower circuit 120c are arranged on the sensor chip 201. Also, the bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120c, the signal hold selection circuit 130b, and the second source follower circuit 140b are arranged on the logic chip 202. However, the arrangement of the sensor chip 201 and the pixel 11c in the sensor chip 201 is not limited to the arrangement described above.
　本変形例においても、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ｃの熱雑音の増大を抑制することができる。したがって、本変形例においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In this modification, as in the first embodiment described above, an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
　（第４変形例）
　図１５は、第４変形例に係る画素の回路構成を示す図である。なお、図１５では、上述した第１実施形態に係る画素１１と同様の回路素子には、同じ符号を付す。図１５に示す画素１１ｄは、光電変換回路１１０ｄと、第１ソースフォロワ回路１２０ｄと、信号保持選択回路１３０ｄと、第２ソースフォロワ回路１４０ｄと、を有する。 (Fourth Modification)
Fig. 15 is a diagram showing a circuit configuration of a pixel according to a fourth modified example. In Fig. 15, the same circuit elements as those of the pixel 11 according to the first embodiment described above are denoted by the same reference numerals. The pixel 11d shown in Fig. 15 has a photoelectric conversion circuit 110d, a first source follower circuit 120d, a signal holding selection circuit 130d, and a second source follower circuit 140d.
　光電変換回路１１０ｄは、フォトダイオード１１１、転送トランジスタ１１２、第１リセットトランジスタ１１３、切替トランジスタ１１６、および容量素子１１７を有する。切替トランジスタ１１６は、Ｎチャネル型のＭＯＳトランジスタで構成され、第１リセットトランジスタ１１３と、ＦＤとの間に配置されている。容量素子１１７の一端は、切替トランジスタ１１６のドレインに接続され、他端は接地されている。切替トランジスタ１１６のゲートには、垂直駆動部２０から駆動信号ＦＤＧが入力される。切替トランジスタ１１６が、駆動信号ＦＤＧに基づいてオン状態になると、容量素子１１７に保持された電荷がＦＤに転送される。 The photoelectric conversion circuit 110d has a photodiode 111, a transfer transistor 112, a first reset transistor 113, a switching transistor 116, and a capacitance element 117. The switching transistor 116 is configured as an N-channel MOS transistor and is disposed between the first reset transistor 113 and the FD. One end of the capacitance element 117 is connected to the drain of the switching transistor 116, and the other end is grounded. A drive signal FDG is input from the vertical drive unit 20 to the gate of the switching transistor 116. When the switching transistor 116 is turned on based on the drive signal FDG, the charge held in the capacitance element 117 is transferred to the FD.
　第１ソースフォロワ回路１２０ｄ、信号保持選択回路１３０ｄ、および第２ソースフォロワ回路１４０ｄの回路構成は、第１実施形態と同様であるため、説明を省略する。ただし、本変形例では、信号保持選択回路１３０ｄの第２リセットトランジスタ１３５と、第２ソースフォロワ回路１４０ｄとは、４つの画素１１ｄで共有されている。 The circuit configurations of the first source follower circuit 120d, the signal holding selection circuit 130d, and the second source follower circuit 140d are the same as those in the first embodiment, and therefore will not be described. However, in this modified example, the second reset transistor 135 of the signal holding selection circuit 130d and the second source follower circuit 140d are shared by four pixels 11d.
　図１６は、第４変形例に係るセンサチップ２０１のレイアウトの一例を示す平面図である。また、図１７は、図１６に示す切断線Ｂ－Ｂに沿った断面図である。 FIG. 16 is a plan view showing an example of the layout of a sensor chip 201 according to the fourth modified example. Also, FIG. 17 is a cross-sectional view taken along the cutting line B-B shown in FIG. 16.
　本変形例では、センサチップ２０１には、画素１１ｄのうち、光電変換回路１１０ｄおよび第１ソースフォロワ回路１２０ｄの第１アンプトランジスタ１２１および第１選択トランジスタ１２２が、配置されている。画素１１ｄの残りの回路素子は、ロジックチップ２０２に配置されている。第１ソースフォロワ回路１２０ｄにおいて、センサチップ２０１に配置された第１選択トランジスタ１２２は、例えば、センサチップ２０１を貫通する配線、またはセンサチップ２０１の上面に設けられたパッドを介して、ロジックチップ２０２に配置されたバイアスカットトランジスタ１２３と電気的に接続される。 In this modified example, the first amplifier transistor 121 and the first selection transistor 122 of the photoelectric conversion circuit 110d and the first source follower circuit 120d of the pixel 11d are arranged on the sensor chip 201. The remaining circuit elements of the pixel 11d are arranged on the logic chip 202. In the first source follower circuit 120d, the first selection transistor 122 arranged on the sensor chip 201 is electrically connected to the bias cut transistor 123 arranged on the logic chip 202, for example, via a wiring that passes through the sensor chip 201 or a pad provided on the upper surface of the sensor chip 201.
　また、本変形例では、図１６に示すようにセンサチップ２０１に配置された複数の画素１１ｄは、分離膜２２０によって、分離されている。分離膜２２０は、例えば、半導体基板２１０を貫通するトレンチ内に形成されるＦＦＴＩ（Front Full Trench Isolation）型の分離膜である。分離膜２２０内には、例えば酸化シリコンから成る側壁膜が形成され、その側壁膜の内側には、ポリシリコンから成る充填剤が埋め込まれている。なお、ＦＦＴＩ内の充填剤はポリシリコンに限定されない。例えば、ＦＦＴＩ内には、酸化膜などの絶縁膜を単層または多層で形成してもよい。また、ＦＦＴＩ内には、絶縁膜だけでなく、金属材料、ポリシリコンなどの導電材を少なくとも１種形成してもよい。 In addition, in this modified example, as shown in FIG. 16, a plurality of pixels 11d arranged on the sensor chip 201 are separated by an isolation film 220. The isolation film 220 is, for example, a front full trench isolation (FFTI) type isolation film formed in a trench penetrating the semiconductor substrate 210. A sidewall film made of, for example, silicon oxide is formed in the isolation film 220, and a filler made of polysilicon is embedded inside the sidewall film. Note that the filler in the FFTI is not limited to polysilicon. For example, an insulating film such as an oxide film may be formed in a single layer or multiple layers in the FFTI. In addition to an insulating film, at least one type of conductive material such as a metal material or polysilicon may be formed in the FFTI.
　また、図１７に示すように、第１アンプトランジスタ１２１では、ソース領域１２１ｅに接する絶縁膜１１５ａの直下に分離膜２２０が形成されている一方で、ドレイン領域１２１ｄに接する絶縁膜１１５ｂの直下には分離膜２００は形成されていない。さらに、半導体基板２１０の表面からの絶縁膜１１５ｂの厚さは、絶縁膜１１５ａよりも厚い。 Also, as shown in FIG. 17, in the first amplifier transistor 121, an isolation film 220 is formed directly below the insulating film 115a in contact with the source region 121e, while an isolation film 200 is not formed directly below the insulating film 115b in contact with the drain region 121d. Furthermore, the thickness of the insulating film 115b from the surface of the semiconductor substrate 210 is thicker than that of the insulating film 115a.
　図１８は、図１６に示すレイアウトにおいて、転送トランジスタ１１２および第１選択トランジスタ１２２周辺の断面図である。図１８に示す分離膜２２０も、半導体基板２１０を貫通して形成されている。分離膜２２０の裏面側（図面下側）には、隣接画素への光の漏れ出しを抑止する遮光膜２２１が形成されている。遮光膜２２１は、例えば、タングステン等の金属材から成る。半導体基板２１０の裏面側には、入射光をフォトダイオード１１１に集光させるＯＣＬ（オンチップレンズ）２２２が形成されている。 FIG. 18 is a cross-sectional view of the transfer transistor 112 and the first selection transistor 122 in the layout shown in FIG. 16. The isolation film 220 shown in FIG. 18 is also formed penetrating the semiconductor substrate 210. A light-shielding film 221 that prevents light from leaking to adjacent pixels is formed on the back side (lower side of the drawing) of the isolation film 220. The light-shielding film 221 is made of a metal material such as tungsten. An OCL (on-chip lens) 222 that focuses incident light on the photodiode 111 is formed on the back side of the semiconductor substrate 210.
　半導体基板２１０の表面側（図面上側）には、トレンチ２２３が開口している。トレンチ２２３には、転送トランジスタ１１２が設けられている。また、半導体基板２１０の上部には、アクティブ領域（Ｐｗｅｌｌ）２２４が形成されている。アクティブ領域２２４内には、素子分離領域２２５が形成されている。なお、転送トランジスタ１１２は、トレンチ２２３内にゲートが形成される掘り込み形状であってもよいし、半導体基板２１０上にゲートが形成されるプレーナ型であってもよい。 A trench 223 is opened on the surface side (upper side of the drawing) of the semiconductor substrate 210. A transfer transistor 112 is provided in the trench 223. An active region (Pwell) 224 is formed in the upper part of the semiconductor substrate 210. An element isolation region 225 is formed in the active region 224. The transfer transistor 112 may be of a recessed type in which the gate is formed in the trench 223, or may be of a planar type in which the gate is formed on the semiconductor substrate 210.
　フォトダイオード１１１と分離膜２２０との間には、分離膜２２０側からフォトダイオード１１１に向かって順にP型固相拡散層２２６とN型固相拡散層２２７が形成されている。フォトダイオード１１１は、N型領域で構成されている。光電変換は、これらN型領域の一部、または全てにおいて行われる。 Between the photodiode 111 and the isolation film 220, a P-type solid-phase diffusion layer 226 and an N-type solid-phase diffusion layer 227 are formed in this order from the isolation film 220 side toward the photodiode 111. The photodiode 111 is composed of N-type regions. Photoelectric conversion takes place in some or all of these N-type regions.
　さらに、分離膜２２０の内壁には、側壁膜２２８が形成されている。側壁膜２２８の内側には、充填材２２９が埋め込まれている。側壁膜２２８には、例えば、酸化シリコンまたは窒化シリコンを用いることができる。一方、充填材２２９には、例えば、ポリシリコンまたはドーピングポリシリコンを用いることができる。なお、充填材２２９は、これらのポリシリコンに限定されない。 Furthermore, a sidewall film 228 is formed on the inner wall of the separation film 220. A filler material 229 is embedded inside the sidewall film 228. For example, silicon oxide or silicon nitride may be used for the sidewall film 228. On the other hand, for example, polysilicon or doped polysilicon may be used for the filler material 229. Note that the filler material 229 is not limited to these polysilicon materials.
　P型固相拡散層２２６は、裏面シリコン界面２４０に接するまで形成されている。一方、N型固相拡散層２２７は、裏面シリコン界面２４０に接していない。その結果、N型固相拡散層２２７と裏面シリコン界面２４０との間には、間隔が設けられている。 The P-type solid-phase diffusion layer 226 is formed up to the rear surface silicon interface 240. On the other hand, the N-type solid-phase diffusion layer 227 does not contact the rear surface silicon interface 240. As a result, a gap is provided between the N-type solid-phase diffusion layer 227 and the rear surface silicon interface 240.
　フォトダイオード１１１およびN型固相拡散層２２７と、裏面シリコン界面２４０との間、すなわち、半導体基板２１０においてフォトダイオード１１１等が形成されていない領域には、P型領域２４１が設けられている。これにより、フォトダイオード１１１およびN型固相拡散層２２７が、裏面シリコン界面２４０付近に存在しないことになる。その結果、裏面シリコン界面２４０付近におけるピニングの弱体化が生じないので、発生した電荷がフォトダイオード１１１に流れ込んでＤａｒｋ特性が悪化してしまう事態の発生を抑止することができる。なお、充填材２２９としてドーピングポリシリコンを充填した場合、または、ポリシリコンを充填した後にN型不純物またはP型不純物をドーピングした場合には、そこに負バイアスを印加すれば、分離膜２２０の側壁のピニングを強化することができるので、Ｄａｒｋ特性をさらに改善することができる。 A P-type region 241 is provided between the photodiode 111 and the N-type solid-phase diffusion layer 227 and the back silicon interface 240, i.e., in the region of the semiconductor substrate 210 where the photodiode 111 and the like are not formed. This means that the photodiode 111 and the N-type solid-phase diffusion layer 227 are not present near the back silicon interface 240. As a result, the pinning near the back silicon interface 240 is not weakened, so that it is possible to prevent the occurrence of a situation in which the generated charge flows into the photodiode 111 and the dark characteristics deteriorate. Note that if doped polysilicon is filled as the filling material 229, or if N-type or P-type impurities are doped after filling polysilicon, applying a negative bias thereto can strengthen the pinning of the sidewall of the isolation film 220, thereby further improving the dark characteristics.
　上記のように構成された画素１１ｄでも、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ｃの熱雑音の増大を抑制することができる。したがって、本変形例においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。特に本変形例では、分離膜２２０の接していない絶縁膜１１５ｂの厚さを分離膜２２０に接している絶縁膜１１５ａの厚さよりも厚くすることによって、低濃度のチャネル領域２１２ａの領域を十分に確保することができる。 In the pixel 11d configured as above, as in the first embodiment described above, the insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. As a result, even if the first amplifier transistor 121 is driven with a low current, the increase in thermal noise of the first source follower circuit 120c can be suppressed. Therefore, in this modified example, it is possible to reduce random noise while suppressing power consumption. In particular, in this modified example, the thickness of the insulating film 115b not in contact with the isolation film 220 is made thicker than the thickness of the insulating film 115a in contact with the isolation film 220, so that the area of the low-concentration channel region 212a can be sufficiently secured.
　なお、本変形例では、第１アンプトランジスタ１２１には、第２実施形態で説明したように、ＳｉＧｅ（シリコンゲルマニウム）層２１５がチャネル領域２１２ａの直下に形成されていてもよい。この場合、ランダムノイズをより一層低減することが可能となる。また、第１アンプトランジスタ１２１には、第３実施形態で説明したＦｉｎ型ＭＯＳトランジスタを適用してもよい。 In this modification, the first amplifier transistor 121 may have a SiGe (silicon germanium) layer 215 formed directly under the channel region 212a, as described in the second embodiment. In this case, it is possible to further reduce random noise. Also, the first amplifier transistor 121 may be a Fin-type MOS transistor as described in the third embodiment.
　図１９は、第４変形例に係る第１アンプトランジスタ１２１にＦｉｎ型ＭＯＳトランジスタを適用した断面図である。第１アンプトランジスタ１２１にＦｉｎ型ＭＯＳトランジスタを適用する場合、分離膜２２０に接する絶縁膜１１５ａの厚さは、分離膜２２０に接しない絶縁膜１１５ｂの厚さと等しい。 FIG. 19 is a cross-sectional view of the fourth modified example in which a Fin-type MOS transistor is applied to the first amplifier transistor 121. When a Fin-type MOS transistor is applied to the first amplifier transistor 121, the thickness of the insulating film 115a in contact with the isolation film 220 is equal to the thickness of the insulating film 115b that is not in contact with the isolation film 220.
　（第５変形例）
　図２０は、第５変形例に係るセンサチップ２０１のレイアウトの一例を示す平面図である。本変形例に係るセンサチップ２０１のサイズは、第４変形例と同じである。また、センサチップ２０１およびロジックチップ２０２にそれぞれ配置される画素１１ｅの回路構成も第４変形例と同じである。 (Fifth Modification)
20 is a plan view showing an example of the layout of a sensor chip 201 according to the fifth modification. The size of the sensor chip 201 according to this modification is the same as that of the fourth modification. In addition, the circuit configurations of the pixels 11e arranged on the sensor chip 201 and the logic chip 202 are also the same as those of the fourth modification.
　その一方で、本変形例では、センサチップ２０１に配置された複数の画素１１ｅが、分離層２３０によって、分離されている。また、各画素１１ｅの回路素子も、分離層２３０によって、分離されている。分離層２３０は、例えば、半導体基板２１０にＰ型の不純物を注入することによって、形成される。そのため、分離層２３０は、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅにそれぞれ接する絶縁膜１１５の下には設けられていない。 On the other hand, in this modified example, the multiple pixels 11e arranged on the sensor chip 201 are separated by an isolation layer 230. The circuit elements of each pixel 11e are also separated by the isolation layer 230. The isolation layer 230 is formed, for example, by injecting P-type impurities into the semiconductor substrate 210. Therefore, the isolation layer 230 is not provided under the insulating film 115 that contacts the drain region 121d and the source region 121e of the first amplifier transistor 121.
　本変形例においても、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ｃの熱雑音の増大を抑制することができる。したがって、本変形例においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In this modification, as in the first embodiment described above, an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
　（第６変形例）
　図２１は、第６変形例に係る画素の回路構成を示す図である。なお、図２１では、上述した第１実施形態に係る画素１１と同様の回路素子には、同じ符号を付す。図２１に示す画素１１ｆは、光電変換回路１１０ｆと、第１ソースフォロワ回路１２０ｆと、信号保持選択回路１３０ｆと、第２ソースフォロワ回路１４０ｆと、を有する。 (Sixth Modification)
Fig. 21 is a diagram showing a circuit configuration of a pixel according to a sixth modified example. In Fig. 21, the same circuit elements as those of the pixel 11 according to the first embodiment described above are denoted by the same reference numerals. The pixel 11f shown in Fig. 21 has a photoelectric conversion circuit 110f, a first source follower circuit 120f, a signal holding selection circuit 130f, and a second source follower circuit 140f.
　光電変換回路１１０ｆは、フォトダイオード１１１、転送トランジスタ１１２、第１リセットトランジスタ１１３、排出トランジスタ１１４、切替トランジスタ１１６、および容量素子１１７を有する。すなわち、本変形例に係る光電変換回路１１０ｆは、第４変形例に係る光電変換回路１１０ｄの回路素子に加えて、排出トランジスタ１１４を有する構成である。排出トランジスタ１１４については、第１実施形態と同様であるため、説明を省略する。 The photoelectric conversion circuit 110f has a photodiode 111, a transfer transistor 112, a first reset transistor 113, a discharge transistor 114, a switching transistor 116, and a capacitance element 117. That is, the photoelectric conversion circuit 110f according to this modification has a discharge transistor 114 in addition to the circuit elements of the photoelectric conversion circuit 110d according to the fourth modification. The discharge transistor 114 is the same as in the first embodiment, so a description thereof will be omitted.
　また、第１ソースフォロワ回路１２０ｆ、信号保持選択回路１３０ｆ、および第２ソースフォロワ回路１４０ｆの回路構成も、第１実施形態と同様であるため、説明を省略する。ただし、本変形例では、信号保持選択回路１３０ｆの第２リセットトランジスタ１３５と、第２ソースフォロワ回路１４０ｆとは、第４変形例および第５変形例と同様に４つの画素１１ｄで共有されている。 The circuit configurations of the first source follower circuit 120f, the signal holding selection circuit 130f, and the second source follower circuit 140f are also similar to those in the first embodiment, and therefore will not be described. However, in this modification, the second reset transistor 135 of the signal holding selection circuit 130f and the second source follower circuit 140f are shared by four pixels 11d, as in the fourth and fifth modifications.
　図２２は、第６変形例に係るセンサチップ２０１のレイアウトの一例を示す平面図である。本変形例に係るセンサチップ２０１のサイズは、第４変形例に係るセンサチップ２０１のサイズよりも大きい。その一方で、センサチップ２０１およびロジックチップ２０２にそれぞれ配置される画素１１ｅの回路構成も第４変形例と同様である。なお、排出トランジスタ１１４は、センサチップ２０１に配置されている。 FIG. 22 is a plan view showing an example of the layout of the sensor chip 201 according to the sixth modified example. The size of the sensor chip 201 according to this modified example is larger than the size of the sensor chip 201 according to the fourth modified example. On the other hand, the circuit configuration of the pixels 11e arranged on the sensor chip 201 and the logic chip 202 is also similar to that of the fourth modified example. The emission transistor 114 is arranged on the sensor chip 201.
　また、本変形例では、第４変形例と同様に、センサチップ２０１に配置された複数の画素１１ｆは、分離膜２２０によって、分離されている。そのため、第１アンプトランジスタ１２１では、ソース領域１２１ｅに接する絶縁膜１１５ａの直下に分離膜２２０が形成されている一方で、ドレイン領域１２１ｄに接する絶縁膜１１５ｂの直下には分離膜２００は形成されていない。さらに、半導体基板２１０の表面からの絶縁膜１１５ｂの厚さは、絶縁膜１１５ａよりも厚い。 In addition, in this modification, similar to the fourth modification, the multiple pixels 11f arranged on the sensor chip 201 are separated by an isolation film 220. Therefore, in the first amplifier transistor 121, the isolation film 220 is formed directly below the insulating film 115a in contact with the source region 121e, while the isolation film 200 is not formed directly below the insulating film 115b in contact with the drain region 121d. Furthermore, the thickness of the insulating film 115b from the surface of the semiconductor substrate 210 is thicker than that of the insulating film 115a.
　上記のように構成された画素１１ｆでも、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ｃの熱雑音の増大を抑制することができる。したがって、本変形例においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In the pixel 11f configured as above, as in the first embodiment described above, the insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modified example as well, it is possible to reduce random noise while suppressing power consumption.
　また、本変形例では、上述した第４変形例と同様に、分離膜２２０の接していない絶縁膜１１５ｂの厚さを分離膜２２０に接している絶縁膜１１５ａの厚さよりも厚くすることによって、低濃度のチャネル領域２１２ａの領域を十分に確保することができる。なお、本変形例では、第１アンプトランジスタ１２１には、第２実施形態で説明したように、ＳｉＧｅ（シリコンゲルマニウム）層２１５がチャネル領域２１２ａの直下に形成されていてもよい。この場合、ランダムノイズをより一層低減することが可能となる。さらに、第１アンプトランジスタ１２１は、第２実施形態で説明したＳｉＧｅ（シリコンゲルマニウム）層２１５を有する構造であってもよいし、第３実施形態で説明したＦｉｎ型ＭＯＳトランジスタの構造であってもよい。 In addition, in this modification, as in the fourth modification described above, the thickness of the insulating film 115b not in contact with the isolation film 220 is made thicker than the thickness of the insulating film 115a in contact with the isolation film 220, so that the low concentration channel region 212a can be sufficiently secured. In this modification, the first amplifier transistor 121 may have a SiGe (silicon germanium) layer 215 formed directly under the channel region 212a as described in the second embodiment. In this case, it is possible to further reduce random noise. Furthermore, the first amplifier transistor 121 may have a structure having the SiGe (silicon germanium) layer 215 described in the second embodiment, or may have a structure of a Fin-type MOS transistor described in the third embodiment.
　（第７変形例）
　図２３は、第７変形例に係るセンサチップ２０１のレイアウトの一例を示す平面図である。本変形例に係るセンサチップ２０１のサイズは、第６変形例と同じである。また、センサチップ２０１およびロジックチップ２０２にそれぞれ配置される画素１１ｆの回路構成も第６変形例と同じである。 (Seventh Modification)
23 is a plan view showing an example of the layout of the sensor chip 201 according to the seventh modification. The size of the sensor chip 201 according to this modification is the same as that of the sixth modification. In addition, the circuit configurations of the pixels 11f arranged on the sensor chip 201 and the logic chip 202 are also the same as those of the sixth modification.
　その一方で、本変形例では、センサチップ２０１に配置された複数の画素１１ｆが、上述した第５変形例と同様に、分離層２３０によって、分離されている。また、各画素１１ｆの回路素子も、分離層２３０によって、分離されている。 On the other hand, in this modification, the multiple pixels 11f arranged on the sensor chip 201 are separated by the separation layer 230, as in the fifth modification described above. In addition, the circuit elements of each pixel 11f are also separated by the separation layer 230.
　本変形例においても、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ｃの熱雑音の増大を抑制することができる。したがって、本変形例においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In this modification, as in the first embodiment described above, an insulating film 115 is formed directly under the drain region 121d and source region 121e of the first amplifier transistor 121. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. This makes it possible to suppress an increase in thermal noise of the first source follower circuit 120c even when the first amplifier transistor 121 is driven with a low current. Therefore, in this modification as well, it is possible to reduce random noise while suppressing power consumption.
　（第４実施形態）
　図２４は、第４実施形態に係るＣＭＯＳイメージセンサの構成を示す図である。上述した第１実施形態と同様の構成要素には、同じ符号を付し、詳細な説明を省略する。本実施形態に係るＣＭＯＳイメージセンサ４は、第１チップ４０１、第２チップ４０２、および第３チップ４０３を備える。第１チップ４０１、第２チップ４０２、および第３チップ４０３は、積層されている。 Fourth Embodiment
24 is a diagram showing the configuration of a CMOS image sensor according to the fourth embodiment. The same components as those in the above-described first embodiment are given the same reference numerals, and detailed description thereof will be omitted. The CMOS image sensor 4 according to this embodiment includes a first chip 401, a second chip 402, and a third chip 403. The first chip 401, the second chip 402, and the third chip 403 are stacked.
　第１チップ４０１には、第１画素アレイ部４０１ａが設けられている。第１画素アレイ部４０１ａには、複数のセンサ画素４０１ｂが行列状に２次元配置されている。センサ画素４０１ｂには、光電変換回路１１０のフォトダイオード１１１、転送トランジスタ１１２、ＦＤ、第１リセットトランジスタ１１３、および排出トランジスタ１１４が配置されている。加えて、センサ画素４０１ｂには、第１ソースフォロワ回路１２０の第１アンプトランジスタ１２１および第１選択トランジスタ１２２も配置されている。 The first chip 401 is provided with a first pixel array section 401a. In the first pixel array section 401a, a plurality of sensor pixels 401b are arranged two-dimensionally in a matrix. In the sensor pixel 401b, the photodiode 111, the transfer transistor 112, the FD, the first reset transistor 113, and the discharge transistor 114 of the photoelectric conversion circuit 110 are arranged. In addition, in the sensor pixel 401b, the first amplifier transistor 121 and the first selection transistor 122 of the first source follower circuit 120 are also arranged.
　第２チップ４０２には、第２画素アレイ部４０２ａが設けられている。第２画素アレイ部４０２ａには、第１ソースフォロワ回路１２０のバイアスカットトランジスタ１２３および負荷トランジスタ１２４が配置されている。加えて、第２画素アレイ部４０２ａには、信号保持選択回路１３０および第２ソースフォロワ回路１４０も配置されている。また、第２画素アレイ部４０２ａでは、画素駆動線８０が行方向に延びるとともに、垂直信号線９０が列方向に延びている。 The second chip 402 is provided with a second pixel array section 402a. The bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120 are arranged in the second pixel array section 402a. In addition, the signal retention selection circuit 130 and the second source follower circuit 140 are also arranged in the second pixel array section 402a. In the second pixel array section 402a, the pixel drive lines 80 extend in the row direction, and the vertical signal lines 90 extend in the column direction.
　第３チップ４０３には、ロジック回路４３１が設けられている。ロジック回路４３１には、垂直駆動部２０、カラム処理部３０、水平駆動部４０、およびシステム制御部５０が配置されている。 The third chip 403 is provided with a logic circuit 431. The logic circuit 431 includes a vertical drive unit 20, a column processing unit 30, a horizontal drive unit 40, and a system control unit 50.
　図２５は、第４実施形態に係るＣＭＯＳイメージセンサ４の一部を垂直方向に切断した断面図である。図２５に示すように、ＣＭＯＳイメージセンサ４では、第１チップ４０１、第２チップ４０２、および第３チップ４０３がこの順番で積層されている。さらに、第１チップ４０１の裏面側（光入射面側）に、カラーフィルタ５００および受光レンズ６００が設けられている。カラーフィルタ５００および受光レンズ６００は、それぞれ、例えば、センサ画素４０１ｂごとに１つずつ設けられている。つまり、ＣＭＯＳイメージセンサ４は、裏面照射型となっている。 FIG. 25 is a vertical cross-sectional view of a portion of the CMOS image sensor 4 according to the fourth embodiment. As shown in FIG. 25, in the CMOS image sensor 4, a first chip 401, a second chip 402, and a third chip 403 are stacked in this order. Furthermore, a color filter 500 and a light receiving lens 600 are provided on the back side (light incident surface side) of the first chip 401. For example, one color filter 500 and one light receiving lens 600 are each provided for each sensor pixel 401b. In other words, the CMOS image sensor 4 is a back-illuminated type.
　第１チップ４０１は、第１半導体基板４１０上に絶縁層４６を積層して構成されている。第１チップ４０１は、層間絶縁膜５１の一部として、絶縁層４６を有している。絶縁層４６は、第１半導体基板４１０と、後述の第２半導体基板４２０との間隙に設けられている。 The first chip 401 is constructed by laminating an insulating layer 46 on a first semiconductor substrate 410. The first chip 401 has the insulating layer 46 as part of an interlayer insulating film 51. The insulating layer 46 is provided in the gap between the first semiconductor substrate 410 and a second semiconductor substrate 420, which will be described later.
　第１半導体基板４１０は、シリコン基板で構成されている。第１半導体基板４１０は、例えば、表面の一部およびその近傍に、ｐウェル層４２を有しており、それ以外の領域（ｐウェル層４２よりも深い領域）に、ｐウェル層４２とは異なる導電型のフォトダイオード１１１を有している。ｐウェル層４２は、ｐ型の半導体領域で構成されている。フォトダイオード１１１は、ｐウェル層４２とは異なる導電型（具体的にはｎ型）の半導体領域で構成されている。第１半導体基板４１０は、ｐウェル層４２内に、ｐウェル層４２とは異なる導電型（具体的にはｎ型）の半導体領域として、ＦＤを有している。 The first semiconductor substrate 410 is made of a silicon substrate. The first semiconductor substrate 410 has a p-well layer 42, for example, in a part of the surface and in its vicinity, and has a photodiode 111 of a different conductivity type from the p-well layer 42 in the other region (region deeper than the p-well layer 42). The p-well layer 42 is made of a p-type semiconductor region. The photodiode 111 is made of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The first semiconductor substrate 410 has an FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.
　第１チップ４０１は、第１半導体基板４１０の表面側（光入射面側とは反対側、第２チップ４０２側）の部分に、転送トランジスタ１１２およびＦＤが設けられた構成となっている。第１チップ４０１は、各センサ画素４０１ｂを分離する素子分離部４３を有している。 The first chip 401 has a configuration in which a transfer transistor 112 and an FD are provided on the front side (the side opposite the light incident surface, the second chip 402 side) of the first semiconductor substrate 410. The first chip 401 has an element isolation section 43 that isolates each sensor pixel 401b.
　素子分離部４３は、第１半導体基板４１０の法線方向（第１半導体基板４１０の表面に対して垂直な方向）に延在して形成されている。素子分離部４３は、互いに隣接する２つのセンサ画素４０１ｂの間に設けられている。素子分離部４３は、互いに隣接するセンサ画素４０１ｂ同士を電気的に分離する。素子分離部４３は、例えば、酸化シリコンによって構成されている。素子分離部４３は、例えば、第１半導体基板４１０を貫通している。 The element isolation portion 43 is formed extending in the normal direction of the first semiconductor substrate 410 (direction perpendicular to the surface of the first semiconductor substrate 410). The element isolation portion 43 is provided between two adjacent sensor pixels 401b. The element isolation portion 43 electrically isolates the adjacent sensor pixels 401b. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates, for example, the first semiconductor substrate 410.
　第１チップ４０１は、例えば、さらに、素子分離部４３の側面であって、かつ、フォトダイオード１１１側の面に接するｐウェル層４４を有している。ｐウェル層４４は、フォトダイオード１１１とは異なる導電型（具体的にはｐ型）の半導体領域で構成されている。 The first chip 401 further has, for example, a p-well layer 44 that is a side surface of the element isolation section 43 and is in contact with the surface on the photodiode 111 side. The p-well layer 44 is composed of a semiconductor region of a different conductivity type (specifically, p-type) from the photodiode 111.
　第１チップ４０１は、例えば、さらに、第１半導体基板４１０の裏面に接する固定電荷膜４５を有している。固定電荷膜４５は、第１半導体基板４１０の受光面側の界面準位に起因する暗電流の発生を抑制するため、負に帯電している。固定電荷膜４５は、例えば、負の固定電荷を有する絶縁膜によって形成されている。そのような絶縁膜の材料としては、例えば、酸化ハフニウム、酸化ジルコン、酸化アルミニウム、酸化チタンまたは酸化タンタルが挙げられる。固定電荷膜４５が誘起する電界により、第１半導体基板４１０の受光面側の界面にホール蓄積層が形成される。このホール蓄積層によって、界面からの電子の発生が抑制される。 The first chip 401 further has, for example, a fixed charge film 45 in contact with the back surface of the first semiconductor substrate 410. The fixed charge film 45 is negatively charged in order to suppress the generation of dark current due to the interface state on the light-receiving surface side of the first semiconductor substrate 410. The fixed charge film 45 is formed, for example, by an insulating film having a negative fixed charge. Examples of materials for such insulating films include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light-receiving surface side of the first semiconductor substrate 410 due to the electric field induced by the fixed charge film 45. This hole accumulation layer suppresses the generation of electrons from the interface.
　カラーフィルタ５００は、第１半導体基板４１０の裏面側に設けられている。カラーフィルタ５００は、例えば、固定電荷膜４５に接して設けられており、固定電荷膜４５を介してセンサ画素４０１ｂと対向する位置に設けられている。 The color filter 500 is provided on the back surface side of the first semiconductor substrate 410. The color filter 500 is provided, for example, in contact with the fixed charge film 45 and is provided at a position facing the sensor pixel 401b via the fixed charge film 45.
　受光レンズ６００は、例えば、カラーフィルタ５００に接して設けられており、カラーフィルタ５００および固定電荷膜４５を介してセンサ画素４０１ｂと対向する位置に設けられている。 The light receiving lens 600 is provided, for example, in contact with the color filter 500 and is provided in a position facing the sensor pixel 401b via the color filter 500 and the fixed charge film 45.
　第２チップ４０２は、第２半導体基板４２０上に絶縁層５２を積層して構成されている。第２チップ４０２は、層間絶縁膜５１の一部として、絶縁層５２を有している。絶縁層５２は、第２半導体基板４２０と、第３半導体基板４３０との間隙に設けられている。第２半導体基板４２０は、シリコン基板で構成されている。第２チップ４０２は、第２半導体基板４２０の表面側（第３チップ４０３側）の部分に第２画素アレイ部４０２ａが設けられた構成となっている。第２チップ４０２は、第１半導体基板４１０の表面側に第２半導体基板４２０の裏面を向けて第１チップ４０１に貼り合わされている。つまり、第２チップ４０２は、第１チップ４０１に、フェイストゥーバックで貼り合わされている。第２チップ４０２は、さらに、第２半導体基板４２０と同一の層内に、第２半導体基板４２０を貫通する絶縁層５３を有している。第２チップ４０２は、層間絶縁膜５１の一部として、絶縁層５３を有している。絶縁層５３は、後述の貫通配線５４の側面を覆うように設けられている。 The second chip 402 is configured by laminating an insulating layer 52 on the second semiconductor substrate 420. The second chip 402 has the insulating layer 52 as a part of the interlayer insulating film 51. The insulating layer 52 is provided in the gap between the second semiconductor substrate 420 and the third semiconductor substrate 430. The second semiconductor substrate 420 is configured of a silicon substrate. The second chip 402 is configured such that a second pixel array section 402a is provided on the surface side (third chip 403 side) of the second semiconductor substrate 420. The second chip 402 is bonded to the first chip 401 with the back surface of the second semiconductor substrate 420 facing the surface side of the first semiconductor substrate 410. In other words, the second chip 402 is bonded to the first chip 401 face-to-back. The second chip 402 further has an insulating layer 53 penetrating the second semiconductor substrate 420 in the same layer as the second semiconductor substrate 420. The second chip 402 has an insulating layer 53 as part of the interlayer insulating film 51. The insulating layer 53 is provided to cover the side of the through wiring 54 described below.
　第１チップ４０１および第２チップ４０２から成る積層体は、層間絶縁膜５１と、層間絶縁膜５１内に設けられた貫通配線５４を有している。上記積層体は、センサ画素４０１ｂごとに、１つの貫通配線５４を有している。貫通配線５４は、第２半導体基板４２０の法線方向に延びており、層間絶縁膜５１のうち、絶縁層５３を含む箇所を貫通して設けられている。第１チップ４０１および第２チップ４０２は、貫通配線５４によって互いに電気的に接続されている。具体的には、貫通配線５４は、ＦＤおよび後述の接続配線５５に電気的に接続されている。 The stack consisting of the first chip 401 and the second chip 402 has an interlayer insulating film 51 and through-wires 54 provided within the interlayer insulating film 51. The stack has one through-wire 54 for each sensor pixel 401b. The through-wires 54 extend in the normal direction of the second semiconductor substrate 420 and are provided penetrating a portion of the interlayer insulating film 51 that includes the insulating layer 53. The first chip 401 and the second chip 402 are electrically connected to each other by the through-wires 54. Specifically, the through-wires 54 are electrically connected to the FD and the connection wires 55 described below.
　第２チップ４０２は、例えば、絶縁層５２内に、第２画素アレイ部４０２ａや第２半導体基板４２０と電気的に接続された複数の接続部５９を有している。第２チップ４０２は、さらに、例えば、絶縁層５２上に配線層５６を有している。配線層５６は、例えば、絶縁層５７と、絶縁層５７内に設けられた複数の画素駆動線８０および複数の垂直信号線９０を有している。配線層５６は、さらに、例えば、絶縁層５７内に複数の接続配線５５を４つのセンサ画素４０１ｂごとに１つずつ有している。 The second chip 402 has, for example, a plurality of connection parts 59 in the insulating layer 52 that are electrically connected to the second pixel array part 402a and the second semiconductor substrate 420. The second chip 402 further has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57, and a plurality of pixel drive lines 80 and a plurality of vertical signal lines 90 provided in the insulating layer 57. The wiring layer 56 further has, for example, a plurality of connection wires 55 in the insulating layer 57, one for each of the four sensor pixels 401b.
　接続配線５５は、第２画素アレイ部４０２ａを共有する４つのセンサ画素４０１ｂに含まれるＦＤに電気的に接続された各貫通配線５４を互いに電気的に接続している。ここで、貫通配線５４の総数は、第１チップ４０１に含まれるセンサ画素４０１ｂの総数よりも多く、第１チップ４０１に含まれるセンサ画素４０１ｂの総数の２倍となっている。また、貫通配線５４の総数は、第１チップ４０１に含まれるセンサ画素４０１ｂの総数よりも多く、第１チップ４０１に含まれるセンサ画素４０１ｂの総数の３倍となっている。 The connection wiring 55 electrically connects each of the through wirings 54 electrically connected to the FDs included in the four sensor pixels 401b that share the second pixel array unit 402a. Here, the total number of through wirings 54 is greater than the total number of sensor pixels 401b included in the first chip 401, and is twice the total number of sensor pixels 401b included in the first chip 401. In addition, the total number of through wirings 54 is greater than the total number of sensor pixels 401b included in the first chip 401, and is three times the total number of sensor pixels 401b included in the first chip 401.
　配線層５６は、さらに、例えば、絶縁層５７内に複数のパッド電極５８を有している。各パッド電極５８は、例えば、Ｃｕ（銅）、Ａｌ（アルミニウム）などの金属で形成されている。各パッド電極５８は、配線層５６の表面に露出している。各パッド電極５８は、第２チップ４０２と第３チップ４０３との電気的な接続と、第２チップ４０２と第３チップ４０３との貼り合わせに用いられる。 The wiring layer 56 further has, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed of a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second chip 402 and the third chip 403, and for bonding the second chip 402 and the third chip 403 together.
　複数のパッド電極５８は、例えば、画素駆動線８０および垂直信号線９０ごとに１つずつ設けられている。ここで、パッド電極５８の総数は、第１チップ４０１に含まれるセンサ画素４０１ｂの総数よりも少ない。 The multiple pad electrodes 58 are provided, for example, one for each pixel drive line 80 and vertical signal line 90. Here, the total number of pad electrodes 58 is less than the total number of sensor pixels 401b included in the first chip 401.
　第３チップ４０３は、例えば、第３半導体基板４３０上に層間絶縁膜６１を積層して構成されている。第３半導体基板４３０は、シリコン基板で構成されている。第３チップ４０３は、第３半導体基板４３０の表面側の部分にロジック回路４３１が設けられた構成となっている。 The third chip 403 is configured, for example, by laminating an interlayer insulating film 61 on a third semiconductor substrate 430. The third semiconductor substrate 430 is configured as a silicon substrate. The third chip 403 is configured such that a logic circuit 431 is provided on the surface side portion of the third semiconductor substrate 430.
　第３チップ４０３は、さらに、例えば、層間絶縁膜６１上に配線層６２を有している。配線層６２は、例えば、絶縁層６３と、絶縁層６３内に設けられた複数のパッド電極６４を有している。複数のパッド電極６４は、ロジック回路４３１と電気的に接続されている。各パッド電極６４は、例えば、Ｃｕ（銅）で形成されている。各パッド電極６４は、配線層６２の表面に露出している。各パッド電極６４は、第２チップ４０２と第３チップ４０３との電気的な接続と、第２チップ４０２と第３チップ４０３との貼り合わせに用いられる。また、パッド電極６４は、必ずしも複数でなくてもよく、１つでもロジック回路４３１と電気的に接続が可能である。 The third chip 403 further has, for example, a wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 431. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used for electrically connecting the second chip 402 and the third chip 403 and for bonding the second chip 402 and the third chip 403 together. In addition, the number of pad electrodes 64 does not necessarily have to be multiple, and even one pad electrode 64 can be electrically connected to the logic circuit 431.
　第２チップ４０２および第３チップ４０３は、パッド電極５８，６４同士の接合によって、互いに電気的に接続されている。つまり、転送トランジスタ１１２のゲートは、貫通配線５４と、パッド電極５８，６４とを介して、ロジック回路４３１に電気的に接続されている。第３チップ４０３は、第２半導体基板４２０の表面側に第３半導体基板４３０の表面を向けて第２チップ４０２に貼り合わされている。つまり、第３チップ４０３は、第２チップ４０２に、フェイストゥーフェイスで貼り合わされている。 The second chip 402 and the third chip 403 are electrically connected to each other by bonding the pad electrodes 58, 64. That is, the gate of the transfer transistor 112 is electrically connected to the logic circuit 431 via the through-wire 54 and the pad electrodes 58, 64. The third chip 403 is bonded to the second chip 402 with the surface of the third semiconductor substrate 430 facing the surface side of the second semiconductor substrate 420. That is, the third chip 403 is bonded to the second chip 402 face-to-face.
　上記のように構成された本実施形態に係るＣＭＯＳイメージセンサ４では、第１アンプトランジスタ１２１は、第２チップ４０２の第２画素アレイ部４０２ａ内に設けられている。第２画素アレイ部４０２ａ内では、上述した第１実施形態と同様に、第１アンプトランジスタ１２１のドレイン領域１２１ｄおよびソース領域１２１ｅの直下に絶縁膜１１５が形成されている。そのため、短チャネル効果を抑制しつつドレイン領域１２１ｄとソース領域１２１ｅとの間におけるＰ型の半導体ウェル領域（チャネル領域２１２ａ）の不純物濃度を低濃度にすることができる。これにより、第１アンプトランジスタ１２１を低電流で駆動しても、第１ソースフォロワ回路１２０ｃの熱雑音の増大を抑制することができる。したがって、本実施形態においても、消費電力を抑制しつつランダムノイズを低減することが可能となる。 In the CMOS image sensor 4 according to this embodiment configured as described above, the first amplifier transistor 121 is provided in the second pixel array section 402a of the second chip 402. In the second pixel array section 402a, an insulating film 115 is formed directly under the drain region 121d and the source region 121e of the first amplifier transistor 121, as in the first embodiment described above. Therefore, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be made low while suppressing the short channel effect. As a result, even if the first amplifier transistor 121 is driven with a low current, the increase in thermal noise of the first source follower circuit 120c can be suppressed. Therefore, in this embodiment as well, it is possible to reduce random noise while suppressing power consumption.
　なお、本実施形態では、第２チップ４０２および第３チップの接合形態は、パッド電極同士の接合であるＣｕ－Ｃｕ接合であるとともに、第１チップ４０１および第２チップ４０２の接合形態は、貫通配線の接合であるＴＳＶ（Through-Silicon Via）接合である。ただし、第２チップ４０２および第３チップ４０３をＴＳＶ接合で接合するとともに、第１チップ４０１および第２チップをＣｕ－Ｃｕ接合で接合することも可能である。 In this embodiment, the bonding form between the second chip 402 and the third chip is Cu-Cu bonding, which is bonding between pad electrodes, and the bonding form between the first chip 401 and the second chip 402 is TSV (Through-Silicon Via) bonding, which is bonding between through-hole wiring. However, it is also possible to bond the second chip 402 and the third chip 403 with TSV bonding and to bond the first chip 401 and the second chip with Cu-Cu bonding.
　（第５実施形態）
　図２６は、第５実施形態に係る電子機器の構成例を示すブロック図である。 Fifth Embodiment
FIG. 26 is a block diagram showing an example of the configuration of an electronic device according to the fifth embodiment.
　図２６に示す電子機器１０００は、ビデオカメラやデジタルスチルカメラ等である。電子機器１０００は、レンズ群１００１、固体ＣＭＯＳイメージセンサ４００２、ＤＳＰ回路１００３、フレームメモリ１００４、表示部１００５、記録部１００６、操作部１００７、および電源部１００８を備える。ＤＳＰ回路１００３、フレームメモリ１００４、表示部１００５、記録部１００６、操作部１００７、および電源部１００８は、バスライン１００９を介して相互に接続されている。 The electronic device 1000 shown in FIG. 26 is a video camera, a digital still camera, or the like. The electronic device 1000 includes a lens group 1001, a solid-state CMOS image sensor 4002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are interconnected via a bus line 1009.
　レンズ群１００１は、被写体からの入射光（像光）を取り込んで固体ＣＭＯＳイメージセンサ４００２の撮像面上に結像する。固体ＣＭＯＳイメージセンサ４００２は、上述した各実施形態のＣＭＯＳイメージセンサのいずれかである。固体ＣＭＯＳイメージセンサ４００２は、レンズ群１００１によって撮像面上に結像された入射光の光量を画素単位で電気信号に変換して画素信号としてＤＳＰ回路１００３に供給する。 The lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state CMOS image sensor 4002. The solid-state CMOS image sensor 4002 is any one of the CMOS image sensors of each of the above-mentioned embodiments. The solid-state CMOS image sensor 4002 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1003.
　ＤＳＰ回路１００３は、固体ＣＭＯＳイメージセンサ４００２から供給される画素信号に対して所定の画像処理を行い、画像処理後の画像信号をフレーム単位でフレームメモリ１００４に供給し、一時的に記憶させる。 The DSP circuit 1003 performs a predetermined image processing on the pixel signals supplied from the solid-state CMOS image sensor 4002, and supplies the processed image signals to the frame memory 1004 on a frame-by-frame basis for temporary storage.
　表示部１００５は、例えば、液晶パネルや有機ＥＬ（Electro Luminescence）パネル等のパネル型表示装置からなり、フレームメモリ１００４に一時的に記憶されたフレーム単位の画素信号に基づいて、画像を表示する。 The display unit 1005 is, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on pixel signals on a frame-by-frame basis that are temporarily stored in the frame memory 1004.
　記録部１００６は、ＤＶＤ（Digital Versatile Disk）、フラッシュメモリ等からなり、フレームメモリ１００４に一時的に記憶されたフレーム単位の画素信号を読み出し、記録する。 The recording unit 1006 is composed of a DVD (Digital Versatile Disk), flash memory, etc., and reads out and records the pixel signals on a frame-by-frame basis that are temporarily stored in the frame memory 1004.
　操作部１００７は、ユーザによる操作の下に、電子機器１０００ が持つ様々な機能について操作指令を発する。電源部１００８は、ＤＳＰ回路１００３、フレームメモリ１００４、表示部１００５、記録部１００６、および操作部１００７に対して電力を供給する。 The operation unit 1007 issues operation commands for various functions of the electronic device 1000 under the operation of a user. The power supply unit 1008 supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.
　本技術を適用する電子機器は、画像取込部（ 光電変換部）にＣＭＯＳイメージセンサを用いる装置であればよく、電子機器１０００のほか、撮像機能を有する携帯端末装置、画像読取部にＣＭＯＳイメージセンサを用いる複写機などがある。 Electronic devices to which this technology can be applied include any device that uses a CMOS image sensor in its image capture section (photoelectric conversion section), such as the electronic device 1000, a portable terminal device with an imaging function, and a copying machine that uses a CMOS image sensor in its image reading section.
　以上説明した本実施形態に係る電子機器１０００では、上述した各実施形態のいずれかのＣＭＯＳイメージセンサが固体ＣＭＯＳイメージセンサ４００２として搭載されている。そのため、固体ＣＭＯＳイメージセンサ４００２は、低ランダムノイズの機能を有するため、撮像性能を向上させることが可能となる。 In the electronic device 1000 according to the present embodiment described above, any one of the CMOS image sensors according to the above-mentioned embodiments is mounted as the solid-state CMOS image sensor 4002. Therefore, the solid-state CMOS image sensor 4002 has a low random noise function, which makes it possible to improve imaging performance.
　＜移動体への応用例＞
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <Application to moving objects>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
　図２７は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 27 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図２７に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ（ｉｎｔｅｒｆａｃｅ）１２０５３が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 27, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020. The body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects information inside the vehicle. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ（Ａｄｖａｎｃｅｄ　Ｄｒｉｖｅｒ　Ａｓｓｉｓｔａｎｃｅ　Ｓｙｓｔｅｍ）の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 The microcomputer 12051 can also control the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing cooperative control aimed at automatic driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０２０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 The microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図２７の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information. In the example of FIG. 27, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
　図２８は、撮像部１２０３１の設置位置の例を示す図である。 FIG. 28 shows an example of the installation position of the imaging unit 12031.
　図２８では、車両１２１００は、撮像部１２０３１として、撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５を有する。 In FIG. 28, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
　撮像部１２１０１，１２１０２，１２１０３，１２１０４，１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２，１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。撮像部１２１０１及び１２１０５で取得される前方の画像は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
　なお、図２８には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 28 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for detecting phase differences.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０ｋｍ／ｈ以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering to avoid a collision via the drive system control unit 12010.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the imaging units 12101 to 12104 and recognizes a pedestrian, the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、撮像部１２０３１に適用され得る。具体的には、撮像部１２０３１に、上述のＣＭＯＳイメージセンサを実装することができる。撮像部１２０３１に、本開示に係る技術を適用することにより、ランダムノイズを低減した撮像環境において、正確な距離情報を得ることができる。その結果、車両１２１００の機能性および安全性を高めることができる。 Above, an example of a vehicle control system to which the technology disclosed herein can be applied has been described. Of the configurations described above, the technology disclosed herein can be applied to, for example, the imaging unit 12031. Specifically, the imaging unit 12031 can be equipped with the above-mentioned CMOS image sensor. By applying the technology disclosed herein to the imaging unit 12031, accurate distance information can be obtained in an imaging environment with reduced random noise. As a result, the functionality and safety of the vehicle 12100 can be improved.
　なお、本技術は、以下のような構成をとることができる。
（１）　入射光を光電変換した画素信号を出力する光電変換回路と、
　前記画素信号を増幅するアンプトランジスタを含むソースフォロワ回路と、を備え、
　前記アンプトランジスタのドレイン領域およびソース領域の各々の直下に、絶縁膜が形成されている、受光素子。
（２）　前記ドレイン領域と前記ソース領域との間における半導体ウェル領域の不純物濃度が、前記アンプトランジスタの駆動中に前記ドレイン領域および前記ソース領域の各々の下端部と同じ深さか、または前記下端部よりも深い位置まで空乏化する濃度である、（１）に記載の受光素子。
（３）　前記不純物濃度が、４ｅ１７（ｃｍ－３）よりも１０倍以上低い、（２）に記載の受光素子。
（４）　前記半導体ウェル領域は、シリコンのエピタキシャル成長層である、（２）または（３）に記載の受光素子。
（５）　前記半導体ウェル領域は、前記アンプトランジスタの駆動中に前記ドレイン領域と前記ソース領域との間に形成されるチャネル領域の直下にシリコンゲルマニウム層を有する、（２）から（４）のいずれかに記載の受光素子。
（６）　前記絶縁膜の厚さが、前記アンプトランジスタの駆動中に生成される空乏層より少なくとも深い、（１）から（５）のいずれかに記載の受光素子。
（７）　前記絶縁膜の厚さが、前記アンプトランジスタを形成する半導体基板の厚さに対して１０％以内である、（６）に記載の受光素子。
（８）　前記絶縁膜が、前記アンプトランジスタを囲んでいる、（１）から（７）のいずれかに記載の受光素子。
（９）　前記ドレイン領域および前記ソース領域の各々一部が、ポリシリコン膜である、（１）から（８）のいずれかに記載の受光素子。
（１０）　前記アンプトランジスタの駆動中に前記ドレイン領域と前記ソース領域との間に形成されるチャネル領域の直下にも前記絶縁膜が形成されている、（１）に記載の受光素子。
（１１）　前記チャネル領域が、Ｓｉ（１１０）面に形成される、（１０）に記載の受光素子。
（１２）　前記アンプトランジスタが、Ｆｉｎ型ＭＯＳトランジスタである、（１１）に記載の受光素子。
（１３）　前記アンプトランジスタが、前記光電変換回路と同じ半導体基板に配置されている、（１）から（１２）のいずれかに記載の受光素子。
（１４）　前記アンプトランジスタが、前記光電変換回路と異なる半導体基板に配置されている、（１）から（１２）のいずれかに記載の受光素子。
（１５）　入射光を光電変換した画素信号を出力する光電変換回路と、前記画素信号を増幅するアンプトランジスタを含むソースフォロワ回路と、を含む受光素子を備える電子機器であって、
　前記アンプトランジスタのドレイン領域およびソース領域の各々の直下に、絶縁膜が形成されている、電子機器。 The present technology can be configured as follows.
(1) a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light;
a source follower circuit including an amplifier transistor that amplifies the pixel signal;
an insulating film is formed directly below each of the drain region and the source region of the amplifier transistor;
(2) The photodiode according to (1), wherein the impurity concentration of the semiconductor well region between the drain region and the source region is a concentration that depletes the semiconductor well region to the same depth as the bottom ends of the drain region and the source region or to a position deeper than the bottom ends while the amplifier transistor is operating.
(3) The light-receiving element according to (2), wherein the impurity concentration is 10 times or more lower than 4e17 (cm −3 ).
(4) The photodiode according to (2) or (3), wherein the semiconductor well region is an epitaxially grown layer of silicon.
(5) The photodiode according to any one of (2) to (4), wherein the semiconductor well region has a silicon germanium layer immediately below a channel region formed between the drain region and the source region during operation of the amplifier transistor.
(6) The light-receiving element according to any one of (1) to (5), wherein the insulating film has a thickness at least deeper than a depletion layer generated during operation of the amplifier transistor.
(7) The light-receiving element according to (6), wherein the thickness of the insulating film is within 10% of the thickness of a semiconductor substrate on which the amplifier transistor is formed.
(8) The light-receiving element according to any one of (1) to (7), wherein the insulating film surrounds the amplifier transistor.
(9) The light-receiving element according to any one of (1) to (8), wherein a part of each of the drain region and the source region is a polysilicon film.
(10) The light-receiving element according to (1), wherein the insulating film is also formed immediately below a channel region that is formed between the drain region and the source region while the amplifier transistor is in operation.
(11) The light-receiving element according to (10), wherein the channel region is formed on a Si(110) surface.
(12) The light receiving element according to (11), wherein the amplifier transistor is a Fin-type MOS transistor.
(13) The light-receiving element according to any one of (1) to (12), wherein the amplifier transistor and the photoelectric conversion circuit are disposed on the same semiconductor substrate.
(14) The light-receiving element according to any one of (1) to (12), wherein the amplifier transistor is disposed on a semiconductor substrate different from that on which the photoelectric conversion circuit is disposed.
(15) An electronic device including a light receiving element including a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light, and a source follower circuit including an amplifier transistor that amplifies the pixel signal,
an insulating film is formed directly below each of the drain region and the source region of the amplifier transistor.
　本開示の態様は、上述した個々の実施形態に限定されるものではなく、当業者が想到しうる種々の変形も含むものであり、本開示の効果も上述した内容に限定されない。すなわち、特許請求の範囲に規定された内容およびその均等物から導き出される本開示の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更および部分的削除が可能である。 The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above. In other words, various additions, modifications, and partial deletions are possible within the scope that does not deviate from the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents.
１：ＣＭＯＳイメージセンサ
１１０：光電変換回路
１１５：絶縁膜
１２０：第１ソースフォロワ回路
１２１：第１アンプトランジスタ
１２１ｄ：ドレイン領域
１２１ｅ：ソース領域
２１２：エピタキシャル成長層
２１２ａ：チャネル領域
２１４：ポリシリコン膜
２１５：ＳｉＧｅ層
１０００：電子機器 1: CMOS image sensor 110: photoelectric conversion circuit 115: insulating film 120: first source follower circuit 121: first amplifier transistor 121d: drain region 121e: source region 212: epitaxial growth layer 212a: channel region 214: polysilicon film 215: SiGe layer 1000: electronic device

Claims (15)

  1. 　入射光を光電変換した画素信号を出力する光電変換回路と、
    　前記画素信号を増幅するアンプトランジスタを含むソースフォロワ回路と、を備え、
    　前記アンプトランジスタのドレイン領域およびソース領域の各々の直下に、絶縁膜が形成されている、受光素子。     a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light;
    a source follower circuit including an amplifier transistor that amplifies the pixel signal;
    an insulating film is formed directly below each of the drain region and the source region of the amplifier transistor;
  2. 　前記ドレイン領域と前記ソース領域との間における半導体ウェル領域の不純物濃度が、前記アンプトランジスタの駆動中に前記ドレイン領域および前記ソース領域の各々の下端部と同じ深さか、または前記下端部よりも深い位置まで空乏化する濃度である、請求項１に記載の受光素子。 The light receiving element according to claim 1, wherein the impurity concentration of the semiconductor well region between the drain region and the source region is a concentration that depletes the semiconductor well region to the same depth as the bottom ends of the drain region and the source region, or to a position deeper than the bottom ends while the amplifier transistor is in operation.
  3. 　前記不純物濃度が、４ｅ１７（ｃｍ－３）よりも１０倍以上低い、請求項２に記載の受光素子。 3. The light-receiving element according to claim 2, wherein the impurity concentration is at least 10 times lower than 4e 17 (cm −3 ).
  4. 　前記半導体ウェル領域は、シリコンのエピタキシャル成長層である、請求項２に記載の受光素子。 The light receiving element according to claim 2, wherein the semiconductor well region is an epitaxially grown layer of silicon.
  5. 　前記半導体ウェル領域は、前記アンプトランジスタの駆動中に前記ドレイン領域と前記ソース領域との間に形成されるチャネル領域の直下にシリコンゲルマニウム層を有する、請求項２に記載の受光素子。 The light receiving element according to claim 2, wherein the semiconductor well region has a silicon germanium layer directly below a channel region formed between the drain region and the source region while the amplifier transistor is in operation.
  6. 　前記絶縁膜の厚さが、前記アンプトランジスタの駆動中に生成される空乏層より少なくとも深い、請求項１に記載の受光素子。 The photodetector according to claim 1, wherein the thickness of the insulating film is at least deeper than the depletion layer generated while the amplifier transistor is in operation.
  7. 　前記絶縁膜の厚さが、前記アンプトランジスタを形成する半導体基板の厚さに対して１０％以内である、請求項６に記載の受光素子。 The photodetector according to claim 6, wherein the thickness of the insulating film is within 10% of the thickness of the semiconductor substrate on which the amplifier transistor is formed.
  8. 　前記絶縁膜が、前記アンプトランジスタを囲んでいる、請求項１に記載の受光素子。 The light receiving element according to claim 1, wherein the insulating film surrounds the amplifier transistor.
  9. 　前記ドレイン領域および前記ソース領域の各々一部が、ポリシリコン膜である、請求項１に記載の受光素子。 The light receiving element according to claim 1, wherein a portion of each of the drain region and the source region is a polysilicon film.
  10. 　前記アンプトランジスタの駆動中に前記ドレイン領域と前記ソース領域との間に形成されるチャネル領域の直下にも前記絶縁膜が形成されている、請求項１に記載の受光素子。 The light receiving element according to claim 1, wherein the insulating film is also formed directly below a channel region formed between the drain region and the source region while the amplifier transistor is in operation.
  11. 　前記チャネル領域が、Ｓｉ（１１０）面に形成される、請求項１０に記載の受光素子。 The light receiving element according to claim 10, wherein the channel region is formed on a Si(110) surface.
  12. 　前記アンプトランジスタが、Ｆｉｎ型ＭＯＳトランジスタである、請求項１１に記載の受光素子。 The light receiving element according to claim 11, wherein the amplifier transistor is a Fin-type MOS transistor.
  13. 　前記アンプトランジスタが、前記光電変換回路と同じ半導体基板に配置されている、請求項１に記載の受光素子。 The light receiving element according to claim 1, wherein the amplifier transistor is disposed on the same semiconductor substrate as the photoelectric conversion circuit.
  14. 　前記アンプトランジスタが、前記光電変換回路と異なる半導体基板に配置されている、請求項１に記載の受光素子。 The light receiving element according to claim 1, wherein the amplifier transistor is disposed on a semiconductor substrate different from the photoelectric conversion circuit.
  15. 　入射光を光電変換した画素信号を出力する光電変換回路と、前記画素信号を増幅するアンプトランジスタを含むソースフォロワ回路と、を含む受光素子を備える電子機器であって、
    　前記アンプトランジスタのドレイン領域およびソース領域の各々の直下に、絶縁膜が形成されている、電子機器。     An electronic device including a light receiving element including a photoelectric conversion circuit that outputs a pixel signal obtained by photoelectrically converting incident light, and a source follower circuit including an amplifier transistor that amplifies the pixel signal,
    an insulating film is formed directly below each of the drain region and the source region of the amplifier transistor.
PCT/JP2023/034818 2022-10-31 2023-09-26 Light receiving element and electronic device WO2024095639A1 (en)

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JPH06120473A (en) * 1992-10-08 1994-04-28 Olympus Optical Co Ltd Solid-state image sensing device and driving method therefor the same
US20080179625A1 (en) * 2007-01-30 2008-07-31 Kyung-Ho Lee CMOS image sensor having transistor with conduction band offset
JP2009295890A (en) * 2008-06-06 2009-12-17 Sony Corp Mos transistor, solid-state imaging apparatus, electronic apparatus, and methods for manufacturing of them
JP2011254060A (en) * 2010-06-04 2011-12-15 Sharp Corp Semiconductor device
JP2018207000A (en) * 2017-06-06 2018-12-27 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2021084959A1 (en) * 2019-10-29 2021-05-06 ソニーセミコンダクタソリューションズ株式会社 Imaging device and electronic device

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Publication number Priority date Publication date Assignee Title
JPH06120473A (en) * 1992-10-08 1994-04-28 Olympus Optical Co Ltd Solid-state image sensing device and driving method therefor the same
US20080179625A1 (en) * 2007-01-30 2008-07-31 Kyung-Ho Lee CMOS image sensor having transistor with conduction band offset
JP2009295890A (en) * 2008-06-06 2009-12-17 Sony Corp Mos transistor, solid-state imaging apparatus, electronic apparatus, and methods for manufacturing of them
JP2011254060A (en) * 2010-06-04 2011-12-15 Sharp Corp Semiconductor device
JP2018207000A (en) * 2017-06-06 2018-12-27 ルネサスエレクトロニクス株式会社 Semiconductor device
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