WO2024088040A1

WO2024088040A1 - Wafer-level packaging structure and manufacturing method therefor, and electronic device

Info

Publication number: WO2024088040A1
Application number: PCT/CN2023/123433
Authority: WO
Inventors: 于睿; 贾国朋; 吕鹏
Original assignee: 华为技术有限公司
Priority date: 2022-10-29
Filing date: 2023-10-08
Publication date: 2024-05-02
Also published as: CN117954403A

Abstract

Provided in the present application are a wafer-level packaging structure (100) and a manufacturing method therefor, and an electronic device. The wafer-level packaging structure (100) comprises a substrate layer (10), a wall film (20) and a top film (30), which are sequentially stacked, wherein the wall film (20) is provided with an avoidance groove (22) on the side in the same direction as a cutting side surface (100a), and a side surface (221) of the avoidance groove (22) and the cutting side surface (100a) are spaced apart from each other. During the cutting of a wafer, a cutter (40a) passes through the top film (30) and the substrate layer (10) without touching the wall film (20), the avoidance groove (22) of the wall film (20) can avoid the cutter (40a), and the avoidance groove (22) can block or reduce the transmission of a cutting normal stress to the wall film (20) near a cavity (21), such that layering between the wall film (20) and the substrate layer (10) is reduced, the wall film (20) and the substrate layer (10) are bonded better, and the sealing performance of the cavity (21) is better, thereby improving the structural reliability and production yield. When the top film (30) is arranged on the wall film (20), the top film (30) can be partially squeezed into a filling groove (23) of the wall film (20), such that a bonding area between the wall film (20) and the top film (30) is increased to improve the bonding strength, and during the cutting of a wafer, a shearing force in a direction perpendicular to the cutting side surface (100a) can be blocked or reduced, thereby satisfying miniaturization of the wafer-level packaging structure (100).

Description

Wafer-level packaging structure and manufacturing method thereof, and electronic device

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 29, 2022, with application number 202211352556.8 and application name “A wafer-level packaging structure, its manufacturing method, and electronic device”, all contents of which are incorporated by reference in this application.

Technical Field

The embodiments of the present application relate to the field of wafer-level packaging structure and manufacturing technology, and in particular, to a wafer-level packaging structure and a manufacturing method thereof, and an electronic device.

Background technique

Surface acoustic wave (SAW) filter is a passive filter widely used in the field of wireless communications. SAW filter includes a piezoelectric material substrate layer and multiple pairs of interdigital transducers (IDT) arranged on the substrate layer. When a pair of interdigital transducers are connected to a high-frequency electrical signal, the surface of the substrate layer will produce mechanical vibrations and excite surface acoustic waves with the same frequency as the external electrical signal, and the surface acoustic waves will propagate along the surface of the substrate layer. Another pair of interdigital transducers can detect the surface acoustic waves and convert them into electrical signals. SAW filters can filter out unnecessary signals and noise, and improve the quality of signal reception.

SAW filters or other similar devices can be packaged at the wafer level (WLP). The wall film and top film are pasted on the surface of the substrate layer by film pasting equipment to form a cavity for placing functional devices. The chip pads are brought out of the device surface by electroplating and other processes to complete the device packaging. There are hundreds to tens of thousands of small chips on the wafer. There are cutting paths of a certain width between the small chips. A cutting knife is used to cut along the cutting paths to separate single small chips. The positive stress of wafer cutting can easily cause delamination between the wall film and the substrate layer. The wall film is torn and fails. There is a possibility that the cavity is not closed, and the structural reliability is weak.

Summary of the invention

The embodiments of the present application provide a wafer-level packaging structure and a manufacturing method thereof, and an electronic device, which solve the problem of easy delamination between the wall film and the substrate layer during the manufacturing process of the wafer-level packaging structure.

The embodiment of the present application adopts the following technical solution:

In a first aspect, an embodiment of the present application provides a wafer-level packaging structure, comprising: a substrate layer, a wall film, and a top film stacked in sequence. The wafer-level packaging structure has a cutting side, and the cutting side is formed on the same side surface of the substrate layer and the top film. The wall film has a cavity for placing functional devices, and the substrate layer and the top film are respectively covered at opposite ends of the cavity. The wall film has an avoidance groove on one side in the same direction as the cutting side, and the side of the avoidance groove is spaced apart from the cutting side.

The wafer-level packaging structure provided by the embodiment of the present application includes a substrate layer, a wall film and a top film which are stacked in sequence, and the wall film has an avoidance groove on the side in the same direction as the cutting side, and the side of the avoidance groove is spaced apart from the cutting side. When the wafer is cut, the cutting knife passes through the position of the top film and the substrate layer without touching the wall film, and the avoidance groove of the wall film can avoid the cutting knife. The avoidance groove can block or reduce the transmission of the cutting positive stress to the wall film near the cavity, reduce the delamination between the wall film and the substrate layer, make the wall film and the substrate layer better combined, and make the cavity more sealed, thereby improving the structural reliability and production yield.

In an optional implementation, the distance between the side of the avoidance groove and the cutting side is in the range of 2 μm to 10 μm. The width of the avoidance groove is set small so that the cutting blade does not touch the wall film when the wafer is cut.

In an optional implementation, the avoidance groove is arranged through the wall film along the thickness direction of the wall film, that is, when the wall film is arranged on the substrate layer, the substrate layer at the avoidance groove is exposed.

In an optional implementation, the avoidance groove is formed by extending the top surface of the wall film to a predetermined depth, and the bottom surface of the avoidance groove is spaced apart from the substrate layer. When the wall film is arranged on the substrate layer, the substrate layer at the avoidance groove is not exposed.

In an optional implementation, the top film has a first filling portion that at least partially fills the avoidance groove, and the first filling portion covers the side of the avoidance groove. This can enhance the bonding strength between the wall film and the top film, so that the wall film and the top film are not easily pulled apart by the cutting stress during wafer cutting, thereby enhancing the structural reliability.

In an optional implementation, a filling groove is provided on the top surface of the wall film between the cavity and the avoidance groove, the depth of the filling groove is less than the thickness of the wall film, and the top film has a second filling portion that at least partially fills the filling groove. The bonding area between the wall film and the top film is increased to improve the bonding strength, and the wall film and the top film are not easily pulled apart by the cutting stress, thereby meeting the miniaturization of the wafer-level packaging structure.

In an optional implementation, the minimum distance between the wall film on the side in the same direction as the cutting side and the inner wall of the cavity is in the range of 20 μm to 60 μm. Setting the minimum distance within the above range can better achieve miniaturization of the wafer-level packaging structure.

In an optional implementation, the filling groove is a V-shaped groove, a positive trapezoidal groove, an inverted trapezoidal groove or a rectangular groove. It can enter various filling grooves better, and the second filling part can be fully connected with the wall surface of the filling groove to enhance the bonding strength between the wall film and the top film.

In an optional implementation, the cavity, the avoidance groove and the filling groove are formed by exposure and development or laser drilling.

In a second aspect, an embodiment of the present application provides a wafer-level packaging structure, comprising: a substrate layer, a wall film, and a top film stacked in sequence. The wafer-level packaging structure has a cutting side. The cutting side is formed on the same side surface of the substrate layer and the top film; or, the cutting side is formed on the same side surface of the substrate layer, the wall film, and the top film. The wall film has a cavity for placing functional devices, and the substrate layer and the top film are respectively covered at opposite ends of the cavity. The top surface of the wall film between the cavity and the cutting side has a filling groove, and the top film has a second filling portion that at least partially fills the filling groove.

The wafer-level packaging structure provided by the embodiment of the present application includes a substrate layer, a wall film and a top film stacked in sequence. When the top film is set on the wall film, the top film has a certain fluidity and ductility, and the top film can be partially squeezed into the filling groove, that is, the second filling part enters the filling groove, and the second filling part and the wall surface of the filling groove are fully connected, increasing the bonding area between the wall film and the top film to improve the bonding strength. When the wafer is cut, the shear force in the direction perpendicular to the cutting side can be blocked or reduced. The wall film and the top film are not easily pulled apart by the cutting stress, which improves the structural reliability and meets the miniaturization of the wafer-level packaging structure. The top film material at the cavity sinks or does not sink within an acceptable range, so that the functional device in the cavity can work normally without being affected.

In an optional implementation, the wall film has an avoidance groove on the side in the same direction as the cutting side, and the side of the avoidance groove is spaced apart from the cutting side. When the wafer is cut, the cutting knife passes through the top film and the substrate layer without touching the wall film, and the avoidance groove of the wall film can avoid the cutting knife. The avoidance groove can block or reduce the positive stress of cutting from being transmitted to the wall film near the cavity, reduce the delamination between the wall film and the substrate layer, make the wall film and the substrate layer better combined, and make the cavity more sealed, thereby improving the structural reliability and production yield.

In an optional implementation, the filling groove is a V-shaped groove, a regular trapezoidal groove, an inverted trapezoidal groove or a rectangular groove. The top film part material can enter various filling grooves well, and the second filling part can be fully connected with the wall surface of the filling groove to improve the bonding strength between the wall film and the top film.

In an optional implementation, the cavity and the filling groove are formed by exposure and development or laser drilling.

In a third aspect, an embodiment of the present application provides an electronic device, including a circuit board and a wafer-level packaging structure of any of the above embodiments, wherein the wafer-level packaging structure is arranged on the circuit board.

In a fourth aspect, an embodiment of the present application provides a method for manufacturing a wafer-level packaging structure, comprising the following steps:

Providing a substrate layer, on which connected electroplating lines and pads are arranged, wherein the electroplating lines are located within the cutting path;

A wall film is arranged on the substrate layer, wherein the wall film has cavities and first grooves which are distributed at intervals, and the edge of the cutting path passes through the first groove;

A top film is arranged on the wall film to obtain a wafer;

The wafer is cut along the cutting path, and a portion of the first groove forms an avoidance groove of the wall film, thereby obtaining a wafer-level packaging structure.

According to the manufacturing method of the wafer-level packaging structure provided in the embodiment of the present application, when cutting the wafer along the cutting path, the cutting knife passes through the position of the top film and the substrate layer without touching the wall film. The first groove of the wall film can avoid the cutting knife. The first groove can block or reduce the cutting positive stress transmitted to the wall film near the cavity, reduce the delamination between the wall film and the substrate layer, make the wall film and the substrate layer better combined, better seal the cavity, and improve the structural reliability and production yield.

In an optional implementation, the wall film covers the electroplating line. During the process of forming and connecting the conductive pillars with pads, the wall film covers the electroplating line, which can reduce the situation of over-plating.

In an optional implementation, the electroplating line is located in the first groove. The first groove of the wall film can avoid the cutting knife and reduce the delamination between the wall film and the substrate layer.

In an optional implementation, the top film has a second groove, the second groove is located in the cutting road, and the width of the second groove is less than or equal to The width of the cutting path. When cutting the wafer, the stress on the top film and the wall film is smaller, which reduces the wafer warping when cutting the wafer and reduces the risk of cracking and delamination.

In an optional implementation, the top film covers the cutting path and is arranged opposite to the electroplating line. When the wafer is cut along the cutting path, the first groove of the wall film can avoid the cutting knife, and the first groove can block or reduce the cutting positive stress transmitted to the wall film near the cavity, thereby reducing the delamination between the wall film and the substrate layer.

In an optional implementation, when a top film is arranged on the wall film, part of the material of the top film is filled in the first groove, which can enhance the bonding strength between the wall film and the top film, so that the wall film and the top film are not easily pulled apart by the cutting stress during wafer cutting, thereby enhancing the structural reliability.

In an optional implementation, the wall film is formed by laminating, exposing and developing on the substrate layer, and the top film is formed by laminating, exposing and developing on the wall film.

In an optional implementation, the wall film is formed by pasting a film on the base material layer and punching holes with a laser, and the top film is formed by pasting a film on the wall film and punching holes with a laser.

In an optional implementation, when the top surface of the wall film between the cavity and the avoidance groove has a filling groove, the filling groove is formed by exposure and development, and a first mask is configured in the exposure step, and the width of the first mask in the area corresponding to the filling groove is smaller than the minimum resolution width of the material of the wall film. A filling groove with a depth smaller than the thickness of the wall film can be formed on the wall film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a top view of a partial structure of a wafer in the related art;

(a) and (b) in FIG2 are respectively a cross-sectional view of the wafer of FIG1 along line A-A when it is not cut, and a cross-sectional view of the wafer-level packaging structure obtained by cutting;

(a) and (b) in FIG3 are cross-sectional views of a wafer before and after cutting to obtain a wafer-level packaging structure in another related art, respectively;

FIG4 is a top view of a portion of the structure of a wafer provided in an embodiment of the present application;

(a) and (b) in FIG5 are respectively a cross-sectional view of the wafer of FIG4 along the B-B line when it is not cut, and a cross-sectional view of the wafer-level packaging structure obtained by cutting;

FIG6 (a) and (b) are cross-sectional views of a wafer before and after cutting to obtain a wafer-level packaging structure provided by another embodiment of the present application, respectively;

(a) to (d) in FIG. 7 are schematic structural diagrams of different steps of setting a wall film on a substrate layer;

(a) to (c) in FIG8 are schematic diagrams of structures of different steps of setting a top film on a wall film;

FIG9 (a) and (b) are cross-sectional views of a wafer before and after cutting to obtain a wafer-level packaging structure provided by another embodiment of the present application, respectively;

FIG10 (a) and (b) are cross-sectional views of a wafer before and after cutting to obtain a wafer-level packaging structure provided by another embodiment of the present application, respectively;

(a) and (b) in FIG. 11 are cross-sectional views of a wafer provided in another embodiment of the present application before and after cutting to obtain a wafer-level packaging structure, respectively.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. Although the description of the present application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to the implementation mode. On the contrary, the purpose of introducing the application in conjunction with the implementation mode is to cover other options or modifications that may be extended based on the claims of the present application. In order to provide a deep understanding of the present application, many specific details will be included in the following description. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It should be understood that in the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; The terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present application.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The character "/" in this article generally indicates that the objects associated with each other are in an "or" relationship.

References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

Referring to (a) and (b) in FIG. 1 and FIG. 2, in the wafer-level packaging structure of the related art, a wall film 2 and a top film 3 are sequentially arranged on the substrate layer 1, the wall film 2 has a cavity 2a, and the substrate layer 1 and the top film 3 are respectively covered at the upper and lower ends of the cavity 2a. In order to reduce the delamination between the substrate layer 1, the wall film 2 and the top film 3 during the manufacturing process, a large-area wall film 2 support and a small-area cavity 2a design are usually adopted, which will occupy a large area and limit the reduction of the size of the packaging structure. In the process of setting the top film 3 on the wall film 2, the top film 3 is in a semi-cured state, the thickness of the top film 3 will be flattened to a certain extent, and part of the top film 3 material will be squeezed into the cavity 2a. If a wall film 2 with an overly large area and a cavity 2a with a small area is used, more top film 3 material will be squeezed into the cavity 2a, and the top film 3 is easy to sink and touch the functional device in the cavity 2a (not shown), thereby affecting the performance of the functional device. The production yield and application reliability of the conventional wafer-level packaging structure are poor.

FIG1 schematically shows two small chips C on a wafer. In practice, there are hundreds to tens of thousands of small chips C on a wafer, and there is a cutting path 4 of a certain width between the small chips C. After the whole wafer is processed, a cutting knife 4a is used to cut the wafer along the cutting path 4 to separate a single small chip (i.e., wafer-level packaging structure) C. This is wafer cutting.

Referring to (a) and (b) in FIG. 1 and FIG. 2 , the related art provides a wafer-level packaging structure, including a substrate layer 1, a wall film 2 and a top film 3 stacked in sequence, and the wall film 2 has a cavity 2a. The wall film 2 and the top film 3 are both covered on the cutting road 4. When the wafer is cut, the overall warping of the wafer is large, and the operability is poor. Due to the different moduli of the wall film 2 and the substrate layer 1, the cutting positive stress during wafer cutting can easily cause delamination between the wall film 2 and the substrate layer 1, which will generate a tearing force on the wall film 2, causing the wall film 2 to tear and fail, and even the cavity 2a is not airtight.

Referring to (a) and (b) in FIG. 3 , the related art provides another wafer-level packaging structure, including a substrate layer 1′, a wall film 2′ and a top film 3′ which are stacked in sequence, and the wall film 2′ has a cavity 2a′. The top film 3′ is provided with a groove 3a′ at the cutting path 4′, and only the wall film 2′ covers the cutting path 4′. When the wafer is cut, the wafer warping can be reduced, and the stress during cutting can be reduced to cause the delamination of the wall film 2′ and the top film 3′. When the wafer is cut, the positive stress of cutting can easily cause the delamination between the wall film 2′ and the substrate layer 1′, which will generate a tearing force on the wall film 2′, causing the wall film 2′ to tear and fail, and even the cavity 2a′ is not airtight. The width of the groove 3a′ is greater than the width of the cutting path 4′, which reduces the bonding area between the wall film 2′ and the top film 3′, and the wall film 2′ and the top film 3′ are easily delaminated. When the top film 3′ is formed by exposure and development, the developer can easily attack the contact position between the wall film 2′ and the top film 3′, causing the wall film 2′ and the top film 3′ to delaminate.

In order to solve the problem of easy delamination between the wall film and the substrate layer during the manufacturing process of the wafer-level packaging structure, referring to (a) and (b) in Figures 4 and 5, an embodiment of the present application provides a wafer-level packaging structure 100, including: a substrate layer 10, a wall film 20 and a top film 30 stacked in sequence. The wafer-level packaging structure 100 has a cutting side surface 100a, and the cutting side surface 100a is formed on the same side surface of the substrate layer 10 and the top film 30. The wall film 20 has a cavity 21 for placing a functional device (not shown in the figure), and the substrate layer 10 and the top film 30 are respectively covered at opposite ends 211 of the cavity 21. The wall film 20 has an avoidance groove 22 on one side in the same direction as the cutting side surface 100a, and the side surface 221 of the avoidance groove 22 is spaced apart from the cutting side surface 100a (the spacing distance is d1).

The wafer-level packaging structure 100 can be used for wafer-level packaging of SAW filters or other similar devices. Exemplarily, when applied to SAW filters, the functional device placed in the cavity 21 of the wafer-level packaging structure 100 is an interdigital transducer. The substrate layer 10 is a substrate made of piezoelectric effect material. The wall film 20 and the top film 30 can be made of polymers (such as polyimide, epoxy resin), silicon or glass. The wafer-level packaging structure 100 can also be used in micro electro mechanical systems (MEMS). Fabrication of MEMS chips.

Referring to (a) and (b) in FIG5 , the surface that contacts the cutting blade 40a during wafer cutting and is formed on the wafer-level packaging structure 100 is the cutting side surface 100a. The cutting side surface 100a is formed on the same side surface of the base material layer 10 and the top film 30, that is, when the wafer is cut, the cutting blade 40a contacts the base material layer 10 and the top film 30, but does not contact the wall film 20, and the cutting side surface 100a is the side surface 10a of the base material layer 10 and the side surface 30a of the top film 30.

The cavity 21 of the wall film 20 can be understood as an opening, and the opposite ends of the opening are ports. The wall film 20 is sandwiched between the substrate layer 10 and the top film 30, and the two ports are covered by the substrate layer 10 and the top film 30. The top film 30 can be partially collapsed at the corresponding port, or the top film 30 is not deformed and collapsed. The wall film 20 can be provided with a plurality of cavities 21, and each cavity 21 can be placed with a functional device. The plurality of cavities 21 can be distributed on the wall film 20 in a predetermined manner. The side of the avoidance groove 22 refers to the side surface of the avoidance groove 22 in the direction perpendicular to the cutting side surface 100a. The top film 30 can be a single-layer or multi-layer material.

The wafer-level packaging structure 100 provided in the embodiment of the present application comprises a substrate layer 10, a wall film 20 and a top film 30 which are stacked in sequence. The wall film 20 has an avoidance groove 22 on the side in the same direction as the cutting side surface 100a, and the side surface 221 of the avoidance groove 22 is spaced from the cutting side surface 100a. When the wafer is cut, the cutting knife 40a passes through the position of the top film 30 and the substrate layer 10 without touching the wall film 20. The avoidance groove 22 of the wall film 20 can avoid the cutting knife 40a. The avoidance groove 22 can block or reduce the transmission of the cutting positive stress to the wall film 20 near the cavity 21, reduce the delamination between the wall film 20 and the substrate layer 10, make the wall film 20 and the substrate layer 10 better combined, make the cavity 21 more sealed, and improve the structural reliability and production yield.

In order to meet the requirements of miniaturization of the wafer-level packaging structure 100 and reduce the transmission of the cutting normal stress, referring to (a) and (b) in FIG5 , in some embodiments, the distance d1 between the side 221 of the avoidance groove 22 and the cutting side 100a ranges from 2 μm to 10 μm. The distance d1 between the side 221 of the avoidance groove 22 and the cutting side 100a is the width of the avoidance groove 22 in the direction perpendicular to the cutting side 100a. The width of the avoidance groove 22 is set to be small so that the cutting blade 40a does not touch the wall film 20 during wafer cutting.

Exemplarily, the distance d1 between the side surface 221 of the avoidance groove 22 and the cutting side surface 100 a may be 2 μm, 5 μm, 6 μm, 7 μm, 9 μm, 10 μm, etc., which can be set as required.

There are different ways to implement the avoidance groove 22. In the embodiment shown in FIG5, the avoidance groove 22 is arranged through the wall film 20 along the thickness direction of the wall film 20, that is, when the wall film 20 is arranged on the substrate layer 10, the substrate layer 10 at the avoidance groove 22 is exposed.

In the embodiment shown in FIG6 , the avoidance groove 22 is formed by extending the top surface of the wall film 20 to a predetermined depth, and the bottom surface of the avoidance groove 22 is spaced apart from the substrate layer 10. The top surface of the wall film 20 refers to the side of the wall film 20 that contacts the top film 30. The bottom surface of the avoidance groove 22 refers to the side of the avoidance groove 22 that is close to the substrate layer 10. When the wall film 20 is set on the substrate layer 10, the substrate layer 10 at the avoidance groove 22 is not exposed. The above two methods are selected as needed.

In some embodiments, referring to (a) and (b) in FIG. 5 , the top film 30 has a first filling portion 31 that at least partially fills the avoidance groove 22, and the first filling portion 31 covers the side of the avoidance groove 22. When the top film 30 is set on the wall film 20, the top film 30 has a certain fluidity and ductility, and part of the material of the top film 30 can be squeezed into the avoidance groove 22, that is, the first filling portion 31 enters the avoidance groove 22 and covers the side of the avoidance groove 22, and the first filling portion 31 and the side of the avoidance groove 22 have a certain overlap. When using exposure and development, the developer is not easy to attack the contact position between the wall film 20 and the top film 30. It can enhance the bonding force between the wall film 20 and the top film 30, so that the wall film 20 and the top film 30 are not easily pulled apart by the cutting stress during wafer cutting, thereby improving the structural reliability.

In order to meet the requirements of miniaturization of the wafer-level packaging structure 100 and to form a good bonding force between the wall film 20 and the top film 30, referring to (a) and (b) in FIG5 , in some embodiments, the top surface of the wall film 20 between the cavity 21 and the avoidance groove 22 has a filling groove 23, the depth of the filling groove 23 is less than the thickness of the wall film 20, and the top film 30 has a second filling portion 32 that is at least partially filled in the filling groove 23. The top surface of the wall film 20 refers to the side of the wall film 20 that contacts the top film 30. The depth direction of the filling groove 23 is the same as the thickness direction of the wall film 20, which is the up and down direction in FIG5 .

When the top film 30 is set on the wall film 20, the top film 30 has a certain fluidity and ductility. The top film 30 can be partially squeezed into the filling groove 23, that is, the second filling part 32 enters the filling groove 23, and the second filling part 32 is fully connected to the wall surface of the filling groove 23, increasing the bonding area between the wall film 20 and the top film 30 to improve the bonding strength. When the wafer is cut, it can block or reduce the shear force in the direction perpendicular to the cutting side 100a, reduce the stress concentration effect, and the wall film 20 and the top film 30 are not easily pulled apart by the cutting stress, thereby improving the structural reliability and meeting the miniaturization of the wafer-level packaging structure 100. The material of the top film 30 at the cavity 21 sinks or does not sink within an acceptable range, so that the functional device in the cavity 21 can work normally without being affected. Among them, the filling groove 23 can be set to one or more, and accordingly, the top film 30 has one or more second filling parts 32 filled in the corresponding filling groove 23.

As shown in FIG. 2 , in the wafer-level packaging structure of the related art, the wall film 2 is connected to the inner side 2b of the cavity 2a on the same side as the cutting side. The minimum spacing d2' of the wall is usually in the range of 60μm to 100μm. Only when the minimum spacing d2' is met can the structure be safe, and a certain bonding force can be formed between the wall film 2 and the top film 3 to avoid delamination of the wall film 2 and the top film 3 during wafer cutting. If the minimum spacing d2' is less than 60μm, the wall film 2 and the top film 3 are easily pulled apart and fail due to the cutting stress during wafer cutting, which shows that the wafer-level packaging structure of the related technology is difficult to be further miniaturized.

In order to achieve miniaturization of the wafer-level packaging structure 100, in some embodiments, referring to (b) in FIG. 5 , the top surface of the wall film 20 between the cavity 21 and the avoidance groove 22 has a filling groove 23, the depth of the filling groove 23 is less than the thickness of the wall film 20, and the top film 30 has a second filling portion 32 at least partially filled in the filling groove 23. The minimum distance d2 between the wall film 20 and the inner wall of the cavity 21 on the side 221 in the same direction as the cutting side surface 100a is in the range of 20 μm to 60 μm.

The minimum distance d2 between the side 221 of the wall film 20 in the same direction as the cutting side 100a and the inner wall of the cavity 21 refers to the width of the local area of the wall film 20 with the filling groove 23 in the direction perpendicular to the cutting side 100a. By setting the minimum distance d2 within the above range, the wafer-level packaging structure 100 can be miniaturized better. The material of the top film 30 at the cavity 21 sinks or does not sink within an acceptable range, so that the functional devices in the cavity 21 can work normally without being affected.

In some embodiments, the minimum distance d2 between the wall film 20 on the side 221 in the same direction as the cutting side 100a and the inner wall of the cavity 21 is in the range of 30 μm to 50 μm, which can better meet the miniaturization of the wafer-level packaging structure 100 and form a good bonding force between the wall film 20 and the top film 30. Exemplarily, the minimum distance d2 between the wall film 20 on the side 221 in the same direction as the cutting side 100a and the inner wall of the cavity 21 can be 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc.

There are multiple optional implementations when setting the filling groove 23. The filling groove 23 can be a V-shaped groove, a regular trapezoidal groove, an inverted trapezoidal groove or a rectangular groove. Among them, the regular trapezoidal groove refers to a groove structure with a trapezoidal cross section and a bottom side of the trapezoid longer than the top side. The inverted trapezoidal groove refers to a groove structure with a trapezoidal cross section and a bottom side of the trapezoid shorter than the top side.

When the top film 30 is arranged on the wall film 20 , part of the material of the top film 30 can enter the various filling grooves 23 well, and the second filling portion 32 can be fully connected with the wall surface of the filling groove 23 to enhance the bonding force between the wall film 20 and the top film 30 .

There are different ways to form holes on the wall film 20. The cavity 21, the avoidance groove 22 and the filling groove 23 are formed by exposure and development or laser drilling. Exposure and development is to expose the photosensitive polymer of the wall film 20 or the top film 30 to produce a photochemical reaction, change the solubility in the developer, use the developer to dissolve the unnecessary part of the wall film 20 or the top film 30, and transfer the pattern on the mask to the wall film 20 or the top film 30. Laser drilling is to use a high-power laser beam to irradiate the processed substrate, so that the processed substrate is instantly heated to the vaporization temperature, evaporated to form holes or cavities.

Referring to (a) and (b) in FIG. 4 and FIG. 5 , an embodiment of the present application provides a wafer-level packaging structure 100, comprising: a substrate layer 10, a wall film 20 and a top film 30 stacked in sequence. The wafer-level packaging structure 100 has a cutting side surface 100a. The cutting side surface 100a is formed on the same side surface of the substrate layer 10 and the top film 30; or, the cutting side surface 100a is formed on the same side surface of the substrate layer 10, the wall film 20 and the top film 30. The wall film 20 has a cavity 21 for placing a functional device (not shown), and the substrate layer 10 and the top film 30 are respectively covered at opposite ends 211 of the cavity 21. The top surface of the wall film 20 between the cavity 21 and the cutting side surface 100a has a filling groove 23, and the top film 30 has a second filling portion 32 that at least partially fills the filling groove 23.

The top surface of the wall film 20 refers to the side of the wall film 20 that contacts the top film 30 .

The cutting side surface 100a is formed on the same side surface of the base material layer 10 and the top film 30, that is, when the wafer is cut, the cutting blade 40a is in contact with the base material layer 10 and the top film 30, but not with the wall film 20. The cutting side surface 100a is formed on the same side surface of the base material layer 10, the wall film 20 and the top film 30, that is, when the wafer is cut, the cutting blade 40a is in contact with the base material layer 10, the wall film 20 and the top film 30.

The wafer-level packaging structure 100 provided in the embodiment of the present application includes a substrate layer 10, a wall film 20 and a top film 30 stacked in sequence. When the top film 30 is arranged on the wall film 20, the top film 30 has a certain fluidity and ductility, and the top film 30 can be partially squeezed into the filling groove 23, that is, the second filling part 32 enters the filling groove 23, and the second filling part 32 is fully connected to the wall surface of the filling groove 23, increasing the bonding area between the wall film 20 and the top film 30 to improve the bonding strength, and can block or reduce the shear force in the direction perpendicular to the cutting side 100a when the wafer is cut. The wall film 20 and the top film 30 are not easily pulled apart by the cutting stress, thereby improving the structural reliability and meeting the miniaturization of the wafer-level packaging structure 100. The material of the top film 30 at the cavity 21 sinks or does not sink within an acceptable range, so that the functional device in the cavity 21 can work normally without being affected.

It can be understood that when setting the wafer-level packaging structure 100 , reference may be made to the various embodiments of the wafer-level packaging structure 100 described above, which will not be described in detail here.

5 and 6 , an embodiment of the present application provides an electronic device, including a circuit board and a wafer-level packaging structure 100 according to any of the above embodiments, wherein the wafer-level packaging structure 100 is disposed on the circuit board.

Among them, the electronic devices can be mobile phones, tablet computers, wearable devices, cameras, multimedia players, e-book readers, personal computers, laptops, headphones, speakers, large-screen display devices, vehicle-mounted devices, etc.

Exemplarily, the wafer-level packaging structure 100 is applied to a SAW filter, which is disposed on a circuit board of a mobile phone to filter unnecessary signals and noises and improve the quality of received signals.

The electronic device provided in the embodiment of the present application has the above-mentioned wafer-level packaging structure 100 and has the same technical effect.

The embodiment of the present application provides a method for manufacturing a wafer-level packaging structure 100, comprising the following steps:

Referring to FIG. 4 and FIG. 7 (a), a substrate layer 10 is provided, on which a plating line 11 and a pad 12 connected to each other are provided, and the plating line 11 is located in a cutting path 40;

Referring to (b) to (d) of FIG. 7 , a wall film 20 is disposed on the substrate layer 10 , and the wall film 20 has cavities 21 and first grooves 22 a that are spaced apart, and the edge of the cutting path 40 passes through the first groove 22 a ;

Referring to (a) to (c) in FIG. 8 , a top film 30 is disposed on the wall film 20 to obtain a wafer;

5 (a) and (b), the wafer is cut along the cutting road 40, and a portion of the first groove 22a forms the avoidance groove 22 of the wall film 20, thereby obtaining a wafer-level packaging structure 100.

In the manufacturing method of the wafer-level packaging structure 100 provided in the embodiment of the present application, when cutting the wafer along the cutting path 40, the cutting knife 40a passes through the position of the top film 30 and the substrate layer 10 without touching the wall film 20, and the first groove 22a of the wall film 20 can avoid the cutting knife 40a. The first groove 22a can block or reduce the cutting positive stress transmitted to the wall film 20 near the cavity 21, reduce the delamination between the wall film 20 and the substrate layer 10, make the wall film 20 and the substrate layer 10 better combined, and the cavity 21 is more sealed, thereby improving the structural reliability and production yield.

Wherein, referring to FIG. 4, the electroplating line 11 on the substrate layer 10 is connected to a plurality of pads 12, a first opening 24 is respectively arranged at each pad 12 on the wall film 20, and a second opening 34 is respectively arranged at each pad 12 on the top film 30, and the pad 12, the first opening 24 and the second opening 34 are respectively arranged, and the first opening 24 and the second opening 34 are correspondingly connected. When the pad 12 is electroplated, the plated metal is used as the anode, the electroplating line 11 and the pad 12 are electrically connected and used as the cathode, the pad 12 and the anode are placed in the electroplating solution, and a predetermined power supply is connected to form a conductive column (not shown) filled in the first opening 24 and the second opening 34 and connected to the pad 12. The conductive column can be made of copper or other metals. The end of the conductive column exposed from the top film 30 is used to connect the solder joint (not shown), and the solder joint is used to connect to the external circuit. The solder joint can be made of tin or other metals and can be set to a spherical or other shape. The electroplating line 11 includes a main line 111 and a plurality of branch lines 112 connected to the main line 111 . The main line 111 is located in the cutting path 40 . The branch lines 112 are used to connect the main line 111 and the pads 12 adjacent to the branch lines 112 .

In some embodiments, the wafer-level packaging structure 100 is applied to a SAW filter, and the substrate layer 10 having the electroplating lines 11 and the pads 12 is manufactured using a conventional front-end wafer manufacturing process.

There are different ways to set the wall film 20 at the cutting path 40. The first way to set the wall film 20 at the cutting path 40: refer to (a) in FIG. 5 , the wall film 20 covers the electroplating line 11. During the process of forming the conductive pillar connected to the pad 12, the wall film 20 covers the electroplating line 11, and the electroplating liquid will not contact the electroplating line 11 too much, so as to seal and protect the electroplating line 11 and reduce the overflow plating.

The second implementation method of setting the wall film 20 at the cutting path 40: Referring to FIG9 , the electroplating line 11 is located in the first groove 22a. When the wafer is cut along the cutting path 40, the first groove 22a of the wall film 20 can avoid the cutting knife 40a, and the first groove 22a can block or reduce the cutting positive stress transmitted to the wall film 20 near the cavity 21, thereby reducing the delamination between the wall film 20 and the substrate layer 10.

There are different implementations for setting the top film 30 at the cutting path 40. The first implementation for setting the top film 30 at the cutting path 40: Referring to (a) in FIG. 5 , the top film 30 has a second groove 33, the second groove 33 is located in the cutting path 40, and the width d3 of the second groove 33 is less than or equal to the width d4 of the cutting path 40. When the width d3 of the second groove 33 is less than the width d4 of the cutting path 40, only the two side edges of the second groove 33 of the top film 30 are affected by the cutting blade 40a, and the cutting blade 40a cuts off the two side edges of the second groove 33, and makes a larger bonding area between the wall film 20 and the top film 30 to improve the bonding strength. When the width d3 of the second groove 33 is equal to the width d4 of the cutting path 40, the cutting blade 40a does not act on the top film 30 when cutting the wafer. With these two methods, the stress of the top film 30 and the wall film 20 is smaller when cutting the wafer, which reduces the warping of the wafer when cutting the wafer, and reduces the risk of cracking and delamination. The second groove 33 of the wall film 20 and the cutting path 40 are arranged correspondingly, which can improve the feasibility of electroplating, ball implantation, cutting, and wafer testing (chip probing, CP).

The second implementation method of setting the top film 30 at the cutting street 40: Referring to FIG9 , the top film 30 covers the cutting street 40 and is arranged opposite to the electroplating line 11. When the wafer is cut along the cutting street 40, the first groove 22a of the wall film 20 can avoid the cutting knife 40a, and the first groove 22a can block or reduce the cutting positive stress transmitted to the wall film 20 near the cavity 21, thereby reducing the delamination between the wall film 20 and the substrate layer 10.

It can be understood that the two implementations of setting the wall film 20 at the cutting road 40 and the two implementations of setting the top film 30 at the cutting road 40 can be used in any combination. For example, in the embodiment shown in FIG5, the wall film 20 covers the electroplating line 11, and the top film 30 has a second groove 33, and the second groove 33 is located in the cutting road 40. In the embodiment shown in FIG9, the electroplating line 11 is located in the first groove 22a, and the top film 30 covers the cutting road 40 and is arranged opposite to the electroplating line 11. In the embodiment shown in FIG10, the electroplating line 11 is located in the first groove 22a, and the top film 30 has a second groove 33, and the second groove 33 is located in the cutting road 40, and the first groove 22a and the second groove 33 are connected. In the embodiment shown in FIG11, the wall film 20 covers the electroplating line 11, and the top film 30 covers the cutting road 40 and is arranged opposite to the electroplating line 11.

In some embodiments, referring to (a) and (b) in FIG. 5 , when the top film 30 is disposed on the wall film 20, part of the material of the top film 30 is filled in the first groove 22a. When the top film 30 is disposed on the wall film 20, the top film 30 has a certain fluidity and ductility, and the top film 30 can be partially squeezed into the first groove 22a, and part of the top film 30 enters the first groove 22a and covers the side of the first groove 22a. When exposure and development are adopted, the developer is not easy to attack the contact position between the wall film 20 and the top film 30. The bonding force between the wall film 20 and the top film 30 can be improved, so that the wall film 20 and the top film 30 are not easily pulled apart by the cutting stress when the wafer is cut, thereby improving the structural reliability.

There are different ways to form holes on the wall film 20 and the top film 30. The first way to form holes on the film is: the wall film 20 is formed by laminating, exposing and developing on the substrate layer 10, and the top film 30 is formed by laminating, exposing and developing on the wall film 20. Exposure and development is to expose the photosensitive polymer of the wall film 20 or the top film 30 to cause a photochemical reaction, change the solubility in the developer, use the developer to dissolve the unnecessary part of the wall film 20 or the top film 30, and transfer the pattern on the mask to the wall film 20 or the top film 30.

Among them, photosensitive polymers are divided into positive photoresists and negative photoresists according to their solubility after exposure. The exposed part of the positive photoresist dissolves in the developer, and the unexposed part of the positive photoresist solidifies. The unexposed part of the negative photoresist dissolves in the developer, and the exposed part of the negative photoresist solidifies.

Exemplarily, in the embodiments shown in FIG. 7 and FIG. 8, the photosensitive polymer adopts a negative photoresist, and a first mask plate 210 for molding the wall film 20 and a second mask plate 220 for molding the top film 30 are configured. Referring to (c) and (d) in FIG. 7, the first groove 22a and the cavity 21 on the first mask plate 210 corresponding to the wall film 20 are set as a light-shielding area 211, and the area that needs molding and curing is set as a light-transmitting area 212. Referring to (b) and (c) in FIG. 8, the second groove 33 on the second mask plate 220 corresponding to the top film 30 is set as a light-shielding area 221, and the area that needs molding and curing is set as a light-transmitting area 222.

Referring to (a) and (b) in FIG7 , when forming the wall film 20, the film is first pasted on the substrate layer 10; in conjunction with (c) in FIG7 , the initial wall film 20 is then exposed under the first mask plate 210, and the negative photoresist corresponding to the first groove 22a and the cavity 21 is not exposed; in conjunction with (d) in FIG7 , the unexposed portion is finally dissolved in the developer, thereby manufacturing the wall film 20 having the first groove 22a and the cavity 21. Referring to (a) in FIG8 , when forming the top film 30, the film is first pasted on the wall film 20; in conjunction with (b) in FIG8 , the initial top film 30 is then exposed under the second mask plate 220, and the negative photoresist corresponding to the second groove 33 is not exposed; in conjunction with (c) in FIG8 , the unexposed portion is finally dissolved in the developer, thereby manufacturing the top film 30 having the second groove 33.

In addition, the photosensitive polymer uses a positive photoresist, and is configured with a first mask plate 210 for molding the wall film 20 and a second mask plate 220 for molding the top film 30. The first groove 22a and the cavity 21 on the first mask plate 210 corresponding to the wall film 20 are set as light-transmitting areas, and the areas that need molding and curing are set as light-shielding areas; the second groove 33 on the second mask plate 220 corresponding to the top film 30 is set as a light-transmitting area, and the areas that need molding and curing are set as light-shielding areas. The molding process is similar and will not be repeated.

The second method of forming a cavity on the film is: the wall film 20 is formed by laminating the substrate layer 10 and punching holes with a laser, and the top film 30 is formed by laminating the wall film 20 and punching holes with a laser. Laser punching is to irradiate the processed substrate with a high-power laser beam, so that the processed substrate is instantly heated to the vaporization temperature, and evaporates to form holes or cavities.

In some embodiments, referring to (c) and (d) in FIG. 7 , when the top surface of the wall film 20 between the cavity 21 and the avoidance groove 22 has a filling groove 23, the filling groove 23 is formed by exposure and development, and a first mask plate 210 is configured in the exposure step, and the width d5 of the first mask plate 210 in the area 211a corresponding to the filling groove 23 is smaller than the minimum resolution width of the material of the wall film 20. This solution can form a filling groove 23 on the wall film 20 with a depth smaller than the thickness of the wall film 20. The minimum resolution width of the wall film 20 material refers to the minimum width size of the hole or solid area that can be produced when the wall film 20 is produced by exposure and development.

Exemplarily, the photosensitive polymer uses a negative resist, and the first mask plate 210 is set as a light shielding area 211a at the filling groove 23 of the wall film 20. The minimum resolution width of the wall film 20 material is 20um, and the width of the light shielding area 211a corresponding to the filling groove 23 on the first mask plate 210 is set to 5um to 15um. When the light shielding area 211a with a width lower than the minimum resolution width of the wall film 20 material is used for shielding, the light sources on both sides of the light shielding area 211a are scattered and reflected, so that the bottom material of the wall film 20 corresponding to the light shielding area 211a is solidified, but the top of the wall film 20 at this position is blocked and cannot be effectively photocured, thereby forming a wall film 20 with a depth deeper than the wall film 20. The thickness of the filling groove 23 is small. The width of the light shielding area on the first mask plate 210 corresponding to the filling groove 23 of the wall film 20 can be 5um, 8um, 10um, 12um, 15um, etc.

In addition, the photosensitive polymer uses positive resist, and the filling groove 23 corresponding to the wall film 20 on the first mask plate 210 is set as a light-transmitting area. When the light-transmitting area with a width lower than the minimum resolution width of the wall film 20 material is used for light transmission, a filling groove 23 with a depth smaller than the thickness of the wall film 20 can also be formed on the wall film 20.

5(a), after the filling groove 23 is formed on the top surface of the wall film 20, the top film 30 is arranged on the wall film 20, so that part of the top film 30 is squeezed into the filling groove 23, that is, the second filling portion 32 enters the filling groove 23, and the second filling portion 32 is fully connected to the wall surface of the filling groove 23, thereby increasing the bonding area between the wall film 20 and the top film 30 to enhance the bonding strength. When the wafer is cut, the shear force in the direction perpendicular to the cutting side surface 100a can be blocked or reduced, and the wall film 20 and the top film 30 are not easily pulled apart by the cutting stress.

It can be understood that in the method for manufacturing the wafer-level packaging structure 100 , reference may be made to the various structural embodiments of the wafer-level packaging structure 100 described above, which will not be described in detail herein.

Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A wafer-level packaging structure, characterized in that it comprises: a substrate layer, a wall film and a top film stacked in sequence;

The wafer-level packaging structure has a cutting side surface, and the cutting side surface is formed on the same side surface of the substrate layer and the top film;

The wall film has a cavity for placing functional devices, and the substrate layer and the top film are respectively covered at two opposite ends of the cavity;

The wall film has an avoidance groove on one side in the same direction as the cutting side surface, and the side surface of the avoidance groove is spaced apart from the cutting side surface.
The wafer-level packaging structure according to claim 1 is characterized in that the spacing between the side of the avoidance groove and the cutting side is in a range of 2 μm to 10 μm.
The wafer-level packaging structure according to claim 1 or 2, characterized in that the avoidance groove is arranged through the wall film along the thickness direction of the wall film;

Alternatively, the avoidance groove is formed by extending the top surface of the wall film to a predetermined depth, and the bottom surface of the avoidance groove is spaced apart from the substrate layer.
The wafer-level packaging structure according to any one of claims 1 to 3 is characterized in that the top film has a first filling portion that at least partially fills the avoidance groove, and the first filling portion covers the side surface of the avoidance groove.
The wafer-level packaging structure according to any one of claims 1 to 4 is characterized in that a filling groove is provided on the top surface of the wall film between the cavity and the avoidance groove, the depth of the filling groove is less than the thickness of the wall film, and the top film has a second filling portion at least partially filled in the filling groove.
The wafer-level packaging structure according to claim 5, characterized in that a minimum spacing between the wall film on a side in the same direction as the cutting side and an inner wall of the cavity ranges from 20 μm to 60 μm.
The wafer-level packaging structure according to claim 5 or 6 is characterized in that the filling groove is a V-shaped groove, a regular trapezoidal groove, an inverted trapezoidal groove or a rectangular groove.
The wafer-level packaging structure according to any one of claims 5 to 7 is characterized in that the cavity, the avoidance groove and the filling groove are formed by exposure and development or laser drilling.
A method for manufacturing a wafer-level packaging structure according to any one of claims 1 to 8, characterized in that it comprises the following steps:

Providing a substrate layer, on which a connected electroplating line and a pad are provided, wherein the electroplating line is located within the cutting path;

A wall film is arranged on the substrate layer, wherein the wall film has cavities and first grooves that are spaced apart, and the edge of the cutting path passes through the first groove;

Arranging a top film on the wall film to obtain a wafer;

The wafer is cut along the cutting path, and a portion of the first groove forms an avoidance groove of the wall film, thereby obtaining a wafer-level packaging structure.
The method for manufacturing a wafer-level packaging structure according to claim 9, wherein the wall film covers the electroplating line;

Alternatively, the electroplating line is located in the first tank.
The method for manufacturing a wafer-level packaging structure according to claim 9 or 10, characterized in that the top film has a second groove, the second groove is located in the cutting street, and the width of the second groove is less than or equal to the width of the cutting street;

Alternatively, the top film covers the cutting path and is arranged opposite to the electroplating line.
The method for manufacturing a wafer-level packaging structure according to any one of claims 9 to 11, characterized in that when the top film is arranged on the wall film, part of the material of the top film is filled in the first groove.
The method for manufacturing a wafer-level packaging structure according to any one of claims 9 to 12, characterized in that the wall film is formed by laminating, exposing and developing on the substrate layer, and the top film is formed by laminating, exposing and developing on the wall film;

Alternatively, the wall film is formed by pasting a film on the base material layer and punching holes with a laser, and the top film is formed by pasting a film on the wall film and punching holes with a laser.
The method for manufacturing a wafer-level packaging structure according to any one of claims 9 to 13, characterized in that when the top surface of the wall film between the cavity and the avoidance groove has a filling groove, the filling groove is formed by exposure and development, and in the exposure step A first mask plate is configured in the step, and the width of the first mask plate in the area corresponding to the filling groove is smaller than the minimum resolution width of the material of the wall film.
A wafer-level packaging structure, characterized in that it comprises: a substrate layer, a wall film and a top film stacked in sequence;

The wafer-level packaging structure has a cutting side surface; the cutting side surface is formed on the same side surface of the substrate layer and the top film, or the cutting side surface is formed on the same side surface of the substrate layer, the wall film and the top film;

The wall film has a cavity for placing functional devices, and the substrate layer and the top film are respectively covered at two opposite ends of the cavity;

The top surface of the wall film between the cavity and the cutting side surface has a filling groove, and the top film has a second filling portion at least partially filled in the filling groove.
The wafer-level packaging structure according to claim 15 is characterized in that a minimum spacing between the wall film on a side in the same direction as the cutting side and an inner wall of the cavity is in a range of 20 μm to 60 μm.
The wafer-level packaging structure according to claim 15 or 16 is characterized in that the cavity and the filling groove are formed by exposure and development or laser drilling.
An electronic device, characterized in that it comprises a circuit board and a wafer-level packaging structure as described in any one of claims 1 to 8 and 15 to 17, wherein the wafer-level packaging structure is arranged on the circuit board.