WO2024087394A1

WO2024087394A1 - Semiconductor structure and method for manufacturing semiconductor structure

Info

Publication number: WO2024087394A1
Application number: PCT/CN2023/070536
Authority: WO
Inventors: 邬林
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-10-27
Filing date: 2023-01-04
Publication date: 2024-05-02
Also published as: CN117995817A

Abstract

The embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure comprises: a substrate, which is internally provided with conductive vias and contact layers, wherein the conductive vias are electrically connected to the contact layers, the conductive vias and the contact layers extend and are arranged in a first direction, each contact layer comprises at least a non-closed bending portion, and the section of the non-closed bending portion in a direction that is perpendicular to the first direction is in the shape of a bending line; and isolation layers, which are located in the substrate and cover side walls of the contact layers. The embodiments of the present disclosure can at least improve the performance of the semiconductor structure.

Description

Semiconductor structure and method for manufacturing semiconductor structure

cross reference

This application refers to Chinese Patent Application No. 202211327703.6, filed on October 27, 2022, entitled “Semiconductor Structure and Method for Manufacturing Semiconductor Structure,” which is incorporated herein by reference in its entirety.

Technical Field

The embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background technique

Through Silicon Via (TSV) technology is a high-density packaging technology that fills through-holes with conductive materials to achieve vertical electrical interconnection. TSV technology is conducive to reducing signal delay, reducing parasitic capacitance, achieving low power consumption and high-speed communication between chips, and realizing miniaturization of device integration.

In the three-dimensional integrated packaging technology of chips, when the chips communicate with each other through TSV interconnection, TSV will be electrically connected to the pads close to the chip surface through the contact layer. However, there are still some shortcomings in the design of the contact layer, which will affect the performance of the semiconductor structure.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the semiconductor structure, which are at least beneficial to improving the performance of the semiconductor structure.

According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate, wherein the substrate has a conductive through hole and a contact layer, the conductive through hole is electrically connected to the contact layer, and both extend along a first direction, and the two are arranged in the first direction; the contact layer includes at least a non-closed curved portion, and the cross-section of the non-closed curved portion perpendicular to the first direction is in the shape of a curved line; an isolation layer, located in the substrate and covering the side wall of the contact layer.

According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure, wherein the method for manufacturing a semiconductor structure includes providing a substrate;

A contact layer and a conductive through hole are formed in the substrate, wherein the conductive through hole is electrically connected to the contact layer, and both extend along a first direction and are arranged in the first direction;

The contact layer at least includes a non-closed curved portion, and the cross-section of the non-closed curved portion perpendicular to the first direction is in the shape of a curved line; an isolation layer is formed in the substrate, and the isolation layer also covers the side wall of the contact layer.

The technical solution provided by the embodiment of the present disclosure has at least the following advantages: compared with the point array contact layer, the contact layer in the embodiment of the present disclosure includes at least a non-closed bending portion, which reduces the tensile stress on the isolation layer and has a larger cross-sectional area, thereby effectively ensuring the safety and reliability of the semiconductor structure and significantly improving the communication performance of the chip.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

FIG1 shows a top view of a contact layer and an isolation layer;

FIG2 is a partial enlarged view of FIG1;

FIG3 shows a cross-sectional view of a contact layer and an isolation layer;

FIG4 shows a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure;

5 to 11 show top views of a contact layer and an isolation layer in a semiconductor structure provided by an embodiment of the present disclosure;

12 to 16 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

Detailed ways

FIG. 1 is a top view of the contact layer 200 and the isolation layer 300, FIG. 2 is a partial enlarged view of FIG. 1, and FIG. 3 is a cross-sectional interface view of the contact layer 200 and the isolation layer 300. Referring to FIG. 1-FIG. 3, the contact layer 200 is covered by the isolation layer 300, and the thermal expansion coefficients of the contact layer 200 and the isolation layer 300 are different. After the contact layer 200 is formed, an annealing treatment is usually performed to reduce the internal stress of the contact layer 200. During the cooling process of the annealing treatment, the volume of the contact layer 200 and the isolation layer 300 changes from expansion to contraction. When the temperature is close to 100°C to 120°C, the tensile stress between the contact layer 200 and the isolation layer 300 is small. When the temperature reaches room temperature, the contraction volume of the contact layer 200 is much larger than the contraction volume of the isolation layer 300, thereby generating tensile stress on the isolation layer 300, causing the isolation layer 300 to be torn. That is, when the temperature changes, there is a difference in the deformation amount of the contact layer 200 and the isolation layer 300, so that the isolation layer 300 is subjected to tensile stress, which in turn affects the safety and reliability of the semiconductor structure. The material of the isolation layer 300 is usually a brittle material, which is easily torn, and the judgment standard applicable to its failure criterion is the maximum tensile stress theoretical standard. Therefore, the commonly used design structure of the contact layer 200 is a dot array type. The advantage of such a design is to make the cross-sectional area of each contact layer 200 as small as possible, ensuring that its deformation amount is also small during thermal expansion and contraction, thereby achieving the purpose of reducing tensile stress.

As shown in FIG2 , the dotted line frame is the location where the isolation layer 300 is subjected to the maximum tensile stress. Taking the isolation layer 300 as silicon oxide as an example, the tensile strength of silicon oxide is 50 MPa. At the dotted line frame, the tensile stress on silicon oxide is 49.374 MPa, which is close to 50 MPa. Therefore, there is a risk of the silicon oxide being torn.

In addition, the cross-sectional area of the dot array contact layer 200 is small, resulting in a small total effective communication area, so that the electrical signal transmitted by the TSV cannot pass in time, thereby reducing the communication rate.

The disclosed embodiment provides a semiconductor structure, wherein the contact layer includes at least a non-closed curved portion, and the cross-sectional shape of the non-closed curved portion is in the shape of a curved line. The non-closed curved portion can effectively disperse the tensile stress generated by the contact layer on the isolation layer, thereby reducing the maximum tensile stress in the contact layer, and can achieve the purpose of improving the safety and reliability of the semiconductor structure; in addition, compared with the point-shaped structure, the non-closed curved portion can increase the total cross-sectional area of the contact layer, thereby improving the communication performance.

The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

As shown in Figures 4 to 11, an embodiment of the present disclosure provides a semiconductor structure. It should be noted that, in order to facilitate description and clearly illustrate the semiconductor structure, Figures 4 to 11 are all schematic diagrams of the local structure of the semiconductor structure. The semiconductor structure includes: a substrate 1, the substrate 1 has a conductive through hole 5 and a contact layer 2, the conductive through hole 5 is electrically connected to the contact layer 2, and both extend along the first direction X, and the two are arranged in the first direction X; the contact layer 2 includes at least a non-closed bend 21, and the cross-section of the non-closed bend 21 perpendicular to the first direction X is in the shape of a curved line; an isolation layer 3, located in the substrate 1 and covering the side wall of the contact layer 2.

Such a design has at least the following benefits:

First, the cross section of the non-closed curved portion 21 is in the shape of a curved line, that is, the cross section of the non-closed curved portion 21 is slender. When the temperature decreases, the deformation amount of the slender structure in the line width direction is small, so the tensile stress on the two opposite sides is small, which can avoid the concentration of thermal stress here. In addition, the slender structure is convenient for increasing the length of the contact layer 2, so that the contact area between the contact layer 2 and the isolation layer 3 is larger, thereby increasing the area for dispersing the tensile stress, so that the tensile stress can be evenly dispersed on the surface of the contact layer 3, thereby reducing the influence of the tensile stress on the isolation layer 3.

Second, the cross-sectional shape of the non-closed curved portion 21 is curved. The curved shape is conducive to increasing the total length of the non-closed curved portion 21, that is, increasing its cross-sectional area, so that the total resistance of the contact layer 2 is smaller, which is conducive to reducing the RC delay effect, so as to improve the operating rate of the semiconductor structure. In addition, the curved shape enables the non-closed curved portion 21 to have a smoothly transitioned sidewall, thereby reducing the stress concentration point, so that there will be no phenomenon of excessive local stress. In addition, it should be noted that when the straight structure undergoes thermal expansion and contraction, its length changes greatly, and this degree of change will be concentrated at the end of the straight structure, thereby increasing the thermal stress at the end, while when the curved structure undergoes thermal expansion and contraction, its deformation amount can be dispersed in different directions and positions, which is conducive to reducing the tensile stress at the end.

Third, since the non-closed curved portion 21 is not a closed shape connected end to end, its shape design and position arrangement are more flexible. That is, the bending degree, bending direction, overall extension direction and arrangement direction of the non-closed curved portion 21 can be flexibly adjusted to meet the requirements of low resistance and high communication rate.

The semiconductor structure will be described in detail below with reference to the accompanying drawings.

Referring to FIG4 , in some embodiments, the base 1 may include a substrate 11 and a device layer 12 formed on the substrate 11, and the substrate 11 may be a silicon substrate 11 or a germanium substrate 11. That is, the base 1 may be understood as the overall structure of the chip, and the conductive vias 5, the contact layer 2, and the isolation layer 3 all belong to the internal structure of the chip, and all three may be formed in the device layer 12. In other embodiments, the base 1 may also be a substrate that acts as an intermediary, serving as a bridge between the chip and the circuit board. The conductive vias 5 and the contact layer 2 are used to realize the electrical interconnection of multiple semiconductor structures in the first direction X.

The first direction X may be the thickness direction of the substrate 1 , and the extension directions of the conductive via 5 and the contact layer 2 may be the same, and both extend in the thickness direction of the substrate 1 .

In some embodiments, the conductive via 5 may be a TSV, and its material may include copper. The material of the contact layer 2 may be a metal, such as tungsten, gold, copper, molybdenum, etc. Since the contact layer 2 penetrates the isolation layer 3, the contact layer 2 may also be regarded as a structure similar to a conductive via.

The material of the isolation layer 3 can be silicon oxide, silicon nitride, silicon oxynitride or other insulating materials with low dielectric constant. The insulating material with low dielectric constant can be either an organic material or an inorganic material. The insulating material with low dielectric constant can improve the isolation effect of the isolation layer 3 and reduce the parasitic capacitance between the contact layers 2 to increase the operating speed of the semiconductor structure. The isolation layer 3 can be a single-layer structure or a multi-layer composite structure.

The semiconductor structure further includes: a first pad M0 and a second pad M1 respectively located on opposite sides of the contact layer 2, the first pad M0 is connected to the conductive via 5 and the contact layer 2, and the second pad M1 is connected to the contact layer 2. That is, the conductive via 5 lands on the first pad M0 and then communicates to the second pad M1 through the contact layer 2, thereby facilitating connection and communication between the two semiconductor structures in the first direction X.

The semiconductor structure may include a first metal layer and a second metal layer, the first pad M0 is a part of the first metal layer, and the second pad M1 is a part of the second metal layer. In addition, the first metal layer and the second metal layer may also include metal traces to achieve interconnection of components within the chip.

The shape and position of the contact layer 2 will be described in detail below.

Referring to FIGS. 5 to 11 , the non-closed curved portion 21 includes a plurality of connected bands 211, and the cross-section of the plurality of connected bands 211 is wavy in shape in a direction perpendicular to the first direction X. Since the tensile stress at the end of the contact layer 2 is relatively large, the connection of the plurality of bands 211 is conducive to reducing the number of ends of the contact layer 2, thereby reducing the concentration of tensile stress. In addition, the connection of the plurality of bands 211 is also conducive to increasing the length of the non-closed curved portion 21, that is, increasing the cross-sectional area of the contact layer 2, thereby improving the communication performance.

The shape of the wave line is relatively regular, which is conducive to improving the dispersion effect of tensile stress and improving the uniformity of the semiconductor structure. For example, the bending directions of two adjacent bands 211 are opposite. Compared with the bending of two adjacent bands 211 in the same direction, bending in opposite directions can make the connection between the two adjacent bands 211 have a smooth transition, thereby avoiding the generation of sharp corners, thereby reducing the tensile stress at the connection and avoiding the problem of tip discharge at the connection.

Continuing to refer to FIG. 5 to FIG. 11 , in some embodiments, the curvatures of the multiple bands 211 of the same non-closed curved portion 21 are the same. Thus, the tensile stress on the isolation layer 3 around each band 211 can be balanced, and it is also beneficial to improve the space utilization rate in the substrate 1. In other words, the non-closed curved portion has alternately arranged crests 212 and troughs 213. For two adjacent bands 211, one band 211 includes the crest 212, and the other band 211 includes the trough 213, and the protrusion of the crest 212 relative to the connection is equal to the protrusion of the trough 213 relative to the connection.

In some embodiments, the spacing between adjacent crests 212 in the non-closed bending portion is greater than or equal to 1um. That is, the spacing between adjacent troughs 213 in the non-closed bending portion is greater than or equal to 1um. It should be noted that if the distance between adjacent crests 212 or adjacent troughs 213 is too close, the curvature of the band 211 may be increased, thereby reducing the smoothness of the band 211, which is not conducive to dispersing tensile stress. When the spacing between adjacent crests 212 or troughs 213 is within the above range, it is helpful to avoid the above problem. In other embodiments, the spacing between adjacent crests 212 or troughs 213 can also be less than 3um, thereby avoiding the curvature of the band 211 from being too small, thereby ensuring that the non-closed bending portion 21 has a larger length, and then ensuring that the contact layer 2 has a larger cross-sectional area.

Referring to Figures 5 to 9, in some embodiments, there are multiple non-closed bends 21, and the multiple non-closed bends 21 are separated from each other. That is, the multiple non-closed bends 21 can be arranged in an array within the substrate 1, which is conducive to increasing the cross-sectional area of the contact layer 2, thereby improving the communication rate. In addition, the multiple non-closed bends 21 are separated from each other, which also makes the design of the contact layer 2 more flexible, so that the contact layer 2 can be specifically adjusted according to the size and shape of the first pad M0 to simultaneously meet the requirements of reducing tensile stress and improving communication performance.

In some embodiments, a plurality of non-closed bends 21 are arranged in parallel, thereby facilitating the improvement of uniformity of the semiconductor structure and the effect of dispersing tensile stress.

In addition, the plurality of non-closed curved portions 21 may be arranged at equal intervals, so that the tensile stress on the isolation layer 3 at various locations can be balanced to avoid tensile stress concentration, and it is also beneficial to improve space utilization to ensure that the contact layer 2 has a larger cross-sectional area.

Continuing to refer to Figures 5 to 9, the arrangement direction of the multiple non-closed bends 21 is the second direction Y, and the overall extension direction of the non-closed bends 21 is the third direction Z. It should be noted that the overall extension direction of the non-closed bend 21 is different from its local bending direction. In some embodiments, the second direction Y is perpendicular to the third direction Z, and both are perpendicular to the first direction X. The shape of the first pad M0 can be rectangular, and the two adjacent sides of the first pad M0 can be parallel to the second direction Y and the third direction Z, respectively. In this way, the matching degree between the contact layer 2 and the first pad M0 can be improved, so that the multiple non-closed bends 21 have the same length.

For example, the spacing between adjacent non-closed curved portions 21 is greater than or equal to 0.5um, that is, the spacing between adjacent wavy lines is greater than or equal to 0.5um. It should be noted that if the spacing between adjacent non-closed curved portions 21 is too large, it is not conducive to increasing the cross-sectional area of the contact layer 2; if the distance between adjacent non-closed curved portions 21 is too small, it is not conducive to dispersing stress. When the spacing between adjacent non-closed curved portions 21 is within the above range, it is conducive to taking into account both of the above problems.

6 to 8 , the contact layer 2 further includes: a closed curved portion 22, which is connected to the non-closed curved portion 21 and is located at opposite ends of the non-closed curved portion 21, and the cross-section of the closed curved portion 22 perpendicular to the first direction X is annular. As can be seen from the foregoing, the tensile stress at both ends of the non-closed curved portion 21 is relatively large, and the closed curved portion 22 can form a smooth transition at the opposite ends of the non-closed curved portion 21, that is, the closed curved portion 22 does not have obvious ends, thereby reducing stress concentration points to avoid the problem of excessive local stress.

It is worth noting that the closed curved portion 22 is a hollow structure that can cut the isolation layer 3, thereby dividing the isolation layer 3 into two parts, the inner and outer parts. When the temperature decreases, the closed curved portion 22 has a tendency to shrink inward, and the area of the isolation layer 3 in the closed curved portion 22 is small, so the isolation layer 3 in the closed curved portion 22 is subjected to a smaller tensile stress. In addition, although the isolation layer 3 outside the closed curved portion 22 is subjected to a greater tensile stress, the volume of the isolation layer 3 outside the closed curved portion 22 is usually larger than that of the isolation layer 3 in the closed curved portion 22. The larger volume helps to disperse thermal stress. Therefore, the closed curved portion 22 can avoid the problem of thermal stress concentration at both the inner and outer positions.

In addition, the hollow shape of the closed curved portion 22 is also beneficial for increasing the contact area between the contact layer 2 and the isolation layer 3, thereby increasing the area for dispersing the tensile stress, so that the tensile stress can be evenly dispersed on the surface of the contact layer 3, thereby reducing the influence of the tensile stress on the isolation layer 3.

Experimental data show that the maximum tensile stress of the isolation layer 3 shown in Figure 6 is 44.62MPa, which is less than the maximum tensile stress of the isolation layer covering the dot array structure (49.374MPa). In this way, the isolation layer 3 can be prevented from being damaged or cracked, and defects such as pores can be prevented from being formed in the isolation layer 3, thereby reducing the risks of leakage, short circuit, etc. in the semiconductor structure.

In addition, compared with the dot-shaped portion 23, the cross-sectional area of the closed curved portion 22 is larger, and the total resistance of the contact layer 2 is smaller, which is beneficial to reduce the RC delay effect to improve the operating speed of the semiconductor structure. When the size of the first pad M0 is 8*8um ² , the total cross-sectional area of the contact layer 2 can reach 12.349um ² , while the total cross-sectional area of the dot-shaped array contact layer is 8.3304um ^2. It can be seen that the combination of the closed curved portion 22 and the non-closed curved portion 21 can effectively increase the communication area to improve the communication rate.

In some embodiments, the cross-sectional shape of the closed bend 22 perpendicular to the first direction X can be a circular ring. That is, the degree of curvature of the closed bend 22 is equal everywhere, thereby effectively improving the uniformity of the tensile stress distribution. In other embodiments, the cross-sectional shape of the closed bend 22 perpendicular to the first direction X can also be a rounded square. Compared with the circular ring, the circumference of the rounded square is longer, which is beneficial to increase the cross-sectional area of the closed bend 22. In addition, the cross-sectional shape of the closed bend 22 perpendicular to the first direction X can also be a rounded triangle and other rounded polygons. The rounded corner design can improve the smoothness of the closed bend 22, reduce the tensile stress on the isolation layer 3, and avoid the problem of tip discharge, which is beneficial to improve the electrical performance of the semiconductor structure.

In some embodiments, the shapes of the multiple closed bends 22 of the same contact layer 2 may be the same, which is helpful to simplify the production process and improve the uniformity of the semiconductor structure. In other embodiments, the shapes of the multiple closed bends 22 of the same contact layer 2 may also be different, so that the design of the contact layer 2 is more flexible to meet the needs of reducing thermal stress, tensile stress and resistance, and at the same time improve the space utilization rate in the substrate 1.

Continuing to refer to Figures 6 to 8, the two opposite sides of the closed curved portion 22 can be aligned with the crest 212 and the trough 213, respectively. That is, the width of the wavy overall protrusion is the same as the diameter of the closed curved portion 22. It should be noted that if the diameter of the closed curved portion 22 is too large, the spacing between adjacent closed curved portions 22 may be too small, which is not conducive to dispersing tensile stress. If the diameter of the closed curved portion 22 is too small, it is not conducive to improving space utilization. Therefore, when the two opposite sides of the closed curved portion 22 are aligned with the crest 212 and the trough 213, respectively, space waste can be avoided to increase the total area of the cross section of the contact layer 2, and it is also beneficial to reduce the concentration of thermal stress.

In some embodiments, the non-closed bend 21 has a uniform line width, and the closed bend 22 may also have a uniform line width. In this way, the production process is simpler and helps to avoid the problem of stress concentration. In addition, the line width of the non-closed bend 21 may be equal to the line width of the closed bend 22. For example, the line width of the non-closed bend 21 and the closed bend 22 is less than or equal to 0.25um, such as a line width of 0.2um, 0.1um or 0.15um. When the line width is within the above range, the tensile stress on the isolation layer 3 can be effectively reduced.

Referring to Figures 7-8, in some embodiments, the closed bend 22 can also be located between two adjacent non-closed bends 21. In other words, multiple rings can be added between adjacent wavy lines. In this way, the closed bend 22 makes full use of the space between adjacent non-closed bends 21 to increase the cross-sectional area of the contact layer 2. In some embodiments, referring to Figure 7, the closed bend 22 can be set at the center position between adjacent non-closed bends 21, that is, the closed bend 22 is at the same distance from the non-closed bends 21 on both sides. In this way, the uniformity of the distribution of the closed bends 22 can be improved to balance the tensile stress on the isolation layer 3 at different positions. It should be noted that since the closed bends 22 are in the shape of wavy lines, the closed bends 22 are staggered in the third direction Z, that is, the adjacent closed bends 22 are not in a directly opposite relationship in the third direction Z.

It should be noted that each band 211 includes an inner sidewall 215 and an outer sidewall 214 that are arranged opposite to each other, wherein the length of the inner sidewall 215 is less than the length of the outer sidewall 214. In other words, the inner sidewall 215 can be understood to be concave, and the outer sidewall 214 can be convex. When the temperature decreases, since the non-closed curved portion 21 has a tendency to shrink inward, the tensile stress on the isolation layer 3 close to the inner sidewall 215 of the band 211 is less than the tensile stress on the isolation layer 3 close to the outer sidewall 214 of the band 211. As shown in FIG8 , for the closed curved portion 22 located between adjacent non-closed curved portions 21, one side of the closed curved portion 22 faces the inner sidewall 215 of one band 211, and the other side of the closed curved portion 22 faces the outer sidewall 214 of another band 211. Based on the above analysis, it can be seen that the tensile stress near the outer side wall 214 is greater, so the closed curved portion 22 may not be located at the center position between the two bands 211, but closer to the inner side wall 215 of the band 211 and farther away from the outer side wall 214 of the band 211. In this way, stress concentration can be avoided. In addition, by comparing Figures 7 and 8, it can be seen that compared with when the closed curved portion 22 is located at the center position between adjacent non-closed curved portions 21, when the closed curved portion 22 is closer to the inner side wall 215, the distance between adjacent closed curved portions 22 is farther, which is conducive to improving the dispersion of thermal stress.

Referring to FIG9 , in some embodiments, the contact layer 2 may further have a dot-shaped portion 23 at opposite ends, and the sidewall of the dot-shaped portion 23 does not have a sharp chamfer, thereby also being able to reduce tensile stress. In addition, by comparing FIG8 and FIG9 , it can be seen that the width of the dot-shaped portion 23 may be smaller than the diameter of the closed curved portion 22. Because the dot-shaped portion 23 is a solid structure, the degree of thermal expansion and contraction of the dot-shaped portion 23 is greater at the same size, and therefore, the width of the dot-shaped portion 23 may be appropriately reduced to reduce the tensile stress on the isolation layer 3.

Referring to FIG. 10 and FIG. 11 , the contact layer 2 further includes a plurality of connecting portions 24, one connecting portion 24 is connected between two adjacent non-closed curved portions 21, and the plurality of connecting portions 24 and the plurality of non-closed curved portions 21 form an S-shape in a cross section perpendicular to the first direction X. That is, the plurality of non-closed curved portions 21 form an integral structure connected end to end through the connecting portion 24, thereby reducing the end of the non-closed curved portion exposed in the isolation layer 3, thereby reducing the degree of stress concentration. For example, the arrangement direction of the plurality of non-closed curved portions 21 is the second direction Y, and the overall extension direction of the connecting portion 24 is also the second direction Y.

For example, two adjacent non-closed bends 21 can be axially symmetrically arranged, that is, the protruding directions of adjacent non-closed bends 21 are opposite, so that the connecting portion 24 can form a smooth transition between adjacent non-closed bends 21, avoiding corners and spikes, thereby reducing stress concentration.

Continuing to refer to Figures 10 and 11, since two adjacent non-closed curved portions 21 are arranged axially symmetrically rather than being arranged in translation, the spacing between adjacent non-closed curved portions 21 at different positions is not uniform. In other words, the spacing between two bands 211 protruding toward each other is smaller than the spacing between two bands 211 protruding in opposite directions. Specifically, referring to Figure 10, a closed curved portion 22 is added between two bands 211 protruding in opposite directions; referring to Figure 11, a dot-shaped portion 23 is added between two bands 211 protruding in opposite directions. In this way, the density of the contact layer 2 can be balanced, thereby improving the uniformity of the tensile stress distribution.

In addition, the shapes of the closed curved portion 22 and the dot-shaped portion 23 can also be adjusted according to the spatial shape between the two back-protruding bands 211. For example, the spacing between the two back-protruding bands 211 in the second direction Y is greater than the width of the bands 211 in the third direction Z. Thus, the width of the closed curved portion 22 in the second direction Y can be set to be greater than the width in the first direction X. Thus, the spacing between the closed curved portion 22 and the non-closed curved portion 21 can be balanced. Similarly, the width of the dot-shaped portion 23 in the second direction Y can be set to be greater than the width in the first direction X.

It should be noted that the above description of the shape and position of the contact layer 2 is only an exemplary description. The embodiments of the present disclosure are not limited thereto. The non-closed curved portion 21, the closed curved portion 22, and the dot-shaped portion 23 can be arranged, nested, combined, etc. according to the specific requirements of the semiconductor structure performance. In addition, the directions of the line width, spacing, length, diameter, etc. of the embodiments of the present disclosure are all perpendicular to the first direction X.

To sum up, even if the internal space of the substrate 1 is limited, and the area of the designed first pad M0 or the second pad M1 is very small (the side length is usually a few microns), the non-closed bending portion 21 provided in the embodiment of the present disclosure can effectively increase the linear circumference of the contact layer 2, that is, increase the total cross-sectional area of the contact layer 2, thereby achieving the purpose of improving its communication performance; in addition, the non-closed bending portion 21 can effectively reduce the tensile stress generated by the contact layer 2 on the isolation layer 3, reduce the maximum tensile stress inside the isolation layer 3, and thereby improve the isolation effect of the isolation layer 3, thereby achieving the purpose of improving the safety and reliability of the semiconductor structure.

As shown in Figures 4 and 12-16, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure provided in the aforementioned embodiment. The detailed description of this semiconductor structure can refer to the aforementioned embodiment. The following will describe in detail the method for manufacturing a semiconductor structure provided in one embodiment of the present application in conjunction with the accompanying drawings. It should be noted that, in order to facilitate the description and clearly illustrate the steps of the semiconductor structure manufacturing method, Figures 4, 12 to 16 are all schematic diagrams of the partial structure of the semiconductor structure.

12-16 and FIG. 4 , a substrate 1 is provided, a conductive via 5 and a contact layer 2 are formed in the substrate 1 , the conductive via 5 is electrically connected to the contact layer 2 , both extend along a first direction X, and both are arranged in the first direction X.

The substrate 1 may be a composite multi-layer structure. In some embodiments, the substrate 1 includes a substrate 11 and a device layer 12 formed on the substrate 11, that is, the substrate 1 may be regarded as a whole chip. Therefore, the substrate 1 is formed through multiple process steps.

12 , a substrate 11 may be provided first, and metal may be deposited on the substrate 11 to form a second pad M1 . Silicon oxide may be deposited on the second pad M1 to serve as an isolation layer 3 .

Referring to FIG. 13 , the isolation layer 3 is patterned to form a through hole. Specifically, a photoresist layer is first formed on the isolation layer 3, and the photoresist layer is photolithographically processed to form a patterned photoresist layer. The patterned photoresist layer is used as a mask to etch the isolation layer 3 to form a through hole. Thereafter, tungsten is electroplated in the through hole to serve as the contact layer 2, and thereafter the contact layer 2 and the isolation layer 3 are planarized so that the top surface of the contact layer 2 is flush with the top surface of the isolation layer 3.

The contact layer 2 at least includes a non-closed curved portion 21, and the cross section of the non-closed curved portion 21 perpendicular to the first direction X is annular. That is, the aforementioned step of patterning the isolation layer 3 is to define the shape of the contact layer 2 in the isolation layer 3. At this point, the contact layer 2 and the isolation layer 3 covering the sidewalls of the contact layer 2 can be formed in the substrate 1.

14 , the isolation layer 3 is etched back to remove a portion of the thickness of the isolation layer 3 and expose a portion of the thickness of the contact layer 2 .

15 , a protective layer 4 is formed, and the protective layer 4 covers the partial thickness of the contact layer 2 exposed by the isolation layer 3. By way of example, silicon nitride is deposited by a chemical vapor deposition process as the protective layer 4. Thereafter, the protective layer 4 and the contact layer 2 are planarized so that the top surface of the protective layer 4 is flush with the top surface of the contact layer 2.

Silicon nitride has higher hardness and density than silicon oxide, therefore, adding the protective layer 4 can improve the supporting effect of the isolation layer 3 on the contact layer 2, and can also provide better protection for the contact layer 2. In other embodiments, the protective layer 4 may not be formed, that is, the process steps shown in FIG. 14-FIG. 15 are omitted, thereby simplifying the production process and reducing the production cost.

16 , a first pad M0 is formed covering the contact layer 2 and the isolation layer 3. By way of example, tungsten is deposited on the contact layer 2 and the isolation layer 3 by an electroplating process to serve as the first pad M0.

Referring to FIG4 , after forming the first pad M0, an isolation structure, transistors, capacitors, control circuits, and other component layers for realizing chip functions are also formed on the first pad M0. Thereafter, a conductive via 5 is formed to penetrate the component layer. The component layer and the aforementioned first pad M0, second pad M1, contact layer 2, isolation layer 3, and other structures together constitute a device layer 12.

In summary, the contact layer 2 having the non-closed bent portion 21 can be formed on the isolation layer 3. The contact layer 2 can be a symmetrical structure to balance the tensile stress at various locations in the isolation layer 3. In addition, the number of nested and arranged arrays of these non-closed bent portions 21 can be one or more, thereby making full use of the spatial position in the isolation layer 3 to increase the communication area.

In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope of the patent of the present disclosure.

Claims

A semiconductor structure comprising:

A substrate, wherein the substrate has a conductive through hole and a contact layer, the conductive through hole is electrically connected to the contact layer, and both extend along a first direction, and the two are arranged in the first direction;

The contact layer at least includes a non-closed curved portion, and the cross section of the non-closed curved portion perpendicular to the first direction is in the shape of a curved line;

The isolation layer is located in the substrate and covers the sidewall of the contact layer.
The semiconductor structure according to claim 1, wherein the non-closed curved portion comprises a plurality of connected wave bands, and a cross-section of the plurality of connected wave bands perpendicular to the first direction is in the shape of a wavy line.
The semiconductor structure according to claim 2, wherein the contact layer further comprises: a closed bend portion, the closed bend portion is connected to the non-closed bend portion and is located at opposite ends of the non-closed bend portion, and the cross-section of the closed bend portion perpendicular to the first direction is annular.
The semiconductor structure according to claim 3, wherein the non-closed bending portion has a crest and a trough, and opposite sides of the closed bending portion are aligned with the crest and the trough respectively.
The semiconductor structure according to claim 3, wherein the line width of the non-closed bend portion is equal to the line width of the closed bend portion.
The semiconductor structure according to claim 2, wherein the bending curvatures of the plurality of bands of the same non-closed curved portion are the same.
The semiconductor structure according to claim 5, wherein the spacing between adjacent wave peaks in the non-closed bending portion is greater than or equal to 1 um.
The semiconductor structure according to claim 3, wherein the number of the non-closed bent portions is multiple and the multiple non-closed bent portions are separate from each other.
The semiconductor structure according to claim 8, wherein a plurality of the non-closed bends are arranged in parallel.
The semiconductor structure according to claim 9, wherein the plurality of non-closed bends are arranged at equal intervals.
The semiconductor structure according to claim 10, wherein the arrangement direction of the plurality of non-closed curved portions is a second direction, the overall extension direction of the non-closed curved portions is a third direction, the second direction is perpendicular to the third direction, and both are perpendicular to the first direction;

The distance between adjacent non-closed curved portions is greater than or equal to 0.5 um.
The semiconductor structure according to claim 1, wherein the line width of the non-closed bend is less than or equal to 0.25 um.
The semiconductor structure according to claim 2, wherein the contact layer further comprises a plurality of connecting portions, one of the connecting portions is connected between two adjacent non-closed bending portions, and a plurality of the connecting portions and a plurality of the non-closed bending portions form an S-shape in a cross-section perpendicular to the first direction.
The semiconductor structure according to claim 1, further comprising: a first pad and a second pad respectively located on opposite sides of the contact layer, the first pad being connected to the conductive via and the contact layer, and the second pad being connected to the contact layer.
A method for manufacturing a semiconductor structure, comprising:

providing a substrate;

A contact layer and a conductive through hole are formed in the substrate, wherein the conductive through hole is electrically connected to the contact layer, and both extend along a first direction and are arranged in the first direction;

The contact layer at least includes a non-closed curved portion, and the cross section of the non-closed curved portion perpendicular to the first direction is in the shape of a curved line;

An isolation layer is formed in the substrate, and the isolation layer also covers the sidewalls of the contact layer.