WO2024087012A1

WO2024087012A1 - Encoding apparatus and method, and decoding apparatus and method

Info

Publication number: WO2024087012A1
Application number: PCT/CN2022/127350
Authority: WO
Inventors: 刘可; 童佳杰; 王献斌; 张华滋; 李榕; 王俊
Original assignee: 华为技术有限公司
Priority date: 2022-10-25
Filing date: 2022-10-25
Publication date: 2024-05-02

Abstract

The present application relates to the technical field of wireless communications, and provides an encoding apparatus and method, and a decoding apparatus and method. The decoding apparatus can perform decoding in an analog domain, such that the problems of large power consumption of analog-to-digital conversion and high operation complexity and performance loss caused by quantization are avoided, and the storage space of a digital circuit can be saved. The decoding apparatus comprises an analog circuit. The analog circuit is used for acquiring an analog signal. The analog signal is determined by the decoding apparatus according to a received encoded sequence, wherein the encoded sequence is a sequence obtained after a sequence to be encoded is encoded, the length of the sequence to be encoded is N, N=2n, and n is a positive integer. The analog circuit is also used for decoding the analog signal to obtain a decoding result.

Description

Coding and decoding device and method

Technical Field

The present application relates to the field of wireless communication technology, and in particular to a coding device and method.

Background technique

Communication systems mostly transmit signals in the analog domain. After the receiving device obtains the analog signal, it quantizes the analog signal through the analog to digital (AD) module to obtain a digital signal, and then decodes the digital signal through a digital circuit. However, the analog to digital conversion module consumes a lot of power, and the quantization process introduces the complexity of floating point to fixed point quantization, which may also cause performance loss, and the digital circuit has a large storage capacity.

Summary of the invention

The present application provides a coding device and method, wherein the decoding device and method can perform decoding in the analog domain, thereby reducing power consumption and computational complexity, and saving storage space.

In a first aspect, a decoding device is provided, the decoding device comprising an analog circuit. The analog circuit is used to obtain an analog signal. The analog signal is determined by the decoding device according to a received coded sequence, the coded sequence is a sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N= ²ⁿ , and n is a positive integer. The analog circuit is also used to decode the analog signal to obtain a decoding result.

That is to say, after the decoding device obtains the analog signal, it decodes it in the analog domain. There is no problem of high power consumption of analog-to-digital conversion, high computational complexity and performance loss caused by quantization, and it can also save storage space for digital circuits.

In one possible design, the sequence to be encoded includes a first information bit and a second information bit. The analog circuit includes a first f operation circuit, a first decoding circuit, a first delay control circuit, a first g operation circuit, and a second decoding circuit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: a first f operation circuit, which is used to perform an f operation on the analog signal. The first decoding circuit is used to decode the result of the first f operation circuit to obtain an estimated value of the first information bit. The code length corresponding to the result decoded by the first decoding circuit is N/2, and the code rate is A/(N/2), where A represents the number of first information bits. The first delay control circuit is used to control the time when the analog signal is input into the first g operation circuit. The first g operation circuit is used to perform a g operation on the analog signal and the first bit value. The first bit value is an estimated value of the first information bit. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit. The code length corresponding to the result decoded by the second decoding circuit is N/2, and the code rate is B/(N/2), where B represents the number of second information bits. The decoding result includes an estimated value of the first information bit and an estimated value of the second information bit.

That is to say, when the first N/2 bits of the sequence to be encoded include A first information bits and the last N/2 bits include B second information bits, the analog circuit adopts a nested manner, using the first decoding circuit with a code length of N/2 and a code rate of A/(N/2) and the second decoding circuit with a code length of N/2 and a code rate of B/(N/2), combined with the first f operation circuit, the first g operation circuit and the first delay control circuit, to realize the decoding function with a code length of N and a code rate of (A+B)/N.

In one possible design, the first decoding circuit includes a ninth g operation circuit and a first sub-decoding circuit. The first decoding circuit is used to decode the result of the first f operation circuit to obtain an estimated value of the first information bit, including: a ninth g operation circuit, used to perform a g operation on the result of the first f operation circuit. The first sub-decoding circuit is used to decode the result of the ninth g operation circuit to obtain an estimated value of the first information bit. The code length corresponding to the result decoded by the first sub-decoding circuit is N/4 and the code rate is A/(N/4).

That is to say, the first decoding circuit can also be nested, with the first sub-decoding circuit for a code length of N/4 and a code rate of A/(N/4) combined with the ninth g operation circuit to realize the decoding function with a code length of N/2 and a code rate of A/(N/2).

In one possible design, the second decoding circuit includes a second sub-decoding circuit and a third sub-decoding circuit. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a second sub-decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of C first information bits. The code length corresponding to the result decoded by the second sub-decoding circuit is N/4, the code rate is C/(N/4), and C is a positive integer. The third sub-decoding circuit is used to decode the result of the first g operation circuit and the result of the second sub-decoding circuit to obtain an estimated value of D first information bits. The code length corresponding to the result decoded by the third sub-decoding circuit is N/4, the code rate is D/(N/4), and D is a positive integer. C+D=B.

That is to say, the second decoding circuit can also be nested, using the second sub-decoding circuit for the code length of N/4 and the code rate of C/(N/4) and the third sub-decoding circuit for the code length of N/4 and the code rate of D/(N/4) to realize the decoding function of the code length of N/2 and the code rate of B/(N/2).

In one possible design, the first f operation circuit includes a first real number to absolute value sign RTAS converter, a minimum WTA module, a first multiplier and a second multiplier. The first f operation circuit is used to perform f operation on an analog signal, and includes: a first RTAS converter, which is used to receive and process the first signal to obtain the sign and absolute value corresponding to each log-likelihood ratio LLR value in the first signal. The first signal includes two LLR values in the analog signal. The WTA module is used to determine the minimum value of the absolute values obtained by the first RTAS converter. The first multiplier is used to multiply the signs obtained by the first RTAS converter. The second multiplier is used to multiply the result of the WTA module and the result of the first multiplier. Among them, the number of the first f operation circuits is N/2, and the result of the first f operation circuit includes the results of N/2 second multipliers.

That is, the first f operation circuit implements the f operation function through the first RTAS converter, the WTA module, the first multiplier and the second multiplier.

In one possible design, the sequence to be encoded includes a second information bit. The analog circuit includes a first g operation circuit and a second decoding circuit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: a first g operation circuit, which is used to perform a g operation on the analog signal and a first bit value. The first bit value is determined based on the first N/2 LLR values in the analog signal. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit. The result of decoding by the second decoding circuit corresponds to a code length of N/2 and a code rate of B/(N/2), where B represents the number of second information bits. Wherein, the decoding result includes an estimated value of the second information bit.

That is to say, when the last N/2 bits of the sequence to be encoded include B second information bits, the analog circuit adopts a nested manner, combining the second decoding circuit with a code length of N/2 and a code rate of B/(N/2) with the first g operation circuit to realize the decoding function with a code length of N and a code rate of B/N.

In one possible design, the first g operation circuit includes a third multiplier and a first adder. The first g operation circuit is used to perform a g operation on the analog signal and the first bit value, including: the third multiplier is used to multiply the first bit value and an LLR value in the first signal. The first signal includes two LLR values in the analog signal. The first adder is used to add the result of the third multiplier and another LLR value in the first signal. The number of the first g operation circuits is N/2, and the result of the first g operation circuit includes the results of N/2 first adders.

That is to say, the first g operation circuit realizes the g operation function through the third multiplier and the first adder.

In one possible design, the first g operation circuit includes a second RTAS converter, a fourth multiplier, a fifth multiplier, a second delay control circuit, and a second adder. The first g operation circuit is used to perform a g operation on an analog signal and a first bit value, and includes: a second RTAS converter, which is used to receive and process an LLR value in the first signal to obtain a first symbol and a first absolute value. The first signal includes two LLR values in the analog signal. The fourth multiplier is used to multiply the first bit value and the first symbol. The fifth multiplier is used to multiply the result of the fourth multiplier and the first absolute value. The second delay control circuit is used to control the time when another LLR value in the first signal is input into the second adder. The second adder is used to add the result of the fifth multiplier and the LLR value input by the second delay control circuit. Among them, the number of the first g operation circuits is N/2, and the result of the first g operation circuit includes the results of N/2 second adders.

That is, the first g operation circuit implements the g operation function through the second RTAS converter, the fourth multiplier, the fifth multiplier, the second delay control circuit and the second adder.

In one possible design, the sequence to be encoded also includes frozen bits. The first decoding circuit includes a first operation circuit and a symbol conversion circuit. The first decoding circuit is used to decode the result of the first f operation circuit to obtain an estimated value of the first information bit, including: a first operation circuit, used to receive the result of the first f operation circuit, and perform a g operation on the value of the frozen bit and the result of the first f operation circuit. The symbol conversion circuit is used to perform a sign-taking process on the result of the first operation circuit to obtain an estimated value of the first information bit.

That is to say, in the first decoding circuit, the first operation circuit first performs the g operation, and then the sign conversion circuit extracts the sign to obtain the estimated value of the first information bit.

In one possible design, the sequence to be encoded also includes frozen bits. The first decoding circuit includes a first operation circuit and a path metric circuit. The first decoding circuit is used to decode the result of the first f operation circuit to obtain an estimated value of the first information bit, including: a first operation circuit, used to receive the result of the first f operation circuit, and perform a g operation on the value of the frozen bit and the result of the first f operation circuit. The path metric circuit is used to determine the estimated value of the first information bit based on the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of the first decoding path, and the first decoding path indicates the value of the bit before the first information bit.

That is to say, in the first decoding circuit, the first operation circuit first performs the g operation, and then the path metric circuit determines the estimated value of the first information bit according to the path metric value.

In a possible design, the candidate values of the first information bit include a first candidate value and a second candidate value. The path metric circuit includes a first processing module, a second processing module and a comparator. The path metric circuit is used to determine the estimated value of the first information bit according to the first path metric value and the result of the first operation circuit, including: a first processing module, used to receive the first path metric value and the result of the first operation circuit, and determine the second path metric value according to the first candidate value, the first path metric value and the result of the first operation circuit. The second processing module is used to receive the first path metric value and the result of the first operation circuit, and determine the third path metric value according to the second candidate value, the first path metric value and the result of the first operation circuit. The comparator is used to compare the second path metric value and the third path metric value, and output the estimated value of the first information bit. The estimated value of the first information bit is the candidate value corresponding to the larger path metric value of the second path metric value and the third path metric value.

That is to say, in the path metric circuit, the first processing module first determines the second path metric value, the second processing module determines the third path metric value, and then the comparator determines the larger path metric value to output the candidate value corresponding to the larger path metric value.

In one possible design, the first processing module includes a third RTAS converter, a sixth multiplier, a first calculation unit, a seventh multiplier, and a third adder. The first processing module is used to receive the first path metric value and the result of the first operation circuit, and determine the second path metric value according to the first candidate value, the first path metric value, and the result of the first operation circuit, including: a third RTAS converter, used to receive and process the result of the first operation circuit to output a second symbol and a second absolute value. A sixth multiplier, used to multiply the first candidate value and the second symbol. A first calculation unit, used to receive and process the result of the sixth multiplier. A seventh multiplier, used to multiply the result of the first calculation unit and the second absolute value. A third adder, used to add the first path metric value and the result of the seventh multiplier to obtain a second path metric value.

That is, the first processing module implements the calculation function of the second path metric value through the third RTAS converter, the sixth multiplier, the first calculation unit, the seventh multiplier and the third adder.

In one possible design, the second processing module includes a fourth RTAS converter, an eighth multiplier, a second calculation unit, a ninth multiplier, and a fourth adder. The second processing module is used to receive the first path metric value and the result of the first operation circuit, and determine the third path metric value according to the second candidate value, the first path metric value, and the result of the first operation circuit, including: a fourth RTAS converter, used to receive and process the result of the first operation circuit to output a third symbol and a third absolute value. An eighth multiplier, used to multiply the second candidate value and the third symbol. A second calculation unit, used to receive and process the result of the eighth multiplier. A ninth multiplier, used to multiply the result of the second calculation unit and the third absolute value. A fourth adder, used to add the first path metric value and the result of the ninth multiplier to obtain a third path metric value.

That is, the second processing module implements the calculation function of the third path metric value through the fourth RTAS converter, the eighth multiplier, the second calculation unit, the ninth multiplier and the fourth adder.

In one possible design, the frozen bit includes a first frozen bit, a second frozen bit, and a third frozen bit. The result of the first f operation circuit includes a first partial result and a second partial result, the first partial result includes the results of the first N/4 first f operation circuits, and the second partial result includes the results of the last N/4 first f operation circuits. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit is used to receive the result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit, including: the second g operation circuit is used to perform a g operation on the value of the first frozen bit and the first partial result. The third g operation circuit is used to perform a g operation on the value of the second frozen bit and the second partial result. The fourth g operation circuit is used to perform a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain the result of the first operation circuit.

That is, the first operation circuit realizes the function of processing the value of the frozen bit and the result of the first f operation circuit through three g operation circuits (ie, the second g operation circuit, the third g operation circuit and the fourth g operation circuit).

In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a sign conversion circuit. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: an operation unit of the i-th subcircuit, used to determine the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit is used to perform a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

That is to say, in the B sub-circuits of the second decoding circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a symbol conversion circuit.

In one possible design, B=3. The previous bit of the first second information bit is a first frozen bit. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit, used to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain the probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first conversion circuit is used to perform a sign operation on the probability distribution of the first first information bit to obtain the estimated value of the first first information bit. The first conversion circuit is a symbol conversion circuit of the first sub-circuit. The second operation unit is used to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain the probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second conversion circuit is used to perform a sign operation on the probability distribution of the second second information bit to obtain the estimated value of the second second information bit. The second conversion circuit is a symbol conversion circuit of the second sub-circuit. The third operation unit is used to receive and process the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit to obtain the probability distribution of the third second information bit. The third operation unit is an operation unit of the third sub-circuit. The third conversion circuit is used to perform a sign operation on the probability distribution of the third second information bit to obtain the estimated value of the third second information bit. The third conversion circuit is a sign conversion circuit of the third sub-circuit.

That is, in the second decoding circuit, each operation unit and conversion circuit are combined (such as the first operation unit and the first conversion circuit are combined, or the second operation unit and the second conversion circuit are combined, or the third operation unit and the third conversion circuit are combined) to calculate an estimated value of a second information bit.

In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a path metric circuit. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: an operation unit of the i-th subcircuit, used to determine the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit is used to receive the path metric value of the i-th decoding path, and determine the estimated value of the i-th second information bit according to the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit before the i-th second information bit in the encoded sequence.

That is to say, in the B sub-circuits of the second decoding circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a path metric circuit.

In one possible design, B=3. The previous bit of the first second information bit is a first frozen bit. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit, used to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain the probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first path metric circuit is used to receive the path metric value of the first decoding path, and determine the estimated value of the first second information bit according to the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit before the first second information bit. The first path metric circuit is the path metric circuit of the first sub-circuit. The second operation unit is used to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain the probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second path metric circuit is used to receive the path metric value of the second decoding path, and determine the estimated value of the second second information bit according to the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit before the second second information bit. The second path metric circuit is the path metric circuit of the second sub-circuit. The third operation unit is used to receive and process the estimated values of both the first second information bit and the second second information bit and the result of the first g operation circuit to obtain the probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third path metric circuit is used to receive the path metric value of the third decoding path, and determine the estimated value of the third second information bit according to the path metric value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit before the third second information bit. The third path metric circuit is the path metric circuit of the third sub-circuit.

That is to say, in the second decoding circuit, each operation unit is combined with a path measurement circuit (such as the first operation unit is combined with a first path measurement circuit, or the second operation unit is combined with a second path measurement circuit, or the third operation unit is combined with a third path measurement circuit) to calculate an estimated value of a second information bit.

In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit. The first operation unit is used to receive and process the value of the first frozen bit and the result of the first g operation circuit, including: the second f operation circuit is used to receive a second signal and perform an f operation on the second signal. The second signal is a part of the result of the first g operation circuit. The third f operation circuit is used to receive a third signal and perform an f operation on the second signal. The third signal is a signal other than the second signal in the result of the first g operation circuit. The fifth g operation circuit is also used to perform a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain the processing result of the first operation unit.

That is to say, the first operation unit implements the processing function of the first operation unit through the second f operation circuit, the third f operation circuit and the fifth g operation circuit.

In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit and a fourth f operation circuit. The second operation unit is used to receive and process the estimated value of the first second information bit and the result of the first g operation circuit, including: the sixth g operation circuit, which is used to perform a g operation on the estimated value of the first information bit and the second signal. The second signal is a part of the result of the first g operation circuit. The seventh g operation circuit is used to perform a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal other than the second signal in the result of the first g operation circuit. The fourth f operation circuit is used to perform an f operation on the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain the processing result of the second operation unit.

That is to say, the second operation unit implements the processing function of the second operation unit through the sixth g operation circuit, the seventh g operation circuit and the fourth f operation circuit.

In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit is used to receive and process the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit, including: the sixth g operation circuit, which is used to perform a g operation on the estimated value of the first first information bit and the second signal. The second signal is a part of the result of the first g operation circuit. The seventh g operation circuit is used to perform a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal other than the second signal in the result of the first g operation circuit. The eighth g operation circuit is used to perform a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain the processing result of the third operation unit.

That is to say, the third operation unit implements the processing function of the third operation unit through the sixth g operation circuit, the seventh g operation circuit and the eighth g operation circuit.

In one possible design, the coding sequence includes a first information bit. The analog circuit includes a first operation circuit and a sign conversion circuit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: the first operation circuit is used to perform a g operation on the analog signal. The sign conversion circuit is used to perform a sign processing on the result of the first operation circuit to obtain an estimated value of the first information bit.

That is to say, in the analog circuit, the first operation circuit first performs the g operation, and then the sign conversion circuit extracts the sign to obtain the estimated value of the first information bit.

In one possible design, the coding sequence includes a first information bit. The analog circuit includes a first operation circuit and a path metric circuit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: a first operation circuit, which is used to perform a g operation on the analog signal. The path metric circuit is used to determine an estimated value of the first information bit according to the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of a first decoding path, and the first decoding path indicates the value of a bit before the first information bit.

That is to say, in the analog circuit, the first operation circuit first performs the g operation, and then the path metric circuit determines the estimated value of the first information bit according to the path metric value.

In one possible design, the frozen bit includes a first frozen bit, a second frozen bit, and a third frozen bit. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit is used to perform a g operation on the analog signal, including: the second g operation circuit is used to perform a g operation on the value of the first frozen bit and the first N/2 LLR values in the analog signal. The third g operation circuit is used to perform a g operation on the value of the second frozen bit and the last N/2 LLR values in the analog signal. The fourth g operation circuit is used to perform a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain the result of the first operation circuit. The analog signal includes N LLR values.

That is to say, the first operation circuit realizes the processing function of the frozen bit value and the analog signal through three g operation circuits (ie, the second g operation circuit, the third g operation circuit and the fourth g operation circuit).

In one possible design, the coding sequence includes B second information bits. The analog circuit includes B subcircuits, and each of the B subcircuits includes an operation unit and a sign conversion circuit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: an operation unit of the i-th subcircuit, used to determine the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit is used to perform a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

That is, in the B sub-circuits of the analog circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a symbol conversion circuit.

In one possible design, B=3. The previous bit of the first second information bit is a first frozen bit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: a first operation unit, used to receive and process the value of the first frozen bit and the analog signal to obtain the probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first conversion circuit is used to perform a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit. The first conversion circuit is a symbol conversion circuit of the first sub-circuit. The second operation unit is used to receive and process the estimated value of the first second information bit and the analog signal to obtain the probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second conversion circuit is used to perform a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit. The second conversion circuit is a symbol conversion circuit of the second sub-circuit. The third operation unit is used to receive and process the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit to obtain the probability distribution of the third second information bit. The third operation unit is an operation unit of the third sub-circuit. The third conversion circuit is used to perform a sign operation on the probability distribution of the third second information bit to obtain the estimated value of the third second information bit. The third conversion circuit is a sign conversion circuit of the third sub-circuit.

That is, in the analog circuit, each operation unit and conversion circuit are combined (such as the first operation unit and the first conversion circuit are combined, or the second operation unit and the second conversion circuit are combined, or the third operation unit and the third conversion circuit are combined) to calculate an estimated value of a second information bit.

In one possible design, the analog circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a path metric circuit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: an operation unit of the i-th subcircuit, used to determine the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit is used to receive the path metric value of the i-th decoding path, and determine the estimated value of the i-th second information bit according to the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit before the i-th second information bit in the encoded sequence.

That is to say, in the B sub-circuits of the analog circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a path metric circuit.

In one possible design, B=3. The previous bit of the first second information bit is a first frozen bit. The analog circuit is also used to decode the analog signal to obtain a decoding result, including: a first operation unit, used to receive and process the value of the first frozen bit and the analog signal to obtain the probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first path metric circuit is used to receive the path metric value of the first decoding path, and determine the estimated value of the first second information bit according to the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit before the first second information bit. The first path metric circuit is a path metric circuit of the first sub-circuit. The second operation unit is used to receive and process the estimated value of the first second information bit and the analog signal to obtain the probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second path metric circuit is used to receive the path metric value of the second decoding path, and determine the estimated value of the second second information bit according to the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit before the second second information bit. The second path measurement circuit is the path measurement circuit of the second sub-circuit. The third operation unit is used to receive and process the estimated values and analog signals of the first second information bit and the second second information bit to obtain the probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third path measurement circuit is used to receive the path measurement value of the third decoding path, and determine the estimated value of the third second information bit according to the path measurement value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit before the third second information bit. The third path measurement circuit is the path measurement circuit of the third sub-circuit.

That is, in the analog circuit, each operation unit is combined with a path measurement circuit (such as a first operation unit is combined with a first path measurement circuit, or a second operation unit is combined with a second path measurement circuit, or a third operation unit is combined with a third path measurement circuit) to calculate an estimated value of a second information bit.

In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit and a fifth g operation circuit. The first operation unit is used to receive and process the value of the first frozen bit and the analog signal, including: the second f operation circuit is used to receive the second signal and perform an f operation on the second signal. The second signal is a part of the analog signal. The third f operation circuit is used to receive the third signal and perform an f operation on the second signal. The third signal is a signal in the analog signal other than the second signal. The fifth g operation circuit is also used to perform a g operation on the value of the first frozen bit, the result of the first f operation circuit and the result of the second f operation circuit to obtain a processing result of the first operation unit.

In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit and a fourth f operation circuit. The second operation unit is used to receive and process the estimated value of the first second information bit and the analog signal, including: the sixth g operation circuit, which is used to perform a g operation on the estimated value of the first information bit and the second signal. The second signal is a part of the analog signal. The seventh g operation circuit is used to perform a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal in the analog signal other than the second signal. The fourth f operation circuit is used to perform an f operation on the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain the processing result of the second operation unit.

In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit is used to receive and process the estimated values and analog signals of both the first second information bit and the second second information bit, including: the sixth g operation circuit, which is used to perform a g operation on the estimated value of the first first information bit and the second signal. The second signal is a part of the analog signal. The seventh g operation circuit is used to perform a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal other than the second signal in the analog signal. The eighth g operation circuit is used to perform a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain the processing result of the third operation unit.

In a second aspect, a decoding method is provided, which is applied to a decoding device, and the decoding device includes an analog circuit. The method includes: the analog circuit obtains an analog signal. The analog signal is determined by the decoding device according to the received coded sequence, and the coded sequence is a sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N= ²ⁿ , and n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result.

In one possible design, the sequence to be encoded includes a first information bit and a second information bit. The analog circuit includes a first f operation circuit, a first decoding circuit, a first delay control circuit, a first g operation circuit, and a second decoding circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the first f operation circuit performs an f operation on the analog signal. The first decoding circuit decodes the result of the first f operation circuit to obtain an estimated value of the first information bit. The code length corresponding to the result decoded by the first decoding circuit is N/2, and the code rate is A/(N/2), where A represents the number of first information bits. The first delay control circuit controls the time when the analog signal is input into the first g operation circuit. The first g operation circuit performs a g operation on the analog signal and the first bit value. The first bit value is an estimated value of the first information bit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit. The code length corresponding to the result decoded by the second decoding circuit is N/2, and the code rate is B/(N/2), where B represents the number of second information bits. Wherein, the decoding result includes the estimated value of the first information bit and the estimated value of the second information bit.

In one possible design, the first f operation circuit includes a first real number to absolute value sign RTAS converter, a minimum WTA module, a first multiplier and a second multiplier. The first f operation circuit performs an f operation on an analog signal, including: the first RTAS converter receives and processes the first signal to obtain a sign and an absolute value corresponding to each log-likelihood ratio LLR value in the first signal. The first signal includes two LLR values in the analog signal. The WTA module determines the minimum value of the absolute values obtained by the first RTAS converter. The first multiplier multiplies the signs obtained by the first RTAS converter. The second multiplier multiplies the result of the WTA module and the result of the first multiplier. Among them, the number of the first f operation circuits is N/2, and the result of the first f operation circuit includes the results of N/2 second multipliers.

In one possible design, the sequence to be encoded includes a second information bit. The analog circuit includes a first g operation circuit and a second decoding circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the first g operation circuit performs a g operation on the analog signal and the first bit value. The first bit value is determined based on the first N/2 LLR values in the analog signal. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit. The result of the decoding by the second decoding circuit corresponds to a code length of N/2 and a code rate of B/(N/2), where B represents the number of second information bits. Wherein, the decoding result includes an estimated value of the second information bit.

In one possible design, the first g operation circuit includes a third multiplier and a first adder. The first g operation circuit performs a g operation on the analog signal and the first bit value, including: the third multiplier multiplies the first bit value and an LLR value in the first signal. The first signal includes two LLR values in the analog signal. The first adder adds the result of the third multiplier and another LLR value in the first signal. The number of the first g operation circuits is N/2, and the result of the first g operation circuit includes the results of N/2 first adders.

In one possible design, the first g operation circuit includes a second RTAS converter, a fourth multiplier, a fifth multiplier, a second delay control circuit and a second adder. The first g operation circuit performs a g operation on the analog signal and the first bit value, including: the second RTAS converter receives and processes an LLR value in the first signal to obtain a first symbol and a first absolute value. The first signal includes two LLR values in the analog signal. The fourth multiplier multiplies the first bit value and the first symbol. The fifth multiplier multiplies the result of the fourth multiplier and the first absolute value. The second delay control circuit controls the time when another LLR value in the first signal is input to the second adder. The second adder adds the result of the fifth multiplier and the LLR value input by the second delay control circuit. Among them, the number of the first g operation circuits is N/2, and the result of the first g operation circuit includes the results of N/2 second adders.

In one possible design, the sequence to be encoded further includes frozen bits. The first decoding circuit includes a first operation circuit and a symbol conversion circuit. The first decoding circuit decodes the result of the first f operation circuit to obtain an estimated value of the first information bit, including: the first operation circuit receives the result of the first f operation circuit, and performs a g operation on the value of the frozen bit and the result of the first f operation circuit. The symbol conversion circuit performs a sign-taking process on the result of the first operation circuit to obtain an estimated value of the first information bit.

In one possible design, the sequence to be encoded also includes frozen bits. The first decoding circuit includes a first operation circuit and a path metric circuit. The first decoding circuit decodes the result of the first f operation circuit to obtain an estimated value of the first information bit, including: the first operation circuit receives the result of the first f operation circuit, and performs a g operation on the value of the frozen bit and the result of the first f operation circuit. The path metric circuit determines the estimated value of the first information bit according to the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of the first decoding path, and the first decoding path indicates the value of the bit before the first information bit.

In a possible design, the candidate values of the first information bit include a first candidate value and a second candidate value. The path metric circuit includes a first processing module, a second processing module and a comparator. The path metric circuit determines the estimated value of the first information bit according to the first path metric value and the result of the first operation circuit, including: the first processing module receives the first path metric value and the result of the first operation circuit, and determines the second path metric value according to the first candidate value, the first path metric value and the result of the first operation circuit. The second processing module receives the first path metric value and the result of the first operation circuit, and determines the third path metric value according to the second candidate value, the first path metric value and the result of the first operation circuit. The comparator compares the second path metric value and the third path metric value, and outputs the estimated value of the first information bit. The estimated value of the first information bit is the candidate value corresponding to the larger path metric value of the second path metric value and the third path metric value.

In one possible design, the first processing module includes a third RTAS converter, a sixth multiplier, a first calculation unit, a seventh multiplier, and a third adder. The first processing module receives the first path metric value and the result of the first operation circuit, and determines the second path metric value according to the first candidate value, the first path metric value, and the result of the first operation circuit, including: the third RTAS converter receives and processes the result of the first operation circuit to output a second sign and a second absolute value. The sixth multiplier multiplies the first candidate value and the second sign. The first calculation unit receives and processes the result of the sixth multiplier. The seventh multiplier multiplies the result of the first calculation unit and the second absolute value. The third adder adds the first path metric value and the result of the seventh multiplier to obtain the second path metric value.

In one possible design, the second processing module includes a fourth RTAS converter, an eighth multiplier, a second calculation unit, a ninth multiplier, and a fourth adder. The second processing module receives the first path metric value and the result of the first operation circuit, and determines the third path metric value according to the second candidate value, the first path metric value, and the result of the first operation circuit, including: the fourth RTAS converter receives and processes the result of the first operation circuit to output a third symbol and a third absolute value. The eighth multiplier multiplies the second candidate value and the third symbol. The second calculation unit receives and processes the result of the eighth multiplier. The ninth multiplier multiplies the result of the second calculation unit and the third absolute value. The fourth adder adds the first path metric value and the result of the ninth multiplier to obtain the third path metric value.

In one possible design, the frozen bit includes a first frozen bit, a second frozen bit, and a third frozen bit. The result of the first f operation circuit includes a first partial result and a second partial result, the first partial result includes the results of the first N/4 first f operation circuits, and the second partial result includes the results of the last N/4 first f operation circuits. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit receives the result of the first f operation circuit, and performs a g operation on the value of the frozen bit and the result of the first f operation circuit, including: the second g operation circuit performs a g operation on the value of the first frozen bit and the first partial result. The third g operation circuit performs a g operation on the value of the second frozen bit and the second partial result. The fourth g operation circuit performs a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain the result of the first operation circuit.

In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a sign conversion circuit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit, including: the operation unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit performs a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

In one possible design, B=3. The previous bit of the first second information bit is a first frozen bit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit receives and processes the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit. The first operation unit is an operation unit of the first subcircuit. The first conversion circuit performs a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit. The first conversion circuit is a symbol conversion circuit of the first subcircuit. The second operation unit receives and processes the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit. The second operation unit is an operation unit of the second subcircuit. The second conversion circuit performs a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit. The second conversion circuit is a symbol conversion circuit of the second subcircuit. The third operation unit receives and processes the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit to obtain the probability distribution of the third second information bit. The third operation unit is an operation unit of the third sub-circuit. The third conversion circuit performs a sign operation on the probability distribution of the third second information bit to obtain the estimated value of the third second information bit. The third conversion circuit is a sign conversion circuit of the third sub-circuit.

In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a path metric circuit. The second decoding circuit decodes the result of the first g operation circuits to obtain an estimated value of the second information bit, including: the operation unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit receives the path metric value of the i-th decoding path, and determines the estimated value of the i-th second information bit according to the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit before the i-th second information bit in the encoded sequence.

In one possible design, B=3. The previous bit of the first second information bit is a first frozen bit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit receives and processes the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first path metric circuit receives the path metric value of the first decoding path, and determines the estimated value of the first second information bit according to the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit before the first second information bit. The first path metric circuit is a path metric circuit of the first sub-circuit. The second operation unit receives and processes the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second path metric circuit receives the path metric value of the second decoding path, and determines the estimated value of the second second information bit according to the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit before the second second information bit. The second path metric circuit is the path metric circuit of the second sub-circuit. The third operation unit receives and processes the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit to obtain the probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third path metric circuit receives the path metric value of the third decoding path, and determines the estimated value of the third second information bit according to the path metric value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit before the third second information bit. The third path metric circuit is the path metric circuit of the third sub-circuit.

In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit. The first operation unit receives and processes the value of the first frozen bit and the result of the first g operation circuit, including: the second f operation circuit receives a second signal and performs an f operation on the second signal. The second signal is a part of the result of the first g operation circuit. The third f operation circuit receives a third signal and performs an f operation on the second signal. The third signal is a signal other than the second signal in the result of the first g operation circuit. The fifth g operation circuit performs a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain a processing result of the first operation unit.

In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit, and a fourth f operation circuit. The second operation unit receives and processes the estimated value of the first second information bit and the result of the first g operation circuit, including: the sixth g operation circuit performs a g operation on the estimated value of the first information bit and the second signal. The second signal is a part of the result of the first g operation circuit. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal other than the second signal in the result of the first g operation circuit. The fourth f operation circuit performs an f operation on the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain the processing result of the second operation unit.

In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit receives and processes the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit, including: the sixth g operation circuit performs a g operation on the estimated value of the first first information bit and the second signal. The second signal is a part of the result of the first g operation circuit. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal other than the second signal in the result of the first g operation circuit. The eighth g operation circuit performs a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain the processing result of the third operation unit.

In one possible design, the coding sequence includes a first information bit. The analog circuit includes a first operation circuit and a sign conversion circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the first operation circuit performs a g operation on the analog signal. The sign conversion circuit performs a sign-taking process on the result of the first operation circuit to obtain an estimated value of the first information bit.

In one possible design, the coding sequence includes a first information bit. The analog circuit includes a first operation circuit and a path metric circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the first operation circuit performs a g operation on the analog signal. The path metric circuit determines an estimated value of the first information bit according to the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of a first decoding path, and the first decoding path indicates a value of a bit before the first information bit.

In one possible design, the frozen bit includes a first frozen bit, a second frozen bit, and a third frozen bit. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit performs a g operation on the analog signal, including: the second g operation circuit performs a g operation on the value of the first frozen bit and the first N/2 LLR values in the analog signal. The third g operation circuit performs a g operation on the value of the second frozen bit and the last N/2 LLR values in the analog signal. The fourth g operation circuit performs a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain the result of the first operation circuit. The analog signal includes N LLR values.

In one possible design, the coding sequence includes B second information bits. The analog circuit includes B subcircuits, and each of the B subcircuits includes an operation unit and a sign conversion circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the operation unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit performs a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

In one possible design, B=3. The previous bit of the first second information bit is the first frozen bit. The analog circuit decodes the analog signal to obtain a decoding result, including: a first operation unit receives and processes the value of the first frozen bit and the analog signal to obtain a probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first conversion circuit performs a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit. The first conversion circuit is a symbol conversion circuit of the first sub-circuit. The second operation unit receives and processes the estimated value of the first second information bit and the analog signal to obtain a probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second conversion circuit performs a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit. The second conversion circuit is a symbol conversion circuit of the second sub-circuit. The third operation unit receives and processes the estimated values of both the first second information bit and the second second information bit and the result of the first g operation circuit to obtain a probability distribution of the third second information bit. The third operation unit is an operation unit of the third sub-circuit. The third conversion circuit performs a sign operation on the probability distribution of the third second information bit to obtain an estimated value of the third second information bit. The third conversion circuit is a sign conversion circuit of the third sub-circuit.

In one possible design, the analog circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a path metric circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the operation unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit receives the path metric value of the i-th decoding path, and determines the estimated value of the i-th second information bit according to the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit before the i-th second information bit in the encoded sequence.

In one possible design, B=3. The previous bit of the first second information bit is a first frozen bit. The analog circuit decodes the analog signal to obtain a decoding result, including: a first operation unit receives and processes the value of the first frozen bit and the analog signal to obtain a probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first path metric circuit receives the path metric value of the first decoding path, and determines the estimated value of the first second information bit according to the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit before the first second information bit. The first path metric circuit is a path metric circuit of the first sub-circuit. The second operation unit receives and processes the estimated value of the first second information bit and the analog signal to obtain a probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second path metric circuit receives the path metric value of the second decoding path, and determines the estimated value of the second second information bit according to the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit before the second second information bit. The second path measurement circuit is a path measurement circuit of the second sub-circuit. The third operation unit receives and processes the estimated values and analog signals of the first second information bit and the second second information bit to obtain the probability distribution of the third second information bit. The third operation unit is an operation unit of the third sub-circuit. The third path measurement circuit receives the path measurement value of the third decoding path, and determines the estimated value of the third second information bit according to the path measurement value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit before the third second information bit. The third path measurement circuit is a path measurement circuit of the third sub-circuit.

In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit. The first operation unit receives and processes the value of the first frozen bit and the analog signal, including: the second f operation circuit receives the second signal and performs an f operation on the second signal. The second signal is a part of the analog signal. The third f operation circuit receives the third signal and performs an f operation on the second signal. The third signal is a signal in the analog signal other than the second signal. The fifth g operation circuit performs a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain a processing result of the first operation unit.

In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit, and a fourth f operation circuit. The second operation unit receives and processes the estimated value of the first second information bit and the analog signal, including: the sixth g operation circuit performs a g operation on the estimated value of the first information bit and the second signal. The second signal is a part of the analog signal. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal in the analog signal other than the second signal. The fourth f operation circuit performs an f operation on the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain a processing result of the second operation unit.

In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit receives and processes the estimated values and analog signals of the first second information bit and the second second information bit, including: the sixth g operation circuit performs a g operation on the estimated value of the first first information bit and the second signal. The second signal is a part of the analog signal. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal other than the second signal in the analog signal. The eighth g operation circuit performs a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain the processing result of the third operation unit.

In a third aspect, a coding device is provided, the coding device comprising a processing module and a transceiver module. The processing module is used to encode a sequence to be coded to obtain a coded sequence. The sequence to be coded includes at least one sub-block, and the at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit. The transceiver module is used to send the coded sequence.

In a fourth aspect, a coding method is provided, which is applied to a coding device, and the method includes a coding device encoding a sequence to be coded to obtain a coded sequence. The sequence to be coded includes at least one sub-block, and the at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit. The coding device sends the coded sequence.

In a fifth aspect, a computer-readable storage medium is provided, wherein a program is stored in the computer-readable storage medium, and when the program is called by a processor, the method of the second aspect or any one of the second aspects is executed. For example, when the program is called by a processor, the analog circuit in the decoding device performs the following steps: the analog circuit obtains an analog signal. The analog signal is determined by the decoding device according to the received encoded sequence, and the encoded sequence is a sequence after the sequence to be encoded is encoded, and the length of the sequence to be encoded is N, N= ²ⁿ , and n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result. Alternatively, when the program is called by a processor, the method of the fourth aspect or any one of the fourth aspects is executed.

In a sixth aspect, a computer program product comprising instructions is provided. When the computer program product is called by a processor, the method of the second aspect or any one of the second aspects is executed. For example, when the program is called by a processor, the analog circuit in the decoding device performs the following steps: the analog circuit obtains an analog signal. The analog signal is determined by the decoding device according to the received encoded sequence, and the encoded sequence is a sequence after the sequence to be encoded is encoded. The length of the sequence to be encoded is N, N= ²ⁿ , and n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result. Alternatively, when the program is called by a processor, the method of the fourth aspect or any one of the fourth aspects is executed.

Among them, the technical effects brought about by any design in the second to sixth aspects can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application;

FIG2 is a schematic diagram of a basic flow of wireless communication provided in an embodiment of the present application;

FIG3 is a schematic diagram of an encoding process provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of a decoding device provided in an embodiment of the present application;

FIG5 is a schematic diagram of the structure of an f operation circuit provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of a g operation circuit provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of another g operation circuit provided in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of a path metric circuit provided in an embodiment of the present application;

FIG9 is a schematic diagram of the structure of another path metric circuit provided in an embodiment of the present application;

FIG10a is a schematic diagram of a decoding process of a polar code provided in an embodiment of the present application;

FIG10b is a schematic diagram of the structure of an analog circuit provided in an embodiment of the present application;

FIG10c is a schematic diagram of the structure of another analog circuit provided in an embodiment of the present application;

FIG11a is a schematic diagram of a decoding process of another polar code provided in an embodiment of the present application;

FIG11b is a schematic diagram of the structure of another analog circuit provided in an embodiment of the present application;

FIG11c is a schematic diagram of the structure of another analog circuit provided in an embodiment of the present application;

FIG12a is a schematic diagram of a decoding process of another polar code provided in an embodiment of the present application;

FIG12b is a schematic diagram of the structure of another analog circuit provided in an embodiment of the present application;

FIG12c is a schematic diagram of the structure of another analog circuit provided in an embodiment of the present application;

FIG13a is a schematic diagram of a decoding process of another polar code provided in an embodiment of the present application;

FIG13b is a schematic diagram of the structure of another analog circuit provided in an embodiment of the present application;

FIG14 is a schematic diagram of a flow chart of a coding method provided in an embodiment of the present application;

FIG15 is a first structural diagram of an encoding device provided in an embodiment of the present application;

FIG16 is a second schematic diagram of the structure of the encoding device provided in an embodiment of the present application.

Detailed ways

FIG. 1 is a schematic diagram of the architecture of a communication system 1000 used in an embodiment of the present application. As shown in FIG. 1 , the communication system 1000 includes at least one network device (such as 110a and 110b in FIG. 1 ) and at least one terminal device (such as 120a-120j in FIG. 1 ). The terminal device is connected to the network device wirelessly. FIG. 1 is only a schematic diagram, and other network devices may also be included in the communication system, such as wireless relay devices and wireless backhaul devices, which are not shown in FIG. 1 .

The network equipment can be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), the next generation NodeB (gNB) in the fifth generation (5G) mobile communication system, the next generation base station in the sixth generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a wireless fidelity (WiFi) system; it can also be a module or unit that completes part of the functions of a base station, for example, it can be a centralized unit (CU) or a distributed unit (DU). Here, the CU completes the functions of the radio resource control (RRC) protocol and the packet data convergence layer protocol (PDCP) of the base station, and can also complete the function of the service data adaptation protocol (SDAP); the DU completes the functions of the radio link control (RLC) layer and the medium access control (MAC) layer of the base station, and can also complete the functions of part of the physical layer or all of the physical layer. For the specific description of each of the above-mentioned protocol layers, reference can be made to the relevant technical specifications of the third generation partnership project (3GPP). The network device can be a macro base station (such as 110a in Figure 1), a micro base station or an indoor station (such as 110b in Figure 1), or a relay node or a donor node. The embodiments of the present application do not limit the specific technology and specific device form adopted by the network device. For the convenience of description, the following description is taken as an example of a network device.

The terminal device may also be referred to as a terminal, user equipment (UE), mobile station, mobile terminal, etc. The terminal device can be widely used in various scenarios, for example, device-to-device (D2D), vehicle to everything (V2X) communication, machine-type communication (MTC), Internet of Things (IOT), virtual reality, augmented reality, industrial control, automatic driving, telemedicine, smart grid, smart furniture, smart office, smart wear, smart transportation, smart city, etc. The terminal device may be a mobile phone, a tablet computer, a computer with wireless transceiver function, a wearable device, a vehicle, a drone, a helicopter, an airplane, a ship, a robot, a mechanical arm, a smart home device, etc. The embodiments of the present application do not limit the specific technology and specific device form adopted by the terminal device.

The network equipment and terminal equipment can be fixed or movable. The network equipment and terminal equipment can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on the water surface; they can also be deployed on aircraft, balloons and artificial satellites in the air. The embodiments of the present application do not limit the application scenarios of the network equipment and terminal equipment.

The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in FIG. 1 can be configured as a mobile base station. For the terminal devices 120j that access the wireless access network through 120i, the terminal device 120i is a network device; but for the

network device

110a, 120i is a terminal device, that is, 110a and 120i communicate through the wireless air interface protocol. Of course, 110a and 120i can also communicate through the interface protocol between base stations. In this case, relative to 110a, 120i is also a network device. Therefore, network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in FIG. 1 can be referred to as communication devices with network device functions, and 120a-120j in FIG. 1 can be referred to as communication devices with terminal device functions.

Network devices and terminal devices, network devices and network devices, and terminal devices and terminal devices may communicate through authorized spectrum, unauthorized spectrum, or both; may communicate through spectrum below 6 gigahertz (GHz), spectrum above 6 GHz, or spectrum below 6 GHz and spectrum above 6 GHz. The embodiments of the present application do not limit the spectrum resources used for wireless communication.

In the embodiments of the present application, the functions of the network device may also be performed by a module (such as a chip) in the network device, or by a control subsystem including the network device function. The control subsystem including the network device function here may be a control center in the above-mentioned application scenarios such as smart grid, industrial control, smart transportation, smart city, etc. The functions of the terminal device may also be performed by a module (such as a chip or a modem) in the terminal device, or by a device including the terminal device function.

Next, the basic process of wireless communication is introduced.

FIG2 shows a basic process of wireless communication. At the transmitting device, the information source is sent out after source coding, channel coding and modulation, and then transmitted to the receiving device through the channel. At the receiving device, the information destination is output through demodulation, channel decoding and source decoding. It is easy to understand that in uplink transmission, the transmitting device is the terminal device in FIG1, and the receiving device is the network device in FIG1. In downlink transmission, the transmitting device is the network device in FIG1, and the receiving device is the terminal device in FIG1.

It should be understood that the basic process of wireless communication also includes additional processes, such as precoding and interleaving. Since these additional processes are common knowledge to those skilled in the art, they are not listed one by one.

It should be understood that the coding device and method of the embodiment of the present application can be applied to the source coding process and the channel coding process. In the scenario of source coding, the source coding can be encoded using Hadamard transform. In the scenario of channel coding, the channel coding can be encoded using Hadamard transform, and in addition to Hadamard transform, other technologies still need to be used for processing to complete channel coding.

In order to facilitate understanding of the embodiments of the present application, the following is a brief description of the technologies involved in the embodiments of the present application. It should be understood that these descriptions are only for facilitating understanding of the embodiments of the present application and should not constitute any limitation to the present application.

Polar codes

Polar code is a channel coding scheme that can be rigorously proven to asymptotically reach the Shannon capacity of a binary input channel. It has the characteristics of good performance and low complexity.

See Figure 3, which is a typical schematic diagram of 8X8 polar code encoding. In Figure 3, the sequence to be encoded includes

According to the reliability of each bit, the bits of the sequence to be encoded are divided into frozen bits and information (data) bits. Generally, bits with higher reliability are set as information bits, and bits with lower reliability are set as frozen bits. The value of the frozen bit is usually set to 0, which is known to both the transmitting device and the receiving device. As shown in Figure 3, _u7 , _u6 , _u5 , _u3 are the four bits with the highest reliability, which are set as information bits. _u4 , _u2 , _u1 , _u0 are the four bits with the lowest reliability, which are set as frozen bits.

The decoding method of polar codes is mainly the continuous erasure decoding algorithm. The so-called continuous erasure decoding algorithm means that the decoder decodes bit by bit according to the natural timing of the polar code design. At present, the main continuous erasure decoding algorithms include successive cancellation (SC) decoding, successive cancellation list (SCL) decoding, etc.

At present, most communication systems transmit signals in the analog domain. Specifically, the transmitting device converts the digital signal into an analog signal through the digital to analog (DA) module for transmission. Correspondingly, after the receiving device obtains the analog signal, it quantizes the analog signal through the analog to digital (AD) module to obtain the digital signal, and then decodes the digital signal through the digital circuit.

In the above-mentioned digital-to-analog conversion or analog-to-digital conversion process, there are two main ways to utilize ultra-bandwidth:

Method 1: divide the entire bandwidth into narrower sub-bands and use parallel low-speed converters. However, this method requires a large number of low-speed converters and local oscillator circuits to ensure timing and bandwidth matching.

Method 2: Using a single digital-to-analog converter (DAC)/analog-to-digital converter (DAC) across the entire ultra-wideband. However, the power consumption of such DAC/ADC is linearly related to the bandwidth of the input signal, i.e., the larger the bandwidth, the greater the power consumption of the DAC/ADC. Moreover, the power consumption of such DAC/ADC also increases exponentially with the accuracy, i.e., the higher the accuracy, the greater the power consumption of the DAC/ADC.

In addition, the quantization process of analog-to-digital conversion introduces the quantization complexity of floating-point to fixed-point, which may also cause performance loss and large storage capacity of digital circuits.

In view of this, an embodiment of the present application provides a coding device, wherein the coding device can encode a sequence to be coded, and the decoding device can decode in an analog domain.

Next, the decoding device 400 proposed in the embodiment of the present application is described in detail with reference to FIG. 4 to FIG. 12c :

As shown in FIG4 , the decoding device 400 includes an analog circuit 401 and a transceiver 402. The analog circuit 401 is used to receive an analog signal from the transceiver 402. The analog signal is determined by the decoding device 400 according to the received coded sequence. The coded sequence is a sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N=2 ⁿ , and n is a positive integer. The analog circuit 401 is also used to decode the analog signal to obtain a decoding result. That is to say, after the decoding device 400 obtains the analog signal, it decodes in the analog domain without performing analog-to-digital conversion, and there is no problem of high power consumption of analog-to-digital conversion, high computational complexity and performance loss caused by quantization, and it can also save the storage space of the digital circuit.

In the embodiment of the present application, when the length of the sequence to be encoded is different and the code rate is different, the circuit structure of the analog circuit 401 is also different.

In order to more clearly introduce the circuit structure of the analog circuit 401, first, the structure of the f operation circuit, the structure of the g operation circuit and the structure of the path metric circuit are introduced:

1. Structure of f operation circuit

Referring to FIG5 , FIG5 shows a schematic diagram of the structure of an f operation circuit. In FIG5 , the f operation circuit includes a real to absolute value and sign (RTAS) converter 501, a sign multiplier (SM) 502, a minimum winner-take-all (WTA) module 503 and an absolute value and sign to real (ASTR) converter 504. The functions of each component are described as follows:

In Fig. 5, RTAS converter 501 is used to convert real values into signs and absolute values. That is, the input of RTAS converter 501 includes one or more real values, and the output of RTAS converter 501 includes the absolute value and sign of each real value.

Exemplarily, taking FIG5 as an example, the input of the RTAS converter 501 includes the real value Lin1 and the real value Lin2. The output of the RTAS converter 501 includes: the absolute value |Lin1| corresponding to the real value Lin1, the sign sign1 corresponding to the real value Lin1; the absolute value |Lin2| corresponding to the real value Lin2, the sign sign2 corresponding to the real value Lin2.

It is easy to understand that in the embodiment of the present application, the symbol refers to the analog domain symbol, and the two can be replaced with each other. For the sake of simplicity, the embodiment of the present application takes the symbol as an example for introduction. When the frozen bit is 1, the value of the symbol corresponding to the frozen bit is +1. Conversely, when the frozen bit is 0, the value of the symbol corresponding to the frozen bit is -1. In the process of XOR operation of symbols, if the symbols to be XORed are the same, the result of the XOR operation is the symbol of the frozen bit. If the symbols to be XORed are different, the result of the XOR operation is another symbol of the frozen bit. For example, referring to Table 1, Table 1 shows the following four XOR operation situations:

When the frozen bit X is 1 and the information bit Y is 1, the values of the symbols are all +1, and the frozen result of the XOR operation of the two symbols is +1.

When the frozen bit X is 0 and the information bit Y is 0, the value of the symbol is -1, and the result of the XOR operation of these two symbols is -1.

When the frozen bit X is 0 and the information bit Y is 1, the value of the symbol corresponding to the frozen bit is -1, and the value of the symbol corresponding to the information bit is +1. The XOR operation of these two symbols results in a frozen result of +1.

When the frozen bit X is 1 and the information bit Y is 0, the value of the symbol corresponding to the frozen bit is +1, and the value of the symbol corresponding to the information bit is -1. The XOR operation of these two symbols results in a freezing result of -1. This is explained here uniformly and will not be repeated in the following text.

Table 1

In Fig. 5, SM502 is used to multiply at least two symbols. That is, the input of SM502 includes two or more symbols, and the output of SM502 includes one symbol, which is the symbol obtained by multiplying the symbols input by SM502.

Exemplarily, taking FIG5 as an example, the input of SM502 includes a symbol sign1 and a symbol sign2. The output of SM502 includes: a symbol, which is a symbol obtained by multiplying the symbol sign1 and the symbol sign2.

In FIG5 , the WTA module 503 is used to obtain the minimum value among multiple absolute values. That is, the input of the WTA module 503 includes two or more absolute values, and the output of the WTA module 503 includes an absolute value, which is the minimum of the multiple absolute values input to the WTA module 503.

Exemplarily, taking FIG5 as an example, the input of the WTA module 503 includes an absolute value |Lin1| and an absolute value |Lin2|. The output of the WTA module 503 includes: an absolute value |L _i |, and the absolute value |L _i | is the smaller of the absolute value |Lin1| and the absolute value |Lin2|.

5 , the ASTR converter 504 is used to multiply the absolute value and the sign. That is, the input of the ASTR converter 504 includes an absolute value and a sign, and the output of the ASTR converter 504 includes a real value, which is the product of the absolute value and the sign input to the ASTR converter 504.

Exemplarily, taking FIG5 as an example, the input of the ASTR converter 504 includes the absolute value |L _i | and the sign output by SM502. The output of the ASTR converter 504 includes: a real value obtained by multiplying the absolute value |L _i | and the sign output by SM502. In FIG5, it is denoted as f(Lin1, Lin2).

As can be seen from the introduction of FIG. 5 above, the circuit structure shown in FIG. 5 can realize the function of the f operation. The formula of the f operation is f(Lin1, Lin2) = sign(Lin1)sign(Lin2)min(|Lin1|,|Lin2|), that is, the input of the f operation is two real values (that is, the real value Lin1 and the real value Lin2), and the output of the f operation is a real value (that is, the real value sign(lin1)sign(Lin2)min(|Lin1|,|Lin2|)).

It is easy to understand that FIG5 exemplarily shows the analog circuit structure of the f operation circuit, which should not be understood as limiting the embodiment of the present application. Of course, if there are other analog circuit structures that can realize the f operation function, they also fall within the protection scope of the embodiment of the present application.

It is easy to understand that in the embodiments of the present application, the f operation circuit involved can refer to the circuit structure shown in Figure 5, which is uniformly explained here and will not be repeated in the following text.

2. Structure of g operation circuit

Referring to FIG6 , FIG6 shows a schematic diagram of a g operation circuit structure. In FIG6 , the g operation circuit includes a sign and real multiplier (SRM) 601 and a real adder (RA) 602. The functions of each component are described as follows:

In Fig. 6, SRM601 is used to multiply a real value and a sign. That is, the input of SRM601 includes a real value and a sign, and the output of SRM601 includes a real value, which is the product of the real value and the sign input to SRM601.

Exemplarily, taking FIG6 as an example, the input of SRM601 includes the real value Lin2 and the symbol b. The output of SRM601 includes: the product of the real value Lin2 and the symbol b.

In Fig. 6, RA602 is used to add at least two real values. That is, the input of RA602 includes two or more real values, and the output of RA602 includes a real value obtained by adding the real values input by RA602.

For example, taking FIG6 as an example, the input of RA602 includes the real value Lin1 and the real value output by SRM601. The output of RA602 includes: a real value, which is obtained by adding the real value Lin1 and the real value output by SRM601. In FIG6, it is denoted as g(Lin1, Lin2, b).

From the above introduction of FIG. 6 , it can be known that the circuit structure shown in FIG. 6 can realize the function of g operation.

Referring to FIG. 7 , FIG. 7 shows a schematic diagram of a g operation circuit structure. In FIG. 7 , the g operation circuit includes an RTAS converter 701, an SM 702, an ASTR converter 703, an RA 704 and a delay control circuit 705. The functions of each component are described as follows:

In Fig. 7, RTAS converter 701 is used to convert real values into signs and absolute values. That is, the input of RTAS converter 701 includes one or more real values, and the output of RTAS converter 701 includes the absolute value and analog domain sign of each real value.

Exemplarily, taking FIG7 as an example, the input of the RTAS converter 701 includes the real value Lin2. The output of the RTAS converter 701 includes: the absolute value |Lin2| corresponding to the real value Lin2, and the analog domain symbol sign2 corresponding to the real value Lin2.

In Fig. 7, SM702 is used to multiply at least two symbols. That is, the input of SM702 includes two or more symbols, and the output of SM702 includes one symbol obtained by multiplying the symbols input to SM702.

7 , the input of SM702 includes symbol b and the symbol output by RTAS converter 701. The output of SM702 includes: a symbol obtained by multiplying symbol b and the symbol output by RTAS converter 701.

In Fig. 7, ASTR converter 703 is used to multiply an absolute value and a sign. That is, the input of ASTR converter 703 includes an absolute value and a sign, and the output of ASTR converter 703 includes a real value, which is the product of the absolute value and the sign input by ASTR converter 703.

7 , the input of the ASTR converter 703 includes the absolute value |Lin2| and the sign output by SM702. The output of the ASTR converter 703 includes: a real value obtained by multiplying the absolute value |Lin2| and the sign output by SM702.

In Fig. 7, RA704 is used to add at least two real values, that is, the input of RA704 includes two or more real values, and the output of RA704 includes a real value obtained by adding the real values input by RA704.

Exemplarily, taking FIG. 7 as an example, the input of RA704 includes the real value Lin1 and the real value output by the ASTR converter 703. The output of RA704 includes: a real value, which is obtained by adding the real value Lin1 and the real value output by the ASTR converter 703. In FIG. 7, it is denoted as g(Lin1, Lin2, b).

In FIG. 7 , a delay control circuit 705 is used to delay an input signal.

Exemplarily, taking FIG. 7 as an example, the delay control circuit 705 is used to delay the input of the real value Lin1.

From the above introduction of FIG. 7 , it can be known that the circuit structure shown in FIG. 7 can realize the function of g operation.

It is easy to understand that FIG6 or FIG7 exemplarily shows the analog circuit structure of the g operation circuit, which should not be understood as limiting the embodiments of the present application. Of course, if there are other analog circuit structures that can realize the g operation function, they also fall within the protection scope of the embodiments of the present application.

It is easy to understand that in the embodiments of the present application, the g operation circuit involved can refer to the circuit structure shown in Figure 6 or Figure 7, which is uniformly explained here and will not be repeated in the following text.

3. Structure of path metric circuit

First, let's introduce the formula that the path metric satisfies:

in,

represents the path metric value of the i-th decoding path,

Indicates the path metric value of the i-1th decoding path.

express

The absolute value of

represents a log-likelihood ratio (LLR), and the LLR represents the logarithm of the ratio of the probability that the value of the i-th bit is 0 to the probability that the value of the i-th bit is 1. The LLR is based on

and

definite,

represents a value of N bits and is a value determined by the decoding device according to the received coded sequence,

The i-th decoding path indicates the estimated value of the first i bits, and the i-1-th decoding path indicates the estimated value of the first i bits.

In formula (1), the first segment indicates that u _i is an information bit or a correct frozen bit, and

That is, when u _i is an information bit or a correct frozen bit, and

in the case of,

In formula (1), the second segment indicates that u _i is an information bit or a correct frozen bit, and

That is, when u _i is an information bit or a correct frozen bit, and

in the case of,

In formula (1), the third segment indicates that u _i is a frozen bit and has an incorrect value. In this case,

Referring to FIG8 , FIG8 shows a schematic diagram of the structure of a path metric circuit. The path metric circuit includes an RTAS converter 801, an SM 802, a calculation unit 803, a real number multiplier 804 and an RA 805. The functions of each component are described as follows:

In Fig. 8, RTAS converter 801 is used to convert real values into signs and absolute values. That is, the input of RTAS converter 801 includes one or more real values, and the output of RTAS converter 801 includes the absolute value and analog domain sign of each real value.

Exemplarily, taking FIG8 as an example, the input of the RTAS converter 801 includes a real value L. The output of the RTAS converter 801 includes: an absolute value |L| corresponding to the real value L, and an analog domain symbol sign(L) corresponding to the real value L.

In Fig. 8, SM802 is used to multiply at least two symbols. That is, the input of SM802 includes two or more symbols, and the output of SM802 includes one symbol, which is the symbol obtained by multiplying the symbols input by SM802.

Exemplarily, taking FIG8 as an example, the input of SM802 includes a symbol u _i =-1 and a symbol sign(L). The output of SM802 includes: a symbol, which is obtained by multiplying the symbol u _i =-1 and the symbol sign(L). Specifically, when u _i =-1 and the symbol sign(L) is negative, the output of SM802 is +1. When u _i =-1 and the symbol sign(L) is positive, the output of SM802 is -1.

In FIG8 , the calculation unit 803 is used to perform the calculation of 0.5x-0.5.

For example, when the output of SM802 is +1, it means that the value of x in "05x-0.5" is +1. Accordingly, the value output by the calculation unit 803 is 0. When the output of SM802 is -1, it means that the value of x in "05x-0.5" is -1. Accordingly, the value output by the calculation unit 803 is -1.

In Fig. 8, real number multiplier 804 is used to multiply at least two real numbers. That is, the input of real number multiplier 804 includes two or more real numbers, and the output of real number multiplier 804 includes a real number obtained by multiplying the real numbers input to real number multiplier 804.

Exemplarily, taking FIG8 as an example, the input of the real number multiplier 804 includes the absolute value |L| and the value output by the calculation unit 803. The output of the real number multiplier 804 includes: a real number, which is obtained by multiplying the absolute value |L| and the value output by the calculation unit 803. Specifically, when the value output by the calculation unit 803 is -1, the value output by the real number multiplier 804 is -|L|. When the value output by the calculation unit 803 is 0, the value output by the real number multiplier 804 is 0.

In Fig. 8, RA805 is used to add at least two real values, that is, the input of RA805 includes two or more real values, and the output of RA805 includes a real value obtained by adding the real values input by RA805.

For example, taking Figure 8 as an example, the input of RA805 includes

and the value output by the real number multiplier 804. The output of RA805 includes: a real value, which is

Specifically, when the value output by the real number multiplier 804 is 0, the result output by RA805 is

When the value output by the real number multiplier 804 is -|L|, the result output by RA805 is

It is easy to understand that for the scenario where u _i is the correct frozen bit,

In this case, the circuit shown in FIG8 can realize the functions of the first segment and the second segment in formula (1).

It is easy to understand that for the scenario where u _i is a frozen bit and the value is wrong,

And the path metric circuit does not output the decoding result. The circuit shown in FIG8 does not consider this situation.

In the embodiment of the present application, the path measurement circuit of the frozen bit involved can refer to the circuit structure shown in Figure 8, which is uniformly explained here and will not be repeated in the following text.

Referring to FIG. 9 , FIG. 9 shows a schematic diagram of the structure of another path metric circuit. The path metric circuit includes a first processing module 901, a second processing module 902 and a compare converter (compare converter, CC) 903. The functions of each component are described as follows:

In FIG9 , the first processing module 901 is used to determine the path metric value 1 corresponding to _ui =1.

Exemplarily, the circuit structure of the first processing module 901 may be referred to as shown in FIG8 , which will not be described in detail here.

The _ui =1 inputted by the first processing module 901 means that the possible value of the ith bit _ui is 1.

Among them, the path metric value 1 can be recorded as

In FIG9 , the second processing module 902 is used to determine the path metric value 2 corresponding to _ui =-1.

Exemplarily, the circuit structure of the second processing module 902 may be referred to as shown in FIG8 , which will not be described in detail here.

The _ui =-1 inputted by the second processing module 902 means that the possible value of the i-th bit _ui is -1.

Among them, the path metric value 1 can be recorded as

In FIG9 , CC903 is used to compare path metric value 1 and path metric value 2 to output the larger path metric value and _ui corresponding to the larger path metric value. Specifically, when path metric value 1 is larger, CC903 outputs

When the path metric value is 1, CC903 outputs u _i = 1. When the path metric value 2 is larger, CC903 outputs

The path metric value is 2, and _ui output by CC903 is -1.

The _ui output by CC903 is the estimated value of the ith bit _ui . Specifically, when CC903 outputs _ui =1, it means that the estimated value of the ith bit _ui is 1. When CC903 outputs _ui =-1, it means that the estimated value of the ith bit _ui is -1.

It is easy to understand that for the scenario where u _i is an information bit,

In this case, the circuit shown in FIG9 can realize the functions of the first segment and the second segment in formula (1).

It is easy to understand that FIG8 or FIG9 exemplarily shows the analog circuit structure of the path metric circuit, which should not be understood as limiting the embodiments of the present application. Of course, if there are other analog circuit structures that can realize the path metric calculation function, they also fall within the protection scope of the embodiments of the present application.

In the embodiment of the present application, the path measurement circuit of the information bit involved can refer to the circuit structure shown in Figure 9, which is uniformly explained here and will not be repeated in the following text.

Next, taking different code lengths N and code rates R as examples, the analog circuit 401 is introduced:

Embodiment 1:

Taking FIG. 10a as an example, the code length N=4 and the code rate R=1/4. In FIG. 10a, _b1 , _b2 , _b3 are frozen bits and _b4 is an information bit. The symbol value of the frozen bit forward feedback is fixed. Therefore, it is not necessary to perform f operation and g operation for each bit, and it is sufficient to perform the operation on the 4th bit (i.e., _b4 ). The analog signal includes _z1 , _z2 , _z3 , _z4 . Among them, the analog signal is determined by the decoding device 400 according to the received coded sequence, such as the decoding device 400 determines the LLR of the received coded sequence. The above _z1 , _z2 , _z3 , _z4 are LLR values determined by the decoding device 400. _z1 represents the LLR value of the 1st bit, _z2 represents the LLR value of the 2nd bit, _z3 represents the LLR value of the 3rd bit, and _z4 represents the LLR value of the 4th bit.

In some embodiments, taking FIG. 10b as an example, the analog circuit 401 includes a g operation circuit 1001 and a sign conversion circuit 1002. The introduction of each circuit part is as follows:

The functions of the g operation circuit 1001 include: receiving the value of the frozen bit, acquiring the analog signal, and performing the g operation on the value of the frozen bit and the analog signal.

Taking FIG. 10b as an example, the g operation circuit 1001 includes a g operation circuit A, a g operation circuit B and a g operation circuit C. The three g operation circuits are introduced as follows:

The functions of the g operation circuit A include:

The g operation circuit A is used to receive the value of the first frozen bit, such as b ₁ =-1.

The g operation circuit A is used to obtain the value of the first part of bits in the analog signal, wherein the first part of bits includes a part of bits in the encoded sequence, such as z ₁ =-1, z ₂ =-1.

The g operation circuit A is used to perform a g operation on the value of the first frozen bit and the value of the first part of bits. In FIG10 b , the processing of the g operation circuit A is denoted as g1 (z ₁ , z ₂ , b ₁ ).

The functions of the g operation circuit B include:

The g operation circuit B is used to receive the value of the second frozen bit, such as b ₂ =-1.

The g operation circuit B is used to receive the value of the second part of bits. The second part of bits includes the bits in the encoded sequence except the first part of bits, such as z ₃ =-1, z ₄ =-1.

The g operation circuit B is used to perform a g operation on the value of the second frozen bit and the value of the second part of bits. In FIG10 b , the processing of the g operation circuit B is denoted as g2 (z ₃ , z ₄ , b ₂ ).

The functions of the g operation circuit C include:

The g operation circuit C is used to receive the value of the third frozen bit, such as b ₃ =-1.

The g operation circuit C is used to receive the result of the g operation circuit A and the result of the g operation circuit B. In FIG10 b , the result of the g operation circuit A is denoted as g1, and the result of the g operation circuit B is denoted as g2.

The g operation circuit C is used to perform a g operation on the value of the third frozen bit, the result of the g operation circuit A and the result of the g operation circuit B. In Fig. 10b, the processing of the g operation circuit C is denoted as g3 ( _g1 , _g2 , _b3 ).

That is, in the g operation circuit 1001, the conditional probability of the information bit is determined by the g operation circuit A, the g operation circuit B and the g operation circuit C.

The function of the sign conversion circuit 1002 includes: performing sign processing on the result of the g operation circuit 1001 to obtain an estimated value of the information bit.

Taking FIG. 10b as an example, the sign conversion circuit 1002 is used to perform sign-taking (eg, inversion) processing on the result of the g operation circuit C to obtain an estimated value of the information bit, that is, an estimated value of _b4 .

In this way, for some decoding methods of polar codes, such as SC decoding, there is no need to calculate the path metric, and the receiving device can decode the analog signal through the g operation circuit 1001 and the symbol conversion circuit 1002.

In some other embodiments, taking FIG. 10c as an example, the analog circuit 401 includes a g operation circuit 1001 and a path metric circuit 1003. The introduction of each circuit part is as follows:

The g operation circuit 1001 can be referred to the introduction of FIG10b, which will not be described again here.

The functions of the path metric circuit 1003 include:

The path metric circuit 1003 is used to receive a first path metric value, wherein the first path metric value is a metric value of a first decoding path, and the first decoding path indicates a value of a frozen bit.

Taking Figure 10c as an example, the first path metric value can be recorded as

That is, the first decoding path indicates the values of three frozen bits (ie, b ₁ , b ₂ , b ₃ ).

The path metric circuit 1003 is used to determine the estimated value of the information bit according to the first path metric value and the result of the g operation circuit 1001.

Among them, the path measurement circuit 1003 can refer to the introduction of Figure 9, which will not be repeated here.

Taking FIG. 10c as an example, the path metric circuit 1003 is used to determine the estimated value of the information bit, that is, the estimated value of _b4 , according to the first path metric value and the result of the g operation circuit C.

In this way, for some decoding methods of polar codes, such as SCL decoding, it is necessary to calculate the path metric, and the receiving device can decode the analog signal through the g operation circuit 1001 and the path metric circuit 1003.

It is easy to understand that in FIG. 10b and FIG. 10c, the time when the analog current of the frozen bits _b1 and _b2 enters the circuit is controlled, and two g operations (i.e., the g operation performed by the g operation circuit A and the g operation performed by the g operation circuit B) are performed in parallel. After the two g operations are completed, the time when the frozen bit _b3 enters the circuit is controlled to complete the g operation performed by the g operation circuit C. In FIG. 10b or FIG. 10c, the symbols of the forward feedback are all the symbols of the frozen bits, and the moment when the symbols of the frozen bits enter the analog circuit 401 is controlled to complete the entire decoding process. No delay control is required between the g operation circuit A and the g operation circuit B, that is, no delay control circuit is required.

Embodiment 2:

Taking FIG. 11a as an example, the code length N=4 and the code rate R=3/4. In FIG. 11a, _b1 is a frozen bit, and _b2 , _b3 , _b4 are information bits. The symbol value of the frozen bit forward feedback is fixed. Therefore, it is not necessary to perform f operation and g operation for each bit, and it is sufficient to perform the operation on the 2nd, 3rd, and 4th bits (i.e., _b2 , _b3 , _b4 ). Similarly, the analog signal includes _z1 , _z2 , _z3 , _z4 . Among them, the analog signal is determined by the decoding device 400 according to the received coded sequence, such as the decoding device 400 determines the LLR of the received coded sequence. The above _z1 , _z2 , _z3 , _z4 are the LLR values determined by the decoding device 400. z ₁ represents the LLR value of the first bit, z ₂ represents the LLR value of the second bit, z ₃ represents the LLR value of the third bit, and z ₄ represents the LLR value of the fourth bit.

In the second embodiment, the analog signal is divided into two parts, which are respectively recorded as the first signal and the second signal. Exemplarily, the first signal includes z ₁ =-1, z ₃ =-1. The second signal includes z ₂ =-1, z ₄ =-1.

In some embodiments, taking FIG. 11b as an example, the encoded sequence includes K bits, wherein the first bit of the K bits is a frozen bit, the second bit to the Kth bit of the K bits are information bits, and K is a positive integer equal to N. When the code length N=4 and the code rate R=3/4, K=4.

The analog circuit 401 includes K-1 subcircuits. Each of the K-1 subcircuits includes an operation unit and a sign conversion circuit. The operation unit of the ith subcircuit is used to determine the probability distribution of the i+1th bit of the K bits. i is a positive integer less than K, and the ith subcircuit is the ith subcircuit of the K-1 subcircuits. The sign conversion circuit of the ith subcircuit is used to perform a sign operation on the probability distribution of the i+1th bit to obtain an estimated value of the i+1th bit.

Specifically, taking FIG. 11b as an example, the operation unit of the first subcircuit is recorded as the first operation unit 1101, and the sign conversion circuit of the first subcircuit is recorded as the first conversion circuit 1104. The operation unit of the second subcircuit is recorded as the second operation unit 1102, and the sign conversion circuit of the second subcircuit is recorded as the second conversion circuit 1105. The operation unit of the third subcircuit is recorded as the third operation unit 1103, and the sign conversion circuit of the third subcircuit is recorded as the third conversion circuit 1106. The introduction of each part of the circuit is as follows:

The first operation unit 1101 is used to receive the value of the first frozen bit and the target signal, and operate on the value of the first frozen bit and the target signal to determine the probability distribution of the first information bit. Wherein, when the code length N=4 and the code rate R=3/4, the target signal is an analog signal.

Taking FIG. 11 b as an example, the first operation unit 1101 includes an f operation circuit 1 , an f operation circuit 2 , and a g operation circuit 1 .

In FIG11 b , the f operation circuit 1 is used to receive a first signal and perform an f operation on the first signal, wherein the first signal is a part of the target signal.

Exemplarily, in FIG. 11 b , the first signal includes z ₁ =-1, z ₃ =-1.

In FIG11 b , the f operation circuit 2 is used to receive a second signal and perform an f operation on the second signal, wherein the second signal is a signal in the target signal other than the first signal.

Exemplarily, in FIG. 11 b , the second signal includes z ₂ =-1, z ₄ =-1.

In Figure 11b, the g operation circuit 1 is also used to receive the value of the first frozen bit, and perform the g operation on the value of the first frozen bit, the result of the f operation circuit 1 and the result of the f operation circuit 2 to obtain the processing result of the first operation unit (i.e., the probability distribution of the first information bit).

Exemplarily, the value of the first frozen bit is recorded as _b1 = -1, the result of f operation circuit 1 is recorded as f1, and the result of f operation circuit 2 is recorded as f2. The processing result of the first operation unit is recorded as g1 (f1, f2, b1).

That is, the first operation unit 1101 determines the conditional probability of the information bit _b2 through the f operation circuit and the g operation circuit.

The first conversion circuit 1104 is used to perform a sign operation on the processing result of the first operation unit 1101 to obtain an estimated value of the first information bit.

Among them, the first conversion circuit 1104 can refer to the introduction of the symbol conversion circuit in Figure 10b, which will not be repeated here.

Exemplarily, the processing result of the first operation unit 1101 is g1(f1, f2, b1). The first information bit is information bit _b2 . Accordingly, the first conversion circuit 1104 inputs g1(f1, f2, b1) to obtain an estimated value of information bit _b2 .

The second operation unit 1102 is used to receive the estimated value and the target signal of the first information bit, and perform operations on the estimated value and the target signal of the first information bit to obtain the probability distribution of the second information bit.

Taking FIG. 11 b as an example, the second operation unit 1102 includes an f operation circuit 3 , a g operation circuit 2 , and a g operation circuit 3 .

The g operation circuit 2 is used to receive the estimated value of the first information bit and the first signal, and perform a g operation on the estimated value of the first information bit and the first signal. The first signal is a part of the target signal, and the details are described in detail in the f operation circuit 1 in FIG. 11b , which will not be described again here.

The g operation circuit 3 is used to receive the estimated value of the first information bit and the second signal, and perform the g operation on the estimated value of the first information bit and the second signal. The second signal is a signal in the target signal other than the first signal. For details, please refer to the introduction of the f operation circuit 2 in FIG. 11 b, which will not be repeated here.

The f operation circuit 3 is used to process the result of the g operation circuit 2 and the result of the g operation circuit 3 to obtain the processing result of the second operation unit (ie, the probability distribution of the second information bit).

Exemplarily, the result of g operation circuit 2 is recorded as g2, and the result of g operation circuit 3 is recorded as g3. The processing result of the second operation unit is recorded as f3 (g2, g3). The second information bit is _b3 .

That is to say, the second operation unit 1102 can determine the conditional probability of the information bit _b3 through the f operation circuit and the g operation circuit.

The second conversion circuit 1105 is used to perform a sign operation on the processing result of the second operation unit to obtain an estimated value of the second information bit.

Among them, the second conversion circuit 1105 can refer to the introduction of the symbol conversion circuit in Figure 10b, which will not be repeated here.

Exemplarily, the processing result of the second operation unit 1102 is f3(g2, g3). The second information bit is information bit _b3 . Accordingly, the second conversion circuit 1105 inputs f3(g2, g3) to obtain an estimated value of information bit _b3 .

The third operation unit 1103 is used to receive and process the estimated value of the first information bit, the estimated value of the second information bit and the target signal to obtain the probability distribution of the third information bit.

Taking FIG. 11b as an example, the third operation unit 1103 includes g operation circuit 2, g operation circuit 3 and g operation circuit 4. For g operation circuit 2 and g operation circuit 3, refer to the introduction of the second operation unit 1102, which will not be repeated here.

The g operation circuit 4 is used to receive the estimated value of the second information bit, the result of the g operation circuit 2 and the result of the g operation circuit 3, and perform the g operation on the estimated value of the second information bit, the result of the g operation circuit 2 and the result of the g operation circuit 3 to obtain the processing result of the third operation unit 1103 (i.e., the probability distribution of the third information bit).

Exemplarily, the second information bit is b ₃ , the result of g operation circuit 2 is recorded as g2, and the result of g operation circuit 3 is recorded as g3. The processing result of the third operation unit is recorded as g4 (g2, g3, b3). The third information bit is b ₄ .

That is to say, the third operation unit 1103 can determine the conditional probability of the information bit _b4 through the g operation circuit.

The third conversion circuit 1106 is used to perform a sign operation on the processing result of the third operation unit to obtain an estimated value of the third information bit.

Among them, the third conversion circuit 1106 can refer to the introduction of the symbol conversion circuit in Figure 10b, which will not be repeated here.

Exemplarily, the processing result of the third operation unit 1103 is g4 (g2, g3, b3). The third information bit is _b4 . Accordingly, the third conversion circuit 1106 inputs g4 (g2, g3, b3) to obtain an estimated value of the information bit _b4 .

It is easy to understand that, when the code length N=4 and the code rate R=3/4, the analog circuit 401 obtains the estimated values of the information bits b ₂ , b ₃ , and b ₄ , which means that the analog circuit 401 determines the decoding result.

In this way, for some decoding methods of polar codes, such as SC decoding, there is no need to calculate the path metric. When the code length N = 4 and the code rate R = 3/4, the receiving device can decode the analog signal through the operation unit and the symbol conversion circuit.

In some other embodiments, taking FIG. 11c as an example, the encoded sequence includes K bits, wherein the first bit of the K bits is a frozen bit, the second bit to the Kth bit of the K bits are information bits, and K is a positive integer equal to N. When the code length N=4 and the code rate R=3/4, K=4.

The analog circuit 401 includes K-1 subcircuits. Each of the K-1 subcircuits includes an operation unit and a path measurement circuit. The operation unit of the i-th subcircuit is used to determine the probability distribution of the i+1th bit of the K bits. i is a positive integer less than K. The i-th subcircuit is the i-th subcircuit of the K-1 subcircuits. The path measurement circuit of the i-th subcircuit is used to receive the path measurement value of the i-th decoding path, and determine the estimated value of the i+1th bit according to the path measurement value of the i-th decoding path and the probability distribution of the i+1th bit. The i-th decoding path indicates the value of the first i bits of the K bits.

Specifically, taking FIG. 11c as an example, the operation unit of the first subcircuit is recorded as the first operation unit 1101, and the path metric circuit of the first subcircuit is recorded as the first path metric circuit 1107. The operation unit of the second subcircuit is recorded as the second operation unit 1102, and the path metric circuit of the second subcircuit is recorded as the second path metric circuit 1108. The operation unit of the third subcircuit is recorded as the third operation unit 1103, and the path metric circuit of the third subcircuit is recorded as the third path metric circuit 1109. The introduction of each part of the circuit is as follows:

The first operation unit 1101, the second operation unit 1102 and the third operation unit 1103 can be referred to the introduction of FIG. 11b, which will not be described again here.

The first path metric circuit 1107 is used to receive the path metric value of the first decoding path, and determine the estimated value of the first information bit according to the path metric value of the first decoding path and the probability distribution of the first information bit, wherein the first decoding path indicates the value of the first frozen bit.

Taking FIG. 11c as an example, the first frozen bit is _b1 . The first decoding path indicates the value of the frozen bit _b1 . The path metric value of the first decoding path is recorded as

The first information bit is b ₂ , and the probability distribution of the first information bit is recorded as g1(f1, f2, b1). The first path metric circuit 1107 is based on

and g1(f1, f2, b1), determine the estimated value of information bit _b2 . The first path metric circuit 1107 can be referred to the introduction of FIG9, which will not be described again here.

The second path metric circuit 1108 is used to receive the path metric value of the second decoding path, and determine the estimated value of the second information bit according to the path metric value of the second decoding path and the probability distribution of the second information bit, wherein the second decoding path indicates the value of the first frozen bit and the estimated value of the first information bit.

Taking FIG11c as an example, the first frozen bit is _b1 , the first information bit is _b2 , and the second decoding path indicates the value of the frozen bit _b1 and the estimated value of the information bit _b2 . The path metric value of the second decoding path is recorded as

The second information bit is b ₃ , and the probability distribution of the second information bit is recorded as f3(g2, g3). The second path metric circuit 1108 is based on

and f3(g2, g3), determine the estimated value of information bit _b3 . The second path metric circuit 1108 can be referred to the introduction of FIG9, which will not be described again here.

The third path metric circuit 1109 is configured to receive a path metric value of a third decoding path, and determine an estimated value of the third information bit according to the path metric value of the third decoding path and the probability distribution of the third information bit, wherein the third decoding path indicates the value of the first frozen bit, the estimated value of the first information bit, and the estimated value of the second information bit.

Taking FIG. 11c as an example, the first frozen bit is _b1 , the first information bit is _b2 , the second information bit is _b3 , and the third decoding path indicates the value of the frozen bit _b1 , the estimated value of the information bit _b2 , and the estimated value of the information bit _b3 . The path metric value of the third decoding path is recorded as

The third information bit is b ₄ , and the probability distribution of the third information bit is recorded as g4 (g2, g3, b3). The third path metric circuit 1109 is based on

and g4(g2, g3, b3), determine the estimated value of information bit _b4 . The third path metric circuit 1109 can be referred to the introduction of FIG9, which will not be described again here.

In this way, for some decoding methods of polar codes, such as SCL decoding, path metrics need to be calculated. When the code length N=4 and the code rate R=3/4, the receiving device can decode the analog signal through the operation unit and the path metric circuit.

It is easy to understand that in Figure 11b and Figure 11c, after z ₁ , z ₂ , z ₃ , z ₄ enter the f operation circuit 1 and the f operation circuit 2, two f operations (i.e., the f operations performed by the f operation circuit 1 and the f operation circuit 2) are performed in parallel, and z ₁ , z ₂ , z ₃ , z ₄ entering the g operation circuit 2 and the g operation circuit 3 are all delayed until the estimated value of the information bit b ₂ is obtained.

Then, after the results of g operation circuit 2 and g operation circuit 3 enter f operation circuit 3, f operation (i.e., f operation performed by f operation circuit 3) is performed, and the results of g operation circuit 2 and g operation circuit 3 are delayed until an estimated value of information bit _b3 is obtained.

In addition, the analog circuit for information bit _b3 and the analog circuit for information bit _b4 are delayed controlled until the estimated value of information bit _b4 is obtained, and the analog circuit 401 outputs the estimated values of information bits _b2 , _b3 , and _b4 together as the decoding result.

Embodiment three:

Taking FIG. 12a as an example, the code length N=8 and the code rate R=3/8. In FIG. 12a, _b1 , _b2 , _b3 , _b4 , _b5 are frozen bits, and _b6 , _b7 , _b8 are information bits. The symbol value of the frozen bit forward feedback is fixed. Therefore, it is not necessary to perform f operation and g operation for each bit, and it is sufficient to perform the operation on the 6th, 7th, and 8th bits (i.e., _b6 , _b7 , _b8 ). Similarly, the analog signal includes _z1 , _z2 , _z3 , _z4 , _z5 , _z6 , _z7 , _z8 . The analog signal is determined by the decoding device 400 according to the received coded sequence, such as the decoding device 400 determines the LLR of the received coded sequence. The above z ₁ , z ₂ , z ₃ , z ₄ , z ₅ , z ₆ , z ₇ , z ₈ are LLR values determined by the decoding device 400. z ₁ represents the LLR value of the first bit, z ₂ represents the LLR value of the second bit, z ₃ represents the LLR value of the third bit, z ₄ represents the LLR value of the fourth bit, and the same applies to the others, which will not be described in detail.

In the third embodiment, the analog signal is divided into four parts, which are respectively recorded as the third signal, the fourth signal, the fifth signal and the sixth signal. Exemplarily, the third signal includes z ₁ , z ₅ , the fourth signal includes z ₂ , z ₆ , the fifth signal includes z ₃ , z ₇ , and the sixth signal includes z ₄ , z ₈ .

In some embodiments, taking FIG. 12b or FIG. 12c as an example, the encoded sequence includes K bits. Among them, the first bit of the K bits is a frozen bit, the second bit to the Kth bit of the K bits are information bits, and K is a positive integer less than N. In addition to the K bits, the encoded sequence also includes L frozen bits, and the L frozen bits are before the K bits. L is a positive integer less than N. When the code length N=8 and the code rate R=3/4, K=L=4.

The analog circuit 401 includes K-1 subcircuits. Each of the K-1 subcircuits includes an operation unit and a sign conversion circuit. Each of the K-1 subcircuits can be described in the description of FIG. 11b or FIG. 11c, which will not be described here. In addition to the K-1 subcircuits, the analog circuit also includes g operation circuit 5, g operation circuit 6, g operation circuit 7 and g operation circuit 8. The description of g operation circuits 5 to 8 is as follows:

The g operation circuit 5 is used to perform a g operation on the estimated value of the first target bit and the third signal, wherein the first target bit is one of the L frozen bits, and the third signal is a part of the analog signal.

Taking FIG. 12b (or FIG. 12c) as an example, the first target bit is the frozen bit _b4 . The third signal includes _z1 , _z5 . The result of the g operation circuit 5 can be recorded as g5 ( _z1 , _z5 , _b4 ).

The g operation circuit 6 is used to perform a g operation on the estimated value of the first target bit and the fourth signal, wherein the fourth signal is another part of the analog signal, and the third signal is different from the fourth signal.

Taking FIG. 12b (or FIG. 12c) as an example, the first target bit is the frozen bit _b4 . The fourth signal includes _z2 , _z6 . The result of the g operation circuit 6 can be recorded as g6 ( _z2 , _z6 , _b4 ).

The g operation circuit 7 is used to perform a g operation on the estimated value of the first target bit and the fifth signal, wherein the fifth signal is another part of the analog signal, and the third signal, the fourth signal and the fifth signal are different from each other.

Taking FIG. 12b (or FIG. 12c) as an example, the first target bit is the frozen bit _b4 . The fifth signal includes _z3 and _z7 . The result of the g operation circuit 7 can be recorded as g7 ( _z3 , _z7 , _b4 ).

The g operation circuit 8 is used to perform a g operation on the estimated value of the first target bit and the sixth signal, wherein the sixth signal is another part of the analog signal, and the third signal, the fourth signal, the fifth signal and the sixth signal are different from each other.

Taking FIG. 12b (or FIG. 12c) as an example, the first target bit is the frozen bit _b4 . The sixth signal includes _z4 , _z8 . The result of the g operation circuit 8 can be recorded as g8 ( _z4 , _z8 , _b4 ).

It is easy to understand that in FIG. 12b (or FIG. 12c), for f operation circuit 1, f operation circuit 2, g operation circuit 2 and g operation circuit 3, the target signal is determined according to the analog signal. Specifically, the first signal in the target signal includes the result of g operation circuit 5 and the result of g operation circuit 7. The second signal in the target signal includes the result of g operation circuit 6 and the result of g operation circuit 8. In other words, the result of g operation circuit 5 in FIG. 12b (or FIG. 12c) is equivalent to z ₁ in FIG. 11b (or FIG. 11c). The result of g operation circuit 6 in FIG. 12b (or FIG. 12c) is equivalent to z ₂ in FIG. 11b (or FIG. 11c). The result of g operation circuit 7 in FIG. 12b (or FIG. 12c) is equivalent to z ₃ in FIG. 11b (or FIG. 11c). The result of g operation circuit 8 in FIG. 12b (or FIG. 12c) is equivalent to z ₄ in FIG. 11b (or FIG. 11c).

In summary, FIG12b shows an analog circuit structure without calculating the path metric, and for some decoding methods of polar codes, such as SC decoding, no path metric needs to be calculated. When the code length N=8 and the code rate R=3/4, the receiving device can decode the analog signal through the operation unit, the symbol conversion circuit, the g operation circuit 5, the g operation circuit 6, the g operation circuit 7 and the g operation circuit 8.

FIG12c shows an analog circuit structure that needs to calculate the path metric. For some decoding methods of polar codes, such as SCL decoding, the path metric needs to be calculated. When the code length N=8 and the code rate R=3/4, the receiving device can decode the analog signal through the operation unit, the symbol conversion circuit, the g operation circuit 5, the g operation circuit 6, the g operation circuit 7 and the g operation circuit 8.

It is easy to understand that in FIG. 12b and FIG. 12c, z ₁ , z ₂ , z ₃ , z ₄ , z ₅ , z ₆ , z ₇ , z ₈ and frozen bit b ₄ are controlled to enter the circuit at the same time, and four g operations (i.e., g operations performed by g operation circuits 5 to 8) are performed in parallel. For other information, please refer to the introduction of FIG. 11b or FIG. 11c, which will not be described here. In FIG. 12b or FIG. 12c, the symbols of the forward feedback are all the symbols of the frozen bits, and the moment when the symbols of the frozen bits enter the analog circuit 401 is controlled to complete the entire decoding process. No delay control is required before the g operation circuits 5 to 8, that is, no delay control circuit is required.

Embodiment 4:

Taking FIG. 13a as an example, the code length N=8 and the code rate R=1/2. In FIG. 13a, _b1 , _b2 , _b3 , _b4 are frozen bits, and _b5 , _b6 , _b7 , _b8 are information bits. The symbol value of the frozen bit forward feedback is fixed. Therefore, it is not necessary to perform f operation and g operation for each bit, and it is sufficient to perform the operation on the 5th, _6th , 7th, and 8th bits (i.e., _b5 , b6, _b7 , _b8 ). Similarly, the analog signal includes _z1 , _z2 , _z3 , _z4 , _z5 , _z6 , _z7 , _z8 . The analog signal is determined by the decoding device 400 according to the received coded sequence, such as the decoding device 400 determines the LLR of the received coded sequence. The above z ₁ , z ₂ , z ₃ , z ₄ , z ₅ , z ₆ , z ₇ , z ₈ are LLR values determined by the decoding device 400. z ₁ represents the LLR value of the first bit, z ₂ represents the LLR value of the second bit, z ₃ represents the LLR value of the third bit, z ₄ represents the LLR value of the fourth bit, and the same applies to the others, which will not be described in detail.

In the fourth embodiment, the analog signal is still divided into four parts, which are respectively recorded as the third signal, the fourth signal, the fifth signal and the sixth signal. Exemplarily, the third signal includes z ₁ , z ₅ , the fourth signal includes z ₂ , z ₆ , the fifth signal includes z ₃ , z ₇ , and the sixth signal includes z ₄ , z ₈ .

In some embodiments, taking FIG. 13b as an example, the encoded sequence includes K bits. Among them, the first bit of the K bits is a frozen bit, the second bit to the Kth bit of the K bits are information bits, and K is a positive integer less than N. In addition to the K bits, the encoded sequence also includes M bits, and the M bits are before the K bits. The M bits include one information bit and M-1 frozen bits. M is a positive integer less than N. When the code length N=8 and the code rate R=1/2, K=M=4.

The analog circuit 401 includes K-1 subcircuits, g operation circuit 5, g operation circuit 6, g operation circuit 7 and g operation circuit 8. Among them, each subcircuit in the K-1 subcircuits includes an operation unit and a symbol conversion circuit, which can be referred to in the introduction of Figure 11b or Figure 11c, and the g operation circuits 5 to 8 can be referred to in the introduction of Figure 12b or Figure 12c, which will not be repeated here. In addition to this (i.e., K-1 subcircuits, g operation circuits 5 to 8), the analog circuit also includes f operation circuit 4, f operation circuit 5, f operation circuit 6, f operation circuit 7, a first operation circuit and a fourth conversion circuit. Among them, the introduction of each circuit is as follows:

The f operation circuit 4 is used for performing an f operation on the third signal.

Taking FIG. 13 b as an example, the third signal includes z ₁ , z ₅ . The result of f operation circuit 4 can be recorded as f4 (z ₁ , z ₅ ).

The f operation circuit 5 is used for performing an f operation on the fourth signal.

Taking FIG. 13 b as an example, the fourth signal includes z ₂ , z ₆ . The result of f operation circuit 5 can be recorded as f5 (z ₂ , z ₆ ).

The f operation circuit 6 is used for performing an f operation on the fifth signal.

Taking FIG. 13 b as an example, the fifth signal includes z ₃ , z ₇ . The result of f operation circuit 6 can be recorded as f6 (z ₃ , z ₇ ).

The f operation circuit 7 is used for performing an f operation on the sixth signal.

Taking FIG. 13 b as an example, the sixth signal includes z ₄ , z ₈ . The result of f operation circuit 7 can be recorded as f7 (z ₄ , z ₈ ).

The first operation circuit 1301 is used to receive and process the values of M-1 frozen bits, the result of f operation circuit 4 , the result of f operation circuit 5 , the result of f operation circuit 6 and the result of f operation circuit 7 .

Taking FIG. 13b as an example, the first operation circuit 1301 includes a g operation circuit A, a g operation circuit B and a g operation circuit C. For details, please refer to the introduction of FIG. 10b, which will not be repeated here.

The M-1 frozen bits include frozen bits _b1 , _b2 , and _b3 . The result of the first operation circuit 1301 is recorded as g11 (g9, g10, b3). The specific operation process can be found in the introduction of FIG. 10b, which will not be repeated here.

The fourth conversion circuit 1302 is used to perform sign processing on the result of the first operation circuit 1301 to obtain an estimated value of the information bit in the M bits.

Taking FIG. 13b as an example, the fourth conversion circuit 1302 can refer to the introduction of the symbol conversion circuit 1002 in FIG. 10b, which will not be repeated here. The M bits include bits _b1 , _b2 , _b3 , _b4 , the frozen bits include bits _b1 , _b2 , _b3 , and the information bits include bit _b4 . The fourth conversion circuit 1302 performs a sign extraction process on g11 (g9, g10, b3) to obtain an estimated value of the information bit _b4 .

It is easy to understand that, in FIG13b, for g operation circuit A and g operation circuit B, the result of f operation circuit 4 in FIG13b is equivalent to _z1 in FIG10b (or FIG10c). The result of f operation circuit 5 in FIG13b is equivalent to _z2 in FIG10b (or FIG10c). The result of f operation circuit 6 in FIG13b is equivalent to _z3 in FIG10b (or FIG10c). The result of f operation circuit 7 in FIG13b is equivalent to _z4 in FIG10b (or FIG10c).

In summary, FIG13b shows an analog circuit structure without calculating the path metric, and for some decoding methods of polar codes, such as SC decoding, no path metric needs to be calculated. When the code length N=8 and the code rate R=1/2, the receiving device can decode the analog signal through the operation unit, the symbol conversion circuit, the g operation circuit 5, the g operation circuit 6, the g operation circuit 7, the g operation circuit 8, the f operation circuit 4, the f operation circuit 5, the f operation circuit 6, the f operation circuit 7, the first operation circuit and the fourth conversion circuit.

In addition, for some decoding methods of polar codes, such as SCL decoding, path metrics need to be calculated. When the code length N=8 and the code rate R=1/2, the receiving device can decode the analog signal through the operation unit, the symbol conversion circuit, the g operation circuit 5, the g operation circuit 6, the g operation circuit 7, the g operation circuit 8, the f operation circuit 4, the f operation circuit 5, the f operation circuit 6, the f operation circuit 7, the first operation circuit and the fourth conversion circuit.

It is easy to understand that in the embodiment of the present application, in the notation of LLR, taking four LLRs as an example, they are recorded as z ₁ , z ₂ , z ₃ , and z ₄ . Among them, the subscripts are used to distinguish different LLRs. The positions of the four LLR input analog circuit 401 can be replaced with each other. Taking Figure 10b (or Figure 10c, or Figure 11b, or Figure 11c) as an example, z ₂ and z ₃ can be replaced with each other. In the notation of the symbols corresponding to the frozen bits, taking three symbols as an example, they are recorded as b ₁ , b ₂ , and b ₃ . Among them, the subscripts are used to distinguish different symbols. The positions of the three symbols input analog circuit 401 can be replaced with each other. Taking Figure 10b (or Figure 10c) as an example, b ₂ and b ₃ can be replaced with each other, which should not be understood as a limitation on the embodiment of the present application.

Similarly, taking eight LLRs as an example, they are recorded as z ₁ , z ₂ , z ₃ , z ₄ , z ₅ , z ₆ , z ₇ , z ₈ . The subscripts are used to distinguish different LLRs. The positions of the eight LLR input analog circuit 401 can be replaced with each other. Taking Figure 12b (or Figure 12c) as an example, z ₂ and z ₃ can be replaced with each other. In the notation of frozen bit corresponding symbols, taking two symbols as an example, they are recorded as b ₄ and b ₅ . The subscripts are used to distinguish different symbols. The positions of the two symbols input analog circuit 401 can be replaced with each other. Taking Figure 12b (or Figure 12c) as an example, b ₄ and b ₅ can be replaced with each other, which should not be understood as a limitation on the embodiments of the present application.

The embodiment of the present application also provides a coding method 1400. The method is applicable to the communication system shown in Figures 1 to 2. As shown in Figure 14, the decoding method 1400 includes the following steps:

S1401. The encoding device encodes a sequence to be encoded to obtain an encoded sequence.

The encoding device may be located at the transmitting device side. Exemplarily, the encoding device uses Hadamard transform to encode the sequence to be encoded to obtain an encoded sequence.

Wherein, the length of the sequence to be encoded is N, N=2 ⁿ , and n is a positive integer. Exemplarily, the length of the sequence to be encoded is 4, as shown in FIG10 a . Alternatively, the length of the sequence to be encoded is 8, as shown in FIG12 a .

The sequence to be encoded includes at least one sub-block. The at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit.

Exemplarily, taking FIG. 10a as an example, the coded sequence includes 2 sub-blocks. The first sub-block includes b1 and b2, and the second sub-block includes b3 and b4. Each bit corresponding to the first sub-block is a frozen bit.

Exemplarily, taking FIG. 11a as an example, the coded sequence includes 2 sub-blocks. The first sub-block includes b1 and b2, and the second sub-block includes b3 and b4. Each bit corresponding to the second sub-block is an information bit.

Exemplarily, taking Figure 12a as an example, the coded sequence includes 2 sub-blocks. The first sub-block includes b1 to b4, and the second sub-block includes b5 to b8. Among them, each bit corresponding to the first sub-block is a frozen bit. Alternatively, the coded sequence includes 4 sub-blocks. The first sub-block includes b1 and b2, the second sub-block includes b3 and b4, the third sub-block includes b5 and b6, and the fourth sub-block includes b7 and b8. Among them, each bit corresponding to the first and second sub-blocks is a frozen bit, and each bit corresponding to the fourth sub-block is an information bit.

Exemplarily, taking FIG. 13a as an example, the coded sequence includes 4 sub-blocks. The first sub-block includes b1 and b2, the second sub-block includes b3 and b4, the third sub-block includes b5 and b6, and the fourth sub-block includes b7 and b8. Among them, each bit corresponding to the first sub-block is a frozen bit, and each bit corresponding to the fourth sub-block is an information bit.

S1402: The encoding device sends an encoded sequence. Correspondingly, the decoding device receives the encoded sequence.

Exemplarily, the encoding device sends the encoded sequence via a transmitter, and correspondingly, the decoding device receives the encoded sequence via a receiver.

It is easy to understand that the processing of the coded sequence before transmission through the channel, such as rate matching, precoding, interleaving, modulation, etc., is common knowledge to those skilled in the art and is not listed one by one. In the embodiments of the present application, the transmission of the coded sequence is taken as an example for introduction, which should not be understood as a limitation on the embodiments of the present application.

S1403: The decoding device obtains an analog signal according to the encoded sequence.

Exemplarily, the analog circuit in the decoding device obtains an analog signal according to the encoded sequence, such as determining N LLRs. The structure of the analog circuit can be seen in the introduction of FIG. 4 to FIG. 13 b , which will not be described in detail here.

S1404: The decoding device analog circuit decodes the analog signal to obtain a decoding result.

Exemplarily, the analog circuit of the decoding device decodes the analog signal to obtain a decoding result. The process of the analog circuit determining the decoding result can be seen in the introduction of FIG. 4 to FIG. 13 b , which will not be described in detail here.

The method provided by the embodiment of the present application is described in detail above in conjunction with Figure 14. The following describes in detail an encoding device for executing the method provided by the embodiment of the present application in conjunction with Figures 15-16.

For example, Fig. 15 is a schematic diagram of the structure of the encoding device provided in the embodiment of the present application. As shown in Fig. 15, the encoding device 1500 includes: a processing module 1501 and a transceiver module 1502. For ease of description, Fig. 15 only shows the main components of the encoding device 1500.

In some embodiments, the encoding device 1500 may be applicable to the communication system shown in FIG. 1 to perform the functions of the encoding device in the method shown in FIG. 14 .

The processing module 1501 is used to encode the sequence to be encoded to obtain an encoded sequence. The sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit.

The transceiver module 1502 is used to send the encoded sequence.

Optionally, the transceiver module 1502 may include a receiving module and a sending module (not shown in FIG. 15 ). The transceiver module 1502 is used to implement the sending function and the receiving function of the encoding device 1500 .

Optionally, the coding device 1500 may further include a storage module (not shown in FIG. 15 ), which stores a program or instruction. When the processing module 1501 executes the program or instruction, the coding device 1500 may perform the function of the coding device in the method shown in FIG. 14 .

It should be understood that the processing module 1501 involved in the encoding device 1500 can be implemented by a processor or a processor-related circuit component, which can be a processor or a processing module; the transceiver module 1502 can be implemented by a transceiver or a transceiver-related circuit component, which can be a transceiver or a transceiver unit.

In addition, the technical effects of the encoding device 1500 can refer to the technical effects of the method shown in Figure 14, and will not be repeated here.

Exemplarily, FIG16 is a second structural schematic diagram of an encoding device provided in an embodiment of the present application. As shown in FIG16, the encoding device 1600 may include a processor 1601. Optionally, the encoding device 1600 may also include a memory 1602 and/or a transceiver 1603. The processor 1601 is coupled to the memory 1602 and the transceiver 1603, such as being connected via a communication bus.

The following is a detailed introduction to the various components of the encoding device 1600 in conjunction with FIG16 :

The processor 1601 is the control center of the encoding device 1600, which can be a processor or a general term for multiple processing elements. For example, the processor 1601 is one or more central processing units (CPUs), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application, such as one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs).

Optionally, the processor 1601 may perform various functions of the encoding device 1600 by running or executing a software program stored in the memory 1602 , and calling data stored in the memory 1602 .

In a specific implementation, as an embodiment, the processor 1601 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 16 .

In a specific implementation, as an embodiment, the encoding device 1600 may also include multiple processors, such as the processor 1601 and the processor 1604 shown in FIG16. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).

The memory 1602 is used to store the software program for executing the solution of the present application, and the execution is controlled by the processor 1601. The specific implementation method can refer to the above method embodiment, which will not be repeated here.

Optionally, the memory 1602 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1602 may be integrated with the processor 1601, or may exist independently and be coupled to the processor 1601 through an interface circuit (not shown in FIG. 16 ) of the encoding device 1600, which is not specifically limited in the embodiments of the present application.

The transceiver 1603 is used for communication with other devices. For example, the encoding device 1600 is a transmitting device, and the transceiver 1603 can be used for communication with a receiving device.

Optionally, the transceiver 1603 may include a receiver and a transmitter (not shown separately in FIG. 16 ), wherein the receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

Optionally, the transceiver 1603 may be integrated with the processor 1601, or may exist independently and be coupled to the processor 1601 via an interface circuit (not shown in FIG. 16 ) of the encoding device 1600, which is not specifically limited in the embodiments of the present application.

It is easy to understand that the structure of the encoding device 1600 shown in Figure 16 does not constitute a limitation on the encoding device, and the actual encoding device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

In addition, the technical effects of the encoding device 1600 can refer to the technical effects of the method described in the above method embodiment, and will not be repeated here.

It should be understood that the processor in the embodiment of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

Optionally, the embodiment of the present application further provides a computer program product carrying computer instructions, when the computer instructions are executed on a processor, the analog circuit in the decoding device performs the following steps: the analog circuit acquires an analog signal. The analog signal is determined by the decoding device according to the received encoded sequence, the encoded sequence is the sequence after the sequence to be encoded is encoded, and the length of the sequence to be encoded is N, N= ²ⁿ , and n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result.

Alternatively, when the computer instruction is executed on a processor, the encoding device performs the following steps: the encoding device encodes the sequence to be encoded to obtain an encoded sequence. The sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit. The encoding device sends the encoded sequence.

Optionally, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a processor, the analog circuit in the decoding device performs the following steps: the analog circuit acquires an analog signal. The analog signal is determined by the decoding device according to the received encoded sequence, and the encoded sequence is a sequence after the sequence to be encoded is encoded, and the length of the sequence to be encoded is N, N= ²ⁿ , and n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result.

Optionally, an embodiment of the present application further provides a chip, including an analog circuit. The analog circuit is used to obtain an analog signal. The analog signal is determined by the decoding device according to the received coded sequence, the coded sequence is a sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N= ²ⁿ , and n is a positive integer. The analog circuit is also used to decode the analog signal to obtain a decoding result.

Alternatively, the chip includes a processing circuit and an input/output interface. The input/output interface is used to communicate with a module outside the chip. For example, the chip can perform the following steps to implement the above: encode the sequence to be encoded to obtain an encoded sequence, and send the encoded sequence. The sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit.

The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

It should be understood that the term "and/or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character "/" in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and/or" relationship. Please refer to the context for specific understanding.

In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple.

It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or communication device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A decoding device, characterized in that it comprises: an analog circuit; wherein:

The analog circuit is used to obtain an analog signal; the analog signal is determined by the decoding device according to the received coded sequence, the coded sequence is a sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N= 2n , and n is a positive integer;

The analog circuit is also used to decode the analog signal to obtain a decoding result.
The device according to claim 1, characterized in that the sequence to be encoded includes a first information bit and a second information bit; the analog circuit includes a first f operation circuit, a first decoding circuit, a first delay control circuit, a first g operation circuit and a second decoding circuit;

The analog circuit is further used to decode the analog signal to obtain a decoding result, including:

The first f operation circuit is used to perform f operation on the analog signal;

The first decoding circuit is used to decode the result of the first f operation circuit to obtain an estimated value of the first information bit; the code length corresponding to the result decoded by the first decoding circuit is N/2 and the code rate is A/(N/2), where A represents the number of the first information bits;

The first delay control circuit is used to control the time when the analog signal is input into the first g operation circuit;

The first g operation circuit is used to perform a g operation on the analog signal and a first bit value; the first bit value is an estimated value of the first information bit;

The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit; the code length corresponding to the result of decoding by the second decoding circuit is N/2 and the code rate is B/(N/2), where B represents the number of the second information bits;

The decoding result includes an estimated value of the first information bit and an estimated value of the second information bit.
The device according to claim 2, characterized in that the first f operation circuit includes a first real number to absolute value sign RTAS converter, a minimum WTA module, a first multiplier and a second multiplier;

The first f operation circuit is used to perform f operation on the analog signal, including:

The first RTAS converter is used to receive and process a first signal to obtain a sign and an absolute value corresponding to each log-likelihood ratio (LLR) value in the first signal; the first signal includes two LLR values in the analog signal;

The WTA module is used to determine the minimum value among the absolute values obtained by the first RTAS converter;

The first multiplier is used to multiply the symbols obtained by the first RTAS converter;

The second multiplier is used to multiply the result of the WTA module and the result of the first multiplier;

The number of the first f operation circuits is N/2, and the result of the first f operation circuit includes the results of N/2 second multipliers.
The device according to claim 1, characterized in that the sequence to be encoded includes a second information bit; the analog circuit includes a first g operation circuit and a second decoding circuit;

The analog circuit is further used to decode the analog signal to obtain a decoding result, including:

The first g operation circuit is used to perform a g operation on the analog signal and a first bit value; the first bit value is determined according to the first N/2 LLR values in the analog signal;

The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit; the code length corresponding to the result of the decoding by the second decoding circuit is N/2 and the code rate is B/(N/2), where B represents the number of the second information bits;

The decoding result includes an estimated value of the second information bit.
The device according to any one of claims 2 to 4, characterized in that the first g operation circuit comprises a third multiplier and a first adder;

The first g operation circuit is used to perform a g operation on the analog signal and the first bit value, including:

The third multiplier is used to multiply the first bit value and an LLR value in a first signal; the first signal includes two LLR values in the analog signal;

The first adder is used to add the result of the third multiplier and another LLR value in the first signal;

The number of the first g operation circuits is N/2, and the result of the first g operation circuit includes the results of N/2 first adders.
The device according to any one of claims 2 to 4, characterized in that the first g operation circuit comprises a second RTAS converter, a fourth multiplier, a fifth multiplier, a second delay control circuit and a second adder; the first g operation circuit is used to perform a g operation on the analog signal and the first bit value, comprising:

The second RTAS converter is used to receive and process an LLR value in a first signal to obtain a first sign and a first absolute value; the first signal includes two LLR values in the analog signal;

The fourth multiplier is used to multiply the first bit value and the first symbol;

The fifth multiplier is used to multiply the result of the fourth multiplier and the first absolute value;

The second delay control circuit is used to control the time when another LLR value in the first signal is input into the second adder;

The second adder is used to add the result of the fifth multiplier and the LLR value input by the second delay control circuit;

The number of the first g operation circuits is N/2, and the result of the first g operation circuit includes the results of N/2 second adders.
The device according to claim 2 or 3, characterized in that the sequence to be encoded further includes frozen bits; the first decoding circuit includes a first operation circuit and a symbol conversion circuit; the first decoding circuit is used to decode the result of the first operation circuit to obtain an estimated value of the first information bit, including:

The first operation circuit is used to receive the result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit;

The sign conversion circuit is used to perform sign processing on the result of the first operation circuit to obtain an estimated value of the first information bit.
The device according to claim 2 or 3, characterized in that the sequence to be encoded further includes frozen bits; the first decoding circuit includes a first operation circuit and a path metric circuit; the first decoding circuit is used to decode the result of the first operation circuit to obtain an estimated value of the first information bit, including:

The first operation circuit is used to receive the result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit;

The path metric circuit is used to determine the estimated value of the first information bit according to the first path metric value and the result of the first operation circuit; the first path metric value is the metric value of the first decoding path, and the first decoding path indicates the value of the bit before the first information bit.
The device according to claim 8, characterized in that the candidate values of the first information bit include a first candidate value and a second candidate value; the path metric circuit includes a first processing module, a second processing module and a comparator;

The path metric circuit is used to determine the estimated value of the first information bit according to the first path metric value and the result of the first operation circuit, including:

The first processing module is used to receive the first path metric value and the result of the first operation circuit, and determine a second path metric value according to the first candidate value, the first path metric value and the result of the first operation circuit;

The second processing module is used to receive the first path metric value and the result of the first operation circuit, and determine a third path metric value according to the second candidate value, the first path metric value and the result of the first operation circuit;

The comparator is used to compare the second path metric value and the third path metric value, and output an estimated value of the first information bit; the estimated value of the first information bit is a candidate value corresponding to the larger path metric value between the second path metric value and the third path metric value.
The device according to claim 9, characterized in that the first processing module includes a third RTAS converter, a sixth multiplier, a first calculation unit, a seventh multiplier and a third adder; the first processing module is used to receive the first path metric value and the result of the first operation circuit, and determine the second path metric value according to the first candidate value, the first path metric value and the result of the first operation circuit, including:

The third RTAS converter is used to receive and process the result of the first operation circuit to output a second sign and a second absolute value;

The sixth multiplier is used to multiply the first candidate value and the second symbol;

The first computing unit is configured to receive and process a result of the sixth multiplier;

The seventh multiplier is used to multiply the result of the first calculation unit and the second absolute value;

The third adder is used to add the first path metric value and the result of the seventh multiplier to obtain the second path metric value.
The device according to claim 9, characterized in that the second processing module includes a fourth RTAS converter, an eighth multiplier, a second calculation unit, a ninth multiplier and a fourth adder; the second processing module is used to receive the first path metric value and the result of the first operation circuit, and determine the third path metric value according to the second candidate value, the first path metric value and the result of the first operation circuit, including:

The fourth RTAS converter is used to receive and process the result of the first operation circuit to output a third sign and a third absolute value;

The eighth multiplier is used to multiply the second candidate value and the third symbol;

The second computing unit is configured to receive and process a result of the eighth multiplier;

The ninth multiplier is used to multiply the result of the second calculation unit and the third absolute value;

The fourth adder is used to add the first path metric value and the result of the ninth multiplier to obtain the third path metric value.
The device according to any one of claims 7 to 11, characterized in that the frozen bits include a first frozen bit, a second frozen bit and a third frozen bit; the result of the first f operation circuit includes a first partial result and a second partial result, the first partial result includes the results of the first N/4 first f operation circuits, and the second partial result includes the results of the last N/4 first f operation circuits;

The first operation circuit includes a second g operation circuit, a third g operation circuit and a fourth g operation circuit;

The first operation circuit is used to receive the result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit, including:

The second g operation circuit is used for performing a g operation on the value of the first frozen bit and the first partial result;

The third g operation circuit is used for performing a g operation on the value of the second frozen bit and the second partial result;

The fourth g operation circuit is used to perform a g operation on the value of the third frozen bit, the result of the first g operation circuit and the result of the second g operation circuit to obtain the result of the first operation circuit.
The device according to any one of claims 2 to 7, characterized in that the second decoding circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a symbol conversion circuit; the second decoding circuit is used to decode the result of the first operation circuit to obtain the estimated value of the second information bit, including:

The operation unit of the ith subcircuit is used to determine the probability distribution of the ith second information bit among the B second information bits; the ith subcircuit is the ith subcircuit among the B subcircuits;

The sign conversion circuit of the i-th subcircuit is used to perform a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit;

Wherein, i is any positive integer less than or equal to B.
The device according to claim 13, characterized in that B=3; the bit before the first second information bit is a first frozen bit; the second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, comprising:

a first operation unit, configured to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain the probability distribution of the first second information bit; the first operation unit is an operation unit of the first subcircuit;

a first conversion circuit, configured to perform a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit; the first conversion circuit is a sign conversion circuit of the first sub-circuit;

a second operation unit, configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit; the second operation unit is an operation unit of the second subcircuit;

A second conversion circuit, used for performing a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit; the second conversion circuit is a sign conversion circuit of the second sub-circuit;

a third operation unit, configured to receive and process the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit, so as to obtain the probability distribution of the third second information bit; the third operation unit is an operation unit of the third subcircuit;

The third conversion circuit is used to perform a sign operation on the probability distribution of the third second information bit to obtain an estimated value of the third second information bit; the third conversion circuit is a sign conversion circuit of the third sub-circuit.
The device according to any one of claims 2 to 7, characterized in that the second decoding circuit includes B subcircuits, each of the B subcircuits includes an operation unit and a path metric circuit; the second decoding circuit is used to decode the result of the first operation circuit to obtain an estimated value of the second information bit, comprising:

The operation unit of the ith subcircuit is used to determine the probability distribution of the ith second information bit among the B second information bits; the ith subcircuit is the ith subcircuit among the B subcircuits;

The path metric circuit of the i-th subcircuit is used to receive the path metric value of the i-th decoding path, and determine the estimated value of the i-th second information bit according to the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit; the i-th decoding path indicates the value of the bit before the i-th second information bit in the encoded sequence;

Wherein, i is any positive integer less than or equal to B.
The device according to claim 15, characterized in that B=3; the previous bit of the first second information bit is a first frozen bit; the second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, comprising:

a first operation unit, configured to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain the probability distribution of the first second information bit; the first operation unit is an operation unit of the first subcircuit;

a first path metric circuit, configured to receive a path metric value of a first decoding path, and determine an estimated value of the first second information bit according to the path metric value of the first decoding path and the probability distribution of the first second information bit; the first decoding path indicates a value of a bit before the first second information bit; the first path metric circuit is a path metric circuit of the first sub-circuit;

a second operation unit, configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit; the second operation unit is an operation unit of the second subcircuit;

a second path metric circuit, configured to receive a path metric value of a second decoding path, and determine an estimated value of the second second information bit according to the path metric value of the second decoding path and the probability distribution of the second second information bit; the second decoding path indicates a value of a bit before the second second information bit; the second path metric circuit is a path metric circuit of the second sub-circuit;

a third operation unit, configured to receive and process the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit, so as to obtain the probability distribution of the third second information bit; the third operation unit is an operation unit of the third subcircuit;

A third path measurement circuit is used to receive the path measurement value of the third decoding path, and determine the estimated value of the third second information bit based on the path measurement value of the third decoding path and the probability distribution of the third second information bit; the third decoding path indicates the value of the bit before the third second information bit; the third path measurement circuit is the path measurement circuit of the third sub-circuit.
The device according to claim 14 or 16, characterized in that the first operation unit includes a second f operation circuit, a third f operation circuit and a fifth g operation circuit; the first operation unit is used to receive and process the value of the first frozen bit and the result of the first g operation circuit, comprising:

The second f operation circuit is used to receive a second signal and perform an f operation on the second signal; the second signal is a part of the result of the first g operation circuit;

The third f operation circuit is used to receive a third signal and perform f operation on the second signal; the third signal is a signal other than the second signal in the result of the first g operation circuit;

The fifth g operation circuit is further used to perform a g operation on the value of the first frozen bit, the result of the first f operation circuit and the result of the second f operation circuit to obtain a processing result of the first operation unit.
The device according to claim 14 or 16, characterized in that the second operation unit includes a sixth g operation circuit, a seventh g operation circuit and a fourth f operation circuit; the second operation unit is used to receive and process the estimated value of the first second information bit and the result of the first g operation circuit, including:

The sixth g operation circuit is used to perform a g operation on the estimated value of the first information bit and a second signal; the second signal is a part of the result of the first g operation circuit;

The seventh g operation circuit is used to perform a g operation on the estimated value of the first information bit and a third signal; the third signal is a signal other than the second signal in the result of the first g operation circuit;

The fourth f operation circuit is used to perform f operation on the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain the processing result of the second operation unit.
The device according to claim 14 or 16, characterized in that the third operation unit includes a sixth g operation circuit, a seventh g operation circuit and an eighth g operation circuit;

The third operation unit is used to receive and process the estimated values of the first second information bit and the second second information bit and the result of the first g operation circuit, including:

The sixth g operation circuit is used to perform a g operation on the estimated value of the first information bit and the second signal; the second signal is a part of the result of the first g operation circuit;

The seventh g operation circuit is used to perform a g operation on the estimated value of the first information bit and a third signal; the third signal is a signal other than the second signal in the result of the first g operation circuit;

The eighth g operation circuit is used to perform a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain a processing result of the third operation unit.
A coding device, characterized in that it comprises:

A processing module, configured to encode a sequence to be encoded to obtain an encoded sequence; wherein the sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block; each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit;

A transceiver module is used to send the encoded sequence.
A decoding method, characterized in that it comprises: an analog circuit; wherein:

The analog circuit acquires an analog signal; the analog signal is determined by the decoding device according to the received coded sequence, the coded sequence is a sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N=2 n , and n is a positive integer;

The analog circuit decodes the analog signal to obtain a decoding result.
A coding method, characterized by comprising:

The encoding device encodes a sequence to be encoded to obtain an encoded sequence; wherein the sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block; each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit;

The encoding device sends the encoded sequence.
A computer-readable storage medium, characterized in that the computer-readable storage medium stores a program, and when the program is called by a processor, it causes a decoding device to execute the method of claim 21, or causes an encoding device to execute the method of claim 22.
A computer program product comprising instructions, characterized in that when the computer program product is called by a processor, it causes a decoding device to execute the method according to claim 21, or causes an encoding device to execute the method according to claim 22.