WO2024084629A1 - System for compensating the non-linear distortion introduced by a radio power amplifier based on harmonic analysis - Google Patents

System for compensating the non-linear distortion introduced by a radio power amplifier based on harmonic analysis Download PDF

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WO2024084629A1
WO2024084629A1 PCT/JP2022/038955 JP2022038955W WO2024084629A1 WO 2024084629 A1 WO2024084629 A1 WO 2024084629A1 JP 2022038955 W JP2022038955 W JP 2022038955W WO 2024084629 A1 WO2024084629 A1 WO 2024084629A1
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output
memory array
values
signal
stored
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PCT/JP2022/038955
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Ludovico Minati
Narayanan Aravind Tharayil
Hiroyuki Ito
Korkut Kaan TOKGOZ
Shiro Dosho
Aran HAGIHARA
Jim BARTELS
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Tokyo Institute Of Technology
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Abstract

Digital predistortion systems aim to reduce the impact of the non-linear response of radio power amplifiers, usually for improving the spectral performance of wireless telecommunication networks. The present invention pertains to such a system having increased robustness and rapidity. Rather than analyzing the ongoing error between the intended and actual amplifier output in the background during normal operation, or performing iterative adaptations, the response of the amplifier is rapidly probed in the foreground by applying a sinusoidal tone having a variable frequency and amplitude according to a predetermined sequence. The harmonics generated due to the non-linear response of the amplifier are extracted from its output signal. By establishing an approximate correspondence between their amplitudes and the individual parameters of an algebraic relationship suitable for compensating the non-linear response of the amplifier, the present invention enables the direct calculation of said parameters. The possibility of ongoing adjustment of said parameters based on additional transducers is also described.

Description

SYSTEM FOR COMPENSATING THE NON-LINEAR DISTORTION INTRODUCED BY A RADIO POWER AMPLIFIER BASED ON HARMONIC ANALYSIS Field of application of the invention
　　The present invention finds application in the field of the so-called "digital predistortion systems", i.e., systems suitable for preprocessing a baseband signal to be transmitted after amplification by a radio amplifier, to distort it in such way as to at least partially compensate the non-linear distortion introduced by the amplifier itself (for example, gain compression), thereby improving the fidelity of wireless transmission.
　　The systems of this type are frequently used to help increase the performance of wireless transmission networks and/or reduce the requirements imposed on the performance of radio amplifiers. In particular, the digital predistortion systems allow for overcoming the non-ideal behavior of a wide range of amplifiers, resulting in significant reductions in cost and power required for a given transmission application.
　　The systems of this type can also be used to improve the dynamic characteristics of amplifiers driving loads other than antennas, such as long-distance cable connections.
Overview of the prior art
　　Known digital predistortion systems include, first of all, one or more means of evaluating an algebraic relationship (usually a polynomial) which, when the parameters belonging to it are set to suitable values and when the same is applied to a signal to be transmitted before entering the same, after suitable modulation, into a power amplifier included in a transmitting apparatus, can at least partially compensate the non-linear distortion introduced by said amplifier. The values of said parameters are often determined and iteratively tuned by taking as reference an error signal, whose amplitude should be minimized towards zero, and which is obtained by calculating the difference between the signal output by said amplifier, suitably demodulated, and the original signal. Ongoing adjustment of said parameters takes place using optimization algorithms, which under normal conditions are capable of tracking the behavior of said amplifier and compensating for its non-ideal characteristics. This approach (known as "adaptive digital predistortion") is not only commonplace in the presence of amplifiers possessing characteristics susceptible to change as a function of previous inputs (known as "memory effect"), but also widely applied to more recent types of amplifiers, whose output can be more closely approximated as an instantaneous function of the input.
　　The known digital predistortion systems rely on the availability of an accurate continuous representation of the output of said amplifier, because even minimal external interference can reflect in large parameter estimation errors or, worse, the onset of uncontrolled oscillation. This represents a severe drawback, since next-generation telecommunication systems require higher carrier frequencies and denser arrays of transmitters, resulting in increased contamination between the signals belonging to adjacent channels in an array, unavoidably introducing instability in the process of adjusting said parameters.
Object of the invention
　　The object of the present invention is to overcome the aforementioned drawbacks by indicating a non-linear distortion compensation system which, by virtue of its operating principle, is more robust and self-contained than the existing systems of the same type.
Summary and advantages of the invention
　　The object of the present invention is a digital predistortion system comprising:
・　　first means for obtaining (preferably from another device, via connecting to the same, and preferably consisting of a buffer memory of the first-in first-out type) a first baseband signal consisting of digital values representing data to be transmitted;
・　　first evaluating means (preferably consisting of a combination of pipelined single-cycle hardware multipliers and summers) of an algebraic expression (preferably consisting of a memoryless polynomial), from said first baseband signal given a set of parameter values (preferably consisting of coefficients of a memoryless polynomial);
・　　a first memory array (preferably consisting of a static random access memory) suitable for storing the values of said parameters (provided to said first evaluating means);
・　　generating means (preferably consisting of a digital-to-analog converter intended for direct radiofrequency synthesis, combined either with an analog frequency synthesizer combined with a variable gain amplifier and analog switch, or with a digital signal synthesizer and digital multiplexer switch, for example, as found in type ZU48DR by Xilinx Inc.), from the values determined by evaluating said algebraic expression or, upon the assertion of a first logical signal, according to a sinusoidal wave having controllable amplitude and frequency determined by a corresponding first digital value, of an analog signal;
・　　local oscillating means (for example, type ADF5356 by Analog Devices Inc.), providing a carrier signal having a known frequency;
・　　first modulating means (preferably consisting of an up-converter circuit, for example, type ADMV1013 by Analog Devices Inc.), for obtaining from said analog signal (emitted by said generating means) a higher frequency analog signal by means of mixing said analog signal (emitted by said generating means) with said carrier signal (emitted by said local oscillating means);
・　　first radio power amplifying means (preferably consisting of a radio power amplifier realized using complementary metal-oxide-semiconductor technology, for example, as found in type SUMMIT3741 by MixComm Inc.), of said higher frequency analog signal (emitted by said first modulating means);
・　　extracting means (preferably consisting of a power splitter, for example, type EP2KA+ by Mini-Circuits Inc.), of a fraction of the signal emitted by said first radio power amplifier before the same reaches a first load (preferably consisting of a transmitting antenna, connected by means of suitable matching and auxiliary circuits);
・　　first demodulating means (preferably a consisting of a down-converter circuit, for example, type ADMV1014 by Analog Devices Inc.), for obtaining from said signal fraction (emitted by said extracting means) a lower frequency analog signal by means of mixing said signal fraction (emitted by said extracting means) with said carrier signal (emitted by said oscillating means);
・　　measuring means, from said lower frequency analog signal (emitted by said demodulating means), of the spectral amplitude at a selected frequency, determined by a corresponding second digital value.
　　For the sake of convenience, here and in the following of the present invention, the expressions "parameter values" and "spectral amplitudes" mean not only real numbers but also complex numbers, thus being suitable for representing not only magnitudes but also phases and their relationships.
　　According to the invention, said digital predistortion system also includes:
・　　a second memory array (preferably consisting of a static random access memory) suitable for storing the values of said spectral amplitudes (emitted by said measuring means);
・　　controlling means, adapted to control, upon the assertion of a second logical signal, the process of measuring the non-linear distortion introduced by said first radio power amplifier by means of imparting settings, via the corresponding first and second digital values, of the amplitude and frequency of said analog signal (emitted by said generating means, having asserted said first logical signal connected to the same) while simultaneously storing said spectral amplitudes (emitted by said measuring means) in said second memory array, finally asserting a third logical signal upon measurement completion;
・　　first calculating means, of the values of said parameters (provided to said first evaluating means), from the spectral amplitudes stored in second other memory array,
said first calculating means being adapted to, upon the assertion of said third logical signal and based on a multitude of measurements of said spectral amplitudes, determine the values that said parameters should be set to so as to cause the output of said first radio power amplifier to be as closely as possible linearly related to said first baseband signal as it would appear after being modulated to a higher frequency by mixing it with said carrier signal emitted by said local oscillating means, that is, so as to compensate as accurately as possible the non-linear distortion introduced by said first radio power amplifier.
　　From the established theorems related to Fourier series expansion, it is known that a sine function, when entered as a variable into a non-linear algebraic expression consisting of a polynomial, produces odd and even harmonics whose amplitudes and phases can be derived analytically and calculated numerically. The same holds when a sine wave is treated as a baseband signal and modulated to a higher frequency determined by a carrier signal before entering such an expression. Therefore, a relationship exists between the parameter values belonging to said expression and the harmonics that are produced by it in response to a given sinusoidal input. Advantageously for the present application, when said expression is exclusively a function of the instantaneous value of said sine function (for example, it consists of a so-called memoryless polynomial) and is such that it evaluates to monotonically increasing values with respect to the input, said relationship is effectively univocal (T.W. Korner, Fourier Analysis, Cambridge University Press, Cambridge UK, 2022).
　　Incidentally, the non-linear response of radio power amplifiers realized using complementary metal-oxide-semiconductor (CMOS) technology can be represented as an algebraic expression consisting of a fourth-degree memoryless polynomial whose coefficient values are such that the output amplitude monotonically increases with respect to the input amplitude (R.G. Saez, N.M. Marques, LDMOS versus GaN RF Power Amplifier Comparison Based on the Computing Complexity Needed to Linearize the Output, Electronics 2019; 8(11), 1260; S. Mariappan, J. Rajendran, H. Ramiah, N.M. Noh, A.A. Manaf, The Evolution of Integrated CMOS Power Amplifiers for Next Generation Mobile Wireless Transceivers, J Circuits Syst Comput 2019; 29(07), 2030007).
　　A multitude of numerical methods for representing in approximate form an algebraic expression such as a memoryless polynomial and its inverse are known. By way of example, insofar as a training set comprising cases covering sufficiently large possible combinations of inputs and coefficient values is available, it is possible to train an artificial neural network, such as one having multilayer perceptron topology, to calculate the coefficient values of a memoryless polynomial based on a multitude of inputs and values taken by it (output), and the accuracy of the calculation depends on numerosity and distribution of said input-output combinations (K. Hornik, M. Stinchcombe, H. White, Multilayer feedforward networks are universal approximators, Neural Netw 1989; 2(5), 359-366; S. Geva, J. Sitte, A constructive method for multivariate function approximation by multilayer perceptrons, IEEE Trans Neural Netw 1992; 3(4), 621-624). Therefore, it is possible to train an artificial neural network, such as one having multilayer perceptron topology, to calculate the coefficient values of a memoryless polynomial representing the non-linear response of a radio power amplifier realized using complementary metal-oxide-semiconductor (CMOS) technology based on measuring the harmonics generated by the same in response to a multitude of sinusoidal inputs.
　　While, except for special cases, memoryless polynomials do not possess an exact inverse, approximate inverses, preferably consisting of memoryless polynomials of higher degree, can be computed over restricted domains (M.F. Gonzalez-Cardel, R. Diaz-Uribe, An analysis on the inversion of polynomials, Rev. Mex. de Fis. 2006; 2, 163-171). Advantageously for the present application, it follows that it is possible to train an artificial neural network, such as one having multilayer perceptron topology, to directly calculate the coefficient values of a memoryless polynomial representing the approximate inverse of the non-linear response of a radio power amplifier realized using complementary metal-oxide-silicon (CMOS) technology based on the harmonics generated by the same in response to a multitude of sinusoidal inputs, so that, when said memoryless polynomial representing the approximate inverse is applied to a signal prior to entering, after suitable modulation, the same into said radio power amplifier, it causes the output of said radio power amplifier to be closer to linearly related to said signal than it would be if said signal were entered directly into said radio power amplifier.
　　Artificial neural networks, such as those having multilayer perceptron topology, are substantially known. More specifically, and advantageously for the present application, it is possible to efficiently implement such networks directly in hardware by means of combining memory arrays storing the corresponding coefficients and offset values, multipliers, adders, and means of evaluating activation functions (P. Lee, I. Lazzizzera, A. Zorat, A. Sartori, G. Tecchiolli, Advances in the design of the TOTEM neurochip, Nucl Instrum Methods Phys Res B 1997; 389(1), 134-137; N. Nedjah, R. Martins da Silva, L. de Macedo Mourelle. Compact yet efficient hardware implementation of artificial neural networks with customized topology. Expert Syst Appl 2012; 39(10), 9191-9206). However, to the best of our knowledge, existing digital predistorsion systems do not calculate the parameter values suitable for compensating the non-linear distortion introduced by a radio power amplifier by means of measuring the harmonics generated by the same in response to a multitude of sinusoidal inputs and processing the resulting measurements by means of an artificial neural network. Instead, they rely primarily on the continuous or iterative calculation of the difference between the signal output by said radio power amplifier, suitably demodulated and scaled, and the original signal, realizing a feedback loop which, in the presence of external interference, may become unstable (L. Guan and A. Zhu, Green Communications: Digital Predistortion for Wideband RF Power Amplifiers, IEEE Microw Mag, 15(7), 84-99). The present invention addresses these shortcomings by describing a system wherein the non-linear distortion introduced by said radio power amplifier is measured, and the subsequent calculations are performed, not continuously in the background (that is, without interrupting normal transmission of the baseband signal) but only once for a brief interval of time in the foreground (that is, without interrupting normal transmission of the baseband signal) in response to the assertion of an externally-provided logical signal, which allows ensuring that such measurements are performed in the absence of possible sources of interference such as the simultaneous operation of other transmitters.
　　For example, US 7,333,559 B2 describes a digital predistortion apparatus to compensate for the non-linearities of a wideband power amplifier. The invention is based on a closed-loop arrangement of two predistorters, which exchange feedback and update information derived from the continuous analysis of their input and output signals. Even though the associated adaptation method requires applying signals containing single and/or multiple sine waves, there is no mention of measuring the harmonics produced by the same. Instead, and fundamentally differently, using the secant algorithm and normalized least mean square adaptation is proposed.
　　Similarly, US 8,805,304 B2 describes a linearizer that is based on analyzing the signal output by an error monitor receiver connected to the output of a radio power amplifier. There is no mention of measuring the harmonics produced by said radio power amplifier. Instead, minimization of the mean-square error via iterative adjustment is proposed.
　　Further, US 10,469,109 B2 describes a predistortion system based on the action of multiple processing systems such that a separate receiving device provides feedback on the signal received from a plurality of transmitters, allowing the adjustment of predistortion coefficients in the same. A calibration procedure involving the application of multiple phase shift settings is described. The invention involves a training processor sequentially selecting different sets of predistortion coefficients, eventually selecting the one yielding the lowest distortion measured, again, by comparing the combined receive signal and the test signal transmitted by the array. There is no mention of measuring the harmonics emitted by the individual transmitters and using such measurements as a basis for directly calculating the predistortion coefficients to be applied to each one of them.
　　Further still, EP 1 205 024 B1 describes a process for determining predistortion parameters which is grounded on a systems identification approach and involves the ongoing, iterative application of stimulation signals during a model adaptation process, also based on the determination of an error signal and the application of algorithms such as least squares and Kalman filtering. Again, there is no mention of measuring the harmonics produced by the amplifier and using the measurements as a basis to directly determine the predistortion parameters.
　　Similarly, US 10,720,891 B2 describes an amplifier linearization system based on the adaptive determination of predistortion coefficients based on an error signal. According to this invention, the instability of the iterative learning process is reduced by means of representing the same as a linear system of equations and applying a conjugate gradient algorithm. Again, there is no mention of measuring the harmonics produced by the amplifier and using the measurements as a basis to directly determine the predistortion parameters.
　　Differently, US 8,736,365 B2 describes a predistortion module whose operation is not based on measuring the non-linear distortion introduced by a radio power amplifier, but on measuring the continuous output of smaller versions of the same coupled thermally to it. There is no mention of measuring the non-linear distortion introduced by said radio power amplifier. Instead, the invention is grounded on assuming that said smaller versions behave similarly and, when appropriated interconnected, can alter the signal in such as way as to partially compensate for the non-linear distortion introduced by said radio power amplifier. Again, there is no mention of measuring the harmonics produced by said radio power amplifier and using the measurements as a basis to directly determine the predistortion parameters.
　　On the other hand, WO 2018/185532 A1 describes a predistortion system where the impact of the interference from nearby transmitters within an array is attenuated by means of incorporating a cross-talk model within a scheme of ongoing adaptation driven by an error signal. Again, there is no mention of measuring the harmonics produced by an amplifier and using the measurements as a basis to directly determine the predistortion parameters.
　　Similarly, WO 2019/190515 A1 describes a scheme for canceling the effect of cross-talk during the process of training a predistortion circuitry based on separately receiving multiple feedback signals. Again, there is no mention of measuring the harmonics produced by an amplifier and using the measurements as a basis to directly determine the predistortion parameters.
　　On the other hand, US 5,089,782 describes a vector network analyzer for performing measurements on nonlinear radio devices and determining their properties by means of measuring the harmonics generated in response to a sinusoidal signal. However, there is no mention of using the harmonics produced by an amplifier in response to a multitude of such inputs as a means of determining obtain the coefficients of a memoryless polynomial representing its response and/or its inverse.
　　Other innovative features of the present invention are illustrated in the following description and referred to in the dependent claims.
　　According to one aspect of the invention, said measuring means comprise:
・　　first filtering means (preferably consisting of a band-pass filter network, for example, type BPF-C510+ by Mini-Circuits Inc.), of an analog signal containing frequencies only within a specified interval, attenuating all frequencies outside it, from said lower frequency analog signal emitted by said first demodulating means;
・　　second synthesizing means (preferably consisting of a fractional phase locked loop, for example, type HMC704LP4E by Analog Devices Inc.), of a sinusoidal analog signal whose frequency is determined by said second corresponding digital value;
・　　second demodulating means (preferably consisting of a down-converter circuit, for example, type AD8348 by Analog Devices Inc.), for obtaining a lower-frequency analog signal from the output of said first filtering means by means of mixing the same with the output of said second synthesizing means;
・　　second filtering means (preferably consisting of a low-pass filter network, for example, type LPF-B0R6+ by Mini-Circuits Inc.), of a signal containing frequencies only within a specified interval, attenuating all frequencies outside it, from the lower-frequency analog signal emitted by said second demodulating means;
・　　second converting means (preferably consisting of an analog-to-digital converter of the successive approximation type, for example, type AD4002 by Analog Devices Inc.), of digital values from the output of said second filtering means,
where the output of said second converting means, representing spectral amplitudes, is provided as input to said controlling means, so that the same can store the corresponding values in said second memory array.
　　According to this aspect of the invention, the process of measuring the harmonics generated by said first radio power amplifier in response to a sinusoidal input involves sequentially setting said second synthesizing means to all the corresponding frequencies, and obtaining the digital values corresponding to their spectral amplitudes from said second converting means. Said first filtering means are provisioned so that the corresponding specified interval encompasses the frequencies corresponding to all harmonics of interest, while said second filtering means are provisioned so that the corresponding specified interval extends down to zero and encompasses frequencies up to a value which is several orders of magnitude lower than the frequencies associated with the harmonics of interest. As a result, said second converting means can advantageously operate at a conversion rate which is several orders of magnitude lower than the frequencies associated with the harmonics of interest, consequently allowing the use of known architectures which are known to minimize converter size, complexity and power dissipation.
　　According to one aspect of the invention, said measuring means comprise:
・　　filtering means (preferably consisting of a band-pass filter network, type BPF-C510+ by Mini-Circuits Inc.), of a signal containing frequencies only within a specified interval, attenuating all frequencies outside it, from said lower frequency analog signal emitted by said first demodulating means;
・　　second converting means (preferably consisting of an analog-to-digital converter of the flash type, for example, type AD9625 by Analog Devices Inc.), of digital values from the output of said filtering means;
・　　a third memory array (preferably consisting of a static random access memory) adapted to store the output of said second converting means and connected to the same through suitable interfacing means (preferably consisting of a register or set of registers);
・　　second calculating means (preferably consisting of a digital signal processor implementing the discrete or fast versions of the Fourier transform, for example, type ADSP-TS101S by Analog Devices Inc.), of the spectral amplitude from the digital values emitted by said second converting means at the frequency determined by said corresponding second digital value.
　　According to this aspect of the invention, the process of measuring the harmonics generated by said first radio power amplifier in response to a sinusoidal input involves converting only once the time-domain analog signal containing all the harmonics into the digital domain, in which the spectral amplitudes are thereafter sequentially calculated one by one. Said filtering means are provisioned so that the corresponding specified interval encompasses the frequencies corresponding to all harmonics of interest. Advantageously, this aspect of the invention allows benefiting from the high conversion speeds made available by known architectures, and from the fact that, after the outputs of said second converting means have been stored in said third memory array, said second calculating means may operate to sequentially calculate at any time the spectral amplitudes independently of the signal input to said filtering means at that time. This substantially reduce the length of the time interval during which said generating means should be set to generate a sinusoidal wave instead of an analog signal corresponding to said first baseband input, therefore reducing the duration of the foreground calibration process, during which the transmitter is not available for its intended application.
　　According to one aspect of the invention, said controlling means comprise:
・　　a fourth memory array (preferably consisting of a preprogrammed read-only memory) suitable for storing settings of amplitude and frequency to be provided via said first digital value to said generating means in order to control the characteristics of the associated sinusoidal wave, alongside settings of frequency to be provided via said second digital value to said measuring means in order to control the frequency at which the spectral amplitude is measured;
・　　interfacing means (preferably consisting of a register or set of registers), of said fourth memory array to said generating means and measuring means;
・　　further interfacing means (preferably consisting of a register or set of registers and an address generator), of the output of said measuring means to said second memory array;
・　　first sequencing means (preferably consisting of a finite state machine or set thereof), of the operation of said interfacing means according to the contents of said fourth memory array, in response to the assertion of said second logical signal (generated externally to the system and indicating a request to initiate foreground calibration), and ending with the assertion of a third logical signal (generated by said first sequencing means to indicate the end of the measurement phase of the calibration process).
　　According to this aspect of the invention, the process of measuring the harmonics generated by said first radio power amplifier is entirely controlled by hardware means in response to the assertion of a logical signal, without necessitating the execution of any software code by a microcontroller or microprocessor. According to said predetermined sequence stored in said fourth memory array, the process consists of emitting a combination of amplitude and frequency settings to said generating means, then sequentially emitting a sequence of frequencies corresponding to the harmonics of interest to said measuring means, then emitting a further combination of amplitude and frequency settings to said generating means, and so on, until a sufficient number of combinations of amplitudes and frequencies of the generated signal have been emitted, while storing the outputs of said measuring means in said second memory array. Advantageously, this aspect of the invention reduces the complexity of the hardware necessary to control the measurement process with respect to using a microprocessor or microcontroller executing software code, allowing it to be realized efficiently in an entirely self-contained and independent form, for example, for each radio power amplifier instantiated in a large array.
　　According to one aspect of the invention, said first calculating means comprise:
・　　a first set of memory arrays (preferably consisting of a set of preprogrammed read-only memories), one for each parameter to be calculated and adapted to store first group of coefficient values used in the calculation of the same;
・　　first addressing means (preferably consisting of a multiplexer and address decoder), of one memory array among those included in said set first of memory arrays;
・　　first multiplying means (preferably consisting of a pipelined single-cycle hardware multiplier), of the values contained in said second memory array by the corresponding first coefficient values stored in the array addressed by said first addressing means;
・　　a second set of memory arrays (preferably consisting of a set of preprogrammed read-only memories), one for each parameter to be calculated and adapted to store a first group of offset values used in the calculation of the same;
・　　second addressing means (preferably consisting of a multiplexer and address decoder), of one memory array among those included in said second set of memory arrays;
・　　first summing means (preferably consisting of a pipelined single-cycle hardware summer), of the output of said first multiplying means to the corresponding first offset values stored in the array addressed by said second addressing means;
・　　second evaluating means (preferably consisting of a look-up table containing the values taken by a hyperbolic tangent function, or consisting of an interpolator combined with a look-up table containing the same), of an activation function as a function of the output of said first summing means;
・　　a third set of memory arrays (preferably consisting of a set of preprogrammed read-only memories), one for each parameter to be calculated and adapted to store a second group of coefficient values used in the calculation of the same;
・　　third addressing means (preferably consisting of a multiplexer and address decoder), of one memory array among those included in said third set of memory arrays;
・　　second multiplying means (preferably consisting of a pipelined single-cycle hardware multiplier), of the output of said second evaluating means by the corresponding second coefficient values stored in the array addressed by said third addressing means;
・　　a fourth set of memory arrays (preferably consisting of a set of preprogrammed read-only memories), each one corresponding to one parameter to be calculated and adapted to store a second group of offset values used in the calculation of the same;
・　　fourth addressing means (preferably consisting of a multiplexer and address decoder), of one memory array among those included in said fourth set of memory arrays;
・　　second summing means (preferably consisting of a pipelined single-cycle hardware summer), of the output of said second multiplying means to the corresponding second offset values stored in the array addressed by said fourth addressing means;
・　　third evaluating means (preferably consisting of a look-up table containing the values taken by a linear function, or consisting of an interpolator combined with a look-up table containing the same), of an activation function as a function of the output of said second summing means;
・　　interfacing means (preferably consisting of a register or set of registers and an address generator), of said third evaluating means with said first memory array, so that the output of the former is stored into the latter;
・　　second sequencing means (preferably consisting of a finite state machine or set thereof), of the operation of said first, second, third and fourth addressing means and said interfacing means, in response to the assertion of said third logical signal (generated by said controlling means to signal the end of the measurement phase of the calibration process).
　　According to this aspect of the invention, the process of calculating the parameters of the algebraic expression (preferably consisting of coefficients of a memoryless polynomial) is realized entirely in hardware, by means of an architecture which is known to be suitable for implementing an artificial neural network having a two-layer perceptron topology (P. Lee, I. Lazzizzera, A. Zorat, A. Sartori, G. Tecchiolli, Advances in the design of the TOTEM neurochip, Nucl Instrum Methods Phys Res B 1997; 389(1), 134-137; N. Nedjah, R. Martins da Silva, L. de Macedo Mourelle. Compact yet efficient hardware implementation of artificial neural networks with customized topology. Expert Syst Appl 2012; 39(10), 9191-9206). It is known that networks of this type are universal approximators and, consequently, are suitable for representing in approximate form the relationship between the spectral amplitudes of the harmonics and the parameters of the algebraic expression required for amplifier linearization (preferably, coefficients of a memoryless polynomial; K. Hornik, M. Stinchcombe, H. White, Multilayer feedforward networks are universal approximators, Neural Netw 1989; 2(5), 359-366; S. Geva, J. Sitte, A constructive method for multivariate function approximation by multilayer perceptrons, IEEE Trans Neural Netw 1992; 3(4), 621-624). Advantageously, this aspect of the invention reduces the complexity of the hardware necessary to implement the calculation process with respect to using a microprocessor or microcontroller executing software code, allowing the calculation to be realized efficiently in an entirely self-contained and independent form, for example, for each radio power amplifier instantiated in a large array. Even more advantageously, this aspect of the invention allows sharing the multiplying means, summing means and evaluating means across the parameters to be calculated, thus further reducing the size of the hardware necessary and making it largely independent of the number of parameters to be calculated.
　　According to one aspect of the invention, the digital predistortion system also comprises:
・　　transducing means of at least one physical magnitude (preferably consisting of a voltage and/or a current and/or a temperature) representing a characteristic of either said first radio power amplifier or said first load, or both;
・　　amplifying means (preferably consisting of an operational amplifier connected according to an active filter topology, for example, type TLC274 from Texas Instruments Inc.) of the output of said transducing means, adapted to magnify the fluctuations associated with the operation of either said first radio power amplifier (for example, in response to swings in the local power supply voltage) or said first load (for example, in response to changes related to beam steering dynamics), or both;
・　　third converting means (preferably consisting of an analog-to-digital converter of the successive approximation type, for example, type AD4002 by Analog Devices Inc.) into digital values of the output of said amplifying means;
・　　a fifth memory array (preferably consisting of a static random access memory) adapted to store a multitude of outputs of said third converting means and connected to said first calculating means, so that the values contained in it are made available to the latter alongside the values contained in said second memory array;
・　　interfacing means (preferably consisting of a register or set of registers and an address generator), of said third means with said fifth memory array, so that the output of the former is stored into the latter.
　　According to this aspect of the invention, the possibility of reacting to changes in the operating conditions of said first radio power amplifier and/or said first load connected to it without requiring the ongoing measurement of the harmonics generated by said radio amplifier is introduced. To realize this functionality, since radio power amplifiers can be highly sensitive to changes in some physical magnitudes characterizing them and/or their load which occur during normal operation and the impact of which can be estimated a priori (S.K. Dhar, M. Helaoui, F.M. Ghannouchi, Temperature Dependent Robust Behavioral Modeling of Non-Linear Power Amplifier, 2018 Asia-Pacific Microwave Conference 2018, 378-380), the values of one or more relevant physical magnitudes are provided to said first calculating means alongside the spectral amplitudes. Advantageously, this aspect of the invention makes it possible to achieve consistently higher accuracy in linearizing the response of said first radio power amplifier without necessitating the ongoing measurement of the harmonics generated by the same (foreground calibration), instead tracking changes in its operating conditions indirectly, by means of one or more transducers, the action of which does not interfere with the continued normal operation of the transmitter. Effectively, this aspect of the invention introduces a form of background calibration into the digital predistortion system.
　　According to one aspect of the invention, the digital predistortion system also comprises modifying means of the values of the parameters belonging to an algebraic expression stored in said first memory array when interposed between the same and said first calculating means, comprising:
・　　a sixth memory array (preferably consisting of a static random access memory) adapted to store a multitude of outputs of said third converting means;
・　　interfacing means (preferably consisting of a register or set of registers and an address generator), of said third converting means with said sixth memory array, so that the output of the former is stored into the latter whenever said third logical signal is asserted;
・　　subtracting means (preferably consisting of a pipelined single-cycle hardware summer with a negative sign input), of the values contained in said sixth memory array from the values contained in said fifth memory array;
・　　a seventh memory array (preferably consisting of a preprogrammed read-only memory) adapted to store a multitude of coefficient values corresponding to the values stored in said fifth and sixth memory arrays;
・　　third multiplying means (preferably consisting of a pipelined single-cycle hardware multiplier), of the output of said subtracting means by the corresponding coefficient values stored in said seventh memory array;
・　　an eight memory array (preferably consisting of a preprogrammed read-only memory) adapted to store the values of a multitude of parameters belonging to an algebraic expression output by said first calculating means, and connected to the same in place of said first memory array;
・　　third summing means (preferably consisting of a pipelined single-cycle hardware summer), of the output of said third multiplying means to the values contained in said eight memory array;
・　　one other set of interfacing means (preferably consisting of a register or set of registers and an address generator), of said third summing means with said first memory array, so that the output of the former is stored into the latter.
　　According to this aspect of the invention, the possibility of reacting to fast changes in the operating conditions of said radio amplifier and/or the load connected to it is introduced by making it possible to more rapidly adjust the parameters of the algebraic expression (preferably, coefficients of a memoryless polynomial) than would be possible through recalculating the same using said first calculating means. To realize this functionality, a perturbation-based approach is introduced, whereby the values of the transduced physical magnitude(s) corresponding to the measured harmonics are captured, and the fluctuations around those values are subsequently calculated in real-time and used as a basis for adjusting according to a linear relationship said parameters of the algebraic expression (preferably, coefficients of a memoryless polynomial; M.H. Holmes, Introduction to perturbation methods, Springer, New York, 2013). Advantageously, this aspect of the invention makes it possible to achieve consistently higher accuracy in linearizing the response of said first radio power amplifier, without necessitating frequent measurement of the harmonics generated by the same (foreground calibration), based on the assumption that said first radio power amplifier is highly sensitive to changes in some physical magnitudes characterizing it and/or its load, which occur quickly during normal operation and the impact of which can be estimated a priori (S.K. Dhar, M. Helaoui, F.M. Ghannouchi, Temperature Dependent Robust Behavioral Modeling of Non-Linear Power Amplifier, 2018 Asia-Pacific Microwave Conference 2018, 378-380). Effectively, this aspect of the invention introduces a form of continuous background calibration into the proposed digital predistortion system.
　　According to one aspect of the invention, the digital predistortion system also comprises:
・　　selecting means (preferably consisting of an analog microwave switch, for example, type MMS006AA by Microchip Inc.), of the input to said first demodulating means from one output of said extracting means, if a fourth logical signal (generated by said controlling means to control the source of the measured signal) is not asserted, otherwise, if said fourth logical signal is asserted, from the output of said first modulating means,
and said controlling means are adapted to additionally emit said fourth logical signal, so that the output of said measuring means is stored into said second memory array both when said logical signal is asserted and when it is not asserted, thus measuring separately the response of the combination of said first modulating means, said first demodulating means, and said measuring means without the non-linear distortion introduced by said first radio power amplifier, and the same response additionally combined with the non-linear distortion introduced by said first radio power amplifier.
　　According to this aspect of the invention, the possibility of correcting the non-ideal frequency response and/or non-linearity of said measuring means in introduced. Advantageously, this aspect of the invention makes it possible to achieve higher accuracy in linearizing the response of said radio power amplifier, because said parameters of the algebraic expression (preferably, coefficients of a memoryless polynomial) are made to reflect more selectively the distortion introduced by the same, through enabling the correction (by said first calculating means) of the response of said measuring means. Incidentally, this aspect of the invention alleviates the design requirements imposed on said measuring means, because it increases the acceptability of non-linearity in the demodulating, filtering and converting means contained in the same (D.E. Root, J. Wood, N. Tufillaro, New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements, Proceedings of the 40th annual Design Automation Conference 2003, 85-90).
　　According to one aspect of the invention, the digital predistortion system also comprises:
・　　a second load (preferably consisting of a resistor, for example, type CH0603-50RJNTA by Vishay Sfernice Inc.);
・　　switching means (preferably consisting of an analog microwave switch, for example, type MMS006AA by Microchip Inc.), of the output of said first radio power amplifier, between said first load and said second load, adapted so that said output is switched to said second load whenever said first logical signal is asserted (indicating the generation of an analog signal containing a sinusoidal wave).
　　According to this aspect of the invention, the possibility of preventing the output of said radio power amplifier from reaching said first load while said generating means are emitting a sinusoidal wave is introduced. Advantageously, when said first load includes an antenna, this aspect of the invention makes it possible to comply with the requirements of several wireless transmission standards, for example, as dictated in the 3GPP specifications, which prohibit the irradiation of continuous wave signals (E. Dahlman, S. Parkvall, J. Skold, 5G NR: The Next Generation Wireless Access Technology, Academic Press, Cambridge MA, USA, 2020).
　　According to one aspect of the invention, the digital predistortion system also comprises:
・　　second means for obtaining (preferably from another device, via connecting to the same, and preferably consisting of a buffer memory of the first-in first-out type) a second baseband signal consisting of digital values representing data to be transmitted;
・　　fourth evaluating means (preferably consisting of a combination of pipelined single-cycle hardware multipliers and summers) of an algebraic expression (preferably consisting of a memoryless polynomial), from said second baseband signal given a set of parameter values (preferably consisting of coefficients of a memoryless polynomial), stored in said first memory array;
・　　fourth converting means (preferably consisting of a digital-to-analog converter intended for direct radiofrequency synthesis, for example, type AD9737A from Analog Devices Inc.), from the digital values emitted by said fourth evaluating means, of an analog signal;
・　　second modulating means (preferably consisting of an up-converter circuit, for example, type ADMV1013 by Analog Devices Inc.), for obtaining from said analog signal (emitted by said fourth converting means) a higher frequency analog signal by means of mixing said analog signal (emitted by said fourth converting means) with said carrier signal (emitted by said local oscillating means);
・　　second radio power amplifying means (preferably consisting of a radio power amplifier realized using complementary metal-oxide-semiconductor technology, for example, as found in type SUMMIT3741 by MixComm Inc.), of said higher frequency analog signal (emitted by said second modulating means);
・　　a third load (preferably consisting of a transmitting antenna, connected by means of suitable matching and auxiliary circuits), connected to the output of said second radio power amplifying means.
　　According to this aspect of the invention, the possibility of applying one set of parameters of the algebraic expression (preferably, coefficients of a memoryless polynomial) to the linearization of more than one radio power amplifier is introduced. Advantageously, this aspect of the invention makes it possible to reduce the amount of circuitry required for the linearization of multiple amplifiers that are expected, by construction, to have similar characteristics. By way of example, in the presence of large arrays of transmitters, this alleviates the design difficulties associated with the high area occupancy incurred when instantiating multiple copies of the entire digital predistortion system.
　　Further objects and advantages of the present invention will become apparent from the detailed description provided below of example embodiments thereof and from the accompanying drawings merely given by way of a non-limiting example, in which:
FIG. 1 shows a schematization of a digital predistortion system according to the present invention; FIG. 2 shows a schematization of one form of realization of the generating means forming part of the system in FIG. 1; FIG. 3 shows a schematization of another form of realization of the generating means forming part of the system in FIG. 1; FIG. 4 shows a schematization of one form of realization of the measuring means forming part of the system in FIG. 1; FIG. 5 shows a schematization of another form of realization of the measuring means forming part of the system in FIG. 1; FIG. 6 shows a schematization of one form of realization of the controlling means forming part of the system in FIG. 1; FIG. 7 shows a schematization of one form of realization of the first calculating means forming part of the system in FIG. 1; FIG. 8 shows a schematization of a variant of the system in FIG. 1, provided with means for transducing at least one physical magnitude representing a radio power amplifier and/or load characteristic; FIG. 9 shows a schematization of one form of realization of the modifying means forming part of a variant of the system in FIG. 1, provided with the same; FIG. 10 shows a schematization of another variant of the system in FIG. 1, provided with additional selecting means between one output of the extracting means and the output of the modulating means; FIG. 11 shows a schematization of another variant of the system in FIG. 1, provided with additional switching means between a first and a second load; FIG. 12 shows a schematization of another variant of the system in FIG. 1, provided with additional obtaining means, evaluating means, converting means, modulating means, amplifying means and load.
Detailed description of some preferred embodiments of the invention
　　In the continuation of the present description, a drawing may also be shown with reference to elements not expressly indicated in that drawing but in other drawings. The scale and proportions of the different elements depicted do not necessarily correspond to the actual ones.
　　FIG. 1 shows a non-linear distortion compensation system 1 applied to a first radio power amplifier 2 in order to distort the signal entered into said amplifier in such way as to at least partially compensate the non-linear distortion introduced by the amplifier itself (for example, gain compression), therefore improving the fidelity of wireless transmission.
　　The system 1, object of invention, includes first means 3 for obtaining a first baseband signal consisting of digital values, preferably from another device, via connecting to the same and preferably consisting of a buffer memory of the first-in first-out type. Said system further includes a first memory array 4, preferably consisting of a static random access memory, suitable for storing the values of a multitude of parameters, preferably consisting of coefficients of a memoryless polynomial, belonging to an algebraic expression. The signal obtained by said first obtaining means 3 is sent to first means 5, preferably consisting of a combination of pipelined single-cycle hardware multipliers and summers, for evaluating an algebraic expression, preferably consisting of a memoryless polynomial, from said first baseband signal in combination with the parameters stored in said first memory array 4 and obtained from the same.
　　The signal output by said first evaluating means 5 is sent to means 6, preferably consisting of a digital-to-analog converter intended for direct radiofrequency synthesis, combined either with an analog frequency synthesizer combined with a variable gain amplifier and analog switch, or with a digital signal synthesizer and digital multiplexer switch, for generating an analog signal from the digital values determined by said algebraic expression as emitted by said evaluating means 5 or according to a sinusoidal wave having controllable amplitude and frequency determined by said first digital value 7 upon the assertion of a first logical signal 8. The analog signal thus generated is fed to first modulating means 9, preferably consisting of an up-converter circuit, alongside a carrier signal having a known frequency emitted by local oscillating means 10 so as to obtain a higher frequency analog signal.
　　In turn, said higher frequency analog signal emitted by said first modulating means 9 is entered into said radio power amplifier 2, preferably realized using complementary metal-oxide-semiconductor technology. The output of the same is conveyed into means 11, preferably consisting of a power splitter, for extracting a fraction of the signal emitted by said radio power amplifier 2 before it reaches a first load 12, preferably consisting of a transmitting antenna, connected by means of suitable matching and auxiliary circuits. Said signal fraction extracted by said extracting means 11 is fed to first demodulating means 13, preferably a consisting of a down-converter circuit, alongside said carrier signal having a known frequency emitted by said local oscillating means 10 so as to obtain a lower frequency analog signal.
　　Said lower frequency analog signal emitted by said first demodulating means 13 is entered into means 14 for measuring the spectral amplitude at a selected frequency, determined by a second digital value 15. As can be seen in FIG. 1, the operation of said generating means 6 and said measuring means 14 is determined by the operation of further means 17 for controlling the process of measuring the non-linear distortion introduced by said first radio power amplifier 2, which, during the measurement process initiated by the external assertion of said second logical signal 18, impart settings of the amplitude and frequency of the analog signal emitted by said generating means 6 by means of the corresponding first digital value 7, having asserted said first logical signal 8 connected to the same, while simultaneously storing the spectral amplitudes obtained by said measuring means 14 at each frequency determined by said corresponding second digital value 15 into said second memory array 16, preferably consisting of a static random access memory.
　　Finally, the contents of said second memory array 16 are provided to first means 20 for calculating, upon the assertion of said third logical signal 19 emitted by said controlling means 17 upon the completion of the measurement process, the values of said multitude of parameters, preferably consisting of coefficients of a memoryless polynomial, belonging to said algebraic expression and stored in said first memory array 4, so as to cause the output of said first radio power amplifier 2 to be as closely as possible linearly related to said first baseband signal as it would appear after being modulated to a higher frequency by mixing it with said carrier signal emitted by said local oscillating means, that is, so as to compensate as accurately as possible the non-linear distortion introduced by said first radio amplifier 2.
　　FIG. 2 shows a form of realization of the non-linear distortion compensation system 1 according to which said generating means 6 comprise first means 21, preferably consisting of a digital-to-analog intended for direct radiofrequency synthesis, for converting the output of said first evaluating means 5 into an analog signal alongside first means 22a, preferably consisting of an analog frequency synthesizer combined with a variable gain amplifier, for synthesizing a sinusoidal analog signal having amplitude and frequency determined by means of said corresponding first digital value 7. The outputs of said first converting means 21 and said first synthesizing means 22a are provided to first means 23a, preferably consisting of an analog switch, for selecting, if said first logical signal 8 is not asserted, the analog signal output by said first converting means 21, otherwise, if said first logical signal 8 is asserted, the analog signal output by said first synthesizing means 22a, and providing the selected signal as input to said first modulating means 9.
　　FIG. 3 shows another form of realization of the non-linear distortion compensation system 1 according to which said generating means 6 comprise first means 22b, preferably consisting of a digital signal synthesizer, for synthesizing digital values corresponding to a sinusoidal wave having amplitude and frequency determined by means of said first corresponding digital value 7. The outputs of said first synthesizing means 22b and of said first evaluating means 5 are provided to first means 23b, preferably consisting of a digital multiplexer switch, for selecting, if said first logical signal 8 is not asserted, the digital values output by said first evaluating means 5, otherwise, if said first logical signal 8 is asserted, the digital values output by said first synthesizing means 22b. In turn, the output of said first selecting means 23b is entered into said first means 21, preferably consisting of a digital-to-analog converter intended for direct radiofrequency synthesis, for converting the same into an analog signal, which is provided as input to said first modulating means 9.
　　It is widely known to those skilled in the art that the forms of realization visible in FIG. 2 and FIG. 3 are equivalent in their function and purpose, being used interchangeably depending on practical design considerations (T.J. Rouphael, RF and Digital Signal Processing for Software-Defined Radio: A Multi-Standard Multi-Mode Approach, Newnes, London, UK, 2008).
　　FIG. 4 shows a form of realization of the measuring means 14, characterized in that said measuring means comprise first means 24, preferably consisting of a band-pass filter network, for filtering, by attenuating all frequencies outside a specified range, connected to the output of said first demodulating means 13, alongside second means 25, preferably consisting of a fractional phase locked loop, for synthesizing a sinusoidal analog signal having frequency determined by means of said second digital value 15. The outputs of said first filtering means 24 and synthesizing means 25 are, in turn, connected to second means 26, preferably consisting of a down-converter circuit, for demodulating to a lower frequency the output of said filtering means 24 by mixing it with the output of said second synthesizing means 25. The output of said demodulating means 26 is entered into second means 27, preferably consisting of a low-pass filter network, for filtering by attenuating all frequencies outside a specified range, whose output is in turn provided to second means 28, preferably consisting of an analog-to-digital converter of the successive approximation type, for converting the same into digital values, which are provided as input to said controlling means 17.
　　FIG. 5 shows a form of realization of the measuring means 14, characterized in that said measuring means comprise first means 24, preferably consisting of a band-pass filter network, for filtering by attenuating all frequencies outside a specified range, receiving as input the output of said first demodulating means 13 and having their output provided to second means 30, preferably consisting of an analog-to-digital converter of the flash type, for converting the same into digital values. The output of said converting means 30 is, in turn, provided to first means 32, preferably consisting of a register or set of registers, for interfacing the same with a third memory array 31, preferably consisting of a static random access memory, so that the output of the former is stored into the latter. To contents of said third memory array 31 are made available to second means 33, preferably consisting of a digital signal processor implementing the discrete or fast versions of the Fourier transform, for calculating, based on the same, the spectral amplitude of the signal output by said filtering means 29 at a frequency determined by means of said second corresponding digital value 15. The output of said second calculating means 33 is, finally, provided as input to said controlling means 17.
　　FIG. 6 shows a form of realization of the controlling means 17, characterized in that said controlling means comprise a fourth memory array 34, preferably consisting of a preprogrammed read-only memory, adapted to store a predetermined sequence of digital values. The output from this memory is connected to said generating means 6 and to said measuring means 14 through corresponding means of interfacing 35,36, both preferably consisting of a register or set of registers and emitting, respectively, said first and second digital values 7,15. Said controlling means 17 also comprise means 37, preferably consisting of a register or set of registers and an address generator, for interfacing said measuring means 14 with said second memory array 16, receiving as input the output of said measuring means 14 and having their output connected to said second memory array 16, so that the output of the former means is stored in the latter memory. Said controlling means 17 furthermore comprise first means 38, preferably consisting of a finite state machine or set thereof, for sequencing, upon the assertion of a second logical signal 18 and according to the predetermined sequence contained in said fourth memory array 34 by means of providing an addressing output to the same, the emission of said first and second digital values 7,15 by means of said interfacing means 35,36 and the storage of the output of said measuring means 14 into said second memory array 16 by means of said interfacing means 37, and asserting said third logical signal 19 upon the completion of said predetermined sequence.
　　FIG. 7 shows a form of realization of the calculating means 20, characterized in that said calculating means comprise a first set of memory arrays 39, preferably consisting of a set of preprogrammed read-only memories, each one corresponding to one parameter to be calculated and adapted to store a first group of coefficient values used in the calculation of the same, having their outputs connected to first means 40, preferably consisting of a multiplexer and address decoder, for addressing one memory array among those included in said first set of memory arrays 39. The output of said first addressing means 40 is connected, alongside the output of said second memory array 16, to the inputs of first means 41, preferably consisting of a pipelined single-cycle hardware multiplier, for multiplying the values contained in the latter by the corresponding first coefficient values stored in the array addressed by said first addressing means 40. Said calculating means 20 further comprise a second set of memory arrays 42, preferably consisting of a set of preprogrammed read-only memories, each one corresponding to one parameter to be calculated and adapted to store a first group of offset values used in the calculation of the same, having their outputs connected to second means 43, preferably consisting of a multiplexer and address decoder, for addressing one memory array among those included in said second set of memory arrays 42. The output of said second addressing means 43 is connected, alongside the output of said first multiplying means 41, to the inputs of first means 44 for summing the output of said first multiplying means 41 to the corresponding first offset values stored in the array addressed by said second addressing means 43. In turn, the output of said first summing means 44, preferably consisting of a pipelined single-cycle hardware summer, is convyed to second means 45 for evaluating an activation function as a function of the output of said first summing means 44. Said calculating means 20 further comprise a third set of memory arrays 46, preferably consisting of a set of preprogrammed read-only memories, each one corresponding to one parameter to be calculated and adapted to store a second group of coefficient values used in the calculation of the same, having their outputs connected to third means 47, preferably consisting of a multiplexer and address decoder, for addressing one memory array among those included in said third set of memory arrays 46. The output of said third addressing means 47 is connected, alongside the output of said second evaluating means 45, preferably consisting of a look-up table containing the values taken by a hyperbolic tangent function or of an interpolator combined with a look-up table containing the same, to the inputs of second means 48, preferably consisting of a pipelined single-cycle hardware multiplier, for multiplying the output of said second evaluating means 45 by the corresponding second coefficient values stored in the array addressed by said third addressing means 47. Said calculating means 20 further comprise a fourth set of memory arrays 49, preferably consisting of a set of preprogrammed read-only memories, each one corresponding to one parameter to be calculated and adapted to store a second group of offset values used in the calculation of the same, having their outputs connected to fourth means 50, preferably consisting of a multiplexer and address decoder, for addressing one memory array among those included in said fourth set of memory arrays 49. The output of said fourth addressing means 50 is connected, alongside the output of said second multiplying means 48, to the inputs of second means 51, preferably consisting of a pipelined single-cycle hardware summer, for summing the output of said second multiplying means 48 to the corresponding second offset values stored in the array addressed by said fourth addressing means 50. In turn, the output of said second summing means 51 is conveyed to third means 52, preferably consisting of a look-up table containing the values taken by a linear function, or an interpolator combined with a look-up table containing the same, for evaluating an activation function as a function of the output of said second summing means 51. Said calculating means 20 also comprise means 53, preferably consisting of a register or set of registers and an address generator, for interfacing said evaluating means 52 with said second memory array 4, receiving as input the output of said evaluating means 52 and having their output connected to said second memory array 4, so that the output of the former means is stored in the latter memory. Said calculating means 20 further comprise second means 54, preferably consisting of a finite state machine or set thereof, for sequencing, at least once upon the assertion of said third logical signal 19 and according to a hardwired sequence, the operation of said first, second, third and fourth addressing means 40,43,47,50 and interfacing means 53, by means of outputs connected to all of said means, so that all the values for the parameters to be stored in said first memory array 4 are calculated based on the values contained in said second memory array 16, and stored in said first memory array 4.
　　FIG. 8 shows a form of realization of the non-linear distortion compensation system 1, characterized in that said system further comprises means 55 for transducing at least one physical magnitude, preferably consisting of a voltage and/or a current and/or a temperature, representing a characteristic of said first radio power amplifier 2 and/or said first load 12, the output of said transducing means 55 being connected to the input of amplifying means 56, preferably consisting of an operational amplifier connected according to an active filter topology, so as to magnify fluctuations associated with the operation of either said first radio power amplifier 2 and/or said first load 12. The output of said amplifying means 56 is, in turn, connected to the input of third means 57, preferably consisting of an analog-to-digital converter of the successive approximation type, for converting the same into digital values. According to this form of realization, said system means 1 also comprises means 59, preferably consisting of a register or set of registers and an address generator, for interfacing said third converting means 57 with said a fifth memory array 58, preferably consisting of a static random access memory, receiving as input the output of said converting means 57 and having their output connected to said fifth memory array 58, so that the output of the former means is stored in the latter memory. Finally, the contents of said fifth memory array 58 are provided to said first calculating means 20 so that the values contained in it are made available to the same alongside the values contained in said second memory array 16.
　　FIG. 9 shows a form of realization of the non-linear distortion compensation system 1, characterized in that said system further comprises modifying means 60, characterized in that said modifying means comprise means 62, preferably consisting of a register or set of registers and an address generator, for interfacing said third converting means 57 with a sixth memory array 61, preferably consisting of a static random access memory, so that the output of the former is stored into the latter whenever said third logical signal 19 is asserted. The contents of said sixth memory array 61 are provided, alongside the contents of said fifth memory array 58, to means 63 for subtracting the former from the latter. The output of said subtracting means 63, preferably consisting of a pipelined single-cycle hardware summer with a negative sign input, is connected to the input of third means 65 for multiplying the same by the corresponding coefficient values stored in a seventh memory array 64, preferably consisting of a preprogrammed read-only memory. When said modifying means 60 are present, the output of the first calculating means 20 is connected, in place of said first memory array 4, to the input of an eight memory array 66, preferably consisting of a static random access memory, so as to be stored in the same. The output of said third multiplying means 65 is connected, together with that of said eight memory array 66, to third means 67 for summing the output of said multiplying means 65, preferably consisting of a pipelined single-cycle hardware multiplier, to the values contained in said eight memory array 66. According to this form of realization, said modifying means 60 also comprise means 68, preferably consisting of a register or set of registers and an address generator, for interfacing said third summing means 67, preferably consisting of a pipelined single-cycle hardware summer, with said first memory array 4, so that the output of the former means is stored in the latter memory.
　　FIG. 10 shows a form of realization of the non-linear distortion compensation system 1, characterized in that said system further comprises second means 69, preferably consisting of an analog microwave switch, for selecting, if a fourth logical signal 70 is not asserted, one output of said extracting means 11, otherwise, if said fourth logical signal 70 is asserted, the output of said first modulating means 9, and providing the selected signal as input to said first demodulating means 13. Differently to the representation in FIG. 1, said extracting means 11 and said first demodulating means 13 are connected not directly but through said second selecting means 69.
　　FIG. 11 shows a form of realization of the non-linear distortion compensation system 1, characterized in that said system further comprises a second load 71, preferably consisting of a resistor, connected to one of the two outputs of means 72, preferably consisting of an analog microwave switch, for switching, having the other output connected to said first load 12, so that, if said first logical signal 8 is not asserted, one output of said extracting means 11 is conveyed to said first load 12, otherwise, if said first logical signal 8 is asserted, the same output of said extracting means 11 is conveyed to said second load 71. Differently to the representation in FIG. 1, said extracting means 11 and said first load 12 are connected not directly but through said switching means 72.
　　FIG. 12 shows a form of realization of the non-linear distortion compensation system 1, characterized in that said system further comprises second means 72 for obtaining a second baseband signal consisting of digital values, preferably from another device, via connecting to the same, and preferably consisting of a buffer memory of the first-in first-out type, whose output is connected to the input of fourth means 73, preferably consisting of a combination of pipelined single-cycle hardware multipliers and summers, for evaluating said algebraic expression based on the parameter values stored in said first memory array 4. The output of said said fourth evaluating means 73 is provided as input to fourth means 74, preferably consisting of a digital-to-analog converter intended for direct radiofrequency synthesis, for converting the same into an analog signal, which is connected to the input of second means 75, preferably consisting of an up-converter circuit, for modulating the same to a higher frequency by mixing it with said carrier signal emitted by said local oscillator 10. The output of said second modulating means 75 is, in turn, connected to the input of a second radio power amplifier 76, preferably consisting of a radio power amplifier realized using complementary metal-oxide-semiconductor technology, whose output is connected to a third load 77, preferably consisting of a transmitting antenna, connected by means of suitable matching and auxiliary circuits.
　　On the basis of the description provided for a preferred example embodiment, it is obvious that some changes may be made by those skilled in the art without departing from the scope of the invention as defined by the following claims.

Claims (10)

  1. 　　A system (1) for compensating the non-linear distortion introduced by a radio power amplifier (2), comprising:
    ・　　first means (3) for obtaining a first baseband signal consisting of digital values;
    ・　　a first memory array (4), adapted to store the values of a multitude of parameters belonging to an algebraic expression;
    ・　　first means (5) for evaluating said algebraic expression as a function of the output of said first obtaining means (3) and based on the parameter values stored in said first memory array (4);
    ・　　means (6) for generating,
    　　°　　if a first logical signal (8) is not asserted, an analog signal based on the output of said first evaluating means (5),
    otherwise,
    　　°　　if said first logical signal (8) is asserted, an analog signal containing a sinusoidal wave having amplitude and frequency determined by means of a corresponding first digital value (7);
    ・　　first means (9) for modulating to a higher frequency the output of said generating means (6) by mixing it with a carrier signal emitted by a local oscillator (10);
    ・　　said first radio power amplifier (2), having as input the output of said first modulating means (9);
    ・　　means (11) for extracting a fraction of the signal emitted by said first radio power amplifier (2) before it reaches a first load (12);
    ・　　first means (13) for demodulating to a lower frequency one output of said extracting means (11) by mixing it with said carrier signal emitted by said local oscillator (10);
    ・　　means (14) for measuring the spectral amplitude of a signal at a frequency determined by means of a corresponding second digital value (15), having as input the output of said first demodulating means (13);
    ・　　a second memory array (16), adapted to store a multitude of outputs of said measuring means (14);
    ・　　means (17) for controlling the process of measuring the non-linear distortion introduced by said first radio power amplifier (2),
    characterized in that, upon the assertion of a second logical signal (18), said controlling means (17) assert said first logical signal (8) while emitting a predetermined sequence of first and second digital values (7,15) and simultaneously storing the output of said measuring means (14) into said second memory array (16), and assert a third logical signal (19) upon the completion of said predetermined sequence,
    said system further comprising:
    ・　　first means (20) for calculating, upon the assertion of said third logical signal (19) and based on the values contained in said second memory array (16), the values for the parameters to be stored in said first memory array (4), and storing them into the same thereby providing them to said first evaluating means (5), so as to cause the output of said first radio power amplifier (2) to be as closely as possible linearly related to the signal output by said first obtaining means (3) as it would appear after being modulated to a higher frequency by mixing it with said carrier signal emitted by said local oscillator (10),
    said generating means (6) comprising either:
    ・　　first means (21) for converting the output of said first evaluating means (5) into an analog signal;
    ・　　first means (22a) for synthesizing a sinusoidal analog signal having amplitude and frequency determined by means of said corresponding first digital value (7);
    ・　　first means (23a) for selecting,
    　　°　　if said first logical signal (8) is not asserted, the analog signal output by said first converting means (21),
    otherwise,
    　　°　　if said first logical signal (8) is asserted, the analog signal output by said first synthesizing means (22a),
    　　and providing the selected signal as input to said first modulating means (9),
    or:
    ・　　first means (22b) for synthesizing digital values representing a sinusoidal wave having amplitude and frequency determined by means of said corresponding first digital value (7);
    ・　　first means (23b) for selecting,
    　　°　　if said first logical signal (8) is not asserted, the digital values output by said first evaluating means (5),
    　　otherwise,
    　　°　　if said first logical signal (8) is asserted, the digital values output by said first synthesizing means (22b);
    ・　　first means (21) for converting the output of said first selecting means (23b) into an analog signal, and providing it as input to said first modulating means (9).
  2. 　　A non-linear distortion compensation system (1) according to claim 1, characterized in that said measuring means (14) comprise:
    ・　　first means (24) for filtering, by attenuating all frequencies outside a specified range, the output of said first demodulating means (13);
    ・　　second means (25) for synthesizing a sinusoidal analog signal having frequency determined by means of a corresponding second digital value (15);
    ・　　second means (26) for demodulating to a lower frequency the output of said filtering means (24) by mixing it with the output of said second synthesizing means (25);
    ・　　second means (27) for filtering, by attenuating all frequencies outside a specified range, the output of said second demodulating means (26);
    ・　　second means (28) for converting into digital values the output of said second filtering means (27), and providing it as input to said controlling means (17).
  3. 　　A non-linear distortion compensation system (1) according to claim 1, characterized in that said measuring means (14) comprise:
    ・　　means (29) for filtering, by attenuating all frequencies outside a specified range, the output of said first demodulating means (13);
    ・　　second means (30) for converting into digital values the output of said filtering means (29);
    ・　　a third memory array (31), adapted to store a multitude of outputs of said second converting means (30);
    ・　　first means (32) for interfacing said second converting means (30) with said third memory array (31), so that the output of the former is stored into the latter;
    ・　　second means (33) for calculating, based on the values contained in said third memory array (31), the spectral amplitude of the signal output by said filtering means (29) at a frequency determined by means of a corresponding second digital value (15), and providing it as input to said controlling means (17).
  4. 　　A non-linear distortion compensation system (1) according to one of the preceding claims, characterized in that said controlling means (17) comprise:
    ・　　a fourth memory array (34) adapted to store a predetermined sequence of first and second digital values (7,15) to be applied, respectively, to said generating means (6) and said measuring means (14) via corresponding second and third means of interfacing (35,36);
    ・　　fourth means (37) for interfacing said measuring means (14) with said second memory array (16), so that the output of the former is stored in the latter;
    ・　　first means (38) for sequencing, upon the assertion of a second logical signal (18) and according to the predetermined sequence contained in said fourth memory array (34), the emission of said first and second digital values (7,15) by means of said second and third interfacing means (35,36) and the storage of the output of said measuring means (14) into said second memory array (16) by means of said fourth interfacing means (37), and asserting said third logical signal (19) upon the completion of said predetermined sequence.
  5. 　　A non-linear distortion compensation system (1) according to one of the preceding claims, characterized in that said first calculating means (20) comprise:
    ・　　a first set of memory arrays (39), each one corresponding to one parameter to be calculated and adapted to store a first group of coefficient values used in the calculation of the same;
    ・　　first means (40) for addressing one memory array among those included in said first set of memory arrays (39);
    ・　　first means (41) for multiplying the values contained in said second memory array (16) by the corresponding first coefficient values stored in the array addressed by said first addressing means (40);
    ・　　a second set of memory arrays (42), each one corresponding to one parameter to be calculated and adapted to store a first group of offset values used in the calculation of the same;
    ・　　second means (43) for addressing one memory array among those included in said second set of memory arrays (42);
    ・　　first means (44) for summing the output of said first multiplying means (41) to the corresponding first offset values stored in the array addressed by said second addressing means (43);
    ・　　second means (45) for evaluating an activation function as a function of the output of said first summing means (44);
    ・　　a third set of memory arrays (46), each one corresponding to one parameter to be calculated and adapted to store a second group of coefficient values used in the calculation of the same;
    ・　　third means (47) for addressing one memory array among those included in said third set of memory arrays (46);
    ・　　second means (48) for multiplying the output of said second evaluating means (45) by the corresponding second coefficient values stored in the array addressed by said third addressing means (47);
    ・　　a fourth set of memory arrays (49), each one corresponding to one parameter to be calculated and adapted to store a second group of offset values used in the calculation of the same;
    ・　　fourth means (50) for addressing one memory array among those included in said fourth set of memory arrays (49);
    ・　　second means (51) for summing the output of said second multiplying means (48) to the corresponding second offset values stored in the array addressed by said fourth addressing means (50);
    ・　　third means (52) for evaluating an activation function as a function of the output of said second summing means (51);
    ・　　fifth means (53) for interfacing said third evaluating means (52) with said first memory array (4), so that the output of the former is stored into the latter;
    ・　　second means (54) for sequencing, at least once upon the assertion of said third logical signal (19) and according to a hardwired sequence, the operation of said first, second, third and fourth addressing means (40,43,47,50) and fifth interfacing means (53), so that all the values for the parameters to be stored in said first memory array (4) are calculated based on the values contained in said second memory array (16), and stored in said first memory array (4).
  6. 　　A non-linear distortion compensation system (1) according to one of the preceding claims, characterized in that it further comprises:
    ・　　means (55) for transducing at least one physical magnitude representing a characteristic of said first radio power amplifier (2) and/or said first load (12);
    ・　　means (56) for amplifying the output of said transducing means (55) to magnify fluctuations associated with the operation of either said first radio power amplifier (2) and/or said first load (12);
    ・　　third means (57) for converting into digital values the output of said amplifying means (56);
    ・　　a fifth memory array (58) adapted to store a multitude of outputs of said third converting means (57) and connected to said first calculating means (20) so that the values contained in it are made available to the latter alongside the values contained in said second memory array (16);
    ・　　sixth means (59) for interfacing said third converting means (57) with said fifth memory array (58), so that the output of the former is stored in the latter.
  7. 　　A non-linear distortion compensation system (1) according to claim 6, characterized in that it further comprises:
    ・　　means (60) for modifying the values of the parameters belonging to an algebraic expression stored in said first memory array (4) when interposed between the same and said first calculating means (20), comprising:
    　　°　　a sixth memory array (61) adapted to store a multitude of outputs of said third converting means (57);
    　　°　　seventh means (62) for interfacing said third converting means (57) with said sixth memory array (61), so that the output of the former is stored into the latter whenever said third logical signal (19) is asserted;
    　　°　　means (63) for subtracting the values contained in said sixth memory array (61) from the values contained in said fifth memory array (58);
    　　°　　a seventh memory array (64) adapted to store a multitude of coefficient values corresponding to the values stored in said fifth and sixth memory arrays (58,61);
    　　°　　third means (65) for multiplying the output of said subtracting means (63) by the corresponding coefficient values stored in said seventh memory array (64);
    　　°　　an eight memory array (66), adapted to store the values of a multitude of parameters belonging to an algebraic expression output by said first calculating means (20), and connected to the same in place of said first memory array (4);
    　　°　　third means (67) for summing the output of said third multiplying means (65) to the values contained in said eight memory array (66);
    　　°　　seventh means (68) for interfacing said third summing means (67) with said first memory array (4), so that the output of the former is stored in the latter,
    so that said first memory array (4) and said calculating means (20) are connected by means of the same.
  8. 　　A non-linear distortion compensation system (1) according to one of the preceding claims, characterized in that it further comprises second means (69) for selecting,
    ・　　if a fourth logical signal (70) is not asserted, one output of said extracting means (11),
    otherwise,
    ・　　if said fourth logical signal (70) is asserted, the output of said first modulating means (9),
    and providing the selected signal as input to said first demodulating means (13), so that said extracting means (11) and said first demodulating means (13) are connected by means of the same,
    said controlling means (17) being adapted to emit, upon the assertion of said second logical signal (18) and in addition to said first logical signal (8), also said fourth logical signal (70), in such a way that the output of said measuring means (14) is stored into said second memory array (16) both when said fourth logical signal (70) is asserted and when the same is not asserted, thus measuring separately the response of the combination of said first modulating means (9), said first demodulating means (13), and said measuring means (14) without the non-linear distortion introduced by said first radio power amplifier (2), and the same response additionally combined with the non-linear distortion introduced by said first radio power amplifier (2).
  9. 　　A non-linear distortion compensation system (1) according to one of the preceding claims, characterized in that it further comprises:
    ・　　a second load (71);
    ・　　means (72) for switching,
    　　°　　if said first logical signal (8) is not asserted, one output of said extracting means (11) so that it is conveyed to said first load (12),
    　　otherwise,
    　　°　　if said first logical signal (8) is asserted, one output of said extracting means (11) so that it is conveyed to said second load (71),
    so that said extracting means (11) and said first load (12) are connected by means of the same.
  10. 　　A non-linear distortion compensation system (1) according to one of the preceding claims, characterized in that it further comprises:
    ・　　second means (72) for obtaining a second baseband signal consisting of digital values;
    ・　　fourth means (73) for evaluating said algebraic expression as a function of the output of said second obtaining means (72) and based on the parameter values stored in said first memory array (4);
    ・　　fourth means (74) for converting the output of said second evaluating means (73) into an analog signal;
    ・　　second means (75) for modulating to a higher frequency the output of said fourth converting means (74) by mixing it with said carrier signal emitted by said local oscillator (10);
    ・　　a second radio power amplifier (76), having as input the output of said second modulating means (75);
    ・　　a third load (77) connected to the output of said second radio power amplifier (76).
PCT/JP2022/038955 2022-10-19 2022-10-19 System for compensating the non-linear distortion introduced by a radio power amplifier based on harmonic analysis WO2024084629A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050058220A1 (en) * 2002-05-31 2005-03-17 Kazuo Nagatani Adaptive control apparatus
JP2012044236A (en) * 2010-08-12 2012-03-01 Nippon Telegr & Teleph Corp <Ntt> Transmitter and transmission method
JP2012060478A (en) * 2010-09-09 2012-03-22 Fujitsu Ltd Signal processing circuit, radio communication apparatus, conversion circuit, adjustment method and adjustment system
US20140119296A1 (en) * 2012-11-01 2014-05-01 Fujitsu Limited Wireless communication device, wireless communication method, and wireless communication system
US20180115288A1 (en) * 2016-10-24 2018-04-26 Fujitsu Limited Arithmetic method, base station device, and arithmetic circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050058220A1 (en) * 2002-05-31 2005-03-17 Kazuo Nagatani Adaptive control apparatus
JP2012044236A (en) * 2010-08-12 2012-03-01 Nippon Telegr & Teleph Corp <Ntt> Transmitter and transmission method
JP2012060478A (en) * 2010-09-09 2012-03-22 Fujitsu Ltd Signal processing circuit, radio communication apparatus, conversion circuit, adjustment method and adjustment system
US20140119296A1 (en) * 2012-11-01 2014-05-01 Fujitsu Limited Wireless communication device, wireless communication method, and wireless communication system
US20180115288A1 (en) * 2016-10-24 2018-04-26 Fujitsu Limited Arithmetic method, base station device, and arithmetic circuit

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