WO2024076395A2 - Communicating electrical signals in a cryogenic system - Google Patents

Abstract

In a general aspect, an apparatus is configured for communicating electrical signals in a cryogenic system. The apparatus includes a metal plate and a circuit board secured to the metal plate. The metal plate includes a first surface on a first side, a second surface on a second, opposite side; and a slot that extends through the metal plate from the first surface to the second surface. The circuit board includes a central portion residing in the slot, first and second end portions residing outside the slot. The first and second end portions include electrical connectors that are configured to interface with one or more electrical cables. The circuit board further includes electrical circuitry configured to communicate electrical signals between the electrical connectors on the first and second end portions. The electrical circuitry includes signal lines each extends from the first end portion, through the central portion, into the second end portion.

Description

Communicating Electrical Signals in a Cryogenic System

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63/349,881, filed June 7, 2022, entitled "Communicating Electrical Signals in a Cryogenic System.” The above-referenced priority document is incorporated herein by reference.

TECHNICAL FIELD

[0002] The following description relates to formation and operation of an apparatus for communicating electrical signals through a flange in a cryogenic system.

BACKGROUND

[0003] Quantum computers can perform computational tasks by storing and processing information within quantum states of quantum systems. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. A variety of physical systems have been proposed for quantum computing applications. Examples include superconducting circuits, trapped ions, spin systems and others.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a block diagram of an example computing environment.

[0005] FIGS. 2A-2E are schematic diagrams showing a perspective view, an exploded view, and cross-sectional views of an example apparatus.

[0006] FIG. 3 is a schematic diagram showing a perspective view of an example apparatus.

[0007] FIG. 4 is a schematic diagram showing a perspective view of an example cryostat.

[0008] FIGS. 5A-5C are schematic diagrams showing a perspective view, an exploded view, and a cross-sectional view of an example circuit board. [0009] FIG. 6 is a schematic diagram showing an exploded view of an example circuit board.

[0010] FIGS. 7A-7C are schematic diagrams showing top and side views of example circuit boards connected to electrical cables.

[0011] FIG. 8 is a schematic diagram showing top view and side views of an example circuit board.

[0012] FIG. 9 is a schematic diagram showing a perspective view of an example circuit board.

[0013] FIGS. 10A-10C are schematic diagrams showing perspective views and an exploded view of an example apparatus.

DETAILED DESCRIPTION

[0014] Ultra-high density, thermalized, and light-tight bulkhead feedthroughs for RF- and DC-signals at the various stages in a cryogenic system are essential for scaling up cryogenic tests and quantum computations. Present-art for this uses coaxial feedthroughs and/or thermalized discrete wiring that has minimum specific areas of only 40 mm²/signal (an equivalent signal density is 0.025 signals/mm²) for RF signals and difficulty in establishing light-tight and thermalized connections for DC signals. The solution proposed here employs a circuit board, oriented out-of-plane of a metal plate, with electrical connectors on the ends of the circuit board for connecting to electrical cables. The electrical signals thus are transitioned from between stages on signal lines of the circuit board. Based on commercially available circuit boards, clamp assembly or other fasteners, and connectors, the specific area, is in a range equal to or less than 5 mm²/signal (an equivalent signal density of 0.2 signals/mm²). The system and method presented here provides improved signal density through flanges in a cryogenic system.

[0015] FIG. 1 is a block diagram of an example computing environment 100. The example computing environment 100 shown in FIG. 1 includes a computing system 101 and user devices 110A, HOB, HOC. A computing environment may include additional or different features, and the components of a computing environment may operate as described with respect to FIG. 1 or in another manner.

[0016] The example computing system 101 includes classical and quantum computing resources and exposes their functionality to the user devices 110A, HOB, HOC (referred to collectively as "user devices 110”). The computing system 101 shown in FIG. 1 includes one or more servers 108, quantum computing systems 103A, 103B, a local network 109 and other resources 107. The computing system 101 may also include one or more user devices (e.g., the user device 110A) as well as other features and components. A computing system may include additional or different features, and the components of a computing system may operate as described with respect to FIG. 1 or in another manner.

[0017] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109 or otherwise).

[0018] The user devices 110 shown in FIG. 1 may include one or more classical processors, memory, user interfaces, communication interfaces, and other components. For instance, the user devices 110 may be implemented as laptop computers, desktop computers, smartphones, tablets or other types of computer devices. In the example shown in FIG. 1, to access computing resources of the computing system 101, the user devices 110 send information (e.g., programs, instructions, commands, requests, input data, etc.) to the servers 108; and in response, the user devices 110 receive information (e.g., application data, output data, prompts, alerts, notifications, results, etc.) from the servers 108. The user devices 110 may access services of the computing system 101 in another manner, and the computing system 101 may expose computing resources in another manner.

[0019] In the example shown in FIG. 1, the local user device 110A operates in a local environment with the servers 108 and other elements of the computing system 101. For instance, the user device 110A may be co-located with (e.g., located within 0.5 to 1 km of) the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, the user device 110A communicates with the servers 108 through a local data connection.

[0020] The local data connection in FIG. 1 is provided by the local network 109. For example, some or all of the servers 108, the user device 110A, the quantum computing systems 103A, 103B and the other resources 107 may communicate with each other through the local network 109. In some implementations, the local network 109 operates as a communication channel that provides one or more low-latency communication pathways from the server 108 to the quantum computer systems 103A, 103B (or to one or more of the elements of the quantum computer systems 103A, 103B). The local network 109 can be implemented, for instance, as a wired or wireless Local Area Network, an Ethernet connection, or another type of wired or wireless connection. The local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements. In some cases, the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.

[0021] In the example shown in FIG. 1, the remote user devices HOB, HOC operate remote from the servers 108 and other elements of the computing system 101. For instance, the user devices 110B, HOC may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, each of the user devices 110B, 110C communicates with the servers 108 through a remote data connection.

[0022] The remote data connection in FIG. 1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network. In some cases, remote user devices use another type of remote data connection (e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108. The wide area network 115 may include one or more internet servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements. Generally, the computing environment 100 can be accessible to any number of remote user devices.

[0023] The example servers 108 shown in FIG. 1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B and the other resources 107.

[0024] As shown in FIG. 1, the servers 108 are classical computing resources that include classical processors 111 and memory 112. The servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115 and possibly other channels. In some implementations, the servers 108 may include a host server, an application server, a virtual server or a combination of these and other types of servers. The servers 108 may include additional or different features, and may operate as described with respect to FIG. 1 or in another manner.

[0025] The classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, by way of example, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these. The memory 112 can include, for example, a random access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium. The memory 112 can include various forms of volatile or non-volatile memory, media and memory devices, etc.

[0026] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum virtual machines (QVMs) or quantum simulators as well as classical (nonquantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.

[0027] In some implementations, the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution. For example, the servers 108 may send programs to the quantum computing system 103A, the quantum computing system 103B or any of the other resources 107. The programs may include classical programs, quantum programs, hybrid classical/quantum programs, and may include any type of function, code, data, instruction set, etc.

[0028] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere. In some instances, programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions) that can be executed directly by a computing resource. Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data. For example, a program can include instructions formatted for a quantum computer system, a quantum virtual machine, a digital microprocessor, co-processor or other classical data processing apparatus, or another type of computing resource.

[0029] In some cases, a program may be expressed in a hardware-independent format. For example, quantum machine instructions may be provided in a quantum instruction language such as Quil, described in the publication "A Practical Quantum Instruction Set Architecture,” arXiv:1608.03355v2, dated Feb. 17, 2017, or another quantum instruction language. For instance, the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or quantum virtual machines. In some cases, a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, or in another form. In some cases, a program may be expressed in terms of control signals (e.g., pulse sequences, delays, etc.) and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.). In some cases, a program may be expressed in another form or format.

[0030] In some implementations, the servers 108 include one or more compilers that convert programs between formats. For example, the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B. In some cases, a compiler can compile a program to a format that targets a specific quantum resource in the computer system 101. For example, a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to be executed by the quantum computing system 103A or the quantum computing system 103B.

[0031] In some cases, a compiler generates a partial binary program that can be updated, for example, based on specific parameters. For instance, if a quantum program is to be executed iteratively on a quantum computing system with varying parameters on each iteration, the compiler may generate the binary program in a format that can be updated with specific parameter values at runtime (e.g., based on feedback from a prior iteration, or otherwise). In some cases, a compiler generates a full binary program that does not need to be updated or otherwise modified for execution.

[0032] In some implementations, the servers 108 generate a schedule for executing programs, allocate computing resources in the computing system 101 according to the schedule, and delegate the programs to the allocated computing resources. The servers 108 can receive, from each computing resource, output data from the execution of each program. Based on the output data, the servers 108 may generate additional programs that are then added to the schedule, output data that is provided back to a user device 110, or perform another type of action. [0033] In some implementations, all or part of the computing environment operates as a cloud-based quantum computing (QC) environment, and the servers 108 operate as a host system for the cloud-based QC environment. The cloud-based QC environment may include software elements that operate on both the user devices 110 and the computer system 101 and interact with each other over the wide area network 115. For example, the cloud-based QC environment may provide a remote user interface, for example, through a browser or another type of application on the user devices 110. The remote user interface may include, for example, a graphical user interface or another type of user interface that obtains input provided by a user of the cloud-based QC environment. In some cases the remote user interface includes, or has access to, one or more application programming interfaces (APIs), command line interfaces, graphical user interfaces, or other elements that expose the services of the computer system 101 to the user devices 110.

[0034] In some cases, the cloud-based QC environment may be deployed in a "serverless” computing architecture. For instance, the cloud-based QC environment may provide on-demand access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, services, quantum computing resources, classical computing resources, etc.) that can be provisioned for requests from user devices 110. Moreover, the cloud-based computing systems 104 may include or utilize other types of computing resources, such as, for example, edge computing, fog computing, etc.

[0035] In an example implementation of a cloud-based QC environment, the servers 108 may operate as a cloud provider that dynamically manages the allocation and provisioning of physical computing resources (e.g., GPUs, CPUs, QPUs, etc.). Accordingly, the servers 108 may provide services by defining virtualized resources for each user account. For instance, the virtualized resources may be formatted as virtual machine images, virtual machines, containers, or virtualized resources that can be provisioned for a user account and configured by a user. In some cases, the cloud-based QC environment is implemented using a resource such as, for example, OPENSTACK ®. OPENSTACK ® is an example of a software platform for cloud-based computing, which can be used to provide virtual servers and other virtual computing resources for users. [0036] In some cases, the server 108 stores quantum machine images (QMI) for each user account. A quantum machine image may operate as a virtual computing resource for users of the cloud-based QC environment. For example, a QM1 can provide a virtualized development and execution environment to develop and run programs (e.g., quantum programs or hybrid classical /quantum programs). When a QMI operates on the server 108, the QMI may engage either of the quantum processor units 102A, 102B, and interact with a remote user device (110B or HOC) to provide a user programming environment. The QMI may operate in close physical proximity to and have a low-latency communication link with the quantum computing systems 103A, 103B. In some implementations, remote user devices connect with QMIs operating on the servers 108 through secure shell (SSH) or other protocols over the wide area network 115.

[0037] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted as hybrid classical/quantum programs that include instructions for execution by one or more quantum computing resources and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum virtual machines (QVMs), one or more quantum simulators, or possibly other types of quantum resources. The classical computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized coprocessor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), applicationspecific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.

[0038] In some cases, the servers 108 can select the type of computing resource (e.g., quantum or classical) to execute an individual program, or part of a program, in the computing system 101. For example, the servers 108 may select a particular quantum processing unit (QPU) or other computing resource based on availability of the resource, speed of the resource, information or state capacity of the resource, a performance metric (e.g., process fidelity) of the resource, or based on a combination of these and other factors. In some cases, the servers 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance.

[0039] Each of the example quantum computing systems 103A, 103B shown in FIG. 1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In some implementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. In some instances, quantum logic can be executed in a manner that allows large-scale entanglement within the quantum system. Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the qubits. In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits.

[0040] In some implementations, a quantum computing system can operate using gatebased models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation. [0041] In some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, quantum error correcting schemes can be deployed to achieve fault-tolerant quantum computation. Other computational regimes may be used; for example, quantum computing systems may operate in non-fault-tolerant regimes. In some implementations, a quantum computing system is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general purpose coherent quantum computing. Other architectures may be used; for example, quantum computing systems may operate in small- scale or non-scalable architectures.

[0042] The example quantum computing system 103A shown in FIG. 1 includes a quantum processing unit 102A and a control system 105A, which controls the operation of the quantum processing unit 102A. Similarly, the example quantum computing system 103B includes a quantum processing unit 102B and a control system 105B, which controls the operation of a quantum processing unit 102B. A quantum computing system may include additional or different features, and the components of a quantum computing system may operate as described with respect to FIG. 1 or in another manner.

[0043] In some instances, all or part of the quantum processing unit 102A functions as a quantum processor, a quantum memory, or another type of subsystem. In some examples, the quantum processing unit 102A includes a quantum circuit system. The quantum circuit system may include qubit devices, readout devices and possibly other devices that are used to store and process quantum information. In some cases, the quantum processing unit 102A includes a superconducting circuit, and the qubit devices are implemented as circuit devices that include Josephson junctions, for example, in superconducting quantum interference device [SQUID] loops or other arrangements, and are controlled by radiofrequency signals, microwave signals, and bias signals delivered to the quantum processing unit 102A. In some cases, the quantum processing unit 102A includes an ion trap system, and the qubit devices are implemented as trapped ions controlled by optical signals delivered to the quantum processing unit 102A. In some cases, the quantum processing unit 102A includes a spin system, and the qubit devices are implemented as nuclear or electron spins controlled by microwave or radio-frequency signals delivered to the quantum processing unit 102A. The quantum processing unit 102A may be implemented based on another physical modality of quantum computing.

[0044] The quantum processing unit 102A may include, or may be deployed within, a controlled environment. The controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems. In some examples, the components in the quantum processing unit 102A operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise. For example, magnetic shielding can be used to shield the system components from stray magnetic fields, optical shielding can be used to shield the system components from optical noise, thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.

[0045] In some implementations, the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A. The control signals can be configured to encode information in the qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits. In some examples, the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits. A quantum logic circuit, which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.

[0046] In some implementations, the example quantum processing unit 102 is a modular quantum processing unit that includes multiple quantum processor modules. For example, the quantum processing unit 102 may include a two-dimensional or three- dimensional array of quantum processor modules, and each quantum processor module may include an array of quantum circuit devices. In some cases, the quantum processor modules are supported on a common substrate, and they are interconnected through circuitry (e.g., superconducting circuitry) on the common substrate. [0047] In some instances, each of the quantum processor modules can include a superconducting quantum integrated circuit (QulC) that includes one or more quantum circuit devices and superconductive lines that connect the one or more quantum circuit devices. For instance, each quantum processor module may include qubit devices, readout resonator devices, tunable-frequency coupler devices, capacitive coupler devices, or other quantum circuit devices. Each quantum processor module may include flux bias control lines, microwave drive lines, readout signal lines, or other types of control lines for providing control signals to respective quantum circuit devices. In some implementations, quantum processor modules can be coupled to each other by inter-chip coupler devices in one or more cap structures.

[0048] The example control system 105A includes controllers 106A and signal hardware 104A. Similarly, control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a roomtemperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B. In some cases, the control systems 105A, 105B include classical computers, signaling equipment (microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems or other types of control systems that support operation of the quantum processing units 102A, 102B.

[0049] The control systems 105A, 105B may be implemented as distinct systems that operate independent of each other. In some cases, the control systems 105A, 105B may include one or more shared elements; for example, the control systems 105A, 105B may operate as a single control system that operates both quantum processing units 102A, 102B. Moreover, a single quantum computer system may include multiple quantum processing units, which may operate in the same controlled (e.g., cryogenic) environment or in separate environments.

[0050] The example signal hardware 104A includes components that communicate with the quantum processing unit 102A. The signal hardware 104A may include, for example, waveform generators, amplifiers, digitizers, high-frequency sources, DC sources, AC sources, etc. The signal hardware may include additional or different features and components. In the example shown, components of the signal hardware 104A are adapted to interact with the quantum processing unit 102 A. For example, the signal hardware 104A can be configured to operate in a particular frequency range, configured to generate and process signals in a particular format, or the hardware may be adapted in another manner.

[0051] In some instances, one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A. The control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A. For instance, the signal hardware 104A may generate signals to implement quantum logic operations, readout operations or other types of operations. As an example, the signal hardware 104A may include arbitrary waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radio-frequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices or other types of components in the quantum processing unit 102A.

[0052] In some instances, the signal hardware 104A receives and processes signals from the quantum processing unit 102A. The received signals can be generated by the execution of a quantum program on the quantum computing system 103A. For instance, the signal hardware 104A may receive signals from the devices in the quantum processing unit 102A in response to readout or other operations performed by the quantum processing unit 102A. Signals received from the quantum processing unit 102A can be mixed, digitized, filtered, or otherwise processed by the signal hardware 104A to extract information, and the information extracted can be provided to the controllers 106A or handled in another manner. In some examples, the signal hardware 104A may include a digitizer that digitizes electromagnetic waveforms (e.g., microwave or radio-frequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or to other signal hardware components. In some instances, the controllers 106A process the information from the signal hardware 104A and provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102A. [0053] In some implementations, the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102A. For example, the signal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers and other types of components. In some instances, the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A. In some instances, signal delivery hardware performs preprocessing, signal conditioning or other operations on readout signals received from the quantum processing unit 102A.

[0054] In some implementations, the signal hardware 104A includes a plurality of apparatuses connected by electrical cables. The apparatus is for communicating electrical signals in a cryogenic system of the quantum processing unit 102A. Each apparatus includes a metal plate and at least one circuit board. In some implementations, each of the at least one circuit board is a rigid circuit board, or at least rigid for the circuit board to avoid touching other components or each other during operation (e.g., cooling down and heating up of the cryostat]. The metal plate has a first surface on a first side and a second opposite surface on a second side. The metal plate includes slots which extend continuously from openings defined in the first surface to openings defined in the second surface. The circuit board extends through a slot of the metal plate such that a central portion of the circuit board resides in the slot; a first end portion resides outside the slot protruding from the first side of the metal plate; and a second end portion resides outside the slot protruding from the second side of the metal plate. The apparatus of the signal hardware 104A maybe implemented as the example apparatus 200, 300, 402 in FIGS. 2A- 2E, 3 and 4, or in another manner. The circuit board of the apparatus in the signal hardware 104A may be implemented as the example circuit board 202, 302, 500, 600, 704, 724, 734, 800, 900, 1002 in FIGS. 2A-2E, 3, 5A-5C, 6, 7A-7C, 8, 9, 10A-10C, or in another manner.

[0055] The example controllers 106A communicate with the signal hardware 104A to control operation of the quantum computing system 103A. The controllers 106A may include classical computing hardware that directly interface with components of the signal hardware 104A. The example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems. The classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array] or an ASIC (application specific integrated circuit), or other types of data processing apparatus. The memory may include any type of volatile or non-volatile memory or another type of computer storage medium. The controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels. The controllers 106A may include additional or different features and components.

[0056] In some implementations, the controllers 106A include memory or other components that store quantum state information, for example, based on qubit readout operations performed by the quantum computing system 103A. For instance, the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in or more of the controllers 106A. In some cases, the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.

[0057] In some implementations, the controllers 106A include memory or other components that store a quantum program containing quantum machine instructions for execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.

[0058] In some instances, the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes. For example, the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals. In some cases, the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a single execution of the quantum program, and a collection of bitsrings from multiple shots may be analyzed to compute quantum state probabilities.

[0059] In some implementations, the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above. For example, the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical/quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.

[0060] The other quantum computer system 103B and its components (e.g., the quantum processing unit 102B, the signal hardware 104B and controllers 106B) can be implemented as described above with respect to the quantum computer system 103A; in some cases, the quantum computer system 103B and its components may be implemented or may operate in another manner.

[0061] In some implementations, the quantum computer systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation. For example, the computer system 101 may include both an adiabatic quantum computer system and a gate-based quantum computer system. As another example, the computer system 101 may include a superconducting circuit-based quantum computer system and an ion trap-based quantum computer system. In such cases, the computer system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations. [0062] FIGS. 2A-2E are schematic diagrams showing a perspective view, an exploded view, and cross-sectional views (along an A-A’ plane) of an example apparatus 200. In some implementations, the example apparatus 200 is for communicating electrical signals through a flange (e.g., a vacuum plate, an isothermal plate, etc.) in a cryogenic system or another type of system, where large numbers of signals are required to be passed through a flange, for example, environmental chambers, vacuum chambers, etc. The example apparatus 200 includes a circuit board 202 and a metal plate 222. In some instances, the metal plate 222 is composed of materials with a high thermal conductivity (e.g., copper, etc.). In some implementations, the circuit board 202 is a printed circuit board, or another type of circuit board. The example apparatus 200 may include additional or different features, and the components of an example apparatus 200 may operate as described with respect to FIGS. 2A-2E or in another manner.

[0063] As shown in FIGS. 2A-2E, the metal plate 222 has a first surface 230 on a first side of the metal plate 222 and a second opposite surface 232 on a second side of the metal plate 222. The metal plate 222 includes slots 226 which extend continuously from openings defined in the first surface 230 to openings defined in the second surface 232. When the circuit board 202 is assembled on the metal plate 222, the circuit board 202 extends through a slot 226 of the metal plate 222 such that a central portion of the circuit board 202 resides in the slot 226; a first end portion resides outside the slot 226 protruding from the first side of the metal plate 222; and a second end portion resides outside the slot 226 protruding from the second side of the metal plate 222. The circuit board 202 can be secured on the metal plate 222 by a clamp assembly 224 or other fasteners.

[0064] In some implementations, the first end portion of the circuit board 202 includes electrical connectors 206A that are configured to interface with one or more first electrical cables 204A on the first side of the metal plate 222; and the second end portion of the circuit board 202 includes electrical connectors 206B that are configured to interface with one or more second electrical cables 204B on the second side of the metal plate 222. In some instances, the firstand second electrical cables 204A, 204B and the electrical connectors 206A, 206B can be secured to the circuit board 202 with respective retaining clips 214A, 214B (e.g., strain-relief clips or other types ofclips). In some implementations, the retaining clips 214A, 214B are in-plane with the circuit board 202; and are configured to secure the electrical connectors 214A, 214B and the electrical cables 204A, 204B to the circuit board 202 and to ensure that the tensile and bending forces occur on the electrical cables 204A, 204B are absorbed by the retaining clips 214A, 214B; and thus, reduce the forces applied by the electrical cables 204A, 204B to the electrical connectors 214A, 214B, and prevent the electrical cables 204A, 204B from getting electrically disconnected from the electrical connectors 214A, 214B, for example, during cooling down or temperature cycling in a cryostat. In some instances, the retaining clips 214A, 214B are configured to reduce or minimize thermal coefficient mismatch between the electrical cables 204A, 204B and the circuit board 202. In some instances, the retaining clips 214A, 214B may be implemented as the retaining clips 1010 shown in FIGS. 10A-10C.

[0065] In some instances, the retaining clips 214A, 214B may be placed out of the plane of the circuit board 202 and may be configured according to the shape, type, geometry, or other properties of the electrical cables 204A, 204B. In some implementations, the retaining clips 214A, 214B are rigid with respect to the circuit board 202. For example, the retaining clip 214A, 214B are made of rigid material, such as metal, to secure the electrical cables 204A, 204B in place on the circuit board 202 to help distribute the force of the electrical cables 204A, 204B evenly across the circuit board and to prevent the electrical cable from being damaged. In some instances, the retaining clips 214A, 214B may be mounted to the circuit board 202 using springs, screws, adhesives, or through another mounting mechanism. Such mounting mechanism of the retaining clips 214A, 214B on the circuit board is strong enough to allow the retaining clips 214A, 214B to maintain rigidly positioned with respect to the circuit board 202.

[0066] In some implementations, the electrical connectors 206A, 206B are configured to interface with flat circuit cables, flat printed circuit cables or other type of flex cables. In some instances, the electrical connectors 206A, 206B may be flat circuit connectors or other types of electrical connectors. As shown in FIG. 2B, the circuit board 202 includes board level connectors 218 configured to provide electrical connection between the electrical connectors 206A to the electrical circuitry of the circuit board 202. In some instances, the first and second electrical cables 204A, 204B and the respective board-level connectors 218 are configured to provide thermal isolation between isothermal plates with different temperatures.

[0067] In some implementations, the electrical cables 204A, 204B are flex cables. For example, each of the electrical cables 204A, 204B may include a stack of multiple metallization layers as electrical ground layers and signal layers, which can be separated by insulating materials. In some instances, the electrical cables 204A, 204B include electrically and thermally conductive vias to connect electrical ground layers at different levels. In some instances, the electrically and thermally conductive vias may be arranged in an array through the insulating materials and between signal lines in order to shield electromagnetic signals transmitted on signal lines.

[0068] In some implementations, the circuit board 202 includes electrical circuitry configured to communicate electrical signals between the electrical connectors 206A on the first end portion of the circuit board 202 and the electrical connectors 206B on the second end portion of the circuit board 202. In some implementations, the electrical circuitry includes signal lines (e.g., the signal lines 508 in the circuit board 500 of FIG. 5B) extending from the first end portion, through the central portion, into the second end portion of the circuit board 202. In some instances, the signal lines may be planar transmission lines, for example coplanar waveguides, substrate integrated waveguides or another type of planar transmission lines. As shown in the cross-sectional view of the example apparatus 200 along the A-A’ plane in FIG. 2D, the electrical circuitry of the circuit board 202 includes circuit elements 250 (e.g., the circuit elements 708 of FIGS. 7A-7C). The circuit elements 250 may be mounted on or in the circuit board 202 connected to at least a subset of the signal lines of the circuit board 202. In some implementations, the circuit elements include one or more passive and/or active radio frequency (RE) circuit devices, e.g., filters, attenuators, amplifiers, and other types of circuit elements for signal conditioning and/or processing. In some implementations, the circuit board 202 is a multilayered circuit board comprising a stack of metallization layers (e.g., the signa layer 244 and the electrical ground layer 246). Each of the metallization layers includes a respective portion of the electrical circuitry. For example, each of the metallization layers includes signal lines and circuit elements configured to communicate or process electrical signals between a subset of the electrical connectors 206A on the first end portion and a subset of the electrical connectors 206B on the second end portion.

[0069] In some instances, the metal plate 222 is configured to mate with a flange (e.g., the thermal stages 404 and the vacuum plate 406 in the cryogenic system 400 in FIG. 4), or another type of flange in another type of system. As shown in FIG. 2A, the metal plates 222 further includes holes 228 which are configured to align with respective holes on a flange to receive screws in order to allow secured assembly of the metal plate 222 to the flange. As shown in the cross-sectional view of the example apparatus 200 along the A- A’ plane in FIG. 2E, when the apparatus 200 resides on a vacuum plate (e.g., the vacuum plate 406 in FIG. 4), the apparatus 200 includes a seal 260 (e.g., epoxy, o-ring, etc.) between the circuit board 202 and the metal plate 222, which is configured to provide vacuum isolation between the first and second sides 230, 232 of the metal plate 222, e.g., on a vacuum flange with one side under room temperature and pressure and the other side under vacuum. When the apparatus 200 resides on an isothermal plate, the circuit board 202 is thermalized to the metal plate 222 and further to the isothermal plate so that the circuit board 202 does not transmit heat radiation between thermal stages in the cryogenic system through the signal lines and other material of the circuit board 202.

[0070] In some implementations, the clamp assembly 224 includes rails 208A, 208B and braces 210A, 210B, which is configured to mechanically secure the circuit board 202 on the metal plate 222 through the slot 226 and provide thermal connection between the circuit bord 202 and the metal plate 222. When assembled with the circuit board 202 and the metal plate 222, the rails 208A, 208B are in contact with the circuit board 202 and the rails 208A, 208B are secured on the first surface 230 of the metal plate 222 by the braces 210A, 210B. In some instances, the circuit board 202 may include thermally conductive cladding on its external surfaces and when assembled on the metal plate 222, the thermally conductive cladding of the circuit board 202 is thermally connected to the metal plate 222. In some implementations, the thermally conductive cladding of the circuit board 202 is thermally connected to the metal plate 222 through the clamp assembly 224. The circuit board 202 includes retention tabs 216, which, together with the rails 208A, 208B is held between the braces 210A, 210B to maintain a light-tight connection to the metal plate 222 with good thermal conduction. As shown in FIGS. 2A and 2D, the rails 208A, 208B and the circuit board 202 include holes 212 for receiving screws or other types of fasteners.

[0071] As shown in FIG. 20, the circuit board 202 is a multi-layered circuit board which includes nine metallization layers. The nine metallization layers include five electrical ground layers 246 and four signal layers 244. Each signal layer 244 is sandwiched between two neighboring electrical ground layer 246 and the electrical ground layers 246 are in between two neighboring signal layers 244 and on the external surfaces of the circuit board 202. The electrical ground layers 246 are configured to shield the signals from each other, including in the blind vias to the inner layers. The electrical ground layer 246 on the external surfaces of the circuit board 202 is used to reduce external radiation entering the circuit board 202. The board-level connectors 218 include IR (infra-red) absorbing material 248 around the connections to reduce external radiation entering the circuit board 202.

[0072] FIG. 3 is a schematic diagram showing a perspective view of an example apparatus 300. As shown in FIG. 3, the example apparatus 300 includes ten circuit boards 302 and a metal plate 304. The example apparatus 300 provides a high density of signals through the metal plate 304 and communication signal pathways between electrical cables 306 from one side of the metal plate to another side of the metal plate 304. The metal plate 304 includes ten slots. The metal plate 304 may be implemented as the metal plate 222 in FIGS. 2A, 2C, 2D, or in another manner. Each of the circuit board 302 may be implemented as the circuit board 202 in FIGS. 2A-2E or in another manner. Each of the circuit board 302 may be assembled with the metal plate 304 in the manner shown in FIGS. 2A-2E or in another manner. The example apparatus 300 may include additional or different features, and the components of an example apparatus may operate as described with respect to FIG. 3 or in another manner.

[0073] FIG. 4 is a schematic diagram showing a perspective view of an example cryogenic system 400. The example cryogenic system 400 includes five isothermal plates 404 and a vacuum plate 406. The example cryogenic system 400 includes six apparatuses 402 which are secured on the respective isothermal plate 404 and the vacuum plate 406 and are connected to one another through electrical cables 408. Each of the five apparatus 402 may be implemented as the example apparatus 200, 1000 in FIGS. 2A-2E, 10A-10C, or in another manner. In some implementations, the apparatuses 402 and the electrical cables 408 are configured for communicating electrical signals from the atmospheric environment to a quantum processing unit 410 or other type of device residing at a lowest-temperature isothermal stage. The example cryogenic system 400 may include additional or different features, and the components of an example cryogenic system may operate as described with respect to FIG. 4 or in another manner.

[0074] In some implementations, the example cryogenic system 400 may be used to expose devices and samples to environments of very low temperature (e.g., T < 120 K). In some implementations, such environments are thermally isolated through insulating walls and are evacuated, typically having a pressure in the range of IO’³ mbar to IO'⁹ mbar, thereby allowing the example cryogenic system 400 to operate at stable temperatures without appreciable thermal losses.

[0075] In some implementations, the thermal stages 404A, 404B, 404C, 404D, 404E may correspond to radiation shields, isothermal plates, or both. In some instances, a thermal stage 404 in the cryogenic system 400 may be formed of a material having a high thermal conductivity at cryogenic temperatures, such as below 120 K. For example, a thermal stage 404 may be formed of a material having a thermal conductivity of at least 1 W/(m-K) as measured at 4 K. In some examples, a high thermal conductivity allows the thermal stage 404 to mitigate the development of temperature gradients, thereby maintaining a substantially uniform temperature across their respective masses. In some implementations, such material in a thermal stage 404 may include oxygen-free high conductivity copper and its alloys, including a C101 copper alloy or a beryllium-copper alloy (e.g., Cu with 0.5 - 3% Be) or another type of alloy.

[0076] In some instances, the cryogenic system 400 may include any number of thermal stages 404 to support subsystems, devices, and samples for cryogenic refrigeration. As a result, the cryogenic system 400 may position the thermal stages 404 to define a spatial sequence of thermal stages, such as in a linear sequence or an angular sequence. FIG. 4 depicts four thermal stages 404 in an equally spaced linear sequence. In some implementations, the cryogenic system 400 may include any number and spacing of thermal stages 404 as needed. In the example shown in FIG. 4, the cryogenic system 400 includes one or more structural supports 414 to position the thermal stages 404 into the spatial sequence of thermal stages. In some examples, the structural supports 414 may be formed of a material having a low thermal conductivity at cryogenic temperatures, e.g., less than 0.5 W/(m-K) at or below 50 K, such as a stainless-steel alloy or a glass-epoxy laminate of G10 grade. In this case, the structural supports 414 thus additionally impede a flow of heat between the thermal stages 404. As such, the cryogenic system 400 may include one or more thermal stages 404 dedicated to a specific temperature during operation. For example, the cryogenic system 400 may be configured such that each thermal stage 404 operates at a progressively decreasing temperature as a depth of the cryogenic system 400 increases.

[0077] In some implementations, the cryogenic system 400 may also include one or more refrigeration systems (not shown] thermally coupled to each of the thermal stages 404. For example, the cryogenic system 400 may include a pulse-tube refrigeration system coupled to a second lowest-temperature thermal stage 404E and a ³He/⁴He dilution refrigerator system thermally coupled to a lowest-temperature thermal stage (e.g., with quantum processing unit 410). The cryogenic system 400 establish specific operating temperatures for the thermal stages 404 to which they are respectively thermally coupled. In some implementations, the cryogenic system 400 may define a distribution of operating temperatures along the spatial sequence of thermal stages 404. In some implementations, a pulse-tube refrigeration unit may be configured to optimally extract heat at temperatures to about 4 K and a ³He/⁴He dilution refrigerator unit may be configured to optimally extract heat at temperatures below 1 K.

[0078] In the example shown in FIG. 4, the quantum processing unit 410 is configured on the lowest-temperature thermal stage of the cryogenic system 400. In some implementations, the quantum processing unit 410 may receive and transmit signals via apparatuses 402 and electrical cables 408. The apparatuses 402 can transmit control signals to the quantum processing unit 410, and readout signals out of the cryogenic system 400. In some instances, the signals communicated on the apparatuses 402 and the electrical cables 408 are microwave or radio-frequency frequency signals. [0079] As shown in FIG. 4, the apparatuses 402 in the cryogenic system 400 are configured separately from the structural supports 414 and the thermal stages 404. In certain instances, the apparatuses 402 may be arranged or routed in another manner. The electrical cables 408 are thermally isolating to suppress heat dissipation between thermal stages 404 through signal lines and material of the circuit board.

[0080] In some implementations, an apparatus 402 includes at least one circuit board and a metal plate. The apparatus 402 may be implemented as the example apparatus 200 in FIGS. 2A-2E or in another manner. The apparatuses 402 on neighboring thermal stages 404 are communicably coupled to one another through at least one electrical cable 408. A vacuum plate 406 supports an apparatus 402, which communicates with a control system (e.g., the control system 150 in FIG. 1) out of the cryogenic system 400. In this case, the apparatus 402 on the vacuum plate 406 includes a seal (e.g., epoxy, o-ring, etc.) between the circuit board of the apparatus 402 and the metal plate of the apparatus 402 and a seal between the metal plate of the apparatus 402 and the vacuum plate 406. In some instances, the seals are configured to provide vacuum isolation between the first and second sides of the vacuum plate 406.

[0081] As shown in FIG. 4, circuit boards of the apparatus 402 extend continuously through slots defined in respective metal plates. In some implementations, circuit boards are thermalized by the respective metal plates and further to the thermal stages. In other words, heat generated in the circuit boards can be dissipated to the thermal stages. For example, the circuit boards contains thermally conductive cladding on their external surfaces (e.g., the thermally conductive cladding 612 on the circuit board 600 as shown in FIG. 6). The thermally conductive cladding on the external surfaces of the circuit board are thermally connected to the respective thermal stages 404. In some implementations, the circuit board may be implemented as the circuit board 202, 302, 500, 600, 704, 724, 734, 800 shown in FIGS. 2A-2E, 3, 5A-5C, 6, 7A-7C, 8, or in another manner.

[0082] In some instances, the circuit boards of the apparatuses 402 and electrical cables 408 include electrical ground layers, which are galvanically connected together. The circuit board of the apparatuses 402 and the electrical cables 408 include signal lines, which are also galvanically connected together. [0083] In some implementations, the quantum processing unit 410 includes a superconducting QulC. In certain instances, the superconducting QulC of the quantum processing unit 410 includes quantum circuit devices, such as qubit devices (e.g., transmon devices, fluxonium devices, or other types of superconducting qubit devices), coupler devices, readout resonators, or other types of quantum circuit devices that are used for quantum information processing in the quantum processing unit 410. In some examples, each of the qubit devices in a quantum processing unit 410 can be encoded with a single bit of quantum information. The quantum circuit devices may include one or more Josephson junctions, capacitors, inductors, and other types of circuit elements.

[0084] In some implementations, the superconducting QulC on the quantum processing unit 410 may further include a variety of circuit elements to control or readout the qubit devices of the quantum processing unit 410. For example, the superconducting QulC may include flux bias lines which can provide magnetic flux locally to tunable-frequency qubit devices to tune their frequencies. The superconducting QulC may include tunable coupler devices, microwave feedlines, and resonator devices to readout qubits. In some examples, the superconducting QulC may include microwave feedlines which are coupled to one or several of the resonator devices quantum processing unit 410 to allow microwave excitation of the resonator devices used to readout qubits. In this case, the superconducting QulC may include microwave drive lines which are capacitively coupled to qubit devices to drive qubits.

[0085] Typically, each of the qubit devices has two eigenstates that are used as computational basis states (e.g., |0) and 11)), and each qubit device can transition between its computational basis states or exist in an arbitrary superposition of its computational basis states. In some examples, the two lowest energy levels (e.g., the ground state and first excited state) of each qubit device are defined as a qubit and used as computational basis states for quantum computation. In some examples, higher energy levels (e.g., a second excited state or a third excited state) can be used to define a qubit, a qutrit, or a multi-level quantum computational device in some instances. Quantum states (e.g., qubits) defined by respective qubit devices can be manipulated by control signals, or read by readout signals, generated by a control system, e.g., the control system 105 in FIG. 1. The qubit devices can be controlled individually, for example, by delivering control signals from a control system to the respective qubit devices. In some cases, readout devices can detect the states of the qubit devices, for example, by interacting directly with the respective qubit devices.

[0086] The superconducting QulC in the quantum processing unit 410 shown in FIG. 4 is fabricated on a substrate. In certain instances, the substrate supporting the superconducting QulC may be an elemental semiconductor, for example silicon (Si), germanium [Ge], selenium (Se), tellurium (Te), or another elemental semiconductor. In some instances, the substrate may also include a compound semiconductor such as aluminum oxide (sapphire), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), gallium indium phosphide (GalnP), or another compound semiconductor. In some instances, the substrate may also include a superlattice with elemental or compound semiconductor layers. In certain instances, the substrate includes an epitaxial layer. In some examples, the substrate may have an epitaxial layer overlying a bulk semiconductor or may include a semiconductor-on-insulator (SOI) structure.

[0087] The superconducting quantum circuit may include superconductive materials and can be formed by patterning one or more superconductive (e.g. superconducting metal) layers or other materials. In some implementations, each of the one or more superconductive layers include a superconducting metal, such as aluminum (Al), niobium (Nb), tantalum (Ta), ttanium (Ti), vanadium (V), tungsten (W), zirconium (Zr), or another superconducting metal. In some implementations, each of the one or more superconductive layers may include a superconducting metal alloy, such as molybdenum-rhenium (Mo/Re), niobium-tin (Nb/Sn), or another superconducting metal alloy. In some implementations, each of the superconductive layers may include a superconducting compound material, including superconducting metal nitrides and superconducting metal oxides, such as titanium-nitride (TiN), niobium-nitride (NbN), zirconium-nitride (ZrN), hafnium-nitride (HfN), vanadium-nitride (VN), tantalum-nitride (TaN), molybdenum-nitride (MoN), yttrium barium copper oxide (Y-Ba-Cu-O), or another superconducting compound material. In some instances, the superconducting quantum circuit may include multilayer superconductor-insulator heterostructures. [0088] In some implementations, the superconducting quantum circuit is fabricated on the top surface of a substrate and patterned using a microfabrication process or in another manner. For example, quantum circuit devices in a superconducting QulC may be formed by performing at least some of the following fabrication steps: using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, and / or other suitable techniques to deposit respective superconducting layers on the substrate; and performing one or more patterning processes (e.g., a lithography process, a dry/wet etching process, a soft/hard baking process, a cleaning process, etc.) to form openings in the respective superconducting layers.

[0089] In some implementations, a subset of the one or more electrically conductive vias are electrically coupled with electrical cables from the apparatus 402 on the second lowest-temperature thermal stage 404E, which are used to supply control signals to, or retrieve readout signals from, the quantum processing unit 410. For example, the control signals can be provided to the quantum processing unit 410 from a control system (e.g., the control system 105 in FIG. 1) or the readout signals can be retrieved from the quantum processing unit 410 to the control system through the apparatuses 402 and electrical cables 408.

[0090] In some implementations, the quantum processing unit 410 includes multiple quantum processor modules each comprising qubit devices and other quantum circuit devices in a range of 40 to 100 or more qubit devices and the quantum processing unit 410 may include in the range of 16 to 100 or more quantum processor modules. Consequently, the quantum processing units 410 can operate up to ~ 10,000 or more qubit devices. The apparatuses 402 and the electrical cables 408 with a high density of signal lines (e.g., in a range of greater than or equal to 0.2 signals /mm² or another range) can be used for communicating electrical signals (e.g., control signals and readout signals) between the quantum circuit devices of the quantum processing unit 410 in the cryogenic system 400 with a control system outside of the cryogenic system 400. In some instances, the apparatuses 402 can be used for communicating electrical signals with other types of devices in the cryogenic system 400. [0091] FIGS. 5A-5C are schematic diagrams showing a perspective view, an exploded view, and a cross-sectional view of an example circuit board 500. The example circuit board 500 may be supported by a metal plate which can be mounted on a flange in a cryogenic system for communicating electrical signals through the flange. The circuit board 500 allows for high-density RF- and DC-signals passing through a flange. For example, aassuming a signal-signal trace spacings of 1 mm and approximately 6 mm spacing between circuit boards on a metal plate, the specific area of the signals can be in a range of 6 mm and below. The example circuit board 500 can be implemented as the circuit board in the example apparatus 200, 300, 402 in FIGS. 2A-2E, 3, 4, or in another manner.

[0092] As shown in FIGS. 5A-5C, the circuit board 500 is a multilayered circuit board with multiple metallization layers 502A, 502B, 502C separated by two insulating layers 504A, 504B. In particular, a first metallization layer 502A is an electrical ground layer residing on a first surface of the circuit board 500; a second metallization layer 502B is also an electrical ground layer residing on a second opposite surface of the circuit board 500; and a third metallization layer 502C is a signal layer. The example circuit board 500 may include additional or different features, and the components of an example circuit board 500 may operate as described with respect to FIGS. 5A-5C or in another manner. For example, the circuit board 500 may include more than three metallization layers 502 separated by more than two insulating layers 504 forming alternating ground/signal/ground layers.

[0093] As shown in FIGS. 5A-5C, the circuit board 500 further includes an array of electrically and thermally conductive through hole vias 506 extending from openings on the first surface to the openings on the second surface. The electrically and thermally conductive through-hole vias 506 are configured to galvanically couple the first and the second metallization layers 502A, 502B. The conductive through-hole vias 506 connecting the first and second metallization layers (e.g., the electrical ground layers) 502A, 502B reside between signal lines 508 in the third metallization layer 508C allowing for improved thermal conduction between the two electrical ground layers and for shielding electromagnetic signals between signal lines. [0094] As shown in FIG. 5B, the third metallization layer 502C includes signal lines 508 or other circuit elements. In some instances, the signal lines 508 may include impedance- matched lines for RF signals, low resistance lines for DC signals, or other types of signal lines.

[0095] In some instances, the circuit board 500 includes electrical connectors configured to interface with electrical cables (e.g., coaxial cables, flex cables or other types of electrical cables). When the circuit board 500 is connected to electrical cables through the electrical connectors, the first and second metallization layer 502A, 502B are galvanically connected to electrical ground of the electrical cables. In some instances, the first and second metallization layers 502A, 502B have a thickness that does not significantly increase the electrical resistance and meanwhile, does not significantly increase the thermal conductance of the metallization layers.

[0096] In some implementations, the metallization layers 502A, 502B, 502C, electrically and thermally conductive through-hole vias 506, and signal lines 508 include superconducting material to allow for low electrical resistance operations of the signal and ground layers at cryogenic environment without significantly increasing the thermal conductance. For example, the metallization layers 502A, 502B, 502C, electrically and thermally conductive through-hole vias 506, and signal lines 508 may be fabricated, plated with one or more superconducting layers, or in another manner.

[0097] In some implementations, the insulating layers 504A, 504B between the metallization layers 502A, 502B, 502C include IR absorbing material that does not allow radiation to pass through it. In some instances, the insulating layers 504A, 504B with the IR absorbing material can suppress transmission of stray radiation through the bulk of the circuit board 500. The insulating layers 504A, 504B are configured to shield at low and high frequencies, suppress noise in the near field range, or provide other functions. For example, the insulating layers 504A, 504B may include microwave absorbing elastomers and films, micro wave absorbing gap fillers made of hybrid absorbers, microwave absorbing thermoplastics, or other types of IR and microwave absorbing material. [0098] FIG. 6 is a schematic diagram showing a perspective view of an example circuit board 600. The example circuit board 600 may be supported by a metal plate which can be mounted on a flange in a cryogenic system for communicating electrical signals through the flange. The example circuit board 500 can be implemented as the circuit boards in FIGS. 2A-2E, 3, 4, 5, or in another manner. Outer surfaces of the example circuit board 600, including first and second surfaces 602, 604 and sidewalls 606, are coated with a thermally conductive cladding 612 to suppress radiation entering the circuit board 600 from a flange with a higher temperature or exiting the circuit board 600 to a flange with a lower temperature. In some implementations, the thermally conductive cladding 612 is formed of a material having a high thermal conductivity at cryogenic temperatures, such as copper, or other materials with a high thermal conductivity. The example circuit board 600 may include additional or different features, and the components of an example circuit board 600 may operate as described with respect to FIG. 6 or in another manner.

[0099] FIGS. 7A-7C are schematic diagrams showing top and side views of example assemblies 700, 720, 730. The example assemblies 700, 720, 730 include example circuit boards with signal lines and circuit elements connected to electrical cables. The example circuit boards 704, 724, 734 each may be supported by a metal plate which can be mounted on a flange in a cryogenic system for communicating electrical signals through the flange. The example circuit board 704, 724, 734 can be implemented as the circuit boards in FIGS. 2A-2E, 3, 4, 5, 6 or in another manner. The example assemblies 700, 720, 730 may include additional or different features, and the components of the example assemblies 700, 720, 730 may operate as described with respect to FIGS. 7A-7C or in another manner.

[00100] As shown in FIG. 7A, the circuit board 704 in the example assembly 700 includes a single signal layer 710. In some instances, the circuit board 704 may further include electrical ground layers e.g., 502A, 502B as shown in FIG. 5A). The signal layer 710 includes signal lines 706 and circuit elements 708. The signal lines are galvanically connected to signal lines 712 in the electrical cables 702A, 702B through respective conductive vias 714 in the circuit board 704.

[00101] As shown in FIG. 7B, the circuit board 724 in the example assembly 720 includes a single signal layer 710. In some instances, the circuit board 724 may further include electrical ground layers (e.g., 502A, 502B as shown in FIG. 5A). The signal layer 710 includes signal lines 706 and circuit elements 708. The signal lines 706 defined in the signal layer 710 in the circuit board 724 are galvanically connected to signal lines 712 in the electrical cables 722-1A, 722-1B, 722-2A, 722-2B, 722-3A, 722-3B through respective conductive vias 714 in the circuit board 704.

[00102] As shown in FIG. 7C, the circuit board 734 in the example assembly 720 includes multiple signal layers 736A, 736B, 736C. In some instances, the circuit board 734 may further include electrical ground layers (e.g., 246 as shown in FIG. 2D). Each of the signal layers 736A, 736B, 736C includes signal lines 706 and circuit elements 708. The signal lines 706 defined in the signal layers 736A, 736B, 736C in the circuit board 734 are galvanically connected to respective signal lines 712 in the electrical cables 732-1A, 732-1B, 732-2A, 732-2B, 732-3A, 732-3B through respective conductive vias 738-1, 738-2, 738-3 in the circuit board 734.

[00103] FIG. 8 includes schematic diagrams showing top view and side views of an example circuit board 800. The example circuit board 800 can be implemented as the circuit board 202 in the example apparatus 200 in FIGS. 2A-2E or in another manner. In some implementations, the electrical connectors 802A on the first end of the circuit board 800 are coaxial cable connectors that are configured to interface with a first plurality of coaxial cables; and the electrical connectors 802B on the second opposite end of the circuit board 800 are coaxial cable connectors that are configured to interface with a second plurality of coaxial cables. The example circuit board 800 may include additional or different features, and the components of an example circuit board 800 may operate as described with respect to FIG. 8 or in another manner.

[00104] FIG. 9 is a schematic diagram showing a perspective view of an example circuit board 900. The example circuit board 900 can be implemented as the circuit board 202 in the example apparatus 200 in FIGS. 2A-2E or in another manner. In some implementations, the electrical connectors 902A on the first end of the circuit board 900 are D-subshell connectors that are configured to interface with a first plurality of electrical wires connectorized with mating D-subshell connectors; and the electrical connectors 902B on the second opposite end of the circuit board 900 are D-subshell connectors that are configured to interface with a second plurality of electrical wires connectorized with mating D-subshell connectors. The example circuit board 900 may include additional or different features, and the components of an example circuit board 900 may operate as described with respect to FIG. 9 or in another manner.

[00105] FIGS. 10A-10C are schematic diagrams showing perspective views and an exploded view of an example apparatus 1000. In some implementations, the example apparatus 1000 is for communicating electrical signals through a flange (e.g., a vacuum plate, an isothermal plate, etc.) in a cryogenic system or another type of system, where large numbers of signals are required to be passed through a flange, for example, environmental chambers, vacuum chambers, etc. The example apparatus 1000 includes a circuit board 1002 and a metal plate 1022. In some instances, the metal plate 1022 is composed of materials with a high thermal conductivity (e.g., copper, etc.). In some implementations, the circuit board 1002 is a printed circuit board, or another type of circuit board. The example apparatus 1000 may include additional or different features, and the components of an example apparatus 1000 may operate as described with respect to FIGS. 10A-10C or in another manner.

[00106] As shown in FIGS. 10A-10C, the metal plate 1022 has a first surface 1030 on a first side of the metal plate 1022 and a second opposite surface 1032 on a second side of the metal plate 1022. The metal plate 1022 includes slots 1026 which extend continuously from openings defined in the first surface 1030 to openings defined in the second surface 1032. When the circuit board 1002 is assembled on the metal plate 1022, the circuit board 1002 extends through a slot 1026 of the metal plate 1022 such that a central portion of the circuit board 1002 resides in the slot 1026; a first end portion resides outside the slot 1026 protruding from the first side of the metal plate 1022; and a second end portion resides outside the slot 1026 protruding from the second side of the metal plate 1022. The circuit board 1002 can be secured on the metal plate 1022 by a clamp assembly 1024 or other fasteners.

[00107] As shown in FIGS. 10A-10C, the circuit board 1002 includes four fingers 1040 on the first and second end portions for receiving the respective retaining clips 1010. In some instances, the first and second electrical cables 1004A, 1004B can be secured to the circuit board 1002 by sliding the respective retaining clips 1010 (e.g., strain-relief clips or other types of clips) onto the respective fingers 1040 of the circuit board 1002. In some implementations, the retaining clips 1010 are in-plane with the circuit board 1002; and are configured to secure the electrical cables 1004A, 1004B to the circuit board 1002 and to ensure the tensile and bending forces that occur on the electrical cables 1004A, 1004B are absorbed by the retaining clips 1010. In some instances, the retaining clips 1010 are configured to reduce or minimize thermal coefficient mismatch between the electrical cables 1004A, 1004B and the circuit board 1002. In some instances, the electrical cables 1004 are aligned with the circuit board 1002 such that electrical contacts on the electrical cable 1004 are aligned with board-level connectors 1018 on the circuit board 1002 by aligning alignment pins 1034 on the circuit board 1002 into alignment holes 1036 on the electrical cable 1036. In some instances, the circuit board 1002 may include more fingers 1040 for connecting to more electrical cables 1004; and each electrical cable 1004 may include more than two alignment holes 1036.

[00108] As shown in FIG. 10C, the circuit board 1002 includes board level connectors 1018 configured to provide electrical connection between the electrical contact on the electrical cable 1004 to the electrical circuitry of the circuit board 1002. In some instances, the first and second electrical cables 1004A, 1004B and the respective board-level connectors 1018 are configured to provide thermal isolation between isothermal plates with different temperatures.

[00109] In some implementations, the electrical cables 1004A, 1004B are flex cables and may be implemented as the electrical cable 204A, 204B as shown in FIGS. 2A-3D or in another manner. In some implementations, the circuit board 1002 includes electrical circuitry configured to communicate electrical signals between a pair of electrical cables 1004A, 1004B; and maybe implemented as the circuit board 202 in FIGS. 2A-2E or in another manner.

[00110] In some instances, the metal plate 1022 is configured to mate with a flange (e.g., the thermal stages 404 and the vacuum plate 406 in the cryogenic system 400 in FIG. 4), or another type of flange in another type of system. In certain instances, the metal plate 1022 may be implemented as the metal plate 222 shown in FIGS. 2A-2E or in another manner. [00111] In some implementations, the clamp assembly 1024 includes rails 1008, which are configured to mechanically secure the circuit board 1002 on the metal plate 1022 through the slot 1026 and provide thermal connection between the circuit board 1002 and the metal plate 1022. In some instances, the clamp assembly 1024 may be implanted as the clamp assembly 224 in FIGS. 2A-2E or in another manner. When assembled with the circuit board 1002 and the metal plate 1022, the rails 1008 are in contact with the circuit board 1002 and the rails 1008 are secured on the first surface 1030 of the metal platel022. In some instances, the circuit board 1002 may include thermally conductive cladding on its external surfaces and when assembled on the metal plate 1022, the thermally conductive cladding of the circuit board 1002 is thermally connected to the metal plate 1022. In some implementations, the thermally conductive cladding of the circuit board 1002 is thermally connected to the metal plate 1022 through the clamp assembly 1024.

[00112] In a general aspect, an apparatus is formed and operated for communicating electrical signals through a flange in a cryogenic system.

[00113] In a first example, an apparatus operated for communicating electrical signals through a flange in a cryogenic system includes a metal plate mate with the flange and a circuit board secured to the metal plate. The metal plate includes a first surface on a first side of the metal plate; a second surface on a second, opposite side of the metal plate; and a slot that extends through the metal plate from a first opening defined in the first surface to a second opening defined in the second surface. The circuit board includes a central portion residing in the slot; a first end portion residing outside the slot and protruding from the first side of the metal plate; and a second end portion residing outside the slot and protruding from the second side of the metal plate, the first end portion including a first plurality of electrical connectors that are configured to interface with one or more first cables; and the second end portion comprising a second plurality of electrical connectors that are configured to interface with one or more second cables. The circuit board further includes electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors. The electrical circuitry includes signal lines. At least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion. [00114] Implementations of the first example may include one or more of the following features. The metal plate includes a plurality of slots that each extend through the metal plate from a respective first opening defined in the first surface to a respective second opening defined in the second surface. The apparatus includes a plurality of circuit boards secured to the metal plate, each circuit board extending through a respective one of the plurality of slots. Each circuit board includes a central portion residing in a respective slot; a first end portion residing outside the respective slot and protruding from the first side of the metal plate; and a second end portion residing outside the respective slot and protruding from the second side of the metal plate. The first end portion includes a first plurality of electrical connectors that are configured to interface with one or more first cables; and the second end portion includes a second plurality of electrical connectors that are configured to interface with one or more second cables. The circuit board further includes electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors. The electrical circuitry includes signal lines. At least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion.

[00115] Implementations of the first example may include one or more of the following features. The first plurality of electrical connectors includes a first plurality of coaxial cable connectors that are configured to interface with a first plurality of coaxial cables; and the second plurality of electrical connectors includes a second plurality of coaxial cable connectors that are configured to interface with a second plurality of coaxial cables. The first plurality of electrical connectors are first D-subshell connectors configured to interface with a first plurality of electrical wires; and the second plurality of electrical connectors are second D-subshell connectors to interface with a second plurality of electrical wires. The apparatus includes strain-relief clips configured to secure electrical cables to the first and second plurality of electrical connectors.

[00116] Implementations of the first example may include one or more of the following features. The first plurality of electrical connectors is configured to interface with a first flex cable; and the second plurality of electrical connectors are configured to interface with a second flex cable. The electrical circuitry includes a plurality of circuit elements connected to at least a subset of the signal lines, and the plurality of circuit elements includes one or more radio frequency filters. The circuit board is a multi-layered circuit board including a stack of metallization layers; and each metallization layer includes a respective portion of the electrical circuitry. The apparatus includes a seal between the circuit board and the metal plate; and the seal provides vacuum isolation between the first and second sides of the metal plate.

[00117] Implementations of the first example may include one or more of the following features. The circuit board includes thermally conductive cladding on a first surface and a second opposite surface of the circuit board; and the thermally conductive cladding is thermally connected to the metal plate. The apparatus includes a clamp assembly that secures the circuit board to the metal plate and provides thermal connectivity between the circuit board and the metal plate. The clamp assembly includes rails that reside in thermal contact with the thermally conductive cladding and the first surface of the metal plate. The clamp assembly further includes braces that secure the rails to the metal plate.

[00118] In a second example, a cryogenic system includes a plurality of isothermal plates; and the apparatus of the first example mated to one of the isothermal plates and configured to communicate electrical signals through the isothermal plate.

[00119] In a third example, an apparatus operated for communicating electrical signals includes a metal plate and a circuit board secured to the metal plate. The metal plate includes a first surface on a first side of the metal plate; a second surface on a second, opposite side of the metal plate; and a slot that extends through the metal plate from a first opening defined in the first surface to a second opening defined in the second surface. The circuit board includes a central portion residing in the slot; a first end portion residing outside the slot and protruding from the first side of the metal plate; and a second end portion residing outside the slot and protruding from the second side of the metal plate, the first end portion including a first plurality of electrical connectors that are configured to interface with one or more first cables; and the second end portion comprising a second plurality of electrical connectors that are configured to interface with one or more second cables. The circuit board further includes electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors. The electrical circuitry includes signal lines. At least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion.

[00120] In a fourth example, an assembly method includes obtaining a metal plate. The metal plate includes: a first surface on a first side of the metal plate; a second surface on a second, opposite side of the metal plate; and a slot that extends through the metal plate from a first opening defined in the first surface to a second opening defined in the second surface. The assembly method further includes inserting a circuit board into the slot; and securing the circuit board in the slot at a first position relative to the metal plate. The circuit board at the first position includes a central portion residing in the slot; a first end portion residing outside the slot and protruding from the first side of the metal plate, the first end portion including a first plurality of electrical connectors that are configured to interface with one or more first cables; a second end portion residing outside the slot and protruding from the second side of the metal plate, the second end portion including a second plurality of electrical connectors that are configured to interface with one or more second cables; and electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors. The electrical circuitry includes signal lines and at least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion.

[00121] Implementations of the fourth example may include one or more of the following features. The assembly method includes securing the metal plate to a flange in a cryogenic system. The circuit board includes thermally conductive cladding on a first surface and a second opposite surface of the circuit board, and the assembly method includes securing the circuit board to the metal plate using a clamp assembly including rails. The rails reside in thermal contact with the thermally conductive cladding of the circuit board and the first surface of the metal plate. The first plurality of electrical connectors includes a first plurality of coaxial cable connectors; and the second plurality of electrical connectors includes a second plurality of coaxial cable connectors, the assembly method includes connecting a first plurality of coaxial cable to the first plurality of coaxial cable connectors; and connecting a second plurality of coaxial cable to the second plurality of coaxial cable connectors.

[00122] Implementations of the fourth example may include one or more of the following features. The assembly method includes connecting the first plurality of electrical connectors to a first flex cable; and connecting the second plurality of electrical connectors to a second flex cable. The circuit board includes strain-relief clips, and the assembly method includes securing the first and second flex cables to the first and second plurality of electrical connectors using the strain-relief clips.

[00123] Implementations of the fourth example may include one or more of the following features. The first plurality of electrical connectors are first D-subshell connectors, and the second plurality of electrical connectors are second D-subshell connectors. The assembly method includes connecting the first D-subshell connectors to a first plurality of electrical wires; and connecting the second D-subshell connectors to a second plurality of electrical wires.

[00124] While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separate implementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

[00125] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[00126] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

CLAIMS What is claimed is:

1. An apparatus for communicating electrical signals through a flange in a cryogenic system, the apparatus comprising: a metal plate configured to mate with the flange, the metal plate comprising: a first surface on a first side of the metal plate; a second surface on a second, opposite side of the metal plate; and a slot that extends through the metal plate from a first opening defined in the first surface to a second opening defined in the second surface; a circuit board secured to the metal plate and extending through the slot, the circuit board comprising: a central portion residing in the slot; a first end portion residing outside the slot and protruding from the first side of the metal plate, the first end portion comprising a first plurality of electrical connectors that are configured to interface with one or more first cables; a second end portion residing outside the slot and protruding from the second side of the metal plate, the second end portion comprising a second plurality of electrical connectors that are configured to interface with one or more second cables; electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors, the electrical circuitry comprising signal lines, wherein at least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion.

2. The apparatus of claim 1, wherein the metal plate comprises a plurality of slots that each extend through the metal plate from a respective first opening defined in the first surface to a respective second opening defined in the second surface, and the apparatus comprises a plurality of circuit boards secured to the metal plate, each circuit board extending through a respective one of the plurality of slots, each circuit board comprising: a central portion residing in a respective slot; a first end portion residing outside the respective slot and protruding from the first side of the metal plate, the first end portion comprising a first plurality of electrical connectors that are configured to interface with one or more first cables; a second end portion residing outside the respective slot and protruding from the second side of the metal plate, the second end portion comprising a second plurality of electrical connectors that are configured to interface with one or more second cables; electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors, the electrical circuitry comprising signal lines, wherein at least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion.

3. The apparatus of claim 1, wherein the first plurality of electrical connectors comprise a first plurality of coaxial cable connectors that are configured to interface with a first plurality of coaxial cables, and the second plurality of electrical connectors comprise a second plurality of coaxial cable connectors that are configured to interface with a second plurality of coaxial cables.

4. The apparatus of claim 1, wherein the first plurality of electrical connectors are first D-subshell connectors configured to interface with a first plurality of electrical wires, and the second plurality of electrical connectors are second D-subshell connectors to interface with a second plurality of electrical wires.

5. The apparatus of claim 1, comprising strain-relief clips configured to secure electrical cables to the first and second plurality of electrical connectors.

6. The apparatus of claim 5, wherein the strain-relief clips are rigidly positioned with respect to the circuit board.

7. The apparatus of claim 1, wherein the first plurality of electrical connectors is configured to interface with a first flex cable, and the second plurality of electrical connectors are configured to interface with a second flex cable.

8. The apparatus of claim 1, wherein the electrical circuitry comprises a plurality of circuit elements connected to at least a subset of the signal lines, and the circuit elements comprise one or more radio frequency filters.

9. The apparatus of claim 1, wherein the circuit board is a multi-layered circuit board comprising a stack of metallization layers, each metallization layer comprising a respective portion of the electrical circuitry.

10. The apparatus of claim 1, wherein the circuit board comprises thermally conductive cladding on a first surface and a second opposite surface of the circuit board, and the thermally conductive cladding is thermally connected to the metal plate.

11. The apparatus of claim 10, comprising a clamp assembly that secures the circuit board to the metal plate and provides thermal connectivity between the circuit board and the metal plate, wherein the clamp assembly comprises rails that reside in thermal contact with the thermally conductive cladding and the first surface of the metal plate.

12. The apparatus of claim 11, wherein the clamp assembly further comprises braces that secure the rails to the metal plate.

13. The apparatus of claim 1, further comprising a seal between the circuit board and the metal plate, wherein the seal provides vacuum isolation between the first and second sides of the metal plate.

14. A cryogenic system comprising: a plurality of isothermal plates; and the apparatus of any one of the preceding claims mated to one of the isothermal plates and configured to communicate electrical signals through the isothermal plate.

15. An apparatus for communicating electrical signals, the apparatus comprising: a metal plate comprising: a first surface on a first side of the metal plate; a second surface on a second, opposite side of the metal plate; and a slot that extends through the metal plate from a first opening defined in the first surface to a second opening defined in the second surface; a circuit board secured to the metal plate and extending through the slot, the circuit board comprising: a central portion residing in the slot; a first end portion residing outside the slot and protruding from the first side of the metal plate, the first end portion comprising a first plurality of electrical connectors that are configured to interface with one or more first cables; a second end portion residing outside the slot and protruding from the second side of the metal plate, the second end portion comprising a second plurality of electrical connectors that are configured to interface with one or more second cables; electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors, the electrical circuitry comprising signal lines, wherein at least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion.

16. An assembly method comprising: obtaining a metal plate comprising: a first surface on a first side of the metal plate; a second surface on a second, opposite side of the metal plate; and a slot that extends through the metal plate from a first opening defined in the first surface to a second opening defined in the second surface; inserting a circuit board into the slot; and securing the circuit board in the slot at a first position relative to the metal plate, the circuit board at the first position comprising: a central portion residing in the slot; a first end portion residing outside the slot and protruding from the first side of the metal plate, the first end portion comprising a first plurality of electrical connectors that are configured to interface with one or more first cables; a second end portion residing outside the slot and protruding from the second side of the metal plate, the second end portion comprising a second plurality of electrical connectors that are configured to interface with one or more second cables; electrical circuitry configured to communicate electrical signals between the first plurality of electrical connectors and the second plurality of electrical connectors, the electrical circuitry comprising signal lines, wherein at least a subset of the signal lines each extend from the first end portion, through the central portion, into the second end portion.

17. The method of claim 16, securing the metal plate to a flange in a cryogenic system.

18. The method of claim 16, where the circuit board comprises thermally conductive cladding on a first surface and a second opposite surface of the circuit board, and the method comprises: securing the circuit board to the metal plate using a clamp assembly comprising rails, wherein the rails reside in thermal contact with the thermally conductive cladding of the circuit board and the first surface of the metal plate.

19. The method of claim 16, wherein the first plurality of electrical connectors comprise a first plurality of coaxial cable connectors and the second plurality of electrical connectors comprise a second plurality of coaxial cable connectors, the method comprises: connecting a first plurality of coaxial cable to the first plurality of coaxial cable connectors; and connecting a second plurality of coaxial cable to the second plurality of coaxial cable connectors.

20. The method of claim 16, comprising: connecting the first plurality of electrical connectors to a first flex cable; and connecting the second plurality of electrical connectors to a second flex cable.

21. The method of claim 20, wherein the circuit board comprises strain-relief clips, and the method comprises: securing the first and second flex cables to the first and second plurality of electrical connectors using the strain-relief clips.

22. The method of claim 21, wherein the strain-relief clips are rigidly positioned with respect to the circuit board.

23. The method of claim 16, wherein the first plurality of electrical connectors are first D-subshell connectors, and the second plurality of electrical connectors are second D- subshell connectors, and the method comprises: connecting the first D-subshell connectors to a first plurality of electrical wires; and connecting the second D-subshell connectors to a second plurality of electrical wires.