WO2024055759A1 - 低噪声放大器和射频芯片 - Google Patents

低噪声放大器和射频芯片 Download PDF

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Publication number
WO2024055759A1
WO2024055759A1 PCT/CN2023/109815 CN2023109815W WO2024055759A1 WO 2024055759 A1 WO2024055759 A1 WO 2024055759A1 CN 2023109815 W CN2023109815 W CN 2023109815W WO 2024055759 A1 WO2024055759 A1 WO 2024055759A1
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Prior art keywords
transistor
resistor
radio frequency
source
inductor
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PCT/CN2023/109815
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English (en)
French (fr)
Inventor
尚鹏飞
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2024055759A1 publication Critical patent/WO2024055759A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the invention relates to the field of amplifier circuits, and in particular to a low-noise amplifier and a radio frequency chip.
  • the radio frequency low-noise amplifier is one of the important components.
  • the low-noise amplifier amplifies the power of the signal. After sufficient radio frequency power is obtained, the signal can be fed to the antenna for radiation.
  • the gain and input dynamic range of the low-noise amplifier are important performance indicators.
  • the related art low noise amplifier includes an input matching circuit, a common gate common source amplifier and an output matching circuit.
  • radio frequency receivers need to have a wide dynamic range, which can not only handle weak small signals, but also receive and process large input signals, all at the same time. To ensure that the signal is not distorted, this puts forward higher requirements for the low-noise amplifier at the front end.
  • Control of low-noise amplifiers in related technologies Low-noise amplifiers in related technologies adjust their gains by adding some feedback controls. However, these feedback controls cannot achieve higher gains when processing weak signals. When processing large signals, there is lower gain or even attenuation to achieve a wide dynamic range.
  • the present invention proposes a low-noise amplifier and radio frequency chip with adjustable circuit gain and wide input dynamic range.
  • embodiments of the present invention provide a low-noise amplifier, which includes a radio frequency input terminal, a first inductor, and a first inductor connected in sequence.
  • the low-noise amplifier further includes a first-stage source inductance adjustment circuit provided with an inductor, a load switching circuit provided with a load resistor, and a bypass mode circuit provided with the first resistor;
  • the first-stage source inductance adjustment circuit is connected to the source of the first transistor and is used to adjust the inductance value of the inductor to adjust the input radiation coefficient of the low-noise amplifier;
  • the load switching circuit is connected across the output end of the first-stage cascode amplifier and the input end of the second-stage cascode amplifier, and is used to adjust the resistance value of the load resistor to achieve Adjust the gain of the low-noise amplifier;
  • the bypass mode circuit is used to broaden the dynamic range of the input signal of the radio frequency input terminal; the first end of the bypass mode circuit is connected to the radio frequency input end, and the second end of the bypass mode circuit is connected to to the output end of the second-stage cascode amplifier, the third end of the bypass mode circuit is connected to the RF output end; the two ends of the first resistor are respectively used to connect the RF input end and the radio frequency output terminal; when the radio frequency signal received by the radio frequency input terminal is within a preset range, the bypass mode circuit connects the output terminal of the second-stage cascode common source amplifier to the radio frequency output terminal.
  • the bypass mode circuit switches the output of the second stage common gate common source amplifier
  • the first resistor is connected to the radio frequency input terminal and the radio frequency output terminal respectively.
  • the resistance value parameter of the first resistor is adjustable.
  • the inductor provided in the first-stage source inductance adjustment circuit has an adjustable inductance parameter.
  • the first-stage source inductance adjustment circuit further includes a third transistor and a fourth transistor, and the inductor includes a second inductor and a third inductor;
  • the first end of the second inductor is connected to the source of the first transistor, and the second end of the second inductor is connected to the drain of the third transistor and the third circuit. the first end of sense;
  • the gate of the third transistor is used to connect an external first control signal, and the source of the third transistor is grounded;
  • the second end of the third inductor is connected to the drain of the fourth transistor
  • the gate of the fourth transistor is used to connect an external second control signal, and the source of the fourth transistor is grounded.
  • the resistance value parameter of the load resistor is adjustable.
  • the load switching circuit includes a fifth transistor, a sixth transistor and a seventh transistor, and the load resistance includes a second resistor, a third resistor and a fourth resistor;
  • the first end of the second resistor is respectively connected to the first end of the third resistor, the first end of the fourth resistor, the output end of the first-stage cascode amplifier and the second The input terminal of the cascode amplifier;
  • the second end of the second resistor is connected to the drain of the fifth transistor
  • the gate of the fifth transistor is used to connect an external third control signal, and the source of the fifth transistor is grounded;
  • the second end of the third resistor is connected to the drain of the sixth transistor
  • the gate of the sixth transistor is used to connect an external fourth control signal, and the source of the sixth transistor is grounded;
  • the second end of the fourth resistor is connected to the drain of the seventh transistor
  • the gate of the seventh transistor is used to connect an external fifth control signal, and the source of the seventh transistor is connected to ground.
  • the bypass mode circuit further includes a tenth transistor, an eleventh transistor and a twelfth transistor;
  • the source of the tenth transistor is connected to the radio frequency input terminal, the drain of the tenth transistor is connected to the first end of the first resistor, and the gate of the tenth transistor is used to connect an external third Six control signals;
  • the source of the eleventh transistor is connected to the second end of the first resistor, the drain of the eleventh transistor is connected to the radio frequency output end, and the gate of the eleventh transistor is used to connect The seventh external control signal;
  • the source of the twelfth transistor is connected to the second-stage cascode amplifier
  • the output terminal of the twelfth transistor is connected to the radio frequency output terminal, and the gate of the twelfth transistor is used to connect an external eighth control signal.
  • the first-stage common-gate common-source amplifier further includes a first capacitor, a second capacitor, a third capacitor, a first bias resistor and a fourth inductor;
  • the first terminal of the first capacitor serves as the input terminal of the first-stage cascode amplifier, and the second terminal of the first capacitor is connected to the second terminal of the first bias resistor and the second terminal of the first bias resistor. the gate of the first transistor;
  • the first end of the first bias resistor is used to connect an external first bias voltage
  • the source of the first transistor is used to connect to the first-stage source inductance adjustment circuit, and the drain of the first transistor is connected to the source of the second transistor;
  • the gate of the second transistor is used to connect an external second bias voltage, and the drain of the second transistor is connected to the second end of the fourth inductor, the second end of the second capacitor and the first terminal of the third capacitor;
  • the first end of the fourth inductor and the first end of the second capacitor are both connected to the power supply voltage
  • the second end of the third capacitor serves as the output end of the first-stage common-gate common-source amplifier.
  • the second-stage cascode amplifier includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a second bias resistor, a fifth inductor, an eighth transistor and a ninth transistor;
  • the first end of the fourth capacitor serves as the input end of the second-stage cascode amplifier, and the second end of the fourth capacitor is connected to the second end of the second bias resistor and the second end of the second bias resistor. the gate of the eighth transistor;
  • the first end of the second bias resistor is used to connect an external third bias voltage
  • the source of the eighth transistor is connected to ground, and the drain of the eighth transistor is connected to the source of the ninth transistor;
  • the gate of the ninth transistor is used to connect an external fourth bias voltage, and the drain of the ninth transistor is connected to the second end of the fifth inductor, the second end of the fifth capacitor and the first terminal of the sixth capacitor;
  • the first terminal of the fifth inductor and the first terminal of the sixth capacitor are both connected to the power supply voltage
  • the second terminal of the sixth capacitor serves as the output terminal of the first-stage cascode amplifier.
  • embodiments of the present invention also provide a radio frequency chip, which includes the low-noise amplifier described above in the embodiments of the present invention.
  • the low-noise amplifier and radio frequency chip of the present invention adopt the structure of a two-stage cascode amplifier, that is, a first-stage cascode amplifier and a second-stage cascode amplifier.
  • This structure satisfies the requirement of low noise
  • the noise performance also improves the gain, further reducing the noise figure and system sensitivity, so that the low-noise amplifier of the present invention can process weaker radio frequency signals.
  • the low-noise amplifier and radio frequency chip of the present invention also adjust the inductance value of the inductor by using the first-stage source inductance adjustment circuit connected to the source of the first transistor of the first-stage cascode amplifier.
  • the input radiation coefficient of the low-noise amplifier is adjusted, so that the low-noise amplifier of the present invention has a better input reflection coefficient under different gains.
  • the low-noise amplifier and radio frequency chip of the present invention also adjust the gain of the low-noise amplifier by using the load switching circuit to adjust the resistance value of the load resistor; the load switching circuit is connected to the first-stage common gate Between the output terminal of the common source amplifier and the input terminal of the second-stage common-gate common-source amplifier, the influence on the input reflection coefficient and the output reflection coefficient of the low-noise amplifier of the present invention can be reduced.
  • the low-noise amplifier and radio frequency chip of the present invention also use the bypass mode circuit, so that the low-noise amplifier of the present invention can process radio frequency signals higher than the preset range, that is, it can process larger input radio frequency signals, thereby achieving The input dynamic range is broadened. Therefore, the circuit gain using the low-noise amplifier and radio frequency chip of the present invention is adjustable and the input dynamic range is wide.
  • FIG. 1 is a circuit structure diagram of a low-noise amplifier according to an embodiment of the present invention.
  • the present invention provides a low noise amplifier 100.
  • FIG. 1 is a circuit structure diagram of a low-noise amplifier 100 according to an embodiment of the present invention.
  • the low-noise amplifier 100 includes a radio frequency input terminal RFIIN, a first inductor L1, a first-stage cascode amplifier 1, a second-stage cascode amplifier 2, a radio frequency output terminal RFOUT, and a first-stage source provided with an inductor.
  • the radio frequency input terminal RFIIN, the first inductor L1, the first stage cascode amplifier 1, the second stage cascode amplifier 2 and the radio frequency output terminal RFOUT are connected in sequence.
  • the first inductor L1 serves as a matching inductor.
  • the first-stage cascode amplifier 1 includes a first transistor M1 used as a common-source transistor and a second transistor M2 used as a common-gate transistor.
  • the low-noise amplifier 100 is made using MOS technology, so the low-noise amplifier 100 is easy to integrate and make a chip, which is beneficial to the wide application of the low-noise amplifier 100 .
  • the first transistor M1 and the second transistor M2 are both MOS transistors.
  • the first transistor M1 functions as an amplifier.
  • the second transistor M2 serves as a common-gate amplifier tube and plays the role of voltage division and isolation.
  • the first transistor M1 and the second transistor M2 are configured in terms of transistor size and current distribution in order to meet low noise performance.
  • the first-stage cascode amplifier 1 is the main circuit to achieve low-noise performance.
  • the first-stage cascode amplifier 1 also includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first bias resistor Rb1 and a fourth inductor L4.
  • first capacitor C1 is a DC blocking capacitor.
  • the second capacitor C2 and the fourth inductor L4 form a parallel resonance, and the resonance is in the working frequency band, that is, the working frequency band in which the radio frequency signal received by the radio frequency input terminal RFIN is within a preset range.
  • the third capacitor C3 serves as a DC blocking capacitor between the first-stage cascode amplifier 1 and the second-stage cascode amplifier 2 .
  • the internal circuit connection relationship of the first-stage cascode amplifier 1 is:
  • the first terminal of the first capacitor C1 serves as the input terminal of the first-stage cascode amplifier 1 .
  • the second terminal of the first capacitor C1 is connected to the second terminal of the first bias resistor Rb1 and the gate of the first transistor M1 respectively.
  • the first end of the first bias resistor Rb1 is used to connect to the external first bias voltage VGS1.
  • the first bias voltage VGS1 is used to ensure that the first transistor M1 operates in the saturation region.
  • the source of the first transistor M1 is used to connect to the first-stage source inductance adjustment circuit 3 .
  • the drain of the first transistor M1 is connected to the source of the second transistor M2.
  • the gate of the second transistor M2 is used to connect the external second bias voltage VGS2.
  • the drain of the second transistor M2 is connected to the second terminal of the fourth inductor L4, the second terminal of the second capacitor C2, and the first terminal of the third capacitor C3 respectively.
  • the first terminal of the fourth inductor L4 and the first terminal of the second capacitor C2 are both connected to the power supply voltage VDD.
  • the second terminal of the third capacitor C3 serves as the output terminal of the first-stage cascode amplifier 1 .
  • the second-stage cascode amplifier 2 includes a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a second bias resistor Rb2, a fifth inductor L5, an eighth transistor M8 and a ninth transistor M9.
  • the eighth transistor M8 and the ninth transistor M9 are both MOS transistors.
  • the eighth transistor M8 plays an amplifying role.
  • the ninth transistor M9 serves as a common-gate configuration amplifier tube and plays the role of voltage dividing and isolation.
  • the fourth capacitor C4 serves as a DC blocking capacitor between the first-stage cascode amplifier 1 and the second-stage cascode amplifier 2 .
  • the fifth capacitor C5 and the fifth inductor L5 form a parallel resonance, which also resonates in the working frequency band.
  • the sixth capacitor C6 serves as the output matching capacitor.
  • the internal circuit connection relationship of the second-stage cascode amplifier 2 is:
  • the first terminal of the fourth capacitor C4 serves as the input terminal of the second-stage cascode amplifier 2 .
  • the second terminal of the fourth capacitor C4 is connected to the second terminal of the second bias resistor Rb2 and the gate of the eighth transistor M8 respectively.
  • the first end of the second bias resistor Rb2 is used to connect to the external third bias voltage VGS3.
  • the source of the eighth transistor M8 is connected to the ground GND.
  • the drain of the eighth transistor M8 is connected to the source of the ninth transistor M9.
  • the gate of the ninth transistor M9 is used to connect to the external fourth bias voltage VGS4.
  • the drain of the ninth transistor M9 is connected to the second terminal of the fifth inductor L5, the second terminal of the fifth capacitor C5, and the first terminal of the sixth capacitor C6 respectively.
  • a first end of the fifth inductor L5 and a first end of the sixth capacitor C6 are both connected to a power supply voltage VDD.
  • the second terminal of the sixth capacitor C6 serves as the output terminal of the first-stage cascode amplifier 1 .
  • the first-stage source inductance adjustment circuit 3 is used to adjust the inductance value of the inductor to adjust the input radiation coefficient of the low-noise amplifier 100 .
  • the first-stage source inductance adjustment circuit 3 enables the low-noise amplifier 100 of the present invention to have a better input reflection coefficient under different gains.
  • the first-stage source inductance adjustment circuit 3 is connected to the source of the first transistor M1.
  • the first-stage source inductance adjustment circuit 3 further includes a third transistor M3 and a fourth transistor M4.
  • the third transistor M3 and the fourth transistor M4 are both MOS transistors.
  • the inductor includes a second inductor L2 and a third inductor L3.
  • the second inductor L2 and the third inductor L3 serve as the source inductance of the first transistor M1 and are controlled by the third transistor M3 and the fourth transistor M4 respectively. They can realize source inductance switching under high and low gain, achieving Different gears have better input reflection coefficients.
  • the first inductor L1, the second inductor L2 and the third inductor L3 all participate in the input matching of the first-stage cascode amplifier 1. Of course, it is not limited to this.
  • the first-stage source inductance adjustment circuit 3 is provided with the The inductance value parameter of the inductor is adjustable. That is, the inductor provided in the first-stage source inductance adjustment circuit 3 uses a device or module that can directly adjust the inductance value.
  • the internal circuit connection relationship of the first-stage source inductance adjustment circuit 3 is:
  • the first terminal of the second inductor L2 is connected to the source of the first transistor M1.
  • the second terminal of the second inductor L2 is connected to the drain of the third transistor M3 and the first terminal of the third inductor L3 respectively.
  • the gate of the third transistor M3 is used to connect to the external first control signal K1.
  • the source of the third transistor M3 is grounded GND.
  • the second terminal of the third inductor L3 is connected to the drain of the fourth transistor M4.
  • the gate of the fourth transistor M4 is used to connect the external second control signal K2.
  • the source of the fourth transistor M4 is connected to the ground GND.
  • the load switching circuit 4 is used to adjust the resistance value of the load resistor to adjust the gain of the low noise amplifier 100 .
  • the load switching circuit 4 is connected across the output terminal of the first-stage cascode amplifier 1 and the input terminal of the second-stage cascode amplifier 2 . This setting can reduce the impact on the input reflection coefficient and the output reflection coefficient of the low noise amplifier 100 of the present invention.
  • the load switching circuit 4 includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7.
  • the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all MOS transistors.
  • the load resistor includes a second resistor R2, a third resistor R3 and a fourth resistor R4.
  • the load switching circuit 4 uses the second resistor R2, the third resistor R3 and the fourth resistor R4 as three-level adjustment. By adjusting the resistance value of the load resistor, the gain can be changed, thereby realizing the load switching function. Of course, it is not limited to this.
  • the resistance parameter of the load resistor is adjustable. That is, the load resistance is implemented by a variable resistor.
  • the internal circuit connection relationship of the load switching circuit 4 is:
  • the first terminals of the second resistor R2 are respectively connected to the third terminals of the third resistor R3. One end, the first end of the fourth resistor R4, the output end of the first-stage cascode amplifier 1 and the input end of the second-stage cascode amplifier 2.
  • the second terminal of the second resistor R2 is connected to the drain of the fifth transistor M5.
  • the gate of the fifth transistor M5 is used to connect to the external third control signal K3.
  • the source of the fifth transistor M5 is connected to the ground GND.
  • the second terminal of the third resistor R3 is connected to the drain of the sixth transistor M6.
  • the gate of the sixth transistor M6 is used to connect the external fourth control signal K4.
  • the source of the sixth transistor M6 is connected to the ground GND.
  • the second terminal of the fourth resistor R4 is connected to the drain of the seventh transistor M7.
  • the gate of the seventh transistor M7 is used to connect the external fifth control signal K5.
  • the source of the seventh transistor M7 is connected to the ground GND.
  • the bypass mode circuit 5 is used to broaden the dynamic range of the input signal of the radio frequency input terminal RFIIN.
  • the first terminal of the bypass mode circuit 5 is connected to the radio frequency input terminal RFIIN.
  • the second terminal of the bypass mode circuit 5 is connected to the output terminal of the second-stage cascode amplifier 2 .
  • the third terminal of the bypass mode circuit 5 is connected to the radio frequency output terminal RFOUT.
  • the resistance parameter of the first resistor R1 is adjustable.
  • the two ends of the first resistor R1 are respectively used to connect the radio frequency input terminal RFIIN and the radio frequency output terminal RFOUT.
  • the working principle of the bypass mode circuit 5 is:
  • the bypass mode circuit 5 connects the output terminal of the second stage cascode amplifier 2 to the radio frequency output terminal RFOUT and Both ends of the first resistor R1 are disconnected.
  • the bypass mode circuit 5 disconnects the output terminal of the second-stage cascode amplifier 2 from the radio frequency output terminal RFOUT and connects both ends of the first resistor R1 to the radio frequency input terminal RFIIN respectively. Connected to the radio frequency output terminal RFOUT.
  • the bypass mode circuit 5 further includes a tenth transistor M10, an eleventh transistor M11, and the twelfth transistor M12.
  • the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are all MOS transistors.
  • the internal circuit connection relationship of the bypass mode circuit 5 is:
  • the source of the tenth transistor M10 is connected to the radio frequency input terminal RFIIN.
  • the drain of the tenth transistor M10 is connected to the first terminal of the first resistor R1.
  • the gate of the tenth transistor M10 is used to connect to the external sixth control signal K6.
  • the source of the eleventh transistor M11 is connected to the second terminal of the first resistor R1.
  • the drain of the eleventh transistor M11 is connected to the radio frequency output terminal RFOUT.
  • the gate of the eleventh transistor M11 is used to connect to the external seventh control signal K7.
  • the source of the twelfth transistor M12 is connected to the output terminal of the second-stage cascode amplifier 2 .
  • the drain of the twelfth transistor M12 is connected to the radio frequency output terminal RFOUT.
  • the gate of the twelfth transistor M12 is used to connect to the external eighth control signal K8.
  • the tenth transistor M10, the eleventh transistor M11 and the first resistor R1 of the bypass mode circuit 5 form an attenuation branch in the passive mode.
  • the amplifier circuit can be turned off. Reduce circuit power consumption while achieving higher linearity indicators.
  • the working process of the bypass mode circuit 5 is:
  • the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 function as radio frequency switches.
  • the two-stage path of the low-noise amplifier 100 (the first-stage cascode amplifier 1 and the second-stage cascode amplifier 2) operates in a normal amplification state, that is, the radio frequency signal is within a preset range.
  • the tenth transistor M10 is turned off, the eleventh transistor M11 is turned off, and the twelfth transistor M12 is turned on.
  • the bypass mode that is, when the radio frequency signal is higher than the preset range, the tenth transistor M10 is turned on, the eleventh transistor M11 is turned on, and the twelfth transistor M12 is turned off.
  • the resistance value of the first resistor R1 changes to achieve the attenuation effect of different gears, which is used to process relatively large input radio frequency signals.
  • An embodiment of the present invention also provides a radio frequency chip, which includes the low noise amplifier 100 .
  • the low-noise amplifier and radio frequency chip of the present invention adopt the structure of a two-stage cascode amplifier, that is, a first-stage cascode amplifier and a second-stage cascode amplifier.
  • This structure satisfies the requirement of low noise
  • the noise performance also improves the gain, further reducing the noise figure and system sensitivity, so that the low-noise amplifier of the present invention can process weaker radio frequency signals.
  • the low-noise amplifier and radio frequency chip of the present invention also adjust the inductance value of the inductor by using the first-stage source inductance adjustment circuit connected to the source of the first transistor of the first-stage cascode amplifier.
  • the input radiation coefficient of the low-noise amplifier is adjusted, so that the low-noise amplifier of the present invention has a better input reflection coefficient under different gains.
  • the low-noise amplifier and radio frequency chip of the present invention also adjust the gain of the low-noise amplifier by using the load switching circuit to adjust the resistance value of the load resistor; the load switching circuit is connected to the first-stage common gate Between the output terminal of the common source amplifier and the input terminal of the second stage common gate common source amplifier, the influence on the input reflection coefficient and the output reflection coefficient of the low noise amplifier of the present invention can be reduced.
  • the low-noise amplifier and radio frequency chip of the present invention also use the bypass mode circuit, so that the low-noise amplifier of the present invention can process radio frequency signals higher than the preset range, that is, it can process larger input radio frequency signals, thereby achieving The input dynamic range is broadened. Therefore, the circuit gain using the low-noise amplifier and radio frequency chip of the present invention is adjustable and the input dynamic range is wide.

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Abstract

一种低噪声放大器（100）和射频芯片，其电路增益可调且输入动态范围宽。其中，低噪声放大器（100）包括射频输入端（RFIIN）、第一电感（L1）、第一级共栅共源放大器（1）、第二级共栅共源放大器（2）、射频输出端（RFOUT）、设有电感的第一级源极电感调节电路（3）、设有负载电阻的负载切换电路（4）以及设有第一电阻（R1）的旁路模式电路（5）；第一级源极电感调节电路（3）用于调节电感的电感值以实现调节低噪声放大器（100）的输入放射系数；负载切换电路（4）跨用于调节负载电阻的电阻值以实现调节低噪声放大器（100）的增益；旁路模式电路（5）用于控制旁路模式。

Description

低噪声放大器和射频芯片 技术领域
本发明涉及放大器电路领域，尤其涉及一种低噪声放大器和射频芯片。
背景技术
目前，在无线收发系统中，射频的低噪声放大器是重要的组成部分之一，低噪声放大器将信号进行功率放大，获得足够的射频功率以后，信号才能馈送到天线上辐射出去。其中，低噪声放大器的增益和输入动态范围为重要的性能指标。
相关技术的低噪声放大器包括输入匹配电路、共栅共源放大器和输出匹配电路。
然而，5G通信时代，面对更加复杂严苛的物理环境，为了保证通信质量，射频接收机需要有宽的动态范围，既能处理微弱的小信号，又能接收处理大的输入信号，同时都要保证信号不失真，这就为位于最前端的低噪声放大器提出了更高的要求。相关技术的低噪声放大器的控相关技术的低噪声放大器对其增益进行调节，采用办法就是增加一些反馈控制，但是这些反馈控制对增益无法做到在处理微弱信号的时候有较高的增益，在处理大信号的时候有较低的增益，甚至是衰减，以达到宽动态范围。
因此，实有必要提供一种新的低噪声放大器和芯片解决上述问题。
发明内容
针对以上现有技术的不足，本发明提出一种电路增益可调且输入动态范围宽的低噪声放大器和射频芯片。
为了解决上述技术问题，第一方面，本发明的实施例提供了一种低噪声放大器，其包括依次连接的射频输入端、第一电感、第一 级共栅共源放大器、第二级共栅共源放大器以及射频输出端，所述第一级共栅共源放大器包括用作共源晶体管的第一晶体管和用作共栅晶体管的第二晶体管；
所述低噪声放大器还包括设有电感的第一级源极电感调节电路、设有负载电阻的负载切换电路以及设有第一电阻的旁路模式电路；
所述第一级源极电感调节电路连接于所述第一晶体管的源极，用于调节所述电感的电感值以实现调节所述低噪声放大器的输入放射系数；
所述负载切换电路跨接于所述第一级共栅共源放大器的输出端与所述第二级共栅共源放大器的输入端之间，用于调节所述负载电阻的电阻值以实现调节所述低噪声放大器的增益；
所述旁路模式电路，用于拓宽所述射频输入端的输入信号的动态范围；所述旁路模式电路的第一端连接至所述射频输入端，所述旁路模式电路的第二端连接至所述第二级共栅共源放大器的输出端，所述旁路模式电路的第三端连接至所述射频输出端；所述第一电阻的两端分别用于连接所述射频输入端和所述射频输出端；所述射频输入端接收的射频信号在预设的范围内时，所述旁路模式电路将所述第二级共栅共源放大器的输出端与所述射频输出端连通并将所述第一电阻的两端断开；所述射频输入端接收的射频信号高于预设的范围时，所述旁路模式电路将所述第二级共栅共源放大器的输出端与所述射频输出端断开并将所述第一电阻的两端分别与所述射频输入端和所述射频输出端连通。
优选的，所述第一电阻的电阻值参数可调。
优选的，所述第一级源极电感调节电路设有的所述电感的电感值参数可调。
优选的，所述第一级源极电感调节电路还包括第三晶体管和第四晶体管，所述电感包括第二电感和第三电感；
所述第二电感的第一端连接至所述第一晶体管的源极，所述第二电感的第二端分别连接至所述第三晶体管的漏极和所述第三电 感的第一端；
所述第三晶体管的栅极用于连接外部的第一控制信号，所述第三晶体管的源极接地；
所述第三电感的第二端连接至所述第四晶体管的漏极；
所述第四晶体管的栅极用于连接外部的第二控制信号，所述第四晶体管的源极接地。
优选的，所述负载电阻的电阻值参数可调。
优选的，所述负载切换电路包括第五晶体管、第六晶体管以及第七晶体管，所述负载电阻包括第二电阻、第三电阻和第四电阻；
所述第二电阻的第一端分别连接至所述第三电阻的第一端、所述第四电阻的第一端、所述第一级共栅共源放大器的输出端以及所述第二级共栅共源放大器的输入端；
所述第二电阻的第二端连接至所述第五晶体管的漏极；
所述第五晶体管的栅极用于连接外部的第三控制信号，所述第五晶体管的源极接地；
所述第三电阻的第二端连接至所述第六晶体管的漏极；
所述第六晶体管的栅极用于连接外部的第四控制信号，所述第六晶体管的源极接地；
所述第四电阻的第二端连接至所述第七晶体管的漏极；
所述第七晶体管的栅极用于连接外部的第五控制信号，所述第七晶体管的源极接地。
优选的，所述旁路模式电路还包括第十晶体管、第十一晶体管和第十二晶体管；
所述第十晶体管的源极连接至所述射频输入端，所述第十晶体管的漏极连接至所述第一电阻的第一端，所述第十晶体管的栅极用于连接外部的第六控制信号；
所述第十一晶体管的源极连接至所述第一电阻的第二端，所述第十一晶体管的漏极连接至所述射频输出端，所述第十一晶体管的栅极用于连接外部的第七控制信号；
所述第十二晶体管的源极连接至所述第二级共栅共源放大器 的输出端，所述第十二晶体管的漏极连接至所述射频输出端，所述第十二晶体管的栅极用于连接外部的第八控制信号。
优选的，所述第一级共栅共源放大器还包括第一电容、第二电容、第三电容、第一偏置电阻和第四电感；
所述第一电容的第一端作为所述第一级共栅共源放大器的输入端，所述第一电容的第二端分别连接至所述第一偏置电阻的第二端和所述第一晶体管的栅极；
所述第一偏置电阻的第一端用于连接外部的第一偏置电压；
所述第一晶体管的源极用于连接所述第一级源极电感调节电路，所述第一晶体管的漏极连接至所述第二晶体管的源极；
所述第二晶体管的栅极用于连接外部的第二偏置电压，所述第二晶体管的漏极分别连接至所述第四电感的第二端、所述第二电容的第二端和所述第三电容的第一端；
所述第四电感的第一端和所述第二电容的第一端均连接至电源电压；
所述第三电容的第二端作为所述第一级共栅共源放大器的输出端。
优选的，所述第二级共栅共源放大器包括第四电容、第五电容、第六电容、第二偏置电阻、第五电感、第八晶体管和第九晶体管；
所述第四电容的第一端作为所述第二级共栅共源放大器的输入端，所述第四电容的第二端分别连接至所述第二偏置电阻的第二端和所述第八晶体管的栅极；
所述第二偏置电阻的第一端用于连接外部的第三偏置电压；
所述第八晶体管的源极接地，所述第八晶体管的漏极连接至所述第九晶体管的源极；
所述第九晶体管的栅极用于连接外部的第四偏置电压，所述第九晶体管的漏极分别连接至所述第五电感的第二端、所述第五电容的第二端和所述第六电容的第一端；
所述第五电感的第一端和所述第六电容的第一端均连接至电源电压；
所述第六电容的第二端作为所述第一级共栅共源放大器的输出端。
第二方面，本发明的实施例还提供了一种射频芯片，所述射频芯片包括如本发明的实施例提供上述的低噪声放大器。
与相关技术相比，本发明的低噪声放大器和射频芯片通过采用两级共栅共源放大器的结构，即第一级共栅共源放大器和第二级共栅共源放大器，该结构满足低噪声性能，同时也提高了增益，进一步降低了噪声系数和系统灵敏度，使本发明的低噪声放大器可以处理更微弱的射频信号。本发明的低噪声放大器和射频芯片还通过采用所述第一级源极电感调节电路连接于第一级共栅共源放大器的所述第一晶体管的源极，调节所述电感的电感值以实现调节所述低噪声放大器的输入放射系数，从而使得本发明的低噪声放大器在不同的增益下都较优的输入反射系数。本发明的低噪声放大器和射频芯片还通过采用所述负载切换电路调节所述负载电阻的电阻值以实现调节所述低噪声放大器的增益；所述负载切换电路接于所述第一级共栅共源放大器的输出端与所述第二级共栅共源放大器的输入端之间，可以减小对本发明的低噪声放大器的输入反射系数和输出反射系数的影响。本发明的低噪声放大器和射频芯片还通过所述旁路模式电路，使得本发明的低噪声放大器可以处理高于预设的范围的射频信号，即可以处理更大的输入的射频信号，从而达到了输入的动态范围拓宽。因此，采用本发明的低噪声放大器和射频芯片的电路增益可调且输入动态范围宽。
附图说明
下面结合附图详细说明本发明。通过结合以下附图所作的详细描述，本发明的上述或其他方面的内容将变得更清楚和更容易理解。附图中,
图1为本发明实施例的低噪声放大器的电路结构图。
具体实施方式
下面结合附图详细说明本发明的具体实施方式。
在此记载的具体实施方式/实施例为本发明的特定的具体实施方式，用于说明本发明的构思，均是解释性和示例性的，不应解释为对本发明实施方式及本发明范围的限制。除在此记载的实施例外，本领域技术人员还能够基于本申请权利要求书和说明书所公开的内容采用显而易见的其它技术方案，这些技术方案包括采用对在此记载的实施例的做出任何显而易见的替换和修改的技术方案，都在本发明的保护范围之内。
本发明提供一种低噪声放大器100。请参考图1所示，图1为本发明实施例的低噪声放大器100的电路结构图。
所述低噪声放大器100包括射频输入端RFIIN、第一电感L1、第一级共栅共源放大器1、第二级共栅共源放大器2、射频输出端RFOUT、设有电感的第一级源极电感调节电路3、设有负载电阻的负载切换电路4以及设有第一电阻R1的旁路模式电路5。
其中，所述射频输入端RFIIN、所述第一电感L1、所述第一级共栅共源放大器1、所述第二级共栅共源放大器2和所述射频输出端RFOUT依次连接。所述第一电感L1作为匹配电感。
所述第一级共栅共源放大器1包括用作共源晶体管的第一晶体管M1和用作共栅晶体管的第二晶体管M2。
本实施例中，所述低噪声放大器100采用MOS工艺制成，因此所述低噪声放大器100易于集成，制成芯片，有利于所述低噪声放大器100的应用广泛。其中，所述第一晶体管M1和所述第二晶体管M2均为MOS管。所述第一晶体管M1起放大作用。所述第二晶体管M2作为共栅组态放大管，起到分压和隔离作用。所述第一晶体管M1和所述第二晶体管M2在晶体管尺寸和电流分配上，为了满足低噪声性能。相对于所述第二级共栅共源放大器2在所述低噪声放大器100的作用，所述第一级共栅共源放大器1实现满足低噪声性能为主要电路。
所述第一级共栅共源放大器1还包括第一电容C1、第二电容C2、第三电容C3、第一偏置电阻Rb1和第四电感L4。第一电容 C1为隔直电容。第二电容C2和第四电感L4组成并联谐振，谐振在工作频段，即所述射频输入端RFIN的接收的射频信号在预设的范围内的工作频段。所述第三电容C3作为所述第一级共栅共源放大器1和所述第二级共栅共源放大器2之间的隔直电容。
所述第一级共栅共源放大器1的内部电路连接关系为：
所述第一电容C1的第一端作为所述第一级共栅共源放大器1的输入端。所述第一电容C1的第二端分别连接至所述第一偏置电阻Rb1的第二端和所述第一晶体管M1的栅极。
所述第一偏置电阻Rb1的第一端用于连接外部的第一偏置电压VGS1。所述第一偏置电压VGS1用于保证所述第一晶体管M1工作在饱和区。
所述第一晶体管M1的源极用于连接所述第一级源极电感调节电路3。所述第一晶体管M1的漏极连接至所述第二晶体管M2的源极。
所述第二晶体管M2的栅极用于连接外部的第二偏置电压VGS2。所述第二晶体管M2的漏极分别连接至所述第四电感L4的第二端、所述第二电容C2的第二端和所述第三电容C3的第一端。
所述第四电感L4的第一端和所述第二电容C2的第一端均连接至电源电压VDD。
所述第三电容C3的第二端作为所述第一级共栅共源放大器1的输出端。
所述第二级共栅共源放大器2包括第四电容C4、第五电容C5、第六电容C6、第二偏置电阻Rb2、第五电感L5、第八晶体管M8和第九晶体管M9。所述第八晶体管M8和所述第九晶体管M9均为MOS管。所述第八晶体管M8起放大作用。所述第九晶体管M9作为共栅组态放大管，起到分压和隔离作用。
第四电容C4作为所述第一级共栅共源放大器1和所述第二级共栅共源放大器2之间的隔直电容。第五电容C5和第五电感L5组成并联谐振，同样谐振在工作频段。第六电容C6作为输出匹配电容。
所述第二级共栅共源放大器2的内部电路连接关系为：
所述第四电容C4的第一端作为所述第二级共栅共源放大器2的输入端。所述第四电容C4的第二端分别连接至所述第二偏置电阻Rb2的第二端和所述第八晶体管M8的栅极。
所述第二偏置电阻Rb2的第一端用于连接外部的第三偏置电压VGS3。
所述第八晶体管M8的源极接地GND。所述第八晶体管M8的漏极连接至所述第九晶体管M9的源极。
所述第九晶体管M9的栅极用于连接外部的第四偏置电压VGS4。所述第九晶体管M9的漏极分别连接至所述第五电感L5的第二端、所述第五电容C5的第二端和所述第六电容C6的第一端。
所述第五电感L5的第一端和所述第六电容C6的第一端均连接至电源电压VDD。
所述第六电容C6的第二端作为所述第一级共栅共源放大器1的输出端。
所述第一级源极电感调节电路3用于调节所述电感的电感值以实现调节所述低噪声放大器100的输入放射系数。所述第一级源极电感调节电路3使得本发明的低噪声放大器100在不同的增益下都较优的输入反射系数。
所述第一级源极电感调节电路3连接于所述第一晶体管M1的源极。
本实施例中，所述第一级源极电感调节电路3还包括第三晶体管M3和第四晶体管M4。所述第三晶体管M3和所述第四晶体管M4均为MOS管。所述电感包括第二电感L2和第三电感L3。第二电感L2和第三电感L3作为所述第一晶体管M1的源极电感，分别受所述第三晶体管M3和所述第四晶体管M4控制，可以实现高低增益下的源极电感切换，达到不同挡位都较优的输入反射系数。其中，所述第一电感L1、所述第二电感L2和所述第三电感L3均参与所述第一级共栅共源放大器1的输入匹配。当然，不限于此，在另外一种实施例中，所述第一级源极电感调节电路3设有的所述 电感的电感值参数可调。即所述第一级源极电感调节电路3设有的所述电感使用可以直接调节电感值的器件或模块。
所述第一级源极电感调节电路3的内部电路连接关系为：
所述第二电感L2的第一端连接至所述第一晶体管M1的源极。所述第二电感L2的第二端分别连接至所述第三晶体管M3的漏极和所述第三电感L3的第一端。
所述第三晶体管M3的栅极用于连接外部的第一控制信号K1。所述第三晶体管M3的源极接地GND。
所述第三电感L3的第二端连接至所述第四晶体管M4的漏极。
所述第四晶体管M4的栅极用于连接外部的第二控制信号K2。所述第四晶体管M4的源极接地GND。
所述负载切换电路4用于调节所述负载电阻的电阻值以实现调节所述低噪声放大器100的增益。
所述负载切换电路4跨接于所述第一级共栅共源放大器1的输出端与所述第二级共栅共源放大器2的输入端之间。该设置可以减小对本发明的低噪声放大器100的输入反射系数和输出反射系数的影响。
本实施例中，所述负载切换电路4包括第五晶体管M5、第六晶体管M6以及第七晶体管M7。所述第五晶体管M5、所述第六晶体管M6以及所述第七晶体管M7均为MOS管。所述负载电阻包括第二电阻R2、第三电阻R3和第四电阻R4。所述负载切换电路4采用第二电阻R2、第三电阻R3和第四电阻R4三种电阻作为三档调节，通过调节所述负载电阻的电阻值可以改变增益大小，实现了负载切换功能。当然，不限于此，可以根据低噪声放大器100的增益的实际设计需要，可以设计多档调节，电阻和晶体管组成的支路个数可以根据增益挡位的需求自由设计。而在另外一种实施例中，所述负载电阻的电阻值参数可调。即所述负载电阻采用可变电阻实现。
所述负载切换电路4的内部电路连接关系为：
所述第二电阻R2的第一端分别连接至所述第三电阻R3的第 一端、所述第四电阻R4的第一端、所述第一级共栅共源放大器1的输出端以及所述第二级共栅共源放大器2的输入端。
所述第二电阻R2的第二端连接至所述第五晶体管M5的漏极。
所述第五晶体管M5的栅极用于连接外部的第三控制信号K3。所述第五晶体管M5的源极接地GND。
所述第三电阻R3的第二端连接至所述第六晶体管M6的漏极。
所述第六晶体管M6的栅极用于连接外部的第四控制信号K4。所述第六晶体管M6的源极接地GND。
所述第四电阻R4的第二端连接至所述第七晶体管M7的漏极。
所述第七晶体管M7的栅极用于连接外部的第五控制信号K5。所述第七晶体管M7的源极接地GND。
所述旁路模式电路5用于拓宽所述射频输入端RFIIN的输入信号的动态范围。所述旁路模式电路5的第一端连接至所述射频输入端RFIIN。所述旁路模式电路5的第二端连接至所述第二级共栅共源放大器2的输出端。所述旁路模式电路5的第三端连接至所述射频输出端RFOUT。
本实施例中,所述第一电阻R1的电阻值参数可调。所述第一电阻R1的两端分别用于连接所述射频输入端RFIIN和所述射频输出端RFOUT。
所述旁路模式电路5的工作原理为:
所述射频输入端RFIIN接收的射频信号在预设的范围内时,所述旁路模式电路5将所述第二级共栅共源放大器2的输出端与所述射频输出端RFOUT连通并将所述第一电阻R1的两端断开。
所述射频输入端RFIIN接收的射频信号高于预设的范围时。所述旁路模式电路5将所述第二级共栅共源放大器2的输出端与所述射频输出端RFOUT断开并将所述第一电阻R1的两端分别与所述射频输入端RFIIN和所述射频输出端RFOUT连通。
本实施例中，所述旁路模式电路5还包括第十晶体管M10、第十一晶体管M11和所述第十二晶体M12管。所述第十晶体管M10、所述第十一晶体管M11和所述第十二晶体M12管均为MOS管。 所述旁路模式电路5的内部电路连接关系为：
所述第十晶体管M10的源极连接至所述射频输入端RFIIN。所述第十晶体管M10的漏极连接至所述第一电阻R1的第一端。所述第十晶体管M10的栅极用于连接外部的第六控制信号K6。
所述第十一晶体管M11的源极连接至所述第一电阻R1的第二端。所述第十一晶体管M11的漏极连接至所述射频输出端RFOUT。所述第十一晶体管M11的栅极用于连接外部的第七控制信号K7。
所述第十二晶体M12管的源极连接至所述第二级共栅共源放大器2的输出端。所述第十二晶体M12管的漏极连接至所述射频输出端RFOUT。所述第十二晶体M12管的栅极用于连接外部的第八控制信号K8。
所述旁路模式电路5的所述第十晶体管M10、所述第十一晶体管M11和所述第一电阻R1组成了无源模式的衰减支路，在衰减挡位下，关闭放大器电路，可以降低电路功耗，同时获得更高的线性度指标。
所述旁路模式电路5的工作过程为：
所述第十晶体管M10、所述第十一晶体管M11和第十二晶体M12管起到射频开关作用。
所述低噪声放大器100两级通路(所述第一级共栅共源放大器1和所述第二级共栅共源放大器2)在正常放大状态工作下，即射频信号在预设的范围内时，所述第十晶体管M10关闭、所述第十一晶体管M11关闭，所述第十二晶体M12管导通。在旁路模式下，即射频信号高于预设的范围时，所述第十晶体管M10导通、所述第十一晶体管M11导通，所述第十二晶体M12管关闭，通过调节所述第一电阻R1的阻值变化，达到了不同挡位的衰减作用，用来处理比较大的输入射频信号。
本发明的实施例还提供一种射频芯片，所述射频芯片包括所述低噪声放大器100。
需要指出的是，本发明采用的相关电路、电阻、电容、电感、及晶体管均为本领域常用的电路、元器件，对应的具体的指标和参 数根据实际应用进行调整，在此，不作详细赘述。
与相关技术相比，本发明的低噪声放大器和射频芯片通过采用两级共栅共源放大器的结构，即第一级共栅共源放大器和第二级共栅共源放大器，该结构满足低噪声性能，同时也提高了增益，进一步降低了噪声系数和系统灵敏度，使本发明的低噪声放大器可以处理更微弱的射频信号。本发明的低噪声放大器和射频芯片还通过采用所述第一级源极电感调节电路连接于第一级共栅共源放大器的所述第一晶体管的源极，调节所述电感的电感值以实现调节所述低噪声放大器的输入放射系数，从而使得本发明的低噪声放大器在不同的增益下都较优的输入反射系数。本发明的低噪声放大器和射频芯片还通过采用所述负载切换电路调节所述负载电阻的电阻值以实现调节所述低噪声放大器的增益；所述负载切换电路接于所述第一级共栅共源放大器的输出端与所述第二级共栅共源放大器的输入端之间，可以减小对本发明的低噪声放大器的输入反射系数和输出反射系数的影响。本发明的低噪声放大器和射频芯片还通过所述旁路模式电路，使得本发明的低噪声放大器可以处理高于预设的范围的射频信号，即可以处理更大的输入的射频信号，从而达到了输入的动态范围拓宽。因此，采用本发明的低噪声放大器和射频芯片的电路增益可调且输入动态范围宽。
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围，本领域的普通技术人员应当理解，在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换，均应涵盖在本发明的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (10)

  1. 一种低噪声放大器，其包括依次连接的射频输入端、第一电感、第一级共栅共源放大器、第二级共栅共源放大器以及射频输出端，所述第一级共栅共源放大器包括用作共源晶体管的第一晶体管和用作共栅晶体管的第二晶体管；其特征在于，
    所述低噪声放大器还包括设有电感的第一级源极电感调节电路、设有负载电阻的负载切换电路以及设有第一电阻的旁路模式电路；
    所述第一级源极电感调节电路连接于所述第一晶体管的源极，用于调节所述电感的电感值以实现调节所述低噪声放大器的输入放射系数；
    所述负载切换电路跨接于所述第一级共栅共源放大器的输出端与所述第二级共栅共源放大器的输入端之间，用于调节所述负载电阻的电阻值以实现调节所述低噪声放大器的增益；
    所述旁路模式电路，用于拓宽所述射频输入端的输入信号的动态范围；所述旁路模式电路的第一端连接至所述射频输入端，所述旁路模式电路的第二端连接至所述第二级共栅共源放大器的输出端，所述旁路模式电路的第三端连接至所述射频输出端；所述第一电阻的两端分别用于连接所述射频输入端和所述射频输出端；所述射频输入端接收的射频信号在预设的范围内时，所述旁路模式电路将所述第二级共栅共源放大器的输出端与所述射频输出端连通并将所述第一电阻的两端断开；所述射频输入端接收的射频信号高于预设的范围时，所述旁路模式电路将所述第二级共栅共源放大器的输出端与所述射频输出端断开并将所述第一电阻的两端分别与所述射频输入端和所述射频输出端连通。
  2. 根据权利要求1所述的低噪声放大器，其特征在于，所述第一电阻的电阻值参数可调。
  3. 根据权利要求1所述的低噪声放大器，其特征在于，所述第一级源极电感调节电路设有的所述电感的电感值参数可调。
  4. 根据权利要求1所述的低噪声放大器，其特征在于，所述 第一级源极电感调节电路还包括第三晶体管和第四晶体管，所述电感包括第二电感和第三电感；
    所述第二电感的第一端连接至所述第一晶体管的源极，所述第二电感的第二端分别连接至所述第三晶体管的漏极和所述第三电感的第一端；
    所述第三晶体管的栅极用于连接外部的第一控制信号，所述第三晶体管的源极接地；
    所述第三电感的第二端连接至所述第四晶体管的漏极；
    所述第四晶体管的栅极用于连接外部的第二控制信号，所述第四晶体管的源极接地。
  5. 根据权利要求1所述的低噪声放大器，其特征在于，所述负载电阻的电阻值参数可调。
  6. 根据权利要求1所述的低噪声放大器，其特征在于，所述负载切换电路包括第五晶体管、第六晶体管以及第七晶体管，所述负载电阻包括第二电阻、第三电阻和第四电阻；
    所述第二电阻的第一端分别连接至所述第三电阻的第一端、所述第四电阻的第一端、所述第一级共栅共源放大器的输出端以及所述第二级共栅共源放大器的输入端；
    所述第二电阻的第二端连接至所述第五晶体管的漏极；
    所述第五晶体管的栅极用于连接外部的第三控制信号，所述第五晶体管的源极接地；
    所述第三电阻的第二端连接至所述第六晶体管的漏极；
    所述第六晶体管的栅极用于连接外部的第四控制信号，所述第六晶体管的源极接地；
    所述第四电阻的第二端连接至所述第七晶体管的漏极；
    所述第七晶体管的栅极用于连接外部的第五控制信号，所述第七晶体管的源极接地。
  7. 根据权利要求1所述的低噪声放大器，其特征在于，所述旁路模式电路还包括第十晶体管、第十一晶体管和第十二晶体管；
    所述第十晶体管的源极连接至所述射频输入端，所述第十晶体 管的漏极连接至所述第一电阻的第一端，所述第十晶体管的栅极用于连接外部的第六控制信号；
    所述第十一晶体管的源极连接至所述第一电阻的第二端，所述第十一晶体管的漏极连接至所述射频输出端，所述第十一晶体管的栅极用于连接外部的第七控制信号；
    所述第十二晶体管的源极连接至所述第二级共栅共源放大器的输出端，所述第十二晶体管的漏极连接至所述射频输出端，所述第十二晶体管的栅极用于连接外部的第八控制信号。
  8. 根据权利要求1所述的低噪声放大器，其特征在于，所述第一级共栅共源放大器还包括第一电容、第二电容、第三电容、第一偏置电阻和第四电感；
    所述第一电容的第一端作为所述第一级共栅共源放大器的输入端，所述第一电容的第二端分别连接至所述第一偏置电阻的第二端和所述第一晶体管的栅极；
    所述第一偏置电阻的第一端用于连接外部的第一偏置电压；
    所述第一晶体管的源极用于连接所述第一级源极电感调节电路，所述第一晶体管的漏极连接至所述第二晶体管的源极；
    所述第二晶体管的栅极用于连接外部的第二偏置电压，所述第二晶体管的漏极分别连接至所述第四电感的第二端、所述第二电容的第二端和所述第三电容的第一端；
    所述第四电感的第一端和所述第二电容的第一端均连接至电源电压；
    所述第三电容的第二端作为所述第一级共栅共源放大器的输出端。
  9. 根据权利要求1所述的低噪声放大器，其特征在于，所述第二级共栅共源放大器包括第四电容、第五电容、第六电容、第二偏置电阻、第五电感、第八晶体管和第九晶体管；
    所述第四电容的第一端作为所述第二级共栅共源放大器的输入端，所述第四电容的第二端分别连接至所述第二偏置电阻的第二端和所述第八晶体管的栅极；
    所述第二偏置电阻的第一端用于连接外部的第三偏置电压；
    所述第八晶体管的源极接地，所述第八晶体管的漏极连接至所述第九晶体管的源极；
    所述第九晶体管的栅极用于连接外部的第四偏置电压，所述第九晶体管的漏极分别连接至所述第五电感的第二端、所述第五电容的第二端和所述第六电容的第一端；
    所述第五电感的第一端和所述第六电容的第一端均连接至电源电压；
    所述第六电容的第二端作为所述第一级共栅共源放大器的输出端。
  10. 一种射频芯片，其特征在于，所述射频芯片包括如权利要求1-9中任意一项所述的低噪声放大器。
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