WO2024055651A1 - 无源光网络的数据同步方法、装置及数据同步系统 - Google Patents

无源光网络的数据同步方法、装置及数据同步系统 Download PDF

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Publication number
WO2024055651A1
WO2024055651A1 PCT/CN2023/099984 CN2023099984W WO2024055651A1 WO 2024055651 A1 WO2024055651 A1 WO 2024055651A1 CN 2023099984 W CN2023099984 W CN 2023099984W WO 2024055651 A1 WO2024055651 A1 WO 2024055651A1
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Prior art keywords
synchronization
data
passive optical
optical network
data signals
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PCT/CN2023/099984
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English (en)
French (fr)
Inventor
杨波
李明生
黄新刚
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中兴通讯股份有限公司
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Publication of WO2024055651A1 publication Critical patent/WO2024055651A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J14/00—Optical multiplex systems
    • H04J14/02—Wavelength-division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/43—Loop networks with decentralised control with synchronous transmission, e.g. time division multiplex [TDM], slotted rings
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes

Definitions

  • the present disclosure relates to the technical field of passive optical networks, and in particular, to a data synchronization method, device and data synchronization system for a passive optical network.
  • optical Access Network Optical Access Network
  • TDM-PON Time Division Multiplexin-Passive Optical Network
  • PON Passive Optical Network
  • the first aspect is to provide a data synchronization method for passive optical networks.
  • the method includes: an alignment recovery step: synchronously aligning multiple channels of first data signals, and recovering the aligned multiple channels of first data signals into a channel of second data signals; performing passive calibration on the second data signals.
  • Optical network synchronization verification if the second data signal does not pass the passive optical network synchronization verification, go to the alignment recovery step, or, after the second data signal passes the passive optical network In the case of synchronization verification, it is determined that the synchronization is successful.
  • a data synchronization device for a passive optical network includes a data recovery module and a passive optical network synchronization module.
  • the data recovery module is used to perform the alignment recovery step.
  • the alignment restoration step includes synchronously aligning multiple channels of first data signals, and restoring the aligned multiple channels of first data signals into one channel of second data signals.
  • the passive optical network synchronization module is used to perform passive optical network synchronization verification on the second data signal; when the second data signal does not pass the passive optical network synchronization verification, indicate the data
  • the recovery module proceeds to perform the alignment recovery step; or, in the case where the second data signal passes the passive optical network synchronization verification, it is determined that the synchronization is successful.
  • an electronic device in a third aspect, includes a processor and a memory.
  • the memory is used to store instructions executable by the processor.
  • the processor is configured to execute the data synchronization method of the passive optical network as described in the first aspect and any embodiment thereof.
  • the fourth aspect also provides a data synchronization system.
  • the data synchronization system includes a data splitting device, a first passive optical network device, a second passive optical network device and a synchronization device connected in sequence. Said number
  • the data splitting device is used to split the third data signal into multiple first data signals, and pass the multiple first data signals through the first passive optical network equipment and the second passive optical network.
  • the device transmits to the synchronization device.
  • the synchronization device is used to perform the data synchronization method of the passive optical network as in the first aspect and any embodiment thereof.
  • a computer-readable storage medium is also provided.
  • Computer instructions are stored on the computer-readable storage medium.
  • the electronic device is caused to perform the data synchronization method of the passive optical network as in the first aspect and any embodiment thereof.
  • Figure 1 is a schematic architectural diagram of a passive optical network according to some embodiments
  • Figure 2 is a schematic diagram of a downlink PON frame according to some embodiments.
  • Figure 3 is a schematic diagram of an uplink PON frame according to some embodiments.
  • Figure 4 is an architectural schematic diagram of a data synchronization system according to some embodiments.
  • Figure 5 is a flow chart of a data synchronization method in a passive optical network according to some embodiments
  • Figure 6 is a schematic diagram of the splitting result of a 50G PON downlink frame according to some embodiments.
  • Figure 7 is a schematic diagram of the operation of a downlink PON synchronization state machine according to some embodiments.
  • Figure 8 is another operational schematic diagram of the downlink PON synchronization state machine according to some embodiments.
  • Figure 9 is a schematic structural diagram of a synchronization device according to some embodiments.
  • Figure 10 is a schematic structural diagram of an electronic device according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • Passive Optical Network is a single-fiber bidirectional optical access network (Optical Access Network, OAN) that adopts point to multipoint (P2MP) structure.
  • Figure 1 is a schematic architectural diagram of a passive optical network according to some embodiments.
  • the PON system mainly consists of three parts: optical line terminal (Optical Line Terminal, OLT), optical distribution network (Optical Distribution Network, ODN) and user-end optical network unit (Optical Network Unit (ONU).
  • OLT is located at the central office and is responsible for allocating and controlling channel connections, and performing real-time monitoring, management and maintenance of the entire PON.
  • the ONU is located at the user end (or user premises side) to implement access to user terminals.
  • ODN is composed of Passive Optical Splitter (POS) and optical fiber lines to realize network connection between OLT and each ONU.
  • POS Passive Optical Splitter
  • the downlink data signals sent by the OLT reach each ONU through the ODN.
  • the upstream data signal sent by each ONU only reaches the OLT and does not reach other ONUs.
  • FIG 2 is a schematic diagram of a downlink PON frame according to some embodiments.
  • the downlink PON frame includes multiple codewords (eg, codeword 1 to codeword N in Figure 2).
  • the plurality of codewords in the downlink PON frame respectively include a first payload (Payload) and a first parity field.
  • the first payload includes data that the OLT needs to pass to the ONU (eg user data).
  • the first parity field is used to check the accuracy of codeword transmission.
  • the downlink physical synchronization block downstream (PSBd) is also included in addition to the first codeword in the downlink PON frame (ie, codeword 1 in Figure 2).
  • PSBd downlink physical synchronization block downstream
  • the remaining codewords in the PON frame do not include PSBd.
  • the codewords in the downlink PON frame can be protected using the Forward Error Correction (FEC) method.
  • FEC Forward Error Correction
  • the codewords protected using the FEC method can be referred to as FEC codewords.
  • PSBd includes a physical synchronization sequence (Psync) field, a superframe counter structure (SFC structure) field and an operational control structure (OC structure) field.
  • Psync physical synchronization sequence
  • SFC structure superframe counter structure
  • OC structure operational control structure
  • the Psync field is used to identify the downlink data frame generated by the OLT. That is to say, the Psync field is used by passive optical network equipment (such as ONU) to synchronize the boundaries of PON frames in downlink data signals.
  • the Psync field is used to carry a preset bit sequence. In the relevant standards, the bit sequence of the Psync field is encoded as 0xC5E51840FD59BB49.
  • the SFC structure field includes SFC and Hybrid Error Correction (Hybrid Error Correction, HEC) fields.
  • the SFC value of each downlink PON frame is increased by 1 relative to the SFC value of the previous downlink PON frame.
  • the SFC value of a certain downlink PON frame reaches the maximum, the SFC value of the next downlink PON frame after the downlink PON frame is configured as 0.
  • FIG 3 is a schematic diagram of an uplink PON frame according to some embodiments.
  • the uplink PON frame includes multiple codewords (for example, codeword 1 to codeword N in Figure 3).
  • the plurality of codewords in the uplink PON frame respectively include a second payload and a second parity field.
  • the second payload includes data that the ONU needs to pass to the OLT (eg user data).
  • the second parity field is used to verify the accuracy of codeword transmission in the uplink PON frame.
  • the first codeword in the upstream PON frame i.e. codeword 1 in Figure 3) also includes the upstream physical synchronization block upstream (PSBu), and the remaining codewords in the upstream PON frame (i.e. codeword 1 in Figure 3) Codeword 2 to codeword N) do not include PSBu.
  • PSBu physical synchronization block upstream
  • PSBu includes a preamble and a delimiter (Delimiter).
  • the preamble is used to discover burst signals through the autocorrelation peak detection method, and the delimiter is used to indicate the start and end bits of the preamble.
  • the preamble and delimiter may include signaling data used to determine the presence of a physical interface (PHY) burst signal from the ONU, delineate the PHY burst signal, and determine the signal clock for proper recovery. send.
  • PHY physical interface
  • SerDes serializer/deserializer
  • the equipment electrical interface between the 50G optical module and the OLT and ONU can include 50G non-return to zero (NRZ), 50G four-level pulse amplitude modulation (Pulse Amplitude Modulation 4, PAM4) and 2 ⁇ 25G NRZ and other three SerDes interface forms.
  • NRZ non-return to zero
  • PAM4 pulse Amplitude Modulation 4
  • 2 ⁇ 25G NRZ interface form is relatively mature and has minimal damage to electrical signal quality. It has been widely used in the field of data communication optical modules and is also an excellent interface form in 50G PON systems.
  • the main purpose is to split the characteristic codeword in the PON signal (the characteristic codeword is PSBu in the uplink data signal, and the characteristic codeword is PSBd in the downlink data signal) into multiple parts by bits or bytes, as Alignment flags for multiple low-speed data signals, but this will shorten the length of the alignment flags.
  • the data rate of passive optical networks increases, the amount of data continues to increase.
  • false synchronization is prone to occur.
  • false synchronization is prone to occur during the synchronization process of multiple parallel low-speed data signals.
  • some embodiments of the present disclosure provide a data synchronization method for a passive optical network.
  • the idea of this method is to perform PON synchronization verification on the high-speed data signals recovered from the data to determine whether false synchronization occurs; and in the case of false synchronization, re-align the multiple low-speed data signals to recover.
  • there is no need to increase the length of the signature codeword thus avoiding the introduction of additional transmission overhead.
  • FEC decoding can be skipped to complete PON signal synchronization first to reduce signal processing delay.
  • FIG. 4 is a schematic architectural diagram of a data synchronization system according to some embodiments.
  • the above data synchronization method is applicable to the data synchronization system 40 .
  • the data synchronization system 40 includes: a data splitting device 401 , a first passive optical network device 402 , a second passive optical network device 403 and a synchronization device 404 .
  • the first passive optical network device 402 may include a first optical module 4021
  • the second passive optical network device 403 may include a second optical module 4031.
  • an optical module (such as the first optical module 4021 or the second optical module 4031) may be used to perform mutual conversion of optical signals and electrical signals.
  • the optical module may be a pluggable optical module, or an onboard optical component, which is not limited in this disclosure.
  • the first passive optical network device 402 may be an OLT, and the second passive optical network device 403 may be an ONU; during the uplink data transmission process, the first passive optical network device 402 may be an OLT. 402 may be an ONU, and the second passive optical network device 403 may be an OLT. It can be understood that the first passive optical network device 402 and the second passive optical network device 403 can communicate through ODN.
  • the data splitting device 401 is connected to the first optical module 4021 in the first passive optical network device 402.
  • the data splitting device 401 is used to split one high-speed electrical signal into multiple low-speed electrical signals, and transmit the multiple low-speed electrical signals to the first optical module 4021.
  • the first optical module 4021 is connected to the second optical module 4031 in the second passive optical network device 403.
  • the first optical module 4021 is used to convert multiple low-speed electrical signals into one high-speed optical signal, and transmit the high-speed optical signal to the second optical module 4031.
  • the second optical module 4031 is connected to the synchronization device 404 .
  • the second optical module 4031 is used to convert one high-speed optical signal into multiple low-speed electrical signals, and transmit the multiple low-speed electrical signals to the synchronization device 404 .
  • the synchronization device 404 is used to restore multiple low-speed electrical signals into one high-speed electrical signal.
  • the synchronization device 404 can restore multiple low-speed electrical signals to a correct high-speed electrical signal by executing the data synchronization method in some embodiments of the present disclosure.
  • the synchronization device 404 may be independent of the second passive optical network device 403 , or may be integrated in the second passive optical network device 403 .
  • the data splitting device 401 may be independent of the first passive optical network device 402 , or may be integrated in the first passive optical network device 402 .
  • Some embodiments of the present disclosure provide a data synchronization method for a passive optical network, which method can be applied to the synchronization device 404 in the data synchronization system 40 shown in FIG. 4 .
  • the method includes steps 101 to 103 (S101 ⁇ S103).
  • step 101 an alignment recovery step is performed.
  • the alignment recovery step includes: synchronously aligning multiple channels of first data signals, and recovering the aligned multiple channels of first data signals into one channel of second data signals.
  • the multiple first data signals can be obtained by splitting the third data signal.
  • the splitting method can be splitting in single-byte units, splitting in single-bit units, splitting in double-byte units, or splitting in units of half the length of Psync. This disclosure does not do this. limited.
  • the third data signal includes one or more consecutive PON frames.
  • Splitting the third data signal can be understood as splitting the PON frame in the third data signal.
  • each first data signal includes a split part of the PON frame.
  • the split part of the PON frame may be called a PON subframe in the following.
  • Figure 6 is a schematic diagram of a splitting result of a 50G PON downlink frame according to some embodiments.
  • the 50G PON downlink frame includes an 8-byte Psync field and an 8-byte SFC structure. field, an 8-byte OC structure field and a 2n-byte payload (such as the first payload).
  • the first PON subframe includes the even bytes of the Psync field, the even bytes of the SFC structure field, and the even numbers of the OC structure field in the 50G PON downlink frame. Bytes and an even number of bytes for the Payload field.
  • the second PON subframe includes the odd bytes of the Psync field, the odd bytes of the SFC structure field, the odd bytes of the OC structure field and the odd bytes of the Payload field in the 50G PON downlink frame.
  • each first data signal needs to carry corresponding synchronization information so that the multiple first data signals can be synchronized and aligned.
  • the synchronization information may have different names, such as synchronization header, alignment flag, etc., which is not limited in this disclosure. It can be understood that the synchronization information corresponding to the multiple first data signals is also obtained by splitting the target information carried by the third data signal.
  • the synchronization information corresponding to each first data signal is obtained by splitting all or part of the fields in the PSBu.
  • the synchronization information corresponding to each first data signal can be obtained by splitting the delimiters in the PSBu.
  • the synchronization information corresponding to each first data signal is obtained by splitting all or part of the fields in the PSBd.
  • the synchronization information corresponding to each first data signal can be obtained by splitting Psync in PSBd.
  • the synchronization information corresponding to the first data signal 11 is a combination of Psync Byte0, Psync Byte2, Psync Byte4, and Psync Byte6d; the first data signal 12 corresponds to
  • the synchronization information is a combination of Psync Byte1, Psync Byte3, Psync Byte5, and Psync Byte7.
  • Pysnc is 0xC5E51840FD59BB49
  • the synchronization information Pysnc_lane0 corresponding to the first data signal 11 is 0xC518FDBB
  • the synchronization information Pysnc_lane1 corresponding to the first data signal 12 is 0xE5405949.
  • synchronizing and aligning each of the first data signals among the multiple first data signals includes: based on the first corresponding relationship, performing synchronization on each of the first data signals among the multiple first data signals.
  • searching for synchronization information the first correspondence relationship is used to indicate the synchronization information corresponding to each first data signal; after successfully searching for the synchronization information corresponding to each first data signal, based on the searched first data signals Corresponding synchronization information is used to align each first data signal.
  • the first correspondence relationship may be pre-configured in the synchronization device 404. Or, taking the data synchronization system 40 shown in FIG. 4 as an example, the first corresponding relationship can be split between the synchronization device 404 and the data.
  • the devices 401 negotiate with each other to determine.
  • the first optical module 4021 and/or the second optical module 4031 may also participate in the negotiation process of the first correspondence relationship.
  • the synchronization device 404 only needs to search for the synchronization information in each first data signal according to one corresponding relationship, which can reduce the search complexity and simplify the structure of the synchronization device 404 .
  • the data synchronization method further includes: if the synchronization information corresponding to each first data signal is not successfully searched after the first preset time period, based on the second correspondence relationship, synchronization information of the multiple first data signals is Each first data signal in the first data signal performs a search for synchronization information.
  • the second correspondence relationship is used to indicate the synchronization information corresponding to each first data signal, and at least one first data signal is in the second correspondence relationship.
  • the corresponding synchronization signal is different from the corresponding synchronization information in the first correspondence relationship.
  • the above-mentioned first preset duration may be configured in advance, or the above-mentioned first preset duration may be determined by the synchronization device 404 according to its own data processing conditions, which is not limited in this disclosure.
  • the synchronization device 404 can quickly and successfully search for the synchronization information corresponding to each first data signal by changing the corresponding relationship used in the synchronization alignment process (ie, changing to the second corresponding relationship).
  • the first corresponding relationship is used to indicate that the synchronization information corresponding to the first data signal 11 is 0xC518FDBB, and the synchronization information corresponding to the first data signal 12 is 0xE5405949;
  • the second corresponding relationship is used to indicate that the synchronization information corresponding to the first data signal 11 is 0xE5405949, and the synchronization information corresponding to the first data signal 12 is 0xC518FDBB.
  • the synchronization device 404 can first search for 0xC518FDBB in the first data signal 11 and search for 0xE5405949 in the first data signal 12 based on the first corresponding relationship.
  • the synchronization device 404 can search for 0xE5405949 in the first data signal 11 and search for 0xC518FDBB in the first data signal 12 based on the second corresponding relationship.
  • synchronizing and aligning each of the first data signals among the multiple first data signals includes: performing multiple search operations simultaneously; each search operation is used to perform a corresponding relationship based on the search operation, Search for synchronization information on each of the multiple first data signals; different search operations correspond to different correspondences, and the correspondence is used to indicate the synchronization information corresponding to each first data signal; in the target After the search operation successfully searches for the synchronization information corresponding to each first data signal, based on the synchronization information corresponding to each first data signal searched for by the target search operation, alignment processing is performed on each first data signal.
  • the target search operation is: Any one of the plurality of search operations.
  • the synchronization device 404 can simultaneously search for synchronization information in each first data signal according to multiple corresponding relationships, so as to quickly and successfully search for synchronization information corresponding to each first data signal.
  • the synchronization device 404 may perform the first search operation and the second search operation simultaneously.
  • the first search operation is used to search for 0xC518FDBB in the first data signal 11 and for 0xE5405949 in the first data signal 12 .
  • the second search operation is used to search for 0xE5405949 in the first data signal 11 and 0xC518FDBB in the first data signal 12 .
  • the first data signal 11 and the first data signal 12 can be aligned according to the position of 0xE5405949 in the first data signal 11 and the position of 0xC518FDBB in the first data signal 12 .
  • searching for corresponding synchronization information in the first data signal can be understood as searching for a target bit sequence matching the synchronization information in the first data signal.
  • matching the target bit sequence with the synchronization information may mean that the target bit sequence and the synchronization information are exactly the same; or that the number of different bits between the target bit sequence and the synchronization information is less than or equal to a preset number.
  • the preset number may be 2.
  • performing alignment processing on multiple first data signals can be understood as: performing alignment processing on multiple first data signals based on the position of the first bit in the synchronization information searched out in each first data signal.
  • the aligned multiple first data signals are restored to one second data signal.
  • the preset condition may include: successfully searching for corresponding synchronization information from each first data signal for K consecutive times, where K is a positive integer. It can be understood that when K is greater than 1, it is necessary to successfully search for the corresponding synchronization information from each channel of the first data signal multiple times in a row before data recovery is performed on the multiple channels of first data information, which can reduce The probability of false synchronization of multiple first data signals. Moreover, the larger K is, the lower the probability of false synchronization of multiple first data signals occurs.
  • restoring the aligned multiple first data signals into one second data signal may include: combining the multiple first data signals into one second data signal in an intermittent manner.
  • the method of data recovery corresponds to the method of data splitting. In other words, data is split in bytes as a unit, and data recovery is also in bytes as a unit. Data is split in bits as a unit, and data recovery is also in bits as a unit.
  • the synchronization information Pysnc_lane0 is successfully searched for the first data signal 11
  • the synchronization information Pysnc_lane0 is 0xC518FDBB
  • the synchronization information Pysnc_lane1 is successfully searched for the first data signal 12
  • the synchronization information Pysnc_lane1 is 0xE5405949. Since Pysnc_lane0 is composed of even bytes in Pysnc, Pysnc_lane1 is composed of odd bytes in Pysnc.
  • the bytes in the first data signal 11 can be regarded as the even bytes in the second data signal, and the bytes in the first data signal 12 can be regarded as the odd bytes in the second data signal, so that the first data
  • the signal 11 and the first data signal 12 are combined into a second data signal in a byte interleaved manner.
  • the second data signal is the above-mentioned third data signal; but in the case of false synchronization, the second data signal is not the above-mentioned third data signal. .
  • step 102 PON synchronization verification is performed on the second data signal.
  • PON synchronization verification is performed on the second data signal through a PON synchronization state machine.
  • the states of the PON synchronization state machine include a search state, a pre-synchronization state, a synchronization state, and a re-synchronization state.
  • the PON synchronization state machine loses synchronization in any state, or when the PON synchronization state machine re-enters the search state, it is determined that the second data signal does not successfully pass the PON synchronization verification.
  • the PON synchronization state machine is in the synchronization state, it is determined that the second data signal passes the synchronization verification.
  • the target state can be any state of the PON synchronization state machine.
  • the PON synchronization state machine When the second data signal is an uplink data signal, the PON synchronization state machine may be called the uplink PON synchronization state machine; when the second data signal is a downlink data signal, the PON synchronization state machine may be called the downlink PON synchronization state. machine.
  • the verification mechanism adopted by the upstream PON synchronization state machine may be different from the verification mechanism adopted by the downlink PON synchronization state machine.
  • the verification mechanism adopted by the downlink PON synchronization state machine includes Psync verification and SFC verification.
  • Psync verification includes: searching for fields matching the preset Psync in the second data signal.
  • SFC verification includes: verifying whether the bit sequence of the preset number of digits after Psync constitutes a valid SFC structure.
  • the specific operation process of the downlink PON synchronization state machine includes:
  • the Psync field is searched in the second data signal. If it is confirmed that the searched Psync field matches the Psync field specified in the relevant standard, then verify that the Psync field in the second data signal Whether the subsequent bit sequence of the preset number of digits constitutes a valid SFC structure. If not, continue to remain in the search state and continue to search the Psync field; if yes, switch from the search state to the pre-synchronization state.
  • each PON frame is identified in the second data signal, and Psync verification and SFC verification are performed on each PON frame. If either Psync verification or SFC verification fails, it switches to the search state; if Psync verification and SFC verification succeed, it switches to the synchronization state.
  • the verification mechanism used by the downlink PON synchronization state machine includes Psync verification, SFC verification and FEC verification.
  • Psync verification The specific implementation details of Psync verification and SFC verification can be referred to above and will not be repeated here.
  • FEC verification may include: determining the boundary position of the FEC codeword according to the above-mentioned Psync field in the downstream data stream, and then performing decoding verification on each FEC codeword.
  • the specific operation process of the downlink PON synchronization state machine includes:
  • the Psync field is searched in the second data signal. If it is confirmed that the searched Psync field matches the Psync field specified in the relevant standards, it is verified whether the bit sequence of the preset number of digits after the Psync field in the second data signal constitutes a valid SFC structure. If not, continue to remain in the search state and continue to search the Psync field; if yes, switch from the search state to the pre-synchronization state.
  • decoding and checking are performed on the FEC codewords in the second data signal; and SFC verification is performed on each PON frame in the second data signal.
  • decoding of an FEC codeword fails, the system remains in the pre-synchronization state and continues to perform decoding verification on the next FEC codeword in the second data signal. If there is an FEC codeword that passes the decoding test among the L FEC codewords, and the SFC verification is successful, the state is switched from the pre-synchronization state to the synchronization state; or, if there is no FEC code that passes the decoding test among the L FEC codewords. word, or SFC verification fails, it switches to the search state.
  • L is a positive integer.
  • Psync verification and SFC verification are performed on each PON frame in the second data signal. If Psync verification and SFC verification are successful, they remain in synchronization state; if Psync verification If the authentication fails and/or the SFC verification fails, it switches from the synchronization state to the resynchronization state.
  • the verification mechanism for the upstream PON synchronization state machine can be judged based on the successful delimitation of the synchronization header defining the delimiter and the successful verification of the frame sublayer (framing sublayer, FS) header of the physical frame payload. Due to the uplink burst signal of the PON system, each uplink burst frame needs to be resynchronized.
  • the frame sublayer (FS) of the physical frame payload here includes the FS frame header, the FS frame payload and the FS trailer.
  • the data in the FS frame header can be protected by the HEC code, so the data in the FS frame header can be HEC checked.
  • the data synchronization method further includes: if the second data signal does not successfully pass the PON synchronization verification within the second preset time period, send a signal to the optical module or passive optical network that generates the multiple first data signals.
  • the device sends instructions for resuming data recovery. It can be understood that if the second data signal fails to pass the PON synchronization verification for a long time, there may be errors in the multiple first data signals transmitted by the optical module or passive network equipment to the synchronization device 404 . Therefore, by sending instruction information for instructing to recover data to the optical module or passive optical network device, the optical module or passive optical network device can transmit correct multiple first data signals to the synchronization device 404 .
  • step 103 If the second data signal passes the PON synchronization verification, perform the following step 103; or, if the second data signal fails the PON synchronization verification, proceed to the above step 101.
  • step 103 if the second data signal passes the PON synchronization verification, it is determined that the synchronization is successful.
  • the PON frame may be identified from the second data signal.
  • PON synchronization verification is performed on the high-speed data signal recovered from the data to determine whether false synchronization occurs; and in the case of false synchronization, the multi-channel
  • the low-speed data signals undergo an alignment recovery step to improve the synchronization success rate of multiple low-speed data signals.
  • the above method can be implemented by the synchronization device 404.
  • Synchronization devices for passive optical networks In order to realize the above functions, it may include hardware structures or software modules corresponding to each function.
  • Those skilled in the art should easily imagine that some embodiments of the present disclosure can be implemented in hardware or a combination of hardware and computer software with the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein. Whether a function is performed by hardware or computer software driving the hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered to be beyond the scope of this disclosure.
  • Some embodiments of the present disclosure may divide the above data synchronization method in a passive optical network into functional modules according to the above method embodiments.
  • each functional module can be divided corresponding to each function.
  • the above integrated modules can be implemented in the form of hardware or software function modules. It should be noted that the division of modules in some embodiments of the present disclosure is schematic and is only a logical function division. In actual implementation, there may be other division methods.
  • FIG. 9 shows a possible structural schematic diagram of the synchronization device involved in the above embodiment.
  • the synchronization device 800 includes a data recovery module 801 and a PON synchronization module 802.
  • the data recovery module 801 is used to perform an alignment recovery step, which includes synchronously aligning multiple channels of first data signals, and recovering the aligned multiple channels of first data signals into a channel of second data signals.
  • the PON synchronization module 802 is used to perform PON synchronization verification on the second data signal; when the second data signal fails the PON synchronization verification, instruct the data recovery module 801 to perform the alignment recovery step; or, when the second data signal passes the PON synchronization verification In the case of PON synchronization verification, it is determined that the synchronization is successful.
  • the data recovery module 801 is configured to: search for synchronization information on each of the multiple first data signals based on a first correspondence relationship, where the first correspondence relationship is used to indicate each first data signal. Synchronization information corresponding to a data signal; after successfully searching for the synchronization information corresponding to each channel of the first data signal, based on the searched synchronization information corresponding to each channel of the first data signal, perform alignment processing on each channel of the first data signal .
  • the data recovery module 801 is further configured to: if the synchronization information corresponding to each first data signal has not been successfully searched after the first preset time period, based on the second correspondence relationship, Each first data signal among the multiple first data signals searches for synchronization information.
  • the second correspondence relationship is used to indicate the synchronization information corresponding to each first data signal, and at least one first data signal is in the second correspondence relationship.
  • the corresponding synchronization signal in is different from the corresponding synchronization information in the first correspondence relationship.
  • the data recovery module 801 is configured to: perform multiple search operations simultaneously; each search operation is used to retrieve each of the multiple first data signals based on the corresponding relationship corresponding to the search operation. Search for synchronization information; different search operations correspond to different correspondence relationships, and the correspondence relationships are used to indicate the synchronization information corresponding to each first data signal; in the target search operation, the synchronization information corresponding to each first data signal is successfully searched Afterwards, alignment processing is performed on each first data signal based on the synchronization information corresponding to each first data signal searched for by a target search operation, which is any search operation among multiple search operations.
  • the PON synchronization module 802 is configured to: perform PON synchronization verification on the second data signal through the PON synchronization state machine, which includes a search state, a pre-synchronization state, a synchronization state and a re-synchronization state; in the PON When the synchronization state machine loses synchronization in any state, or when the PON synchronization state machine re-enters the search state, it is determined that the second data signal has not successfully passed the PON synchronization verification.
  • the PON synchronization module 802 is also configured to: if the second data signal does not successfully pass the PON synchronization verification within the second preset time period, send the signal to the optical module or passive module that generates the multiple first data signals.
  • the optical network device sends instruction information for instructing to recover the data.
  • the synchronization device 800 of the passive optical network includes but is not limited to the unit modules listed above.
  • the specifically implemented functions of the above-mentioned functional units also include, but are not limited to, the functions corresponding to the method steps of the above-mentioned embodiments.
  • the modules of the data synchronization device 800 of the passive optical network please refer to the detailed descriptions of the corresponding method steps, which will not be described again here.
  • the electronic device 900 includes a processor 902 and a bus 904 .
  • the electronic device 900 may further include at least one of a memory 901 or a communication interface 903 .
  • Processor 902 may implement or execute the various illustrative logical blocks, modules, and circuits described in connection with this disclosure.
  • the processor 902 may be a central processing unit (Central Processing Unit, CPU), a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic devices, transistor logic devices, hardware components, or other random combination.
  • the processor 902 may also be a combination that implements computing functions.
  • the processor 902 may be a combination of one or more microprocessors, or a combination of a DSP and a microprocessor, or the like.
  • the communication interface 903 is used to connect with other devices through a communication network.
  • the communication network may be Ethernet, wireless access network, wireless local area network (Wireless Local Area Networks, WLAN), etc.
  • the memory 901 may be a read-only memory (Read-Only Memory, ROM) or other types of static storage devices that can store static information and instructions, a random access memory (Random Access Memory, RAM) or other types that can store information and instructions.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • the memory 901 may exist independently of the processor 902.
  • the memory 901 may be connected to the processor 902 through the bus 904 and be used to store instructions or program codes.
  • the processor 902 calls and executes instructions or program codes stored in the memory 901, it can implement the direct communication method provided by some embodiments of the present disclosure.
  • the memory 901 may also be integrated with the processor 902.
  • the bus 904 may be an Extended Industry Standard Architecture (EISA) bus or the like.
  • EISA Extended Industry Standard Architecture
  • the bus 904 can be divided into an address bus, a data bus, a control bus, etc. For ease of presentation, only one thick line is used in Figure 10, but it does not mean that there is only one bus or one type of bus.
  • Embodiments of the present disclosure also provide a computer-readable storage medium.
  • Computer instructions are stored in the computer-readable storage medium.
  • the computer-readable storage medium may include read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), read-only compact disc (Compact Disc Read-Only Memory, CD-ROM), Tapes, floppy disks and optical data storage devices, etc.
  • embodiments of the present disclosure may be implemented in hardware or special purpose circuitry, software, logic, or any combination thereof.
  • some embodiments may be implemented in hardware, while other embodiments may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the disclosure is not limited thereto.
  • Embodiments of the present disclosure may be implemented by a data processor of an information transmission device executing computer program instructions.
  • embodiments of the present disclosure are implemented by a processor entity, or hardware, or a combination of software and hardware executing computer program instructions.
  • Computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or written in any combination of one or more programming languages source code or object code.
  • ISA Instruction Set Architecture
  • Any logical flow block diagram in the accompanying drawings of the present disclosure may represent program steps, or may represent the interaction between
  • the computer program may be stored in a memory.
  • the memory may be of any type suitable for the local technical environment and may be implemented using any data storage technology, such as a read-only memory (ROM), a random access memory (RAM), an optical storage device and system (digital versatile disc (DVD) or (Compact Disk, CD)), etc., but the present disclosure is not limited thereto.
  • Computer-readable media may include non-transitory storage media.
  • the data processor may be any type of processor suitable for the local technical environment, such as a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (FPGA), or a processor based on a multi-core processor architecture, etc., but the present disclosure is not limited thereto.
  • a general-purpose computer such as a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (FPGA), or a processor based on a multi-core processor architecture, etc., but the present disclosure is not limited thereto.

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Abstract

提供一种无源光网络的数据同步方法。该方法包括：对齐恢复步骤：对多路第一数据信号进行同步对齐，并将对齐后的所述多路第一数据信号恢复成一路第二数据信号；对所述第二数据信号进行无源光网络同步验证；在所述第二数据信号未通过所述无源光网络同步验证的情况下，转至所述对齐恢复步骤；在所述第二数据信号通过所述无源光网络同步验证的情况下，确定同步成功。

Description

无源光网络的数据同步方法、装置及数据同步系统
本申请要求于2022年09月13日提交的、申请号为202211119421.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及无源光网络技术领域，尤其涉及一种无源光网络的数据同步方法、装置及数据同步系统。
背景技术
目前，基于时分复用无源光网络(Time Division Multiplexin-Passive Optical Network，TDM-PON)技术的光接入网络(Optical Access Network，OAN)迅速发展，无源光网络(Passive Optical Network，PON)系统需要较高的数据速率。
发明内容
第一方面，提供一种无源光网络的数据同步方法。该方法包括：对齐恢复步骤：对多路第一数据信号进行同步对齐，并将对齐后的所述多路第一数据信号恢复成一路第二数据信号；对所述第二数据信号进行无源光网络同步验证；在所述第二数据信号未通过所述无源光网络同步验证的情况下，转至所述对齐恢复步骤，或者，在所述第二数据信号通过所述无源光网络同步验证的情况下，确定同步成功。
第二方面，提供一种无源光网络的数据同步装置。该同步装置包括数据恢复模块和无源光网络同步模块。所述数据恢复模块用于执行对齐恢复步骤。所述对齐恢复步骤包括对多路第一数据信号进行同步对齐，并将对齐后的所述多路第一数据信号恢复成一路第二数据信号。所述无源光网络同步模块用于对所述第二数据信号进行无源光网络同步验证；在所述第二数据信号未通过所述无源光网络同步验证的情况下，指示所述数据恢复模块转至执行所述对齐恢复步骤；或者，在所述第二数据信号通过所述无源光网络同步验证的情况下，确定同步成功。
第三方面，还提供一种电子设备。该电子设备包括处理器和存储器。所述存储器用于存储所述处理器可执行指令。所述处理器被配置为执行如第一方面及其任一实施例的所述无源光网络的数据同步方法。
第四方面，还提供一种数据同步系统。所述数据同步系统包括依次连接的数据拆分装置、第一无源光网络设备、第二无源光网络设备以及同步装置。所述数 据拆分装置用于将第三数据信号拆分为多路第一数据信号，并将所述多路第一数据信号通过所述第一无源光网络设备和所述第二无源光网络设备传输至所述同步装置。所述同步装置用于执行如第一方面及其任一实施例的所述无源光网络的数据同步方法。
第五方面，还提供了一种计算机可读存储介质。所述计算机可读存储介质上存储有计算机指令。当所述计算机指令在电子设备上运行时，使得所述电子设备执行如第一方面及其任一实施例的所述无源光网络的数据同步方法。
附图说明
图1为根据一些实施例的一种无源光网络的架构示意图；
图2为根据一些实施例的一种下行PON帧的示意图；
图3为根据一些实施例的一种上行PON帧的示意图；
图4为根据一些实施例的一种数据同步系统的架构示意图；
图5为根据一些实施例的一种无源光网络的数据同步方法的流程图；
图6为根据一些实施例的一种50G PON下行帧的拆分结果的示意图；
图7为根据一些实施例的一种下行PON同步状态机的运行示意图；
图8为根据一些实施例的下行PON同步状态机的另一种运行示意图；
图9为根据一些实施例的一种同步装置的结构示意图；
图10为根据一些实施例的一种电子设备结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。然而，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
无源光网络(Passive Optical Network，PON)是一种采用点到多点(point to multipoint，P2MP)结构的单纤双向光接入网络(Optical Access Network，OAN)。图1为根据一些实施例的一种无源光网络的架构示意图。例如，如图1所示，PON系统主要由3部分构成：光线路终端(Optical Line Terminal，OLT)、光分配网络(Optical Distribution Network，ODN)和用户端的光网络单元(Optical  Network Unit，ONU)。OLT位于局端，以负责分配和控制信道的连接，并对整个PON进行实时监控、管理及维护。ONU位于用户端(或者用户驻地侧)，以实现用户终端的接入。ODN由无源分光器(Passive Optical Splitter，POS)和光纤线路构成，以实现OLT和各个ONU之间的网络连接。
在一些实施例中，在无源光网络的下行方向(即OLT到ONU的数据传输方向)上，OLT发送的下行数据信号通过ODN到达各个ONU。在无源光网络的上行方向(即ONU到OLT的数据传输方向)上，各个ONU发送的上行数据信号仅到达OLT，而不会到达其他ONU。
图2为根据一些实施例的一种下行PON帧的示意图。例如，如图2所示，下行PON帧包括多个码字(例如，图2中的码字1至码字N)。下行PON帧中的多个码字分别包括第一有效载荷(Payload)和第一奇偶校验字段。第一有效载荷包括OLT需要传递至ONU的数据(例如用户数据)。第一奇偶校验字段用于校验码字传输的准确性。在一些示例中，在下行PON帧中，除下行PON帧中的第一个码字(即图2中的码字1)还包括下行物理同步块(physical synchronization block downstream，PSBd)之外，下行PON帧中的其余码字(即图2中的码字2至码字N)不包括PSBd。在一些示例中，下行PON帧中的码字可以用前向纠错(Forward Error Correction，FEC)方法进行保护，采用FEC方法进行保护的码字可以简称为FEC码字。
参考图2，PSBd包括物理同步序列(physical synchronization sequence，Psync)字段，超帧计数器结构(superframe counter structure，SFC structure)字段和操作控制结构(operational control structure，OC structure)字段。
Psync字段用于识别OLT生成的下行数据帧。也就是说，Psync字段用于无源光网络设备(例如ONU)对下行数据信号中的PON帧的边界进行同步。Psync字段用于承载预设的比特序列。相关标准中，Psync字段的比特序列的编码为0xC5E51840FD59BB49。
SFC结构字段包括SFC和混合纠错(Hybrid Error Correction，HEC)字段。每个下行PON帧的SFC值相对于前一个下行PON帧的SFC值增加1。当某一个下行PON帧的SFC值达到最大时，在该下行PON帧之后的下一个下行PON帧的SFC值被配置为0。
图3为根据一些实施例的一种上行PON帧的示意图。例如，如图3所示， 上行PON帧包括多个码字(例如图3中的码字1至码字N)。上行PON帧中的多个码字分别包括第二有效载荷和第二奇偶校验字段。第二有效载荷包括ONU需要传递至OLT的数据(例如用户数据)。第二奇偶校验字段用于校验上行PON帧中的码字传输的准确性。上行PON帧中的第一个码字(即图3中的码字1)还包括上行物理同步块(physical synchronization block upstream，PSBu)，并且上行PON帧中的其余码字(即图3中的码字2至码字N)不包括PSBu。
参考图3，PSBu包括前导码和定界符(Delimiter)。前导码用于通过自相关峰值检测方法发现突发信号，定界符用于指示前导码的起始位和终止位。并且，前导码和定界符可以包括信号数据，该信号数据用于确定来自ONU的物理接口(physical interface，PHY)突发信号的存在，描绘PHY突发信号以及确定信号时钟，以便正确地恢复发送。
随着时分复用无源光网络(TDM-PON)技术的光接入网络迅速发展，更高带宽的光接入网络需求，对无源光网络的带宽提出了更高的要求。基于10千兆比特无源光网络(10Gigabit-Capable Passive Optical Network，10G PON)的规模部署，50千兆比特无源光网络(50G PON)已经开始发展。并且，为了使高数据速率的无源光网络的数据准确稳定的传输，在数据传输过程中，通常利用高性能的串行器/解串器(serializer/deserializer，SerDes)的接口技术将一路高速PON数据信号转换为多路并行的低速数据信号并进行传输，之后将该多路并行的低速数据信号同步以恢复为一路高速PON数据信号。
在50G PON系统中，50G光模块与OLT和ONU的设备电接口可以有50G非归零码(Non Return to Zero，NRZ)，50G四电平脉冲幅度调制(Pulse Amplitude Modulation 4，PAM4)以及2×25G NRZ等三种SerDes接口形式。2×25G NRZ接口形式比较成熟，对电信号质量损伤最小，在数据通信光模块领域中已经被广泛采用，且在50G PON系统中也是一种优秀的接口形式。但是，在50G PON光模块与OLT和ONU的设备电接口为2×25G NRZ接口形式的情况下，由于单板走线，当光模块内部数字信号处理器(Digital Signal Processor，DSP)对数据进行处理时，会存在两条数据通路乱序或者数据不能对齐并同时到达的问题。当PON系统的线路速率上升到100Gb/s或200Gb/s及以上时，光模块与设备电接口变为多路并行的低数据速率的电接口，数据不能同步的情况更加复杂。
在处理多条数据通路乱序或者数据不能对齐并同时到达的问题时，相关技术 主要是将PON信号中的特征码字(在上行数据信号中该特征码字为PSBu，在下行数据信号中该特征码字为PSBd)按比特或者按字节拆分为多个部分，以作为多路低速数据信号的对齐标志位，但这样会导致对齐标志位的长度缩短。随着无源光网络的数据速率提高，数据量不断增加，在通过较短的对齐标志位将多路低速数据信号进行对齐同步时，容易出现假同步的情况。并且，在多路并行的低速数据信号的同步过程中也容易出现假同步的情况。
相关技术中有两种方法降低假同步概率。一种方法是增加PSBd和PSBu长度，但这样会增加无源光网络系统开销。另一种方法是通过在特征码字中增加FEC校验成功判决条件。然而，这种方法随着无源光网络数据速率上升和数据量的增加，数据处理时延会增加，且假同步的概率依然很高。
为了解决上述问题，本公开一些实施例提供一种无源光网络的数据同步方法。该方法的思路在于：对数据恢复出来的高速数据信号进行PON同步验证，以判断是否出现假同步的情况；并在出现假同步的情况下，通过重新对多路低速数据信号进行对齐恢复步骤，以提高多路低速数据信号的同步成功率。这样，一方面无需增加特征码字的长度，从而避免引入额外的传输开销。另一方面，由于无需增加FEC校验，因此可以跳过FEC解码先完成PON信号同步，以降低信号处理时延。
图4为根据一些实施例的一种数据同步系统的架构示意图。上述数据同步方法适用于该数据同步系统40。如图4所示，该数据同步系统40包括：数据拆分装置401、第一无源光网络设备402、第二无源光网络设备403以及同步装置404。
第一无源光网络设备402可以包括第一光模块4021，第二无源光网络设备403可以包括第二光模块4031。在本公开一些实施例中，光模块(如第一光模块4021或第二光模块4031)可以用于进行光信号和电信号的相互转换。在一些示例中，该光模块可以为可插拔光模块，或者为板载光组件等，本公开对此不作限定。
需要说明的是，在下行数据传输过程中，第一无源光网络设备402可以为OLT，第二无源光网络设备403可以为ONU；在上行数据传输过程中，第一无源光网络设备402可以为ONU，第二无源光网络设备403可以为OLT。可以理解的是，第一无源光网络设备402和第二无源光网络设备403之间可以通过ODN进行通信。
数据拆分装置401与第一无源光网络设备402中的第一光模块4021连接。数据拆分装置401用于将一路高速电信号拆分为多路低速电信号，并将多路低速电信号传输至第一光模块4021。
第一光模块4021与第二无源光网络设备403中的第二光模块4031连接。第一光模块4021用于将多路低速电信号转换成一路高速光信号，并将这一路高速光信号传输至第二光模块4031。
第二光模块4031与同步装置404连接。第二光模块4031用于将一路高速光信号转换成多路低速电信号，并将多路低速电信号传输至同步装置404。
同步装置404用于将多路低速电信号恢复成一路高速电信号。这里，同步装置404可以通过执行本公开一些实施例中的数据同步方法以将多路低速电信号恢复成正确地一路高速电信号。
在一些示例中，同步装置404可以独立于第二无源光网络设备403，也可以集成在第二无源光网络设备403中。数据拆分装置401可以独立于第一无源光网络设备402，也可以集成在第一无源光网络设备402中。
下面结合附图对本公开一些实施例提供的无源光网络的数据同步方法进行详细介绍。
本公开一些实施例提供了一种无源光网络的数据同步方法，该方法可以应用于图4所示的数据同步系统40中的同步装置404。如图5所示，该方法包括步骤101至步骤103(S101～S103)。
在步骤101中，执行对齐恢复步骤，该对齐恢复步骤包括：对多路第一数据信号进行同步对齐，并将对齐后的多路第一数据信号恢复成一路第二数据信号。
这里，多路第一数据信号可以由对第三数据信号拆分得到。拆分方法可以为以单字节为单位拆分，以单比特为单位拆分，以双字节为单位拆分，或者以Psync长度一半为单位拆分进行拆分，本公开对此不做限定。
可以理解的是，第三数据信号包括连续的一个或多个PON帧。对第三数据信号进行拆分，可以理解为对第三数据信号中的PON帧进行拆分。在对第三数据信号进行拆分之后，各路第一数据信号分别包括PON帧拆分后的一部分。为了便于描述，下文中可以将PON帧拆分后的部分称为PON子帧。
图6为根据一些实施例的一种50G PON下行帧的拆分结果的示意图。例如，如图6所示，50G PON下行帧包括8个字节的Psync字段、8个字节的SFC结构 字段、8个字节的OC结构字段和2n个字节的有效载荷(如第一有效载荷)。在以字节为单位对50G PON下行帧进行拆分的情况下，第一PON子帧包括50G PON下行帧中的Psync字段的偶数字节、SFC结构字段的偶数字节、OC结构字段的偶数字节和Payload字段的偶数字节。第二PON子帧包括50G PON下行帧中Psync字段的奇数字节、SFC结构字段的奇数字节、OC结构字段的奇数字节和Payload字段的奇数字节。
为了使得多路第一数据信号能够正确地恢复成一路第三数据信号，各路第一数据信号需要携带对应的同步信息，以便于多路第一数据信号能够进行同步对齐。该同步信息可以有不同的名称，例如同步头、对齐标志位等，本公开对此不作限定。可以理解的是，多路第一数据信号所对应的同步信息，也是由第三数据信号所携带的目标信息拆分得到的。
例如，对于上行传输，各路第一数据信号所对应的同步信息由PSBu中全部字段或者部分字段拆分得到。例如，各路第一数据信号所对应的同步信息可以对PSBu中的定界符进行拆分而得到。
又例如，对于下行传输，各路第一数据信号所对应的同步信息由PSBd中全部或者部分字段拆分得到。例如，各路第一数据信号所对应的同步信息可以对PSBd中的Psync进行拆分而得到。
结合图6以下行方向为例进行说明。在将50G PON中的50G数据信号拆成两路25G数据信号的情况下，第一数据信号11对应的同步信息为Psync Byte0、Psync Byte2、Psync Byte4、Psync Byte6d的组合；第一数据信号12对应的同步信息为Psync Byte1、Psync Byte3、Psync Byte5、Psync Byte7的组合。例如，假设Pysnc为0xC5E51840FD59BB49，第一数据信号11对应的同步信息Pysnc_lane0为0xC518FDBB，第一数据信号12对应的同步信息Pysnc_lane1为0xE5405949。
在一些实施例中，所述对多路第一数据信号中各路第一数据信号进行同步对齐，包括：基于第一对应关系，对多路第一数据信号中的各路第一数据信号进行同步信息的搜索，第一对应关系用于指示各路第一数据信号所对应的同步信息；在成功搜索出各路第一数据信号对应的同步信息之后，基于搜索出的各路第一数据信号对应的同步信息，对各路第一数据信号进行对齐处理。
在一些示例中，第一对应关系可以预先配置在同步装置404中。或者，以图4所示的数据同步系统40为例，第一对应关系可以由同步装置404与数据拆分 装置401之间相互协商来确定。在一些示例中，第一光模块4021和/或第二光模块4031也可以参与第一对应关系的协商过程。
这样，在同步对齐过程中，同步装置404仅需要根据一个对应关系来搜索各路第一数据信号中的同步信息，可以降低搜索复杂度，简化同步装置404的结构。
在一些实施例中，所述数据同步方法还包括：在经过第一预设时长之后未成功搜索出各路第一数据信号所对应的同步信息的情况下，基于第二对应关系，对多路第一数据信号中的各路第一数据信号进行同步信息的搜索，第二对应关系用于指示各路第一数据信号所对应的同步信息，并且至少一个第一数据信号在第二对应关系中对应的同步信号与在第一对应关系中对应的同步信息不同。上述第一预设时长可以预先配置，或者上述第一预设时长可以由同步装置404根据自身的数据处理情况来确定，本公开对此不作限定。
可以理解的是，在同步对齐过程中，若长时间未搜索出各路第一数据信号对应的同步信息，说明第一对应关系不正确。因此，同步装置404可以通过更换同步对齐过程中使用的对应关系(即更换为第二对应关系)，以快速地成功搜索出各路第一数据信号对应的同步信息。
例如，假设第一对应关系用于指示第一数据信号11对应的同步信息为0xC518FDBB，第一数据信号12对应的同步信息为0xE5405949；第二对应关系用于指示第一数据信号11对应的同步信息为0xE5405949，第一数据信号12对应的同步信息为0xC518FDBB。在此情况下，同步装置404可以先基于第一对应关系，在第一数据信号11中搜索0xC518FDBB，在第一数据信号12中搜索0xE5405949。在第一预设时长内未搜索出各路第一数据信号所对应的同步信息之后，同步装置404可以基于第二对应关系，在第一数据信号11中搜索0xE5405949，在第一数据信号12中搜索0xC518FDBB。
在另一些实施例中，所述对多路第一数据信号中各路第一数据信号进行同步对齐，包括：同时执行多个搜索操作；各个搜索操作用于基于该搜索操作对应的对应关系，对多路第一数据信号中的各路第一数据信号进行同步信息的搜索；不同的搜索操作对应不同的对应关系，对应关系用于指示各路第一数据信号所对应的同步信息；在目标搜索操作成功搜索出各路第一数据信号对应的同步信息之后，基于目标搜索操作搜索出的各路第一数据信号对应的同步信息，对各路第一数据信号进行对齐处理，目标搜索操作为所述多个搜索操作中的任意一个搜索操作。
这样，在同步对齐过程中，同步装置404可以同时根据多个对应关系搜索各路第一数据信号中的同步信息，以快速地成功搜索出各路第一数据信号对应的同步信息。
例如，同步装置404可以同时执行第一搜索操作和第二搜索操作。第一搜索操作用于在第一数据信号11中搜索0xC518FDBB，在第一数据信号12中搜索0xE5405949。第二搜索操作用于在第一数据信号11中搜索0xE5405949，在第一数据信号12中搜索0xC518FDBB。当基于第二搜索操作成功后，可以根据第一数据信号11中0xE5405949的位置，以及第一数据信号12中0xC518FDBB的位置，对第一数据信号11和第一数据信号12进行对齐处理。
需要说明的是，在第一数据信号中搜索对应的同步信息，可以理解为在第一数据信号中寻找与同步信息相匹配的目标比特序列。在一些示例中，目标比特序列与同步信息相匹配可以指：目标比特序列与同步信息完全相同；或者，目标比特序列与同步信息之间不同的比特的数目小于或等于预设个数。例如，该预设个数可以为2。
另外，对多路第一数据信号进行对齐处理，可以理解为：基于各路第一数据信号中搜索出来的同步信息中第一个比特的位置，对多路第一数据信号进行对齐处理。
在一些实施例中，在所述对齐恢复步骤中，在满足预设条件的情况下，将对齐后的多路第一数据信号恢复成一路第二数据信号。该预设条件可以包括：连续K次成功地从各路第一数据信号中搜索出对应的同步信息，K为正整数。可以理解的是，在K大于1的情况下，需要连续多次成功地从各路第一数据信号中搜索出对应的同步信息，才会对多路第一数据信息进行数据恢复，这样可以降低多路第一数据信号发生假同步的概率。并且，K越大，多路第一数据信号发生假同步的概率也越低。
在一些实施例中，所述将对齐后的多路第一数据信号恢复成一路第二数据信号，可以包括：将多路第一数据信号以间插的方式合并成一路第二数据信号。数据恢复的方式与数据拆分的方式互相对应。也就是说，数据拆分时以字节为单元，数据恢复时也以字节为单元。数据拆分时以比特为单元，数据恢复时也以比特为单元。
结合图6进行举例说明，对第一数据信号11成功搜索到同步信息Pysnc_lane0， 该同步信息Pysnc_lane0为0xC518FDBB；对第一数据信号12成功搜索到同步信息Pysnc_lane1，该同步信息Pysnc_lane1为0xE5405949。由于Pysnc_lane0是由Pysnc中偶数字节构成，Pysnc_lane1是由Pysnc中奇数字节构成。因此，可以将第一数据信号11中的字节作为第二数据信号中的偶数字节，将第一数据信号12中的字节作为第二数据信号中的奇数字节，从而将第一数据信号11和第一数据信号12以字节间插的方式合成一路第二数据信号。
可以理解的是，在多路第一数据信号正确同步的情况下，第二数据信号即为上述第三数据信号；但在出现假同步的情况下，第二数据信号不为上述第三数据信号。
在步骤102中，对所述第二数据信号进行PON同步验证。
在一些实施例中，通过PON同步状态机对第二数据信号进行PON同步验证，PON同步状态机的状态包括搜索状态、预同步状态、同步状态以及重同步状态。在PON同步状态机在任一状态上发生失步的情况下，或者在PON同步状态机重新进入搜索状态的情况下，确定第二数据信号未成功通过PON同步验证。或者，在PON同步状态机处于同步状态的情况下，确定第二数据信号通过同步验证。
PON同步状态机在目标状态上发生失步，是指PON同步状态机在目标状态上对第二数据信号进行相应的验证时，出现验证失败的情况。目标状态可以是PON同步状态机的任意一个状态。
在第二数据信号为上行数据信号的情况下，PON同步状态机可以称为上行PON同步状态机；在第二数据信号为下行数据信号的情况下，PON同步状态机可以称为下行PON同步状态机。在一些示例中，上行PON同步状态机采用的验证机制可以与下行PON同步状态机采用的验证机制不同。
在一些实施例中，如图7所示，下行PON同步状态机采用的验证机制包括Psync验证和SFC验证。Psync验证包括：在第二数据信号中搜寻与预设Psync匹配的字段。SFC验证包括：验证位于Psync之后的预设位数的比特序列是否构成有效的SFC结构。
参考图7，下行PON同步状态机的具体运行过程包括：
从搜索状态开始，在第二数据信号中搜索Psync字段。若确认搜索的Psync字段与相关标准中规定的Psync字段匹配，则验证第二数据信号中在Psync字段 之后的预设位数的比特序列是否构成有效的SFC结构。若不是，则继续保持在搜索状态，并继续搜索Psync字段；若是，则从搜索状态切换至预同步状态。
在切换至预同步状态之后，在第二数据信号中识别各个PON帧，并对各个PON帧执行Psync验证和SFC验证。若Psync验证和SFC验证中任意一个失败，则切换至搜索状态；若Psync验证和SFC验证成功，则切换至同步状态。
在切换至同步状态之后，继续对第二数据信号中余下的PON帧执行Psync验证和SFC验证。若Psync验证和SFC验证中任意一个失败，则切换至重同步状态；若Psync验证和SFC验证成功，则保持在同步状态。
在切换至重同步状态之后，继续对第二数据信号中的PON帧执行Psync验证和SFC验证。若一个PON帧的Psync验证和SFC验证成功，则切换至同步状态；若一个PON帧的Psync验证失败和/或SFC验证失败，则保持在重同步状态；若连续的M-1个PON帧中的每个PON帧的Psync验证失败和/或SFC验证失败，则重新进入搜索状态。M为大于1的整数。
在另一些实施例中，如图8所示，下行PON同步状态机采用的验证机制包括Psync验证、SFC验证和FEC验证。Psync验证和SFC验证的具体实现细节可以参考上文，在此不再赘述。FEC验证可以包括：在下行数据流中根据上述的Psync字段确定FEC码字的边界位置，然后对每个FEC码字进行译码检验。
参考图8，下行PON同步状态机的具体运行过程包括：
从搜索状态开始，在第二数据信号中搜索Psync字段。若确认搜索的Psync字段与相关标准中规定的Psync字段匹配，则验证第二数据信号中在Psync字段之后的预设位数的比特序列是否构成有效的SFC结构。若不是，则继续保持在搜索状态，并继续搜索Psync字段；若是，则从搜索状态切换至预同步状态。
在切换至预同步状态之后，对第二数据信号中的FEC码字进行译码检验；并且，对第二数据信号中的各个PON帧进行SFC验证。在一个FEC码字译码失败时，保持在预同步状态，并继续对第二数据信号中的下一个FEC码字进行译码检验。若L个FEC码字中存在译码检验通过的FEC码字，并且SFC验证成功，则从预同步状态切换至同步状态；或者，若L个FEC码字中不存在译码检验通过的FEC码字，或者SFC验证失败，则切换至搜索状态。L为正整数。
在切换至同步状态之后，对第二数据信号中的各个PON帧进行Psync验证和SFC验证。若Psync验证和SFC验证成功，则保持在同步状态；若Psync验 证失败和/或SFC验证失败，则从同步状态切换至重同步状态。
在切换至重同步状态之后，继续对第二数据信号中的PON帧执行Psync验证和SFC验证。若一个PON帧的Psync验证和SFC验证成功，则切换至同步状态；若一个PON帧的Psync验证失败和/或SFC验证失败，则保持在重同步状态；若连续的M-1个PON帧中的每个PON帧的Psync验证失败和/或SFC验证失败，则重新进入搜索状态。M为大于1的整数。
对于上行PON同步状态机的验证机制可以为界定定界符的同步头定界成功以及物理帧净荷的帧子层(framing sublayer，FS)帧头校验成功作为判断依据。由于PON系统的上行突发信号，每一次上行突发帧都需要重新同步。这里物理帧净荷的帧子层(FS)包括FS帧头、FS帧净荷以及FS尾部。并且，由于物理帧净荷的帧结构，FS帧头的数据可以受到HEC代码保护，因此可以对FS帧头部分的数据进行HEC校验。
在一些实施例中，该数据同步方法还包括：在第二预设时长内第二数据信号未成功通过PON同步验证的情况下，向生成多路第一数据信号的光模块或者无源光网络设备发送用于指示重新恢复数据的指示信息。可以理解的是，若第二数据信号长时间未通过PON同步验证，则光模块或者无源网络设备传输给同步装置404的多路第一数据信号可能存在错误。因此，通过向光模块或者无源光网络设备发送用于指示重新恢复数据的指示信息，可以使得光模块或者无源光网络设备能够向同步装置404传输正确的多路第一数据信号。
在第二数据信号通过PON同步验证的情况下，执行下述步骤103；或者，在第二数据信号未通过PON同步验证的情况下，转至执行上述步骤101。
在步骤103中，在第二数据信号通过PON同步验证的情况下，确定同步成功。
在一些实施例中，在同步成功的情况下，可以从第二数据信号中识别出PON帧。
在本公开一些实施例提供的数据同步方法中，通过对数据恢复出来的高速数据信号进行PON同步验证，以判断是否出现假同步的情况；并在出现假同步的情况下，通过重新对多路低速数据信号进行对齐恢复步骤，以提高多路低速数据信号的同步成功率。
可以理解的是，上述方法可以由同步装置404实现。无源光网络的同步装置 为了实现上述功能，可以包含执行各个功能相应的硬件结构或软件模块。本领域技术人员应该很容易想到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本公开一些实施例能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用使用不同方法来实现所描述的功能，但是这种实现不应认为超出本公开的范围。
本公开一些实施例可以根据上述方法实施例对上述无源光网络的数据同步方法进行功能模块的划分。例如，可以对应各个功能划分各个功能模块。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本公开一些实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图9示出了上述实施例中所涉及的同步装置的一种可能的结构示意图。如图9所示，本公开一些实施例提供一种同步装置800。同步装置800包括数据恢复模块801和PON同步模块802。
数据恢复模块801用于执行对齐恢复步骤，该对齐恢复步骤包括对多路第一数据信号进行同步对齐，并将对齐后的多路第一数据信号恢复成一路第二数据信号。
PON同步模块802用于对第二数据信号进行PON同步验证；在第二数据信号未通过PON同步验证的情况下，指示数据恢复模块801转至执行对齐恢复步骤；或者，在第二数据信号通过PON同步验证的情况下，确定同步成功。
在一些实施例中，数据恢复模块801被配置为：基于第一对应关系，对多路第一数据信号中各路第一数据信号进行同步信息的搜索，第一对应关系用于指示各路第一数据信号所对应的同步信息；在成功搜索出各路第一数据信号对应的同步信息之后，基于搜索出的各路第一数据信号对应的同步信息，对各路第一数据信号进行对齐处理。
在一些实施例中，数据恢复模块801还被配置为：在经过第一预设时长之后还未成功搜索出各路第一数据信号所对应的同步信息的情况下，基于第二对应关系，对多路第一数据信号中各路第一数据信号进行同步信息的搜索，第二对应关系用于指示各路第一数据信号所对应的同步信息，并且至少一个第一数据信号在第二对应关系中对应的同步信号与在第一对应关系中对应的同步信息不同。
在另一些实施例中，数据恢复模块801被配置为：同时执行多个搜索操作；各个搜索操作用于基于该搜索操作对应的对应关系，对多路第一数据信号中各路第一数据信号进行同步信息的搜索；不同的搜索操作对应不同的对应关系，对应关系用于指示各路第一数据信号所对应的同步信息；在目标搜索操作成功搜索出各路第一数据信号对应的同步信息之后，基于目标搜索操作搜索出的各路第一数据信号对应的同步信息，对各路第一数据信号进行对齐处理，目标搜索操作为多个搜索操作中的任意一个搜索操作。
在一些实施例中，PON同步模块802被配置为：通过PON同步状态机对第二数据信号进行PON同步验证，PON同步状态机包括搜索状态、预同步状态、同步状态以及重同步状态；在PON同步状态机在任一状态上发生失步的情况下，或者在PON同步状态机重新进入搜索状态的情况下，确定第二数据信号未成功通过PON同步验证。
在一些实施例中，PON同步模块802还被配置为:在第二预设时长内第二数据信号未成功通过PON同步验证的情况下，向生成多路第一数据信号的光模块或者无源光网络设备发送用于指示重新恢复数据的指示信息。
当然，无源光网络的同步装置800包括但不限于上述所列举的单元模块。并且，上述功能单元的具体实现的功能也包括但不限于上述实施例的方法步骤对应的功能。无源光网络的数据同步装置800的其他模块的详细描述可以参考其所对应方法步骤的详细描述，在此不再赘述。
上述同步装置可以以图10所示的电子设备的结构来实现。如图10所示，该电子设备900包括处理器902和总线904。在一些实施例中，该电子设备900还可以包括存储器901或通信接口903中的至少一个。
处理器902可以是实现或执行结合本公开所描述的各种示例性的逻辑方框，模块和电路。该处理器902可以是中央处理器(Central Processing Unit，CPU)，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。处理器902也可以是实现计算功能的组合。例如，处理器902为包含一个或多个微处理器的组合，或者为DSP和微处理器的组合等。
通信接口903用于与其他设备通过通信网络连接。该通信网络可以是以太网，无线接入网，无线局域网(Wireless Local Area Networks，WLAN)等。
存储器901可以是只读存储器(Read-Only Memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(Random Access Memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，或者电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、磁盘存储介质或者其他磁存储设备,或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但本公开并不限于此。
在一些实施例中，存储器901可以独立于处理器902存在，存储器901可以通过总线904与处理器902相连接，并用于存储指令或者程序代码。处理器902调用并执行存储器901中存储的指令或程序代码时，能够实现本公开一些实施例提供的直连通信方法。
在另一些实施例中，存储器901也可以和处理器902集成在一起。
总线904可以是扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线904可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
本公开的实施例还提供一种计算机可读存储介质。该计算机可读存储介质中存储有计算机指令，当计算机指令在上述电子设备上运行时，使得该电子设备执行上述方法实施例中的各个功能或者步骤。例如，该计算机可读存储介质可以包括只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)、磁带、软盘和光数据存储设备等。
本公开的多个实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些实施例可以在硬件中实现，而其它实施例可以在可以被控制器、微处理器或其它计算装置执行的固件或软件中实现，但本公开并不限于此。本公开的实施例可以通过信息传输装置的数据处理器执行计算机程序指令实现。例如，本公开的实施例通过处理器实体，或者硬件，或者软件和硬件的组合执行计算机程序指令实现。计算机程序指令可以是汇编指令、指令集架构(Instruction Set Architecture，ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本公开附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互 连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适用于本地技术环境的类型并且可以使用任何数据存储技术实现，例如只读存储器(Read-Only Memory，ROM)、随机访问存储器(Random Access Memory，RAM)、光存储器装置和系统(数码多功能光碟(Digital Video Disc，DVD)或(Compact Disk，CD))等，但本公开并不局限于此。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适用于本地技术环境的类型的处理器，例如通用计算机、专用计算机、微处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑器件(Field Programmable Gate Array，FPGA)或基于多核处理器架构的处理器等，但本公开并不局限于此。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何在本公开揭露的技术范围内的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。

Claims (11)

  1. 一种无源光网络的数据同步方法，包括：
    对齐恢复步骤:对多路第一数据信号进行同步对齐，并将对齐后的所述多路第一数据信号恢复成一路第二数据信号；
    对所述第二数据信号进行无源光网络同步验证；
    在所述第二数据信号未通过所述无源光网络同步验证的情况下，转至所述对齐恢复步骤；或者，在所述第二数据信号通过所述无源光网络同步验证的情况下，确定同步成功。
  2. 根据权利要求1所述的方法，其中，所述对所述多路第一数据信号进行同步对齐，包括：
    基于第一对应关系，对所述多路第一数据信号中的各路第一数据信号进行同步信息的搜索；所述第一对应关系用于指示所述各路第一数据信号所对应的同步信息；
    在成功搜索出所述各路第一数据信号对应的同步信息之后，基于搜索出的所述各路第一数据信号对应的同步信息，对所述各路第一数据信号进行对齐处理。
  3. 根据权利要求2所述的方法，还包括：
    在经过第一预设时长之后未成功搜索出所述各路第一数据信号所对应的同步信息的情况下，基于第二对应关系，对所述多路第一数据信号中的各路第一数据信号进行同步信息的搜索，所述第二对应关系用于指示所述各路第一数据信号所对应的同步信息，并且至少一路第一数据信号在所述第二对应关系中对应的同步信息与在所述第一对应关系中对应的同步信息不同。
  4. 根据权利要求1所述的方法，其中，所述对所述多路第一数据信号进行同步对齐，包括：
    同时执行多个搜索操作；各个搜索操作用于基于所述搜索操作对应的对应关系，对所述多路第一数据信号中的各路第一数据信号进行同步信息的搜索；不同的搜索操作对应不同的对应关系，所述对应关系用于指示所述各路第一数据信号所对应的同步信息；
    在目标搜索操作成功搜索出所述各路第一数据信号对应的同步信息之后，基于所述目标搜索操作搜索出的所述各路第一数据信号对应的同步信息，对所述各路第一数据信号进行对齐处理；所述目标搜索操作为所述多个搜索操作中的任意一个搜索操作。
  5. 根据权利要求2至4中任一项所述的方法，其中，
    对于上行传输，所述多路第一数据信号中的各路第一数据信号所对应的同步信息由上行物理同步块中全部字段或者部分字段拆分得到；
    或者，
    对于下行传输，所述多路第一数据信号中的各路第一数据信号所对应的同步信息由下行物理同步块中全部字段或者部分字段拆分得到。
  6. 根据权利要求1所述的方法，其中，所述对所述第二数据信号进行无源光网络同步验证，包括：
    通过无源光网络同步状态机对所述第二数据信号进行所述无源光网络同步验证；所述无源光网络同步状态机包括搜索状态、预同步状态、同步状态以及重同步状态；
    在所述无源光网络同步状态机在任一状态上发生失步的情况下，确定所述第二数据信号未成功通过所述无源光网络同步验证；或者，在所述无源光网络同步状态机重新进入所述搜索状态的情况下，确定所述第二数据信号未成功通过所述无源光网络同步验证；或者，在所述无源光网络同步状态机处于所述同步状态的情况下，确定所述第二数据信号通过所述无源光网络同步验证。
  7. 根据权利要求1或6所述的方法，还包括：
    在第二预设时长内所述第二数据信号未成功通过所述无源光网络同步验证的情况下，向生成所述多路第一数据信号的光模块或者无源光网络设备发送用于指示重新恢复数据的指示信息。
  8. 一种同步装置，包括：
    数据恢复模块，用于执行对齐恢复步骤，所述对齐恢复步骤包括对多路第一数据信号进行同步对齐，并将对齐后的所述多路第一数据信号恢复成一路第二数据信号；
    无源光网络同步模块，用于对所述第二数据信号进行无源光网络同步验证；在所述第二数据信号未通过所述无源光网络同步验证的情况下，指示所述数据恢复模块转至执行所述对齐恢复步骤；或者，在所述第二数据信号通过所述无源光网络同步验证的情况下，确定同步成功。
  9. 一种电子设备，包括：
    处理器；以及
    存储器，用于存储所述处理器可执行指令；
    其中，所述处理器被配置为执行所述指令，使得所述电子设备执行如权利要求1至7中任一项所述的无源光网络的数据同步方法。
  10. 一种数据同步系统，包括：依次连接的数据拆分装置、第一无源光网络设备、第二无源光网络设备以及同步装置；
    其中，所述数据拆分装置用于将第三数据信号拆分为多路第一数据信号，并将所述多路第一数据信号通过所述第一无源光网络设备和所述第二无源光网络设备传输至所述同步装置；
    所述同步装置用于执行如权利要求1至7中任一项所述的无源光网络的数据同步方法。
  11. 一种计算机可读存储介质，存储有计算机指令，当所述计算机指令在电子设备上运行时，使得所述电子设备执行如权利要求1至7中任一项所述的无源光网络的数据同步方法。
PCT/CN2023/099984 2022-09-13 2023-06-13 无源光网络的数据同步方法、装置及数据同步系统 WO2024055651A1 (zh)

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