WO2024051453A1 - 背板系统、计算设备以及用于计算设备的管理方法 - Google Patents

背板系统、计算设备以及用于计算设备的管理方法 Download PDF

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Publication number
WO2024051453A1
WO2024051453A1 PCT/CN2023/113139 CN2023113139W WO2024051453A1 WO 2024051453 A1 WO2024051453 A1 WO 2024051453A1 CN 2023113139 W CN2023113139 W CN 2023113139W WO 2024051453 A1 WO2024051453 A1 WO 2024051453A1
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WIPO (PCT)
Prior art keywords
backplane
slave
control unit
backplanes
main
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PCT/CN2023/113139
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English (en)
French (fr)
Inventor
雷虎宝
包云兵
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华为技术有限公司
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Publication of WO2024051453A1 publication Critical patent/WO2024051453A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/187—Mounting of fixed and removable disk drives
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2200/00—Indexing scheme relating to G06F1/04 - G06F1/32
    • G06F2200/20—Indexing scheme relating to G06F1/20
    • G06F2200/202—Air convective hinge

Definitions

  • the present disclosure relates to the field of computer technology, and more specifically, to a backplane system, a computing device including the backplane system, and a management method for the computing device.
  • This computing device usually includes components such as a central processing unit (CPU), motherboard, and memory. Due to the increasing demand for computing power in various applications, the system power consumption of computing devices has increased significantly, and the temperature rise caused by the greatly increased power consumption can inhibit the performance of processors such as CPUs. Therefore, computing devices have increasingly higher requirements for heat dissipation to ensure that high-power processor performance can still be fully unleashed.
  • CPU central processing unit
  • motherboard motherboard
  • memory main memory
  • the air volume of the system can be increased by increasing the fan speed of the air cooling system.
  • the backplane such as the memory (also called the hard drive backplane) is placed vertically to the mainboard where the CPU is located, the hard drive backplane is placed between the CPU and the fan, which causes the hard drive backplane to block the cooling airflow.
  • the present disclosure provides an improved backplane system, a computing device, and a management method for the computing device.
  • a backplane system including: a plurality of backplanes arranged to be stacked in parallel with each other and spaced apart from each other, each backplane including: a first port; a second port, configured to be connected to the memory; and a third port configured to be connected to the storage controller; and a flexible circuit component connected to the first port of each of the plurality of backplanes, and the flexible circuit component is configured to Transport signals between multiple backplanes.
  • the backplane system further includes: at least one set of first indicator lights disposed on the flexible circuit component, each set of first indicator lights configured to indicate at least one memory connected to the plurality of backplanes. the status of the corresponding memory in the memory, and is adapted to be connected to a set of second indicator lights located on the housing of the corresponding memory via the light guide column.
  • the memory status indicators can be arranged more conveniently and flexibly.
  • each group of first indicator lights includes a plurality of first indicator lights, and each first indicator light is directly disposed on the surface of the flexible circuit component. This avoids the additional cost of specially customizing the first indicator lights that overlap each other, and enhances the versatility of the device.
  • each of the plurality of backplanes includes a plurality of second ports to form a plurality of columns of second ports on one side of the plurality of backplanes, wherein the flexible circuit component includes a plurality of second ports.
  • first sections and second sections interconnecting the plurality of first sections, each first section being disposed adjacent a corresponding column of second ports and extending in the direction of the plurality of backplane stacks, and
  • Each set of first indicator lights is arranged adjacent to the second port for the corresponding memory. Therefore, when each backplane has multiple memories, the corresponding first indicator light, light guide column, and second indicator light can be easily arranged for each memory, which reduces the difficulty of arrangement.
  • each backplane includes at least one notch portion for accommodating the flexible circuit component, and each notch portion is located between two adjacent second ports.
  • Flexible circuit components can be arranged more compactly and take up less space.
  • the backplane system further includes a support board, and the flexible circuit component is fixed to a board surface of the support board. Helps guide and secure flexible circuit components so that they can be connected to various backplanes.
  • the plurality of backplanes include a master backplane and a slave backplane
  • the master backplane is adapted to be connected to a baseboard management controller
  • the baseboard management controller is configured to manage the master backplane and via the master backplane Board management is from the backplane.
  • the main backplane is used to manage other backplanes and flexible circuit components are used to transmit management signals, thereby achieving simple and efficient management when the number of backplanes is large and may be further expanded.
  • each backplane includes a control unit and a master-slave mode control terminal interconnected with each other
  • the flexible circuit component includes a pull-down terminal and a floating terminal
  • the master-slave mode control terminal of the main backplane is is connected to one of the pull-down terminal and the floating terminal
  • the master-slave mode control terminal of the slave backplane is connected to the other of the pull-down terminal and the floating terminal.
  • Master-slave mode can be set up for multiple backplanes in a simple and effective way.
  • each backplane includes: a fourth port connected to the control unit and adapted to be connected to the baseboard management controller. Management of multiple backplanes can be achieved simply and efficiently.
  • each backplane further includes: a first gating device and a second gating device, each including a device connection terminal, a first channel and a second channel, and is configured to control The selection signal of the unit connects the device connection end to the first channel or the second channel, wherein the device connection end of the first strobe device is connected to the fourth port, and the first channel of the first strobe device is connected to the firmware update of the control unit interface, and the second channel of the first strobe device is connected to the satellite management controller of the control unit; and wherein the device connection end of the second strobe device is connected to the first port, and the first channel of the second strobe device is connected to the satellite management controller, and the second channel of the second strobe device is connected to the device connection of the first strobe device, the satellite management controller of the main backplane is configured to connect the second channel from the first strobe device The firmware update data is forwarded to the first channel of the second strobe device.
  • control unit of the main backplane is configured to: in response to a firmware update of the main backplane itself, send a selection signal to the first strobe device of the main backplane to switch the first strobe to the main backplane.
  • the firmware update of the main backplane can be realized, and the firmware update of the slave backplane can be realized with the help of the main backplane.
  • the fourth port is connected to the satellite management controller of the control unit via the data bus, and the satellite management controller is connected to the first port via its high-speed serial interface, and
  • the satellite management controller is configured to obtain information related to at least one of memory status, FRUs of the backplane, and sensed temperature of the backplane of the associated backplane, and wherein the satellite management controller of the primary backplane is further configured To provide the information of the master backplane to the baseboard management controller, and to receive the information from the slave backplane and provide it to the baseboard management controller.
  • the information of the main backplane can be obtained, and the main backplane can be used to obtain the information of the slave backplane, thereby achieving efficient management of multiple backplanes.
  • control unit of each backplane is configured to control one or more groups of first indicator lights corresponding thereto.
  • Memory status indicators can be controlled simply and effectively.
  • each backplane further includes an expander adapted to expand the number of memories connected to the backplane. Can be expanded to connect more storage or hard drives on a single backplane.
  • a second aspect provides a computing device, including: a backplane system according to the first aspect.
  • a third aspect provides a management method for a computing device according to the second aspect, the management method comprising: managing a main backplane among a plurality of backplanes by a baseboard management controller, the baseboard management controller being connected to the main backplane. a backplane; and managing the slave backplanes among the plurality of backplanes via the master backplane by the baseboard management controller.
  • the master-slave mode control terminal of the master backplane is connected to one of the pull-down terminal and the floating terminal of the flexible circuit component, and the master-slave mode control terminal of the slave backplane is connected to the flexible circuit The other of the component's pull-down terminal and the floating terminal.
  • managing the main backplane among the plurality of backplanes by the baseboard management controller includes: the control unit of the main backplane sending a selection signal to the first strobe device of the main backplane; and The baseboard management controller provides firmware update data to the control unit of the main backplane via the first strobe device of the main backplane to perform firmware update on the control unit of the main backplane, and wherein the baseboard management controller performs firmware update via the main backplane.
  • Managing the slave backplane among the plurality of backplanes includes: sending a selection signal from the control unit of the master backplane to the first strobe device and the second strobe device of the master backplane; and sending a selection signal from the control unit of the slave backplane to the slave backplane.
  • the first strobe device and the second strobe device send out the selection signal; and the baseboard management controller passes the first strobe device, the control unit and the second strobe device of the main backplane, the flexible circuit component, and the slave backplane
  • the second gating device and the first gating device provide firmware update data to the control unit of the slave backplane to perform firmware update on the control unit of the slave backplane.
  • managing the main backplane among the multiple backplanes by the baseboard management controller includes: using the control unit of the main backplane to obtain the memory status of the main backplane, the FRU of the backplane, and the backplane. information related to at least one of the sensed temperatures of the board; and forwarding the acquired information to the baseboard management controller by the control unit of the main backplane, and wherein the plurality of backplanes are managed by the baseboard management controller via the main backplane
  • the slave backplanes in the slave backplanes include obtaining, by a control unit of each slave backplane in the slave backplanes, information related to at least one of a memory status, a FRU of the backplane, and a sensed temperature of the backplane belonging to the slave backplane. ; and the control unit of the slave backplane forwards the acquired information to the baseboard management controller via the control unit of the master backplane.
  • a management device for a computing device includes various modules for executing the management method of the computing device in the third aspect or any possible implementation of the third aspect.
  • the present application provides a computer-readable storage medium that stores instructions, which when run on a computer, cause the computer to execute the methods described in the above aspects.
  • the present application provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the methods described in the above aspects.
  • Figure 1 shows a backplane system in a conventional scheme.
  • FIG. 2 shows a schematic diagram of a computing device according to the present disclosure.
  • Figure 3 shows a simplified schematic diagram of a backplane system provided in accordance with the present disclosure.
  • FIG. 4 shows a schematic perspective view of a backplane in a backplane system according to the present disclosure.
  • Figure 5 shows a perspective view of a backplane system provided according to the present disclosure.
  • Figure 6 shows a front view of a backplane system provided in accordance with the present disclosure.
  • Figure 7 shows a side view of a backplane system provided in accordance with the present disclosure.
  • Figure 8 shows a top view of a backplane system provided according to the present disclosure.
  • FIG. 9 shows a perspective view of a backplane system equipped with memory according to the present disclosure.
  • FIG. 10 shows a front view of a backplane system equipped with memory according to the present disclosure.
  • FIG. 11 shows a circuit block diagram of a partial circuit in a computing device according to the present disclosure.
  • FIG. 12 shows a schematic diagram of a partial circuit of a computing device for determining a master-slave backplane according to the present disclosure.
  • FIG. 13 shows a schematic diagram of a partial circuit of a computing device for implementing firmware upgrade according to the present disclosure.
  • FIG. 14 shows a schematic diagram of a partial circuit of a computing device for implementing firmware upgrade according to the present disclosure.
  • FIG. 15 shows a schematic diagram of a partial circuit of a computing device for implementing memory, indicator light, and backplane management according to the present disclosure.
  • FIG. 16 shows a schematic flowchart of a management method for a computing device provided according to the present disclosure.
  • FIG. 17 shows a schematic flowchart of a method for managing a main backplane according to the present disclosure.
  • FIG. 18 shows a schematic flowchart of a method for managing a slave backplane according to the present disclosure.
  • FIG. 19 shows a schematic flowchart of a method for managing a main backplane according to the present disclosure.
  • FIG. 20 shows a schematic flowchart of a method for managing a slave backplane according to the present disclosure.
  • Backplane system 110' Opening 1000: Computing device 100: Backplane system 110-1... 110-N: Backplane 111: First port 112: Second port 113: Third port 114: Notch Part 115: Control unit 1151: Satellite management controller 116: First strobe device 117: Second strobe device 118: Expander 119: Fourth port 120: Flexible circuit component 121: Support plate 122-1, 122-2 : The first section of the flexible circuit component 123: The second section of the flexible circuit component 130-1...130-L: First indicator light 200: Memory 300: Storage controller 400: Baseboard management controller 500: Mainboard and Central processing unit D1: first direction D2: second direction
  • the present disclosure provides an improved backplane system, a computing device including the backplane system, and a method for managing the computing device.
  • multiple backplanes are arranged in a parallel spaced arrangement, and flexible circuit components are used to interconnect the backplanes. This not only effectively reduces airflow resistance and increases air volume, thereby improving system energy efficiency, but also allows for flexible expansion of the number of backplanes and memories without the need to customize devices for different products and applications, thus providing a Energy-efficient, low-cost, and scalable storage solution.
  • FIG 1 shows a backplane system 100' in a conventional arrangement.
  • the backplane system 100' is used to provide connections between the motherboard and the memory (or hard disk) of the server, and is usually provided between the fan and the CPU, where the CPU is a component with high power consumption in the server and is an important heat dissipation object of the fan.
  • the backplane system 100' adopts a vertical integrated backplane solution, and the backplane is provided with openings 110' for cooling airflow to pass through.
  • the board surface of the backplane system 100' is perpendicular to the airflow from the cooling fan, and therefore the cooling airflow needs to pass through the opening 110' of the backplane system 100' to enter the rear area to be cooled, thereby providing the CPU and other components with heat dissipation.
  • the opening ratio of the backplane system 100' is usually low, for example, less than 20%.
  • a server or other computing device equipped with a backplane system 100' if the air volume and heat dissipation capacity are only increased by increasing the fan speed, then this lower opening ratio will cause greater wind resistance in the system and severely limit the air volume. improvement. In this case, the fan will consume more power, resulting in reduced system energy efficiency and unable to meet the energy efficiency requirements in high computing power scenarios.
  • FIG. 2 shows a schematic diagram of a computing device 1000 in accordance with an embodiment of the present disclosure.
  • computing device 1000 may be a server, such as a general purpose rack server, which may be arranged as a node in a network to enable processing of data and information.
  • server such as a general purpose rack server
  • FIG. 2 shows a schematic diagram of a computing device 1000 in accordance with an embodiment of the present disclosure.
  • computing device 1000 may be a server, such as a general purpose rack server, which may be arranged as a node in a network to enable processing of data and information.
  • the implementation of computing device 1000 is not limited in this regard, but may be any suitable type of computing or processing device.
  • computing device 1000 may include a backplane system 100 , at least one memory 200 , at least one storage controller 300 , and a motherboard and central processing unit 500 .
  • motherboard and central processing unit 500 may include a central processing unit and a motherboard carrying the central processing unit and other electrical and electronic components.
  • the central processing unit can access at least one memory 200 through at least one memory controller 300 and the backplane system 100 to perform related operations, such as reading data from the memory 200, processing data, and writing and storing data.
  • the at least one storage controller 300 may include, but is not limited to, a serial attached small computer system interface (SAS) controller, peripheral component interconnect express, PCIe) controller, unified bus (unified bus, UB) controller, computing standard link (compute express link, CXL) controller, etc.
  • the at least one memory 200 may include, but is not limited to, a SAS hard disk, a serial advanced technology attachment (SATA) hard disk, a non-volatile memory express (NVMe) hard disk, and other types of hard disks, And it can also include storage media with memory semantics, such as CXL, UB, etc.
  • the backplane system 100 can couple at least one memory 200 to at least one storage controller 300, so that data reading, writing and storage of the at least one memory 200 can be implemented under the control of the at least one storage controller 300.
  • the backplane system 100 can also provide a framework for power and data signal transmission to the motherboard.
  • FIG. 3 shows a simplified schematic diagram of the backplane system 100 according to an embodiment of the present disclosure
  • FIG. 4 shows a perspective schematic diagram of a plurality of backplanes in the backplane system 100 according to an embodiment of the present disclosure.
  • backplane system 100 is shown above as part of computing device 1000, this description is exemplary only, and it is understood that backplane system 100 may be widely applicable to such devices as network devices and storage devices.
  • ICT Information and communications technology
  • the backplane system 100 includes a plurality of backplanes 110 - 1 ... 110 -N arranged to be stacked parallel to each other and spaced apart from each other. open.
  • each of the plurality of backplanes 110-1...110-N may be a rigid printed circuit board (PCB) to provide high-speed communication between the memory 200 and the memory controller 300. connect.
  • a plurality of back plates 110-1...110-N may be stacked one after another in the first direction D1 and be at a certain distance from each other, thereby forming a sufficiently large gap between adjacent back plates.
  • the cooling fan of the air cooling system can form a cooling airflow traveling along the second direction D2 that is substantially perpendicular to the first direction D1, and the cooling airflow can be between adjacent backplanes. It flows through the gap between the backplane system 100 and enters the rear area to be cooled.
  • the backplane system 100 adopts a horizontal backplane layout. That is to say, the backplane surface of the backplane system 100 is parallel to the airflow from the cooling fan, which effectively increases the opening ratio of the backplane system 100 and reduces wind resistance.
  • This arrangement can greatly reduce the obstruction of the cooling air flow by the backplane system 100, thereby increasing the cooling air volume without excessively increasing the cooling fan speed. This avoids increasing the power consumption of the cooling fan and effectively improves the system performance. efficiency.
  • each of the plurality of backplanes 110-1...110-N may include a first port 111, a second port 112 configured to connect to the memory 200, and a second port 112 configured to connect to the memory 200.
  • the second port 112 may include a memory connector (eg, a hard disk connector), and M second ports 112 may be provided on each backplane so that M memories (ie, memory 1 to memory M) can be connected to the corresponding second port 112, where M is an integer greater than or equal to 1.
  • the third port 113 may include a controller connector.
  • the third port 113 may include a SAS high-speed connector corresponding to the SAS controller, and if the storage controller 300 includes a UB/CXL/PCIe controller, the third port 113 113 may also include a UB/CXL/PCIe high-speed connector corresponding to the UB/CXL/PCIe controller. That is to say, the third port 113 may include one or more ports for connecting to one or more controllers among SAS controllers, UB/CXL/PCIe controllers, and other types of controllers.
  • each backplane is also provided with a first port 111.
  • the first port 111 can provide an interface for each backplane to connect to other backplanes to help realize the connection between multiple backplanes 110-1...110-N. Signal interactions, such as low-speed management signal interactions.
  • the backplane system 100 further includes a flexible circuit component 120 connected to the first port 111 of each of the plurality of backplanes 110-1...110-N, and the flexible circuit component 120 Circuit component 120 is configured to transmit signals between multiple backplanes 110-1...110-N.
  • the flexible circuit component 120 may be a flexible printed circuit (FPC), and each first port 111 may include an FPC connector to connect with the FPC as the flexible circuit component 120 .
  • FPC can be, for example, a flexible printed circuit board made of polyimide or polyester film as a base material, and has the characteristics of high wiring density, light weight, thin thickness, and bendability.
  • selecting the flexible circuit component 120 as the interconnection component between the multiple backplanes 110-1...110-N can provide connection flexibility and various advantages. Specifically, if hard connectors are used to connect multi-layer backplanes, since the distance between adjacent backplanes may change for different products, the hard connectors interconnecting the two backplanes need to be specially designed. custom made To adapt to different products, this results in a lack of device versatility and increases development costs. In addition, due to the limitations of the pin density and structural orientation of the hard connector, the backplane system will not be able to expand more horizontal backplanes and/or more memories or hard drives, thus resulting in poor system scalability.
  • the embodiment of the present disclosure uses a flexible circuit component 120 that can be bent at will, which makes it possible to operate without too much consideration of the spacing distance between adjacent backplanes in the plurality of backplanes 110-1...110-N.
  • Multiple backplanes 110-1...110-N can be flexibly arranged without customizing connectors between backplanes according to the spacing distances of backplanes in different products.
  • backplanes can be easily expanded or added based on storage requirements and the size and specification of the chassis by simply adding wiring to the flexible circuit component 120 and connecting it to the newly expanded backplane.
  • a single horizontal backplane of a 2U (8.89cm thick) device can be configured with 6 2.5-inch hard drives, and can be expanded with 5 layers of backplanes, so up to 30 can be expanded Hard disk slot.
  • each of the backplanes 110-1...110-N may include an expander 118 adapted to expand the number of memory connected to the backplane.
  • the number of expanders 118 provided on the backplane may be one or more, and include but are not limited to SAS expanders (SAS expanders), UB/CXL/PCIe switches (UB/CXL/PCIe switches), and other types of expansion devices. . This allows more storage or hard drives to be expanded on a single backplane. However, it can be understood that some or all of the backplanes may not be provided with the expander 118, and the memory or hard disk may be expanded through SAS and PCIe/UB/CXL direct-out.
  • FIGS. 9 and 10 respectively show an installation according to the embodiment of the present disclosure.
  • a perspective view and a front view of the backplane system 100 of the memory 200 are shown.
  • the following description takes the backplane system including two backplanes 110-1 and 110-2 as an example.
  • each backplane has only two second ports 112 , that is, each backplane can connect up to two memories or hard drives.
  • the number of backplanes in the backplane system 100 and the number of the second ports 112 of each backplane are not limited thereto, and may be other appropriate numbers.
  • indicator lights may be set to display the status of the memory.
  • the backplane system 100 also includes at least one set of first indicator lights 130-1...130-L. At least one set of first indicator lights 130-1...130-L is disposed on the flexible circuit component 120. Each set of first indicators The lamp is configured to indicate a status of a corresponding memory in at least one memory 200 connected to the plurality of backplanes 110-1...110-N, and is adapted to be connected via a light guide column to a set of lights located on the housing 210 of the corresponding memory. Second indicator light 220 (see Figure 10).
  • a corresponding set of first indicator lights may be provided on the flexible circuit component 120 for each memory connected to the backplane system 100 .
  • Each group of first indicator lights can indicate the status of the corresponding memory.
  • each set of first indicator lights may include an indicator light for indicating that the memory is in an active state (ACTIVE) or a fault state (FAULT), and an indicator light for indicating that the memory is in a LOCATE state, where the ACTIVE
  • the indicator light for status (ACTIVE) or fault status (FAULT) can be one indicator light that displays different colors for the two states, or it can be two independent indicator lights. It can be understood that, as needed, more indicator lights or fewer indicator lights for indicating other states of the memory may be additionally provided, or part or all of the above indications may be replaced by indicator lights for indicating other states of the memory. lamp.
  • Each set of first indicator lights can transmit light signals to a corresponding set of second indicator lights 220 on the housing 210 of the corresponding memory through the light guide column, which helps the operator to observe and understand the status of the memory more easily.
  • each set of first indicator lights of the backplane system needs to be coupled to another set of second indicator lights on the casing of the memory through a light guide column that can conduct light signals, so that the operator can observe the light on the casing of the memory or hard disk. Second indicator light to know the status of the memory.
  • each group of first indicator lights in the backplane system is disposed on a horizontal backplane, it is often difficult to arrange the multiple indicator lights in each group of first indicator lights in the same direction as the corresponding second indicator lights on the casing of the memory. The lights remain consistent.
  • devices arranged on a horizontal backplane are usually arranged along the horizontal direction, but multiple indicator lights on the housing of the memory are usually arranged along the vertical direction.
  • multiple indicator lights on the housing of the memory are usually arranged along the vertical direction.
  • the two indicator lights are arranged in the same direction.
  • such two first indicator lights stacked on each other in the vertical direction require special customization, which increases the complexity and cost of the memory indicator light.
  • Embodiments of the present disclosure can avoid the above problems by disposing at least one set of first indicator lights 130-1...130-L on the flexible circuit component 120.
  • the flexible circuit component 120 can be bent as needed, and its length extends substantially in the vertical direction or the stacking direction of the backplane, while its width extends in the horizontal direction. Therefore, the first indicator light can be arranged correspondingly on the flexible circuit component 120 according to the arrangement of the second indicator light on the housing of the memory, and a certain degree of inconsistency can be tolerated without increasing the difficulty of arranging the light guide pillar, which increases the Flexibility in placement of memory status indicators.
  • each group of first indicator lights 130-1...130-L includes a plurality of first indicator lights, and each first indicator light is directly disposed on the surface of the flexible circuit component 200.
  • each first indicator light is directly disposed on the surface of the flexible circuit component 200.
  • the corresponding group of second indicator lights 220 on the housing of the memory is arranged along the vertical direction, there is no need to provide customized indicator lights stacked along the vertical direction as shown in FIG. 2 , but can be All the first indicator lights in each group of first indicator lights are directly arranged on the flexible circuit component 200 in sequence along the vertical direction. This avoids the cost of customizing the first indicator lights that overlap each other and enhances the versatility of the device. sex.
  • each of the plurality of backplanes 110-1...110-N includes a plurality of second ports 112 to connect the plurality of backplanes 110-1...110-N.
  • a plurality of columns of second ports are formed on one side of Section 123 (see FIG. 6 ), each first section 122 - 1 or 122 - 2 is arranged adjacent to a corresponding column of second ports and extends along the direction D1 of the plurality of backplane stacks.
  • each set of first indicator lights 130-1...130-L may be arranged adjacent to the second port 112 for the corresponding memory.
  • each backplane when each backplane has two second ports 112, the first section 122-1 of the flexible circuit component 120 can extend along a first column of second ports, and the first section 122-2 can extend along a first column of second ports. Two columns of second ports extend, and the two first sections 122-1 and 122-2 are interconnected by the second section 123. It is understood that each backplane may have more second ports, and the flexible circuit component 120 may be provided with more first sections corresponding to the number of columns of second ports. Since a section of the flexible circuit component 120 extends near each column of second ports, each group of first indicator lights disposed on the flexible circuit component 120 can be closer to the corresponding second port and therefore closer to the corresponding memory. Therefore, each group of first indicator lights can be conveniently directly connected to a group of second indicator lights 220 on the housing of the corresponding memory through the light guide column.
  • each of the plurality of backplanes 110-1...110-N includes at least one recess portion 114 (see Figure 5) for receiving the flexible circuit component 120, each recess Portion 114 is located between two adjacent second ports 112 . In this way, the flexible circuit component 120 can be arranged more compactly and occupy less space.
  • the backplane system 100 further includes a support plate 121 (see FIG. 5 ) to a board surface of which the flexible circuit component 120 is fixed.
  • the support plate 121 may be provided to guide and fix the flexible circuit component 120. In this manner, the flexible circuit component 120 can be positioned at a desired location to facilitate connection of the flexible circuit component 120 to each backplane.
  • the plurality of backplanes 110-1...110-N may include a main backplane 110-1 and a slave backplane 110-2...110-N, and the main backplane 110-1 is adapted to be connected to the substrate.
  • Management controller (baseboard management controller, BMC) 400, BMC 400 is configured to manage the main backplane 110-1 and manage the slave backplanes 110-2...110-N via the main backplane 110-1.
  • BMC 400 can implement a variety of management functions. It can manage other backplanes through the main backplane 110-1 and use the flexible circuit component 120 to transmit management signals.
  • main backplane in Figure 11 is the first layer backplane 110-1, but any other layer of backplane can also be selected as the main backplane, which can also implement the solution of the present disclosure.
  • each of the plurality of backplanes 110-1...110-N includes a control unit 115 and a master-slave mode control terminal BP_Slot interconnected with each other, and the flexible circuit component 120 includes a pull-down terminal and a The floating terminal, in which the master-slave mode control terminal BP_Slot of the main backplane 110-1 is is connected to one of the pull-down terminal and the floating terminal, and the master-slave mode control terminal BP_Slot of the slave backplane 110-2...110-N is connected to the other of the pull-down terminal and the floating terminal.
  • control unit 115 may be a complex programmable logic device (CPLD), and may include a plurality of modules, such as a satellite manager controller (SMC) 1151, a memory lighting module, and a module for Memory data transmission, status analysis and information collection related modules, etc.
  • SMC satellite manager controller
  • the pin of the CPLD used to control the operating mode can be connected to the 3.3V power supply potential and connected to the master-slave mode control terminal BP_Slot via a resistor.
  • the master-slave mode control terminal BP_Slot of the backplane 110-1 can be connected to the pull-down terminal of the flexible circuit component 120, so that the BP_Slot is placed at zero potential and the control unit 115 of the backplane 110-1 will be considered as the master backplane
  • the control unit; the master-slave mode control terminal BP_Slot of each backplane in the backplane 110-2...110-N can be connected to the floating terminal of the flexible circuit component 120, so that the BP_Slot is placed at a non-zero potential and the backplane
  • the control units of 110-2...110-N will be considered as the control units from the backplane.
  • the setup of the master-slave backplane can be completed simply and effectively.
  • the BP_Slot of the main backplane can also be connected to the floating terminal of the flexible circuit component 120, and the BP_Slot of the slave backplane can be connected to the pull-down terminal of the flexible circuit component 120, which can also implement the solution of the present disclosure.
  • each backplane of the plurality of backplanes 110-1...110-N includes a fourth port 119 connected to the control unit 115 and adapted to be connected to the BMC 400 .
  • fourth port 119 may include a low speed connector.
  • the BMC 400 may be connected to the control unit 115 of the main backplane via the fourth port 119 of the main backplane among the backplanes 110-1...110-N, and manage the plurality of backplanes 110-1...110-N to provide Various management functions.
  • management functions include, for example, hard disk status analysis, obtaining hard disk presence, reset, and status information, collecting backplane FRU (field replacement unit) and sensing temperature information, backplane CPLD firmware upgrade, hard disk management ( It includes management of hard disk temperature, hard disk firmware information, hard disk fault diagnosis information, etc.).
  • FIG. 13 shows a schematic diagram of a portion of circuitry of a computing device 1000 for implementing firmware upgrades, according to an embodiment of the present disclosure.
  • each of the plurality of backplanes 110-1...110-N further includes a first gating device 116 and a second gating device 117.
  • the two gate devices 117 each include a device connection terminal, a first channel (ie channel 0) and a second channel (ie channel 1), and are configured to connect the device connection terminals to the first channel based on a selection signal from the control unit 115 or second channel.
  • the first gating device 116 and the second gating device 117 may be devices such as a multiplexer (MUX).
  • MUX multiplexer
  • the selection signal input to the strobe device is a first level (such as a low level)
  • the selection signal of the device is at the second level (for example, high level)
  • the device connection end of the first strobe device 116 of each backplane is connected to the fourth port 119 , the first channel of the first strobe device 116 is connected to the firmware update interface 1152 of the control unit 115 , and the first strobe device 116 The second channel of 116 is connected to the SMC1151 of the control unit 115.
  • the firmware update interface 1152 may be a joint test action group (JTAG) interface of the CPLD, and is used to receive data to update or upgrade the firmware of the CPLD.
  • JTAG joint test action group
  • the device connection terminal of the second strobe device 117 is connected to the first port 111, the first channel of the second strobe device 117 is connected to the SMC 1151, and the second channel of the second strobe device 117 is connected to the first port 111.
  • the device connection or fourth port 119 of the gate device 116 is gated.
  • the SMC 1151 of the backplane 110-1 configured as a primary backplane is configured to forward firmware update data from the second channel of the first strobe device 116 to the first channel of the second strobe device 117.
  • a data transmission path from the BMC 400 to the firmware update interface 1152 of the control unit 115 of the main backplane can be formed in the main backplane by controlling the first strobe device 116 of the main backplane.
  • a data transmission path from the BMC 400 to the flexible circuit component 120 through the SMC 1151 can be formed in the main backplane by controlling the first gating device 116 and the second gating device 117 of the main backplane, and by controlling the slave The first gating device 116 and the second gating device 117 in the backplane form a data transmission path from the flexible circuit component 120 to the firmware update interface of the control unit in the backplane.
  • the control unit 115 of the main backplane 110-1 is configured to: in response to a firmware update on the main backplane 110-1 itself, to the first strobe of the main backplane 110-1 Device 116 issues a select signal to connect the device connection of first strobe device 116 Receive the first channel.
  • the first strobe device 116 of the main backplane 110-1 needs to be selected to use its first channel (ie, channel 0 in Figures 11 and 13) as the transmission channel .
  • the BMC 400 connected to the main backplane 110-1 can transmit update data to the firmware update interface 1152 via the fourth port 119 of the main backplane 110-1 and the first channel of the first strobe device 116, thereby completing the update.
  • the control unit 115 of the master backplane 110-1 is configured to: in response to a firmware update on the slave backplane 110-2...110-N, the control unit 115 of the master backplane 110-1
  • the first gating device 116 sends a selection signal to connect the device connection end of the first gating device 116 to the second channel, and sends a selection signal to the second gating device 117 of the main backplane 110-1 to connect the second selection signal.
  • the device connection of pass device 117 is connected to the first channel.
  • control unit 115 of the slave backplane 110-2...110-N is configured to: send a selection signal to the first gating device 116 of the slave backplane 110-2...110-N to switch the first gating device
  • the device connection terminal of 116 is connected to the first channel, and a selection signal is sent to the second gate device 117 from the backplane 110-2...110-N to connect the device connection terminal of the second gate device 117 to the second aisle.
  • the BMC 400 can provide data for firmware updates to the target slave backplane via the master backplane.
  • the first gating device 116 of the main backplane 110-1 needs to be selected to use its second channel (ie, channel 1) as the transmission channel , and it is also necessary to select the first channel (ie, channel 0) of the second gate device 117 of the main backplane 110-1 as the transmission channel.
  • the firmware update data from the BMC 400 can be transmitted to the slave backplane 110-N via the gating device 116, the SMC 1151, the gating device 117 and the flexible circuit component 120 of the main backplane 110-1 in sequence.
  • the second gating device (i.e., MUX1) of the backplane 110-N is switched to the second channel (i.e., channel 1), and the first gating device (i.e., MUX0) of the backplane 110-N is switched to the first channel (i.e. channel 0).
  • the firmware update data transmitted to the flexible circuit component 120 may be further transmitted to the firmware update of the control unit of the slave backplane 110-N via the second gating device MUX1 and the first gating device MUX0 of the slave backplane 110-N.
  • Interface JTAG to complete the firmware update for the control unit of the slave backplane 110-N.
  • the SMC 1151 of the master backplane 110-1 can forward the firmware update data from the BMC 400 to each slave backplane 110-2 via the flexible circuit component 120... ...Control unit for 110-N.
  • the CPLD serving as the control unit of the main backplane 110-1 may provide a CPLD_JTAG interface, and the CPLD_JTAG interface may be connected to the control units of each slave backplane 110-2...110-N via the wiring of the flexible circuit component 120.
  • CPLD serving as the control unit of the main backplane 110-1 may provide a CPLD_JTAG interface, and the CPLD_JTAG interface may be connected to the control units of each slave backplane 110-2...110-N via the wiring of the flexible circuit component 120.
  • the CPLD of the main backplane 110-1 can use the CPLD_JTAG interface to interact with the CPLDs of the slave backplanes 110-2...110-N, and help the CPLDs of the slave backplane complete firmware updates.
  • the fourth port 119 is connected to the SMC 1151 of the control unit 115 via the data bus
  • the SMC 1151 is connected to the first port 111 via its high-speed serial interface
  • the SMC 1151 is It is configured to obtain information about at least one of memory status, FRU of the backplane, and sensed temperature of the backplane to which it belongs.
  • the SMC 1151 of the master backplane 110-1 is also configured to provide information from the master backplane 110-1 to the BMC 400, and to receive and provide information from the slave backplanes 110-2...110-N to the BMC 400.
  • the fourth port 119 may also be connected to The SMC 1151 of the control unit 115, and the control unit 115 or the SMC 1151 can obtain and collect various information related to the backplane, such as hard disk status information.
  • the BMC 400 will connect to the fourth port 119 of the backplane and obtain the information collected by the SMC 1151 from the backplane via the I2C bus.
  • BMC 400 can obtain information from the slave backplane with the help of the master backplane.
  • control unit 115 or SMC 1151 of the main backplane can define a high speed serial port (HiSport), and connect the HiSport interface to the first port 111 to connect to other backplanes via the flexible circuit component 120 . Therefore, the control unit 115 or SMC of the main backplane 1151 can receive information from the control unit or SMC of the slave backplane via the HiSport interface, and provide the obtained information of other backplanes to the BMC 400, thereby realizing management of the slave backplane.
  • HiSport high speed serial port
  • the control unit 115 of each backplane of the plurality of backplanes 110-1...110-N is configured to control one or more groups of first indicator lights corresponding thereto.
  • the control unit 115 may be provided with a memory lighting module, and the module may send a signal to the flexible circuit component 120 according to the status of the hard disk parsed by the control unit to control a corresponding set of first indicator lights to emit light, thereby indicating that the hard disk is in In place, active or fault state.
  • the analysis of the hard disk status of each backplane can be independently completed by the backplane's own control unit, and the control unit of each backplane can independently control the corresponding set or sets of first indicator lights. glow.
  • the computing device provided according to the present application is described in detail above with reference to FIGS. 1 to 15 .
  • the device management method provided by the present application based on the above computing device will be described with reference to FIGS. 16 to 20 .
  • FIG. 16 shows a schematic flowchart of a management method 1600 for a computing device 1000 according to an embodiment of the present disclosure.
  • the management method 1600 may be implemented in the computing device 1000 of FIGS. 2 and 11 . It can be understood that various aspects described above with respect to FIGS. 2 to 15 may be applicable to the management method 1600 . For purposes of discussion, the management method 1600 will be described in conjunction with FIGS. 2-15.
  • the main backplane 110-1 of the plurality of backplanes 110-1...110-N is managed by the baseboard management controller 400, which is connected to the main backplane 110-1.
  • the slave backplanes 110-2...110-N of the plurality of backplanes 110-1...110-N are managed by the baseboard management controller 400 via the master backplane 110-1.
  • the master-slave mode control terminal BP_Slot of the master backplane 110-1 is connected to one of the pull-down terminal and the floating terminal of the flexible circuit component 120, and the slave backplanes 110-2...110
  • the master-slave mode control terminal BP_Slot of -N is connected to the other one of the pull-down terminal and the floating terminal of the flexible circuit component 120 .
  • Figure 17 illustrates a schematic flow diagram of a method 1700 of managing a primary backplane in some embodiments of the present disclosure.
  • Method 1700 may be implemented at block 1601 of Figure 16 .
  • a selection signal is sent by the control unit 115 of the main backplane 110-1 to the first gating device 116 of the main backplane 110-1.
  • firmware update data is provided by the baseboard management controller 400 to the control unit 115 of the main backplane 110 - 1 via the first strobe device 116 of the main backplane 110 - 1 to modify the main backplane 110 - 1 .
  • the control unit 115 performs firmware updates.
  • Figure 18 illustrates a schematic flow diagram of a method 1800 of managing a slave backplane in some embodiments of the present disclosure.
  • Method 1800 may be implemented at block 1602 of FIG. 16 .
  • control unit 115 of the main backplane 110-1 sends a selection signal to the first gating device 116 and the second gating device 117 of the main backplane 110-1.
  • a selection signal is sent from the control unit 115 of the slave backplane 110-2...110-N to the first gating device 116 and the second gating device 117 of the slave backplane 110-2...110-N. .
  • the baseboard management controller 400 via the first gating device 116, the control unit 115 and the second gating device 117 of the master backplane 110-1, the flexible circuit component 120, and the slave backplane 110-2...
  • the second gating device 117 and the first gating device 116 of ...110-N provide firmware update data to the control unit 115 of the slave backplane 110-2...110-N to modify the slave backplane 110-2...110 -N's control unit 115 performs a firmware update.
  • Figure 19 illustrates a schematic flow diagram of another method 1900 of managing a primary backplane in some embodiments of the present disclosure.
  • Method 1900 may be implemented at block 1601 of Figure 16 .
  • information related to at least one of memory status, FRUs of the backplane, and sensed temperature of the backplane is obtained by the control unit 115 of the main backplane 110 - 1 .
  • the acquired information is forwarded to the baseboard management controller 400 by the control unit 115 of the main backplane 110-1.
  • Figure 20 illustrates a schematic flow diagram of another method 2000 of managing a slave backplane in some embodiments of the present disclosure.
  • Method 2000 may be implemented at block 1602 of FIG. 16 .
  • the associated slave backplane's and memory status, the backplane's FRUs, and the backplane's sensed temperature are obtained by the control unit 115 of each of the slave backplanes 110 - 2 . . . 110 -N. information related to at least one of the
  • the acquired information is forwarded by the control unit 115 of the slave backplanes 110-2...110-N to the baseboard management controller 400 via the control unit 115 of the master backplane 110-1.
  • the present application also provides a baseboard management controller, which is used to implement the operating steps of the methods performed by the corresponding subjects in the above-mentioned Figures 16 to 20.
  • the management device is used to implement the operation steps of each method in the above-mentioned Figures 16 to 20.
  • a flexibly expandable and energy-efficient storage solution is provided.
  • This solution effectively increases system air volume, reduces power consumption of the air-cooling system, and improves system energy efficiency. It also enables flexible expansion of multi-layer backplanes and memories without the need for high-cost device customization, which expands the backplane system and computing capabilities. Applicable scenarios and scope of the equipment.
  • embodiments of the present disclosure can also achieve efficient management of a backplane system including multiple backplanes.
  • the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the processes or functions described in the embodiments of the present invention are generated in whole or in part.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium may be any available medium that a computer can access, or a data storage device such as a server or a data center that contains one or more sets of available media.
  • the usable media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, DVD), or semiconductor media.
  • the semiconductor medium may be a solid state disk (SSD).

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Abstract

一种背板系统、计算设备以及用于计算设备的管理方法，涉及计算机领域。该背板系统包括：多个背板，被布置为彼此平行地堆叠、并且彼此间隔开，每个背板包括：第一端口；第二端口，被配置为连接到存储器；以及第三端口，被配置为连接到控制器；以及柔性电路部件，连接到多个背板中的每个背板的第一端口，并且柔性电路部件被配置为在多个背板之间传输信号。可以提高系统能效、实现背板和存储器的灵活扩展并且扩大了背板系统和计算设备的适用范围。

Description

背板系统、计算设备以及用于计算设备的管理方法 技术领域
本公开涉及计算机技术领域，更具体地，涉及一种背板系统、包括该背板系统的计算设备、以及用于计算设备的管理方法。
背景技术
随着大数据、云计算等新技术的快速发展，诸如服务器之类的高性能计算设备被广泛应用于各个行业和场景。这种计算设备通常会包括中央处理单元(central processing unit，CPU)、主板、存储器等组件。由于各种应用中对算力需求的不断增长，计算设备的系统功耗大幅增加，并且大幅增加的功耗所引起的温度上升会抑制诸如CPU之类的处理器的性能。因此，计算设备对于散热的要求也越来越高，以便确保高功耗的处理器性能仍然能够充分释放。
目前，为了在诸如服务器之类的计算设备中提升散热能力，可以通过提高风冷系统的风扇转速的方式提升系统的风量。然而，由于诸如存储器的背板(也称为硬盘背板)与CPU所在主板(mainboard)垂直设置，硬盘背板设置在CPU和风扇之间，这就导致硬盘背板阻挡了冷却气流。尽管可以通过在硬盘背板上设置通风孔增加冷却风的流量，但是，由于硬盘背板中需考虑电路走线、器件设置等因素，通风孔的位置和数量均受限，这就导致计算设备中的风量受限，无法满足不断提升的处理器的散热需求。
发明内容
为了解决上述问题，本公开提供了一种改进的背板系统、计算设备以及用于计算设备的管理方法。
第一方面，提供了一种背板系统，该背板系统包括：多个背板，被布置为彼此平行地堆叠、并且彼此间隔开，每个背板包括：第一端口；第二端口，被配置为连接到存储器；以及第三端口，被配置为连接到存储控制器；以及柔性电路部件，连接到多个背板中的每个背板的第一端口，并且柔性电路部件被配置为在多个背板之间传输信号。
在本公开的方案中，通过提供平行布置的多个背板以及将多个背板互连的柔性电路部件，可以在实现低风阻和高能效的同时，实现背板和存储器的灵活扩展，并且无需定制器件，从而以较低成本扩大了背板系统和包括该背板系统的计算设备的适用场景和范围。
在一种可能的实现方式中，背板系统还包括：至少一组第一指示灯，设置在柔性电路部件上，每组第一指示灯被配置为指示连接到多个背板的至少一个存储器中的对应存储器的状态，并且适于经由导光柱连接到位于对应存储器的壳体上的一组第二指示灯。可以更方便灵活地布置存储器状态指示灯。
在另一种可能的实现方式中，每组第一指示灯包括多个第一指示灯，每个第一指示灯均直接设置在柔性电路部件的表面。由此避免了专门定制相互叠置的第一指示灯而增加成本，增强了器件的通用性。
在另一种可能的实现方式中，多个背板中的每个背板均包括多个第二端口，以在多个背板的一侧形成多列第二端口，其中柔性电路部件包括多个第一区段以及将多个第一区段互连的第二区段，每个第一区段被布置为邻近对应的一列第二端口并且沿着多个背板堆叠的方向延伸，并且其中每组第一指示灯被布置为邻近用于对应存储器的第二端口。由此在每个背板均具有多个存储器的情况下，可以针对每个存储器容易地布置对应的第一指示灯、导光柱和第二指示灯，这降低了布置的难度。
在另一种可能的实现方式中，每个背板包括容纳柔性电路部件的至少一个凹口部，每个凹口部位于相邻的两个第二端口之间。可以更加紧凑地布置柔性电路部件并且减少空间占用。
在另一种可能的实现方式中，背板系统还包括支撑板，柔性电路部件被固定至支撑板的板表面。有助于引导和固定柔性电路部件，以便于柔性电路部件连接到各个背板。
在另一种可能的实现方式中，多个背板包括主背板和从背板，主背板适于连接到基板管理控制器，基板管理控制器被配置为管理主背板并且经由主背板管理从背板。通过主背板来管理其他背板并利用柔性电路部件来传输管理信号，从而在背板数目较多并且还可能进一步扩展的情况下实现了简单高效的管理。
在另一种可能的实现方式中，每个背板包括彼此互连的控制单元和主从模式控制端子，柔性电路部件包括下拉端子和悬空端子，并且其中主背板的主从模式控制端子被连接到下拉端子和悬空端子中的一者，并且从背板的主从模式控制端子被连接到下拉端子和悬空端子中的另一者。可以以简单有效的方式针对多个背板进行主从模式的设置。
在另一种可能的实现方式中，每个背板包括：第四端口，连接到控制单元，并且适于连接到基板管理控制器。可以简单高效地实现针对多个背板的管理。
在另一种可能的实现方式中，每个背板还包括：第一选通器件和第二选通器件，各自包括器件连接端、第一通道和第二通道，并且被配置为基于来自控制单元的选择信号将器件连接端连接到第一通道或第二通道，其中第一选通器件的器件连接端连接到第四端口，第一选通器件的第一通道连接到控制单元的固件更新接口，并且第一选通器件的第二通道连接到控制单元的卫星管理控制器；并且其中第二选通器件的器件连接端连接到第一端口，第二选通器件的第一通道被连接到卫星管理控制器，并且第二选通器件的第二通道连接到第一选通器件的器件连接端，主背板的卫星管理控制器被配置为将来自第一选通器件的第二通道的固件更新数据转发给第二选通器件的第一通道。可以提供从基板管理控制器到主背板的控制单元的数据传输路径并且提供从基板管理控制器经由主背板的控制单元到从背板的控制单元的数据传输路径，从而帮助实现主背板和从背板的固件更新。
在另一种可能的实现方式中，主背板的控制单元被配置为：响应于对主背板自身进行固件更新，向主背板的第一选通器件发出选择信号以将第一选通器件的器件连接端连接到第一通道；以及响应于对从背板进行固件更新，向主背板的第一选通器件发出选择信号以将第一选通器件的器件连接端连接到第二通道，并向主背板的第二选通器件发出选择信号以将第二选通器件的器件连接端连接到第一通道，以及其中从背板的控制单元被配置为：向从背板的第一选通器件发出选择信号以将第一选通器件的器件连接端连接到第一通道，并且向从背板的第二选通器件发出选择信号以将第二选通器件的器件连接端连接到第二通道。可以实现主背板的固件更新，并且在主背板的帮助下实现从背板的固件更新。
在另一种可能的实现方式中，在每个背板中，第四端口经由数据总线连接到控制单元的卫星管理控制器，卫星管理控制器经由其高速串行接口连接到第一端口，并且卫星管理控制器被配置为获取所属背板的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息，并且其中主背板的卫星管理控制器还被配置为将主背板的信息提供给基板管理控制器，并且接收来自从背板的信息并提供给基板管理控制器。可以获取主背板的信息，并且利用主背板获取从背板的信息，从而实现多个背板的高效管理。
在另一种可能的实现方式中，每个背板的控制单元被配置为控制与其对应的一组或多组第一指示灯。可以简单有效地控制存储器状态指示灯。
在另一种可能的实现方式中，每个背板还包括扩展器，扩展器适于扩展连接到背板的存储器的数目。可以在单个背板上扩展连接更多的存储器或硬盘。
第二方面，提供了一种计算设备，包括：根据第一方面的背板系统。
第三方面，提供了一种用于根据第二方面的计算设备的管理方法，该管理方法包括：由基板管理控制器管理多个背板中的主背板，基板管理控制器被连接到主背板；以及由基板管理控制器经由主背板来管理多个背板中的从背板。
在一种可能的实现方式中，主背板的主从模式控制端子被连接到柔性电路部件的下拉端子和悬空端子中的一者，并且从背板的主从模式控制端子被连接到柔性电路部件的下拉端子和悬空端子中的另一者。
在另一种可能的实现方式中，由基板管理控制器管理多个背板中的主背板包括：由主背板的控制单元向主背板的第一选通器件发出选择信号；以及由基板管理控制器经由主背板的第一选通器件向主背板的控制单元提供固件更新数据，以对主背板的控制单元进行固件更新，并且其中由基板管理控制器经由主背板来管理多个背板中的从背板包括：由主背板的控制单元向主背板的第一选通器件和第二选通器件发出选择信号；由从背板的控制单元向从背板的第一选通器件和第二选通器件发出选择信号；以及由基板管理控制器经由主背板的第一选通器件、控制单元和第二选通器件、柔性电路部件、以及从背板的第二选通器件和第一选通器件向从背板的控制单元提供固件更新数据，以对从背板的控制单元进行固件更新。
在另一种可能的实现方式中，由基板管理控制器管理多个背板中的主背板包括：由主背板的控制单元获取主背板的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息；以及由主背板的控制单元将获取的信息转发给基板管理控制器，并且其中由基板管理控制器经由主背板来管理多个背板中的从背板包括由从背板中的每个从背板的控制单元获取所属从背板的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息；以及由从背板的控制单元将获取的信息经由主背板的控制单元转发给基板管理控制器。
第四方面，提供了一种计算设备的管理装置，所述管理装置包括用于执行第三方面或第三方面任一种可能实现方式中的计算设备的管理方法的各个模块。
第五方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
第六方面，本申请提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
附图说明
图1示出了示出了一种常规方案中的背板系统。
图2示出了根据本公开提供的一种计算设备的示意图。
图3示出了根据本公开提供的一种背板系统的简化示意图。
图4示出了根据本公开提供的一种背板系统中的背板的立体示意图。
图5示出了根据本公开提供的一种背板系统的立体视图。
图6示出了根据本公开提供的一种背板系统的正视图。
图7示出了根据本公开提供的一种背板系统的侧视图。
图8示出了根据本公开提供的一种背板系统的俯视图。
图9示出了根据本公开提供的一种安装了存储器的背板系统的立体视图。
图10示出了根据本公开提供的一种安装了存储器的背板系统的正视图。
图11示出了根据本公开提供的一种计算设备中的部分电路的电路框图。
图12示出了根据本公开提供的一种计算设备的用于确定主从背板的部分电路的示意图。
图13示出了根据本公开提供的一种计算设备的用于实现固件升级的部分电路的示意图。
图14示出了根据本公开提供的一种计算设备的用于实现固件升级的部分电路的示意图。
图15示出了根据本公开提供的一种计算设备的用于实现存储器、指示灯和背板管理的部分电路的示意图。
图16示出了根据本公开提供的一种用于计算设备的管理方法的示意性流程图。
图17示出了根据本公开提供的一种管理主背板的方法的示意性流程图。
图18示出了根据本公开提供的一种管理从背板的方法的示意性流程图。
图19示出了根据本公开提供的一种管理主背板的方法的示意性流程图。
图20示出了根据本公开提供的一种管理从背板的方法的示意性流程图。
附图标号说明
100’：背板系统 110’：开孔 1000：计算设备 100：背板系统 110-1……110-N：背板 111：第一端口 112：第二端口 113：第三端口 114：凹口部 115：控制单元 1151：卫星管理控制器 116：第一选通器件 117：第二选通器件 118：扩展器 119：第四端口 120：柔性电路部件 121：支撑板 122-1、122-2：柔性电路部件的第一区段 123：柔性电路部件的第二区段 130-1……130-L：第一指示灯 200：存储器 300：存储控制器 400：基板管理控制器 500：主板和中央处理单元 D1：第一方向 D2：第二方向
具体实施方式
为了提升计算设备的散热能力，本公开提供了一种改进的背板系统、包括该背板系统的计算设备以及用于管理计算设备的方法。在改进方案中，采用平行间隔布置的方式布置多个背板，并且利用柔性电路部件来互连这些背板。由此，不仅可以有效减少气流风阻和增大风量，并因此提升系统能效，而且还可以灵活扩展背板的数目和存储器的数目，而无需针对不同产品和应用专门定制器件，从而提供了一种高能效、低成本、并具有良好扩展性的存储解决方案。
下面将参照附图更详细地描述本公开的背板系统。
图1示出了一种常规方案中的背板系统100’。背板系统100’用于为服务器的主板和存储器(或硬盘)提供连接，并且通常设置在风扇与CPU之间，其中CPU是服务器中功耗较大的组件并是风扇的重要散热对象。如图1所示，背板系统100’采用了竖直一体化背板方案，并且在背板上设置有供冷却气流穿过的开孔110’。换言之，背板系统100’的板表面与来自冷却风扇的气流垂直，并且因此冷却气流需要穿过背板系统100’的开孔110’来进入后方的待冷却区域，从而为CPU和其他组件提供散热。
然而，背板系统100’的开孔率通常较低，例如不足20％。在设置有背板系统100’的服务器或其他计算设备中，如果仅通过提高风扇的转速来提升风量和散热能力，那么这种较低的开孔率会使系统风阻较大，并且严重限制风量的提升。在这种情况下，风扇会消耗更多的功率，导致系统能效降低而无法满足高算力场景下对能效的要求。
图2示出了根据本公开的实施例的计算设备1000的示意图。作为示例，计算设备1000可以是服务器，例如通用机架服务器，其可以作为节点被布置在网络中以实现数据和信息的处理。然而，可以理解，计算设备1000的实现方式不受限于此，而可以是任何适当类型的计算或处理装置。
如图2所示，计算设备1000可以包括背板系统100、至少一个存储器200、至少一个存储控制器300以及主板和中央处理单元500。作为示例，主板和中央处理单元500可以包括中央处理单元以及承载中央处理单元和其他电气和电子元件的主板。中央处理单元可以通过至少一个存储控制器300和背板系统100来访问至少一个存储器200以进行相关的操作，例如从存储器200中读取数据、进行数据的处理、以及写入和存储数据。至少一个存储控制器300可以包括但不限于串行连接的小型计算机系统接口(serial attached small computer system interface，SAS)控制器、快捷外围部件互连标准(peripheral component interconnect  express，PCIe)控制器、统一总线(unified bus，UB)控制器、计算标准链接(compute express link，CXL)控制器等。至少一个存储器200可以包括但不限于SAS硬盘、串行高级技术附件(serial advanced technology attachment，SATA)硬盘、非易失性高速传输总线(non-volatile memory express，NVMe)硬盘以及其他类型的硬盘，并且还可以包括内存语义的存储介质，例如CXL、UB等。背板系统100可以将至少一个存储器200耦合到至少一个存储控制器300，从而可以在至少一个存储控制器300的控制下实现对至少一个存储器200的数据读写和存储。此外，除了可以为计算设备1000中的存储器(或硬盘)和主板提供相互连接之外，背板系统100还可以为主板提供电源和数据信号传输的框架。
图3示出了根据本公开的实施例的背板系统100的简化示意图，并且图4示出了根据本公开的实施例的背板系统100中的多个背板的立体示意图。虽然背板系统100在上文中被示出为计算设备1000的一部分，但是这种描述仅仅是示例性的，并且可以理解，背板系统100可以被广泛适用于诸如网络设备和存储设备之类的信息与通信技术(information and communications technology,ICT)基础设施设备、或者需要使用存储器的其他适当设备或装置。如图2至图4所示，背板系统100包括多个背板110-1……110-N，多个背板110-1……110-N被布置为彼此平行地堆叠、并且彼此间隔开。作为示例，多个背板110-1……110-N中的每个背板可以是硬质的印刷电路板(printed circuit board,PCB)，以提供存储器200与存储控制器300之间的高速连接。多个背板110-1……110-N可以在第一方向D1上依次堆叠并且彼此相距一定距离，从而在相邻背板之间形成足够大的间隙。当背板系统100被设置在服务器中时，风冷系统的散热风扇可以形成沿着与第一方向D1基本垂直的第二方向D2行进的冷却气流，并且该冷却气流可以在相邻背板之间的间隙中流过，从而穿过背板系统100进入后方的待冷却区域。
由此可见，与图1中的背板系统100’不同，背板系统100采用了水平背板的布置方式。也就是说，背板系统100的背板表面与来自冷却风扇的气流平行，这有效提升了背板系统100的开孔率并且降低风阻。这种布置方式可以极大的减少背板系统100对冷却气流的阻挡，由此可以提高冷却风量，而无需过多增大散热风扇转速，这避免了增加散热风扇的功耗并有效提升了系统能效。
根据本公开的计算设备，多个背板110-1……110-N中的每个背板可以包括第一端口111、被配置为连接到存储器200的第二端口112、以及被配置为连接到存储控制器300的第三端口113。作为示例，第二端口112可以包括存储器连接器(例如硬盘连接器)，并且可以在每个背板上设置M个第二端口112，以使M个存储器(即存储器1至存储器M)可以连接到对应的第二端口112，其中M是大于或等于1的整数。第三端口113可以包括控制器连接器。例如，如果存储控制器300包括SAS控制器，则第三端口113可以包括与SAS控制器相对应的SAS高速连接器，并且如果存储控制器300包括UB/CXL/PCIe控制器，则第三端口113还可以包括与UB/CXL/PCIe控制器相对应的UB/CXL/PCIe高速连接器。也就是说，第三端口113可以包括一个或多个端口，以分别用于连接SAS控制器、UB/CXL/PCIe控制器和其他类型控制器中的一个或多个控制器。此外，每个背板还设置有第一端口111，第一端口111可以为每个背板提供连接到其他背板的接口，以帮助实现多个背板110-1……110-N之间信号交互，例如低速管理信号交互。
根据本公开的实施例，背板系统100还包括柔性电路部件120，柔性电路部件120连接到多个背板110-1……110-N中的每个背板的第一端口111，并且柔性电路部件120被配置为在多个背板110-1……110-N之间传输信号。作为示例，柔性电路部件120可以是柔性电路板(flexible printed circuit,FPC)，并且每个第一端口111可以包括FPC连接器，以便与作为柔性电路部件120的FPC进行连接。FPC例如可以是以聚酰亚胺或聚酯薄膜为基材制成的可挠性印刷电路板，并且具有配线密度高、重量轻、厚度薄、弯折性等特点。相比于采用硬质连接器来连接多层背板，选择柔性电路部件120作为多个背板110-1……110-N之间的互连部件，可以提供连接的灵活性和多种优势。具体而言，如果采用硬质连接器来连接多层背板，由于相邻背板之间的距离对于不同产品可能会发生变化，因此互连两层背板的硬质连接器需要进行专门的定制 以适配不同产品，这导致器件缺乏通用性并增大了开发成本。此外，由于硬质连接器的Pin密度和结构导向的限制，背板系统将无法扩展更多的水平背板和/或更多的存储器或硬盘，因此会导致系统的可扩展性也比较差，这进一步限制了适用的场景和范围。与此不同，本公开的实施例采用了可随意弯折的柔性电路部件120，这使得无需过多考虑多个背板110-1……110-N中的相邻背板的间隔距离而可以灵活地布置多个背板110-1……110-N，并且不用针对不同产品中的背板的间隔距离来定制背板之间的连接器。此外，可以根据存储要求以及机箱的尺寸和规格方便地扩展或增加背板，而只需要增加柔性电路部件120的配线并且将其连接到新扩展的背板即可。例如，对于19英寸的标准机架服务器，2U(厚度为8.89cm)的设备的单个水平背板可以配置6个2.5英寸的硬盘，并且可以扩展5层背板，因此最多可以扩展多达30个硬盘槽位。
在本公开的一些实施例中，背板110-1……110-N中的每个背板可以包括扩展器118，扩展器118适于扩展连接到背板的存储器的数目。设置在背板上的扩展器118的数目可以一个或多个，并且包括但不限于SAS扩展器(SAS expander)、UB/CXL/PCIe交换机(UB/CXL/PCIe switch)以及其他类型的扩展器件。由此，可以在单个背板上扩展连接更多的存储器或硬盘。然而，可以理解，部分或所有背板也可以不设置扩展器118，并且可以通过SAS和PCIe/UB/CXL直出的方式扩展存储器或硬盘。
由此可见，通过设置柔性电路部件120，可以在提供低风阻和高能效的水平背板布置的同时，实现背板和存储器的灵活扩展，并且无需定制器件，从而以较低成本大大增加了背板系统和计算设备的适用场景和范围。
图5至图8分别示出了根据本公开的实施例的背板系统100的立体视图、正视图、侧视图和俯视图，并且图9和图10分别示出了根据本公开的实施例的安装了存储器200的背板系统100的立体视图和正视图。为了便于理解，接下来，以背板系统包括两个背板110-1和110-2为例进行说明。仅仅作为示例，每个背板仅具有两个第二端口112，即每个背板最多可以连接两个存储器或硬盘。然而，可以理解，背板系统100中的背板的数目以及每个背板的第二端口112的数目并不受此限制，而可以是其他适当数目。
在本公开的一些实施例中，为了便于维护，可以采用设置指示灯方式显示存储器的状态。背板系统100还包括至少一组第一指示灯130-1……130-L，至少一组第一指示灯130-1……130-L设置在柔性电路部件120上，每组第一指示灯被配置为指示连接到多个背板110-1……110-N的至少一个存储器200中的对应存储器的状态，并且适于经由导光柱连接到位于对应存储器的壳体210上的一组第二指示灯220(参见图10)。作为示例，针对连接到背板系统100的每个存储器，可以在柔性电路部件120上提供一组对应的第一指示灯。换言之，在背板数目为N并且每个背板连接的存储器数目为M的情况下，可以提供L组的第一指示灯，其中L＝N×M。每组第一指示灯可以指示对应存储器的状态。例如，每组第一指示灯可以包括用于指示存储器处于活动状态(ACTIVE)或处于故障状态(FAULT)的指示灯、以及用于指示存储器处于在位状态(LOCATE)的指示灯，其中处于活动状态(ACTIVE)或处于故障状态(FAULT)的指示灯可以是针对两种状态分别显示不同颜色的一个指示灯，也可以是两个彼此独立的指示灯。可以理解，根据需要，可以附加地设置用于指示存储器的其他状态的更多指示灯或设置更少的指示灯，或者将用于指示存储器的其他状态的指示灯来替换部分或全部的上述指示灯。每组第一指示灯可以通过导光柱将光信号传递到对应存储器的壳体210上的一组对应的第二指示灯220，这有利于操作人员更容易地观察和了解存储器的状态。
相比于将第一指示灯设置在背板上，将第一指示灯设置在柔性电路部件120上具有更多的益处。具体地，背板系统的每组第一指示灯需要通过能够传导光信号的导光柱耦合至存储器的壳体上另一组第二指示灯，以便操作人员通过观察存储器或硬盘的壳体上的第二指示灯来获知存储器的状态。然而，如果将背板系统中的每组第一指示灯设置在水平背板上，每组第一指示灯中的多个指示灯的布置方向常常难以与存储器的壳体上的对应的第二指示灯保持一致。例如，水平背板上布置的器件通常沿着水平方向布置，但是存储器的壳体上的多个指示灯通常沿着竖直方向布置。在这种情况下，为了便于布置导光柱，只能将同一组 第一指示灯中的两个或更多的第一指示灯沿着竖直方向彼此叠置在一起，以使该组第一指示灯的布置方向与存储器的壳体上的对应的一组第二指示灯的布置方向相同。然而，这种在竖直方向彼此叠置的两个第一指示灯需要进行专门的定制，这增加了存储器指示灯的复杂性和成本。本公开的实施例通过将至少一组第一指示灯130-1……130-L设置在柔性电路部件120上可以避免上述问题。柔性电路部件120可以根据需要进行弯折，并且其长度基本上沿着竖直方向或背板的堆叠方向延伸，而其宽度在水平方向上延伸。因此，可以根据存储器的壳体上的第二指示灯的布置情况在柔性电路部件120对应地布置第一指示灯并且容许具有一定的不一致性，而不会增加导光柱的布置难度，这增加了存储器状态指示灯的布置的灵活性。
在本公开的一些实施例中，每组第一指示灯130-1……130-L包括多个第一指示灯，每个第一指示灯均直接设置在柔性电路部件200的表面。作为示例，在存储器的壳体上的对应组的第二指示灯220沿着竖直方向布置的情况下，无需提供图2所示出的沿竖直方向叠置的定制指示灯，而可以将每组第一指示灯中的所有第一指示灯沿着竖直方向依次直接设置在柔性电路部件200上，这避免了专门定制相互叠置的第一指示灯而增加成本，增强了器件的通用性。
在本公开的一些实施例中，多个背板110-1……110-N中的每个背板均包括多个第二端口112，以在多个背板110-1……110-N的一侧形成多列第二端口，并且柔性电路部件120包括多个第一区段122-1、122-2、以及将多个第一区段122-1、122-2互连的第二区段123(参见图6)，每个第一区段122-1或122-2被布置为邻近对应的一列第二端口并且沿着多个背板堆叠的方向D1延伸。由此，每组第一指示灯130-1……130-L可以被布置为邻近用于对应存储器的第二端口112。例如，当每个背板具有两个第二端口112时，柔性电路部件120的第一区段122-1可以沿着第一列第二端口延伸，第一区段122-2可以沿着第二列第二端口延伸，并且两个第一区段122-1和122-2通过第二区段123互连。可以理解，每个背板可以具有更多的第二端口，并且柔性电路部件120可以设置有与第二端口的列数对应的更多的第一区段。由于在每列第二端口附近都有柔性电路部件120的区段延伸经过，因此设置在柔性电路部件120上的每组第一指示灯可以更加靠近对应的第二端口并因此靠近对应的存储器。由此，每组第一指示灯能够通过导光柱方便地直接连接到对应存储器的壳体上的一组第二指示灯220。
在本公开的一些实施例中，多个背板110-1……110-N中的每个背板包括容纳柔性电路部件120的至少一个凹口部114(参见图5)，每个凹口部114位于相邻的两个第二端口112之间。通过这种方式，可以更加紧凑地布置柔性电路部件120并且减少空间占用。
在本公开的一些实施例中，背板系统100还包括支撑板121(参见图5)，柔性电路部件120被固定至支撑板121的板表面。具体而言，为了便于布置柔性电路部件120，可以设置支撑板121以引导和固定柔性电路部件120。通过这种方式，可以将柔性电路部件120布置在期望的适当位置，以便于柔性电路部件120连接到各个背板。
图11示出了根据本公开的实施例的计算设备1000中的部分电路的电路框图。如图11所示，多个背板110-1……110-N可以包括主背板110-1和从背板110-2……110-N，主背板110-1适于连接到基板管理控制器(baseboard management controller,BMC)400，BMC 400被配置为管理主背板110-1并且经由主背板110-1管理从背板110-2……110-N。作为示例，BMC 400可以实现多种管理功能，其可以通过主背板110-1来管理其他背板并利用柔性电路部件120来传输管理信号，这在背板数目较多并且还可能进一步扩展的情况下实现了简单高效的管理。可以理解，图11中的主背板是第一层背板110-1，但是也可以选择任何其他层的背板作为主背板，这同样可以实现本公开的方案。
图12示出了根据本公开的实施例的计算设备1000的用于确定主从背板的部分电路的示意图。如图11和12所示，多个背板110-1……110-N中的每个背板包括彼此互连的控制单元115和主从模式控制端子BP_Slot，柔性电路部件120包括下拉端子和悬空端子，其中主背板110-1的主从模式控制端子BP_Slot被 连接到下拉端子和悬空端子中的一者，并且从背板110-2……110-N的主从模式控制端子BP_Slot被连接到下拉端子和悬空端子中的另一者。作为示例，控制单元115可以是复杂可编程逻辑器件(complex programmable logic device,CPLD)，并且可以包括多个模块，例如卫星管理控制器(satellite manager controller，SMC)1151、存储器点灯模块、以及用于存储器的数据传输、状态解析和信息收集的相关模块等。CPLD的用于控制工作模式的引脚可以连接到3.3V电源电位并经由电阻连接到主从模式控制端子BP_Slot。例如，可以将背板110-1的主从模式控制端子BP_Slot连接到柔性电路部件120的下拉端子，从而BP_Slot被置于零电位并且背板110-1的控制单元115将被认为是主背板的控制单元；可以将背板110-2……110-N中的每个背板的主从模式控制端子BP_Slot连接到柔性电路部件120的悬空端子，从而BP_Slot被置于非零电位并且背板110-2……110-N的控制单元将被认为是从背板的控制单元。由此，可以简单有效地完成主从背板的设置。此外，也可以是主背板的BP_Slot连接到柔性电路部件120的悬空端子，而从背板的BP_Slot连接到柔性电路部件120的下拉端子，这同样可以实现本公开的方案。
在本公开的一些实施例中，多个背板110-1……110-N中的每个背板包括第四端口119，第四端口119连接到控制单元115，并且适于连接到BMC 400。作为示例，第四端口119可以包括低速连接器。BMC 400可以经由背板110-1……110-N中的主背板的第四端口119连接到主背板的控制单元115，并且管理多个背板110-1……110-N以提供各种管理功能，这些管理功能例如包括硬盘状态解析、获取硬盘在位、复位、状态信息、收集背板的FRU(field replace unit)和感测温度信息、背板的CPLD固件升级、硬盘管理(其包括管理硬盘温度、硬盘固件信息以及硬盘故障诊断信息等)等。
图13示出了根据本公开的实施例的计算设备1000的用于实现固件升级的部分电路的示意图。如图11和13所示，多个背板110-1……110-N中的每个背板还包括第一选通器件116和第二选通器件117，第一选通器件116和第二选通器件117各自包括器件连接端、第一通道(即通道0)和第二通道(即通道1)，并且被配置为基于来自控制单元115的选择信号将器件连接端连接到第一通道或第二通道。作为示例，第一选通器件116和第二选通器件117可以是诸如多路复用器(multiplexer,MUX)之类的器件。例如，当输入到选通器件的选择信号为第一电平(例如低电平)时，可以选择将器件连接端连接到第一通道以通过第一通道进行信号传输，而当输入到选通器件的选择信号为第二电平(例如高电平)时，可以选择将器件连接端连接到第二通道以通过第二通道进行信号传输，由此可以根据需要来选择不同的数据或信号传输路径。
每个背板的第一选通器件116的器件连接端被连接到第四端口119，第一选通器件116的第一通道连接到控制单元115的固件更新接口1152，并且第一选通器件116的第二通道连接到控制单元115的SMC1151。作为示例，固件更新接口1152可以是CPLD的联合测试行动组(joint test action group,JTAG)接口，并且被用于接收数据以对该CPLD的固件进行更新或升级。此外，第二选通器件117的器件连接端连接到第一端口111，第二选通器件117的第一通道被连接到SMC 1151，并且第二选通器件117的第二通道连接到第一选通器件116的器件连接端或者第四端口119。被设置作为主背板的背板110-1的SMC 1151被配置为能够将来自第一选通器件116的第二通道的固件更新数据转发给第二选通器件117的第一通道。
借助于这种布置方式，可以通过控制主背板的第一选通器件116，在主背板中形成从BMC 400到主背板的控制单元115的固件更新接口1152的数据传输路径。此外，还可以通过控制主背板的第一选通器件116和第二选通器件117，在主背板中形成从BMC 400经过SMC 1151到柔性电路部件120的数据传输路径，以及通过控制从背板中的第一选通器件116和第二选通器件117，在从背板中形成从柔性电路部件120到控制单元的固件更新接口的数据传输路径。
如果对主背板进行固件更新，则主背板110-1的控制单元115被配置为：响应于对主背板110-1自身进行固件更新，向主背板110-1的第一选通器件116发出选择信号以将第一选通器件116的器件连接端连 接到第一通道。换言之，当主背板110-1自身进行固件更新时，主背板110-1的第一选通器件116需要被选择为以其第一通道(即图11和13中的通道0)作为传输通道。此时，连接到主背板110-1的BMC 400可以经由主背板110-1的第四端口119和第一选通器件116的第一通道向固件更新接口1152传输更新数据，从而完成对主背板110-1的控制单元115的固件更新。
如果对从背板进行固件更新，则主背板110-1的控制单元115被配置为：响应于对从背板110-2……110-N进行固件更新，向主背板110-1的第一选通器件116发出选择信号以将第一选通器件116的器件连接端连接到第二通道，并向主背板110-1的第二选通器件117发出选择信号以将第二选通器件117的器件连接端连接到第一通道。此外，从背板110-2……110-N的控制单元115被配置为：向从背板110-2……110-N的第一选通器件116发出选择信号以将第一选通器件116的器件连接端连接到第一通道，并且向从背板110-2……110-N的第二选通器件117发出选择信号以将第二选通器件117的器件连接端连接到第二通道。
换言之，BMC 400可以经由主背板向目标从背板提供用于固件更新的数据。具体而言，当从背板110-N的控制单元115进行固件更新时，主背板110-1的第一选通器件116需要被选择为以其第二通道(即通道1)作为传输通道，并且还需要将主背板110-1的第二选通器件117的第一通道(即通道0)选择作为传输通道。由此，来自BMC 400的固件更新数据可以依次经由主背板110-1的选通器件116、SMC 1151、选通器件117和柔性电路部件120传输到从背板110-N。此外，从背板110-N的第二选通器件(即MUX1)切换为第二通道(即通道1)，并且从背板110-N的第一选通器件(即MUX0)切换为第一通道(即通道0)。由此，传输到柔性电路部件120的固件更新数据可以进一步经由从背板110-N的第二选通器件MUX1和第一选通器件MUX0传输到从背板110-N的控制单元的固件更新接口JTAG，从而完成针对从背板110-N的控制单元的固件更新。
图14进一步示出了根据本公开的实施例的计算设备1000的用于实现固件升级的部分电路的示意图。在利用主背板的SMC对从背板进行固件更新的过程中，主背板110-1的SMC 1151可以将来自BMC 400固件更新数据经由柔性电路部件120转发给各个从背板110-2……110-N的控制单元。例如，主背板110-1的作为控制单元的CPLD可以提供CPLD_JTAG接口，该CPLD_JTAG接口可以经由柔性电路部件120的配线分别连接到各个从背板110-2……110-N的作为控制单元的CPLD。通过这种方式，主背板110-1的CPLD可以利用CPLD_JTAG接口与从背板110-2……110-N的CPLD进行交互，并且帮助从背板的CPLD完成固件更新。
图15示出了根据本公开的实施例的计算设备1000的用于实现存储器、指示灯和背板管理的部分电路的示意图。如图11和图15所示，在每个背板中，第四端口119经由数据总线连接到控制单元115的SMC1151，SMC 1151经由其高速串行接口连接到第一端口111，并且SMC 1151被配置为获取其所属背板的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息。主背板110-1的SMC 1151还被配置为将主背板110-1的信息提供给BMC 400，并且接收来自从背板110-2……110-N的信息并提供给BMC 400。
作为示例，在每个背板中，除了第一选通器件116形成的传输路径之外，第四端口119还可以经由内部集成电路(inter-integrated circuit,I2C)总线或者其他类型的总线连接到控制单元115的SMC 1151，并且控制单元115或SMC 1151可以获取和收集与该背板有关的各种信息，例如硬盘状态信息。在该背板是主背板的情况下，BMC 400将连接到该背板的第四端口119，并且经由I2C总线从该背板的SMC 1151获取该SMC 1151收集到的信息。此外，BMC 400可以借助于主背板来获取从背板的信息。具体而言，主背板的控制单元115或SMC 1151可以定义高速串行接口(high speed serial port,HiSport)，并且将HiSport接口连接到第一端口111以经由柔性电路部件120连接到其他背板。由此，主背板的控制单元115或SMC 1151可以经由HiSport接口接收来自从背板的控制单元或SMC的信息，并将获取的其他背板的信息提供给BMC 400，从而实现针对从背板的管理。
在本公开的一些实施例中，多个背板110-1……110-N中的每个背板的控制单元115被配置为控制与其对应的一组或多组第一指示灯。作为示例，控制单元115可以设置有存储器点灯模块，并且该模块可以根据控制单元所解析的硬盘的状态向柔性电路部件120发出信号，以控制对应的一组第一指示灯发光，从而指示硬盘处于在位状态、活动状态或故障状态。在一个实施例中，每个背板的硬盘状态的解析可以由该背板自身的控制单元独立完成，并且每个背板的控制单元可以独立地控制对应的一组或多组第一指示灯发光。
上文中结合图1至图15，详细描述了根据本申请所提供的计算设备，下面将结合图16至图20，描述根据本申请基于上述计算设备所提供的设备管理方法。
图16示出了根据本公开的实施例的用于计算设备1000的管理方法1600的示意性流程图。管理方法1600可以在图2和图11的计算设备1000中实现。可以理解，上面关于图2至图15所描述的各个方面，可以适用于管理方法1600。为了讨论的目的，将结合图2至图15来描述管理方法1600。
在框1601处，由基板管理控制器400管理多个背板110-1……110-N中的主背板110-1，该基板管理控制器400被连接到主背板110-1。
在框1602处，由基板管理控制器400经由主背板110-1来管理多个背板110-1……110-N中的从背板110-2……110-N。
在本公开的一些实施例中，主背板110-1的主从模式控制端子BP_Slot被连接到柔性电路部件120的下拉端子和悬空端子中的一者，并且从背板110-2……110-N的主从模式控制端子BP_Slot被连接到柔性电路部件120的下拉端子和悬空端子中的另一者。
图17示出了在本公开的一些实施例中的管理主背板的方法1700的示意性流程图。方法1700可以在图16的框1601处实现。
在框1701处，由主背板110-1的控制单元115向主背板110-1的第一选通器件116发出选择信号。
在框1702处，由基板管理控制器400经由主背板110-1的第一选通器件116向主背板110-1的控制单元115提供固件更新数据，以对主背板110-1的控制单元115进行固件更新。
图18示出了在本公开的一些实施例中的管理从背板的方法1800的示意性流程图。方法1800可以在图16的框1602处实现。
在框1801处，由主背板110-1的控制单元115向主背板110-1的第一选通器件116和第二选通器件117发出选择信号。
在框1802处，由从背板110-2……110-N的控制单元115向从背板110-2……110-N的第一选通器件116和第二选通器件117发出选择信号。
在框1803处，由基板管理控制器400经由主背板110-1的第一选通器件116、控制单元115和第二选通器件117、柔性电路部件120、以及从背板110-2……110-N的第二选通器件117和第一选通器件116向从背板110-2……110-N的控制单元115提供固件更新数据，以对从背板110-2……110-N的控制单元115进行固件更新。
图19示出了在本公开的一些实施例中的管理主背板的另一方法1900的示意性流程图。方法1900可以在图16的框1601处实现。
在框1901处，由主背板110-1的控制单元115获取主背板110-1的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息。
在框1902处，由主背板110-1的控制单元115将获取的信息转发给基板管理控制器400。
图20示出了在本公开的一些实施例中的管理从背板的另一方法2000的示意性流程图。方法2000可以在图16的框1602处实现。
在框2001处，由从背板110-2……110-N中的每个从背板的控制单元115获取所属从背板的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息。
在框2002处，由从背板110-2……110-N的控制单元115将获取的信息经由主背板110-1的控制单元115转发给基板管理控制器400。
作为一种可能的实现方式中，本申请还提供一种基板管理控制器，该基板管理控制器用于实现上述图16至图20中相应主体所执行方法的操作步骤。
作为一种可能的实现方式中，该管理装置用于实现上述图16至图20中各个方法的操作步骤。
通过本公开的实施例，提供了一种灵活扩展的高能效存储解决方案。该方案在有效提升系统风量、降低风冷系统的功耗和改善系统能效的同时，实现了多层背板和存储器的灵活扩展，而无需高成本的器件定制，这扩大了背板系统和计算设备的适用场景和范围。此外，本公开的实施例还可以实现对包括多个背板的背板系统的高效管理。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本发明本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state disk，SSD)。
通过以上描述和相关附图中所给出的教导，这里所给出的本公开的许多修改形式和其它实施方式将被本公开相关领域的技术人员所意识到。因此，所要理解的是，本公开的实施方式并不局限于所公开的具体实施方式，并且修改形式和其它实施方式意在包括在本公开的范围之内。此外，虽然以上描述和相关附图在部件和/或功能的某些示例组合形式的背景下对示例实施方式进行了描述，但是应当意识到的是，可以由备选实施方式提供部件和/或功能的不同组合形式而并不背离本公开的范围。就这点而言，例如，与以上明确描述的有所不同的部件和/或功能的其它组合形式也被预期处于本公开的范围之内。虽然这里采用了具体术语，但是它们仅以一般且描述性的含义所使用而并非意在进行限制。

Claims (19)

  1. 一种背板系统(100)，其特征在于，包括：
    多个背板(110-1……110-N)，被布置为彼此平行地堆叠、并且彼此间隔开，每个背板(110-1……110-N)包括：
    第一端口(111)；
    第二端口(112)，被配置为连接到存储器(200)；以及
    第三端口(113)，被配置为连接到存储控制器(300)；以及
    柔性电路部件(120)，连接到所述多个背板(110-1……110-N)中的每个背板的第一端口(111)，并且所述柔性电路部件(120)被配置为在所述多个背板(110-1……110-N)之间传输信号。
  2. 根据权利要求1所述的背板系统(100)，其特征在于，还包括：
    至少一组第一指示灯(130-1……130-L)，设置在所述柔性电路部件(120)上，每组第一指示灯(130-1……130-L)被配置为指示连接到所述多个背板(110-1……110-N)的至少一个存储器(200)中的对应存储器的状态，并且适于经由导光柱连接到位于所述对应存储器的壳体(210)上的一组第二指示灯(220)。
  3. 根据权利要求2所述的背板系统(100)，其特征在于，其中每组第一指示灯(130-1……130-L)包括多个第一指示灯，每个第一指示灯均直接设置在所述柔性电路部件(200)的表面。
  4. 根据权利要求3所述的背板系统(100)，其特征在于，其中所述多个背板(110-1……110-N)中的每个背板(110-1……110-N)均包括多个第二端口(112)，以在所述多个背板(110-1……110-N)的一侧形成多列第二端口，
    其中所述柔性电路部件(120)包括多个第一区段(122-1、122-2)以及将所述多个第一区段(122-1、122-2)互连的第二区段(123)，每个第一区段(122-1、122-2)被布置为邻近对应的一列第二端口并且沿着所述多个背板堆叠的方向延伸，并且
    其中每组第一指示灯(130-1……130-L)被布置为邻近用于所述对应存储器的第二端口(112)。
  5. 根据权利要求4所述的背板系统(100)，其特征在于，其中每个背板(110-1……110-N)包括容纳所述柔性电路部件(120)的至少一个凹口部(114)，每个凹口部(114)位于相邻的两个第二端口之间。
  6. 根据权利要求1所述的背板系统(100)，其特征在于，还包括支撑板(121)，所述柔性电路部件(120)被固定至所述支撑板(121)的板表面。
  7. 根据权利要求1所述的背板系统(100)，其特征在于，其中所述多个背板(110-1……110-N)包括主背板(110-1)和从背板(110-2……110-N)，所述主背板(110-1)适于连接到基板管理控制器(400)，所述基板管理控制器(400)被配置为管理所述主背板(110-1)并且经由所述主背板(110-1)管理所述从背板(110-2……110-N)。
  8. 根据权利要求7所述的背板系统(100)，其特征在于，其中每个背板(110-1……110-N)包括彼此互连的控制单元(115)和主从模式控制端子(BP_Slot)，所述柔性电路部件(120)包括下拉端子和悬空端子，并且
    其中所述主背板(110-1)的所述主从模式控制端子(BP_Slot)被连接到所述下拉端子和所述悬空端子中的一者，并且所述从背板(110-2……110-N)的所述主从模式控制端子(BP_Slot)被连接到所述下拉端子和所述悬空端子中的另一者。
  9. 根据权利要求8所述的背板系统(100)，其特征在于，其中每个背板(110-1……110-N)包括：第四端口(119)，连接到所述控制单元(115)，并且适于连接到所述基板管理控制器(400)。
  10. 根据权利要求9所述的背板系统(100)，其特征在于，其中每个背板(110-1……110-N)还包括：第一选通器件(116)和第二选通器件(117)，各自包括器件连接端、第一通道和第二通道，并且被配置为基于来自所述控制单元(115)的选择信号将所述器件连接端连接到所述第一通道或所述第二通道，
    其中所述第一选通器件(116)的所述器件连接端连接到所述第四端口(119)，所述第一选通器件(116)的所述第一通道连接到所述控制单元(115)的固件更新接口(1152)，并且所述第一选通器件(116)的所述第二通道连接到所述控制单元(115)的卫星管理控制器(1151)；并且
    其中所述第二选通器件(117)的所述器件连接端连接到所述第一端口(111)，所述第二选通器件(117)的所述第一通道被连接到所述卫星管理控制器(1151)，并且所述第二选通器件(117)的所述第二通道连接到所述第一选通器件(116)的所述器件连接端，所述主背板(110-1)的卫星管理控制器(1151)被配置为将来自所述第一选通器件(116)的第二通道的固件更新数据转发给所述第二选通器件(117)的第一通道。
  11. 根据权利要求10所述的背板系统(100)，其特征在于，其中所述主背板(110-1)的所述控制单元(115)被配置为：响应于对所述主背板(110-1)自身进行固件更新，向所述主背板(110-1)的第一选通器件(116)发出选择信号以将所述第一选通器件(116)的器件连接端连接到第一通道；以及响应于对所述从背板(110-2……110-N)进行固件更新，向所述主背板(110-1)的所述第一选通器件(116)发出选择信号以将所述第一选通器件(116)的器件连接端连接到第二通道，并向所述主背板(110-1)的所述第二选通器件(117)发出选择信号以将所述第二选通器件(117)的器件连接端连接到第一通道，以及
    其中所述从背板(110-2……110-N)的控制单元(115)被配置为：向所述从背板(110-2……110-N)的第一选通器件(116)发出选择信号以将所述第一选通器件(116)的器件连接端连接到第一通道，并且向所述从背板(110-2……110-N)的第二选通器件(117)发出选择信号以将所述第二选通器件(117)的器件连接端连接到第二通道。
  12. 根据权利要求9所述的背板系统(100)，其特征在于，其中在每个背板(110-1……110-N)中，所述第四端口(119)经由数据总线连接到所述控制单元(115)的卫星管理控制器(1151)，所述卫星管理控制器(1151)经由其高速串行接口连接到所述第一端口(111)，并且所述卫星管理控制器(1151)被配置为获取所属背板的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息，并且
    其中所述主背板(110-1)的卫星管理控制器(1151)还被配置为将所述主背板(110-1)的所述信息提供给所述基板管理控制器(400)，并且接收来自所述从背板(110-2……110-N)的所述信息并提供给所述基板管理控制器(400)。
  13. 根据权利要求8所述的背板系统(100)，其特征在于，其中每个背板(110-1……110-N)的所述控制单元(115)被配置为控制与该背板对应的一组或多组第一指示灯(130-1……130-L)。
  14. 根据权利要求1所述的背板系统(100)，其特征在于，其中每个背板(110-1……110-N)还包括扩展器(118)，所述扩展器(118)适于扩展连接到背板的存储器的数目。
  15. 一种计算设备，其特征在于，所述计算设备包括如权利要求1至14中任一项所述的背板系统。
  16. 一种用于根据权利要求15所述的计算设备(1000)的管理方法，其特征在于，包括：
    由所述基板管理控制器(400)管理多个背板(110-1……110-N)中的主背板(110-1)，所述基板管理控制器(400)被连接到所述主背板(110-1)；以及
    由所述基板管理控制器(400)经由所述主背板(110-1)来管理多个背板(110-1……110-N)中的从背板(110-2……110-N)。
  17. 根据权利要求16所述的管理方法，其特征在于，其中所述主背板(110-1)的主从模式控制端子(BP_Slot)被连接到柔性电路部件(120)的下拉端子和悬空端子中的一者，并且所述从背板 (110-2……110-N)的主从模式控制端子(BP_Slot)被连接到柔性电路部件(120)的下拉端子和悬空端子中的另一者。
  18. 根据权利要求16所述的管理方法，其中由所述基板管理控制器(400)管理多个背板(110-1……110-N)中的主背板(110-1)包括：
    由所述主背板(110-1)的控制单元(115)向所述主背板(110-1)的第一选通器件(116)发出选择信号；以及
    由基板管理控制器(400)经由所述主背板(110-1)的第一选通器件(116)向所述主背板(110-1)的控制单元(115)提供固件更新数据，以对所述主背板(110-1)的控制单元(115)进行固件更新，并且其中由所述基板管理控制器(400)经由所述主背板(110-1)来管理多个背板(110-1……110-N)中的从背板(110-2……110-N)包括：
    由所述主背板(110-1)的控制单元(115)向所述主背板(110-1)的第一选通器件(116)和第二选通器件(117)发出选择信号；
    由所述从背板(110-2……110-N)的控制单元(115)向所述从背板(110-2……110-N)的第一选通器件(116)和第二选通器件(117)发出选择信号；以及
    由基板管理控制器(400)经由所述主背板(110-1)的第一选通器件(116)、控制单元(115)和第二选通器件(117)、柔性电路部件(120)、以及所述从背板(110-2……110-N)的第二选通器件(117)和第一选通器件(116)向所述从背板(110-2……110-N)的控制单元(115)提供固件更新数据，以对所述从背板(110-2……110-N)的控制单元(115)进行固件更新。
  19. 根据权利要求16所述的管理方法，其特征在于，其中由所述基板管理控制器(400)管理多个背板(110-1……110-N)中的主背板(110-1)包括：
    由所述主背板(110-1)的控制单元(115)获取所述主背板(110-1)的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息；以及
    由所述主背板(110-1)的控制单元(115)将获取的信息转发给所述基板管理控制器(400)，并且
    其中由所述基板管理控制器(400)经由所述主背板(110-1)来管理多个背板(110-1……110-N)中的从背板(110-2……110-N)包括
    由所述从背板(110-2……110-N)中的每个从背板的控制单元(115)获取所属从背板的与存储器状态、背板的FRU、以及背板的感测温度中的至少一项有关的信息；以及
    由所述从背板(110-2……110-N)的控制单元(115)将获取的信息经由所述主背板(110-1)的控制单元(115)转发给所述基板管理控制器(400)。
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CN107154856A (zh) * 2016-03-03 2017-09-12 中兴通讯股份有限公司 具有平行背板的通讯设备及其平行背板的布置方法
CN109696948A (zh) * 2017-10-24 2019-04-30 英特尔公司 具有平行背板的计算机机箱
CN109788697A (zh) * 2018-12-04 2019-05-21 华为技术有限公司 具有平行背板的电子设备及存储设备
US20200260608A1 (en) * 2019-02-13 2020-08-13 Ovh Rack adapted for receiving a component, system including the rack and the component and method of delivering power to a component mounted in a rack

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