WO2024051231A1

WO2024051231A1 - Processor and processor error detection method

Info

Publication number: WO2024051231A1
Application number: PCT/CN2023/098504
Authority: WO
Inventors: 刘辉; 俞洲; 杨肖; 邹文
Original assignee: 华为云计算技术有限公司
Priority date: 2022-09-05
Filing date: 2023-06-06
Publication date: 2024-03-14
Also published as: CN117687848A

Abstract

The present application relates to the technical field of computers. Provided are a processor and a processor error detection method. The processor comprises an error detection module and an instruction execution module. The error detection module is used for sending an internal detection instruction to the instruction execution module; the instruction execution module is used for executing the internal detection instruction to obtain a first execution result, and sending the first execution result to the error detection module; and the error detection module is used for determining, according to the first execution result and an expected result corresponding to the internal detection instruction, whether the processor has an error. The present invention does not require an external inspection tool to detect processor errors, such that processors decoding program instructions and sending execution results of the program instructions to inspection tools, etc. can be avoided, thus reducing the processing amount of the processors.

Description

A processor and a method for detecting processor errors

Cross-references to related applications

This application claims priority to the Chinese patent application filed with the China Patent Office on September 5, 2022, with application number 202211080632.4 and the application title "A processor and a method for detecting processor errors", the entire content of which is incorporated by reference. in this application.

Technical field

Embodiments of the present application relate to the field of computer technology, and in particular, to a processor and a method for detecting processor errors.

Background technique

The processor is one of the main components of various computing devices and is used to execute instructions. The processor may make errors while executing instructions.

Currently, one way to detect errors in the execution of instructions by a processor is to use an inspection tool to test whether there are errors in the execution of instructions in the processor. In this mode, the inspection tool can send program instructions to the processor, the processor decodes and executes the program instructions, and feeds back the execution results of the program instructions to the inspection tool. The inspection tool compares the execution result with the pre-stored expected result of the program instruction. If the execution result does not match the expected result of the program instruction, it is determined that the processor has an instruction execution error. However, in this method, the processor needs to receive program instructions from the inspection tool, decode the program instructions, and feed back the execution results of the program instructions to the inspection tool. It can be seen that the processing capacity of the processor is large.

Contents of the invention

Embodiments of the present application provide a processor and a method for detecting processor errors, which are used to reduce the processing volume in the process of detecting processor errors.

In a first aspect, embodiments of the present application provide a processor, including an error detection module and an instruction execution module, wherein: the error detection module is used to send internal detection instructions to the instruction execution module; the instruction execution module, used to execute the internal detection instruction, obtain a first execution result, and send the first execution result to the error detection module; the error detection module is used to calculate the first execution result according to the internal detection The expected result corresponding to the instruction determines whether there is an error in the processor.

In the embodiment of the present application, the instruction execution module can directly execute the internal detection instruction from the error detection module to obtain the first execution result. The error detection module compares the first execution result with the expected result corresponding to the internal detection instruction to determine whether the processor There is an error. In this way, it is equivalent to the processor executing the instructions in the processor, and then determining whether there is an error in the processor. There is no need for the processor to decode the instructions and send the first execution result to the external inspection tool, which is beneficial to reducing the processing time of the processor. It also helps save the computing resource overhead of the processor. Moreover, there is no need to use external inspection tools, which helps reduce the cost of detecting processor errors. In addition, when the processor detects a processor error, it executes instructions in the processor, and the processor can accommodate various types of instructions, so it is helpful to increase the types of instructions to which this method is applicable.

In a possible implementation, the instruction execution module is also used to: read external Program instructions, decode the external program instructions, obtain the decoded result, execute the decoded result, obtain the second execution result, and write the second execution result into the external storage module .

In the above embodiments, in addition to executing the internal detection instructions of the processor, the instruction execution module in the processor can also execute external program instructions in the external storage module. In other words, while the processor executes the internal detection instructions, it also Will affect the execution of external program instructions.

In a possible implementation, the error detection module is further configured to: before sending an internal detection instruction to the instruction execution module, determine that the remaining space in the buffer queue of the processor is greater than or equal to a threshold, and the The buffer queue is used to cache instructions to be processed by the processor.

In the above embodiment, the error detection module can send internal detection instructions to the instruction execution module when the load on the processor is relatively small, so that the instruction execution module can execute external program instructions when the load is relatively small. In this way, the impact of the execution process of internal detection instructions on the execution process of external program instructions can be reduced, which is conducive to reasonable allocation of computing resources of the processor.

In a possible implementation, the error detection module is also configured to add a mark to the internal detection instruction, where the mark represents an instruction used to detect errors of the processor; the instruction execution module is also configured to add a mark to the internal detection instruction. The error detection module is further configured to add the mark to the first execution result and identify the first execution result corresponding to the internal detection instruction based on the mark in the first execution result. .

In the above embodiment, the error detection module can add a mark to the internal detection instruction, so as to facilitate the subsequent instruction error detection module to distinguish the first execution result corresponding to the instruction used to detect processor errors.

In a possible implementation, the processor further includes a register, which stores the expected results corresponding to the internal detection instructions; the error detection module is also configured to read all the information from the register. Describe the expected results corresponding to the internal detection instructions.

In the above embodiment, the user can configure the expected result corresponding to the internal detection instruction in the register manually or by the processor, so that the error detection module can quickly obtain the expected result corresponding to the internal detection instruction, and also facilitates the subsequent rapid detection of whether the processor exists mistake.

In a possible implementation, the error detection module is further configured to obtain the internal detection instructions from instructions that have been executed by the processor; or, the processor further includes a storage device that stores the internal detection instructions. A first storage module for detecting instructions, the first storage module is allowed to be read by the processor, and the error detection module is also used to read the internal detection instructions from the first storage module; or, The processor further includes a second storage module that stores the internal detection instructions, the second storage module is allowed to be read and written by the processor, and the error detection module is also used to read from the third Read the internal detection instructions from the second storage module.

In the above embodiment, three ways for the error detection module to obtain internal detection instructions are provided, which enriches the ways for the error detection module to obtain instructions for detecting processor errors. In the first method, the error detection module can sample the internal detection instructions from instructions that have been executed by the processor. In the first method, the method of obtaining the internal detection instructions is simple and direct. In the second method, the error detection module can read the internal detection instructions from the first storage module, and the instructions in the first storage module can be manually configured. In the third method, the error detection module can read the internal detection instructions from the second storage module. Different from the second method, the second storage module involved in the third method can support processor writing, so that It is advantageous for the processor or the external device to add instructions in the second storage module through the processor.

In a possible implementation, the processor further includes at least one processor core, and one of the at least one processor core corresponds to the instruction execution module; the error detection module is specifically used to: Determine whether there is an error in the processor according to an expected result corresponding to the first execution result and the internal detection instruction.

The above embodiments may be applied when the processor includes one or more processor cores. If the processor includes multiple processor cores, the instruction execution module determines which processor core has the error. In this way, the processing can be accurately located. There is a faulty processor core in the processor. Moreover, in this embodiment, one error detection module can be used to detect errors on multiple processor cores, which is beneficial to reducing the cost of detecting processor errors.

In a possible implementation, the error detection module is further configured to: determine that a detection switch in the management module is in an on state, and the detection switch is used to indicate whether to detect errors of the processor. The management module The module includes one or more of a baseboard management controller, a firmware system or an operating system corresponding to the processor.

In the above embodiments, both the management module and the processor can be provided in the computing device, and the management module can be configured with a detection switch. The error detection module performs detection processing when it is determined that the detection switch in the management module is in an open state. The process of detecting processor errors provides a flexible way to enable detection of processor errors.

In a possible implementation, the processor further includes a control module; the error detection module is further configured to provide alarm information to a management module when it is determined that there is an error in the processor, and the management module includes a substrate One or more of the management controller, the firmware system or the operating system corresponding to the processor, the alarm information is used to indicate that the processor has an error; and/or the control module is used to determine When there is an error in the processor, the processor is controlled to be shut down.

In the above embodiment, when the error detection module determines that there is an error in the processor, the error detection module can provide alarm information to the management module so that the management module can present the alarm information so that the user can know in time that there is an error in the processor. . In addition, the control module in the processor can also control the shutdown of the processor to prevent the processor from continuing to execute instructions incorrectly.

In a second aspect, embodiments of the present application provide a method for detecting processor errors. The method may be executed by a processor or by a computing device including the processor. For the convenience of description, the following description takes the processor executing this method as an example. The processor executes the internal detection instruction to obtain a first execution result; the processor determines whether there is an error in the processor based on the expected result corresponding to the first execution result and the internal detection instruction.

In a possible implementation, the method further includes: reading external program instructions from the external storage module, decoding the external program instructions, obtaining decoded results, and executing the decoded results. As a result, a second execution result is obtained, and the second execution result is written into the external storage module.

In a possible implementation, the method further includes: the processor determining that the remaining space in the buffer queue is greater than or equal to a threshold, and the buffer queue is used to cache instructions to be processed by the processor.

In a possible implementation, the method further includes: the processor adding a mark to the internal detection instruction, the mark indicating an instruction for detecting an error of the processor; The mark is added to the first execution result; the processor identifies the first execution result corresponding to the internal detection instruction based on the mark in the first execution result.

In a possible implementation, the method further includes: the processor includes a register, and the register stores expected results corresponding to the internal detection instructions; the method further includes: the processor obtains the In the register, read the expected result corresponding to the internal detection instruction.

In a possible implementation, the method further includes: the processor obtaining the internal detection instruction from instructions that have been executed by the processor; or, the processor further includes storing the internal detection instruction. A first storage module for internal detection instructions, the first storage module is allowed to be read by the processor, and the processor reads the internal detection instructions from the first storage module; or, the processor It also includes a second storage module that stores the internal detection instructions, the second storage module is allowed to be read and written by the processor, and the processor reads from the second storage module The internal detection instructions.

In a possible implementation, the processor includes at least one processor core; the processor determines whether there is an error in the processor based on the expected result corresponding to the first execution result and the internal detection instruction. , including: the processor determines whether there is an error in the processor core used to obtain the first execution result based on the expected result corresponding to the first execution result and the internal detection instruction.

In a possible implementation, the method further includes: the processor determines that a detection switch in the management module is in an on state, and the detection switch is used to indicate whether to detect an error of the processor, and the The management module includes one or more of a baseboard management controller, a firmware system corresponding to the processor, or an operating system.

In a possible implementation, the method further includes: when the processor determines that there is an error in the processor, providing alarm information to a management module, where the management module includes a baseboard management controller, the processor In one or more of the corresponding firmware systems or operating systems, the alarm information is used to indicate that the processor has an error; and/or, when it is determined that the processor has an error, the processor shuts down the processor.

In a third aspect, embodiments of the present application provide a method for detecting processor errors. The method may be executed by a processor or by a computing device including a processor. For the convenience of description, the following description takes the processor executing this method as an example. The processor includes: instruction execution module and error detection module. The method includes: the error detection module sends an internal detection instruction to the instruction execution module; the instruction execution module executes the internal detection instruction, obtains a first execution result, and sends the first execution result to the error detection module. An execution result; the error detection module determines whether there is an error in the processor based on the expected result corresponding to the first execution result and the internal detection instruction.

In a possible implementation, before sending an internal detection instruction to the instruction execution module, the method further includes:

The error detection module determines that the remaining space in a buffer queue of the processor, which is used to cache instructions to be processed by the processor, is greater than or equal to a threshold.

In a possible implementation, the method further includes: the error detection module adding a mark to the internal detection instruction, the mark indicating an instruction for detecting an error of the processor; the error detection module based on The mark identifies the first execution result corresponding to the internal detection instruction.

In a possible implementation, the processor further includes a register that stores expected results corresponding to the internal detection instructions; the method further includes: the error detection module reads from the register Get the expected result corresponding to the internal detection instruction.

In a possible implementation, the method further includes: the error detection module obtains the internal detection instructions from instructions that have been executed by the processor; or, the error detection module obtains the internal detection instructions from the processing instructions. The internal detection instruction is read from the first storage module in the processor, and the first storage module is allowed to be read by the processor; or, the error detection module reads the internal detection instruction from the second storage module in the processor. , the internal detection instruction is read, and the second storage module is allowed to be read and written by the processor.

In a possible implementation, the processor includes at least one processor core, and one of the at least one processor core corresponds to the instruction execution module; according to the first execution result and the The error detection module determines whether there is an error in the processor core according to the expected result corresponding to the internal detection instruction, including: based on the expected result corresponding to the first execution result and the internal detection instruction, the error detection module determines and Whether there is an error in the processor core corresponding to the instruction execution module.

In a possible implementation, the method further includes: the error detection module determines that a detection switch in the management module is in an on state, and the detection switch is used to indicate whether to detect errors of the processor, so narrate management The management module includes one or more of a baseboard management controller, a firmware system corresponding to the processor, or an operating system.

In a possible implementation, when the error detection module determines that there is an error in the processor, the error detection module provides alarm information to the management module. The management module includes a baseboard management controller, a firmware system corresponding to the processor, or One or more operating systems, the alarm information is used to indicate that there is an error in the processor; and/or, when it is determined that there is an error in the processor, the control module in the processor controls to shut down the processor. processor.

In a fourth aspect, embodiments of the present application provide a computing device, which may include any of the processors in the first aspect.

In a fifth aspect, embodiments of the present application provide a computing device. The computing device includes a processor and a power supply circuit. The power supply circuit is used to supply power to the processor. The processor is used to implement the second aspect or the third aspect. Either method.

In a sixth aspect, embodiments of the present application provide a computing device cluster, including at least one computing device. Each computing device can execute the method in any one of the above-mentioned second aspect or the above-mentioned third aspect.

Optionally, each computing device in the computing device cluster may be the computing device of any one of the above-mentioned fourth aspect or the above-mentioned fifth aspect.

A seventh aspect provides a computer program product containing instructions that, when run on a computer, implements the method of any one of the above second or third aspects.

In an eighth aspect, embodiments of the present application provide a computer-readable storage medium. The computer-readable storage medium is used to store computer programs or instructions. When executed, the computer program or instructions implement any one of the above-mentioned second aspect or the above-mentioned third aspect. Methods.

Regarding the beneficial effects of the above-mentioned second aspect to the above-mentioned eighth aspect, reference may be made to the beneficial effects discussed in the above-mentioned first aspect, which will not be repeatedly listed here.

Description of the drawings

Figure 1 is a schematic diagram of the deployment of an inspection tool;

Figure 2 is a schematic structural diagram of a processor provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of another processor provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of an error detection module provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram of a computing device provided by an embodiment of the present application;

Figure 6 is a schematic diagram of the deployment of a cloud data center provided by an embodiment of the present application;

Figure 7 is a schematic architectural diagram of a cloud data center provided by an embodiment of the present application;

Figure 8 is a schematic flowchart of a method for detecting processor errors provided by an embodiment of the present application;

Figure 9 is a schematic diagram of a detection switch of a management module provided by an embodiment of the present application;

Figure 10 is a schematic diagram of a process for processing internal detection instructions and external program instructions provided by an embodiment of the present application;

Figure 11 is a schematic flowchart of yet another method for detecting processor errors provided by an embodiment of the present application;

Figure 12 is a schematic diagram of another process for processing internal detection instructions and external program instructions provided by the embodiment of the present application;

Figure 13 is a schematic architectural diagram of a computing device cluster provided by an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

In the following, some terms used in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

1. Silent data corruption (SDC), also known as silent data corruption, refers to an error that occurs during the execution of instructions by the processor, but the operating system in the device corresponding to the processor does not perceive this error. Causes the error result corresponding to the instruction executed by the processor to be stored.

2. The processor can be a central processing unit (CPU), or other general-purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), Field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

In the embodiments of this application, the number of nouns means "singular noun or plural noun", that is, "one or more", unless otherwise specified. "At least one" means one or more, and "plurality" means two or more. "And/or" describes the relationship between associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. For example, A/B means: A or B. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c Can be single or multiple.

In order to reduce silent data errors that may occur in the processor, inspection tools can currently be used to test whether there are errors in the processor. Please refer to Figure 1, which is a schematic diagram of the deployment of an inspection tool. Alternatively, Figure 1 can be understood as an architectural schematic diagram of the device. As shown in Figure 1, the device includes a processor, multiple running applications (APPs), and an operating system. Among them, multiple applications include application 1, inspection tools, application 2, etc. as shown in Figure 1.

The inspection tool can have built-in program instructions and expected results corresponding to the program instructions. When the inspection tool detects processor errors, the inspection tool can load program instructions into external memory. The external memory and processor are configured independently of each other. The processor reads program instructions from external memory and decodes the program instructions. The processor executes the decoded program instructions and sends the execution results of the program instructions to the inspection tool.

The inspection tool compares the execution results of program instructions with the expected results. If the execution results match the expected results, the inspection tool determines that there is no processor error. If the execution results do not match the expected results, the inspection tool determines that there is a processor error. When the inspection tool determines that there is an error in the processor, the inspection tool can feedback to the operating system that the processor has an error.

It can be seen that in the current method of detecting processor errors, the processor needs to read program instructions from external memory, decode the program instructions, and subsequently send execution results to the inspection tool, etc., resulting in a large processing capacity of the processor.

In view of this, embodiments of the present application provide a processor. The processor includes an error detection module and an instruction execution module. The error detection module may send (or transfer) instructions for detecting processor errors (such as internal detection instructions) to the instruction execution module. The instruction execution module executes the internal detection instruction, obtains the first execution result of the internal detection instruction, and sends the first execution result of the internal detection instruction to the error detection module. The error detection module determines whether there is an error in the processor based on the first execution result and the expected result of the internal detection instruction. In this way, the processor can detect whether there are errors in the processor by itself without resorting to external inspection tools. Since there is no need for the processor to decode external program instructions and send the execution results of external program instructions to the inspection tool, it can reduce the number of processor tasks. processing volume.

The processor in the embodiment of the present application may be any type of processor, including, for example, a single-core processor or a multi-core processor.

Please refer to FIG. 2 , which is a schematic structural diagram of a processor provided by an embodiment of the present application. Figure 2 shows an example of a single-core processor The structural diagram of the processor. As shown in FIG. 2 , the processor 200 includes an error detection module 210 and an instruction execution module 220 . Among them, the error detection module 210 and the instruction execution module 220 can communicate with each other.

The error detection module 210 and the instruction execution module 220 can be implemented by hardware, such as logic circuits. This application does not limit the specific structures of the error detection module 210 and the instruction execution module 220 . The instruction execution module 220 is, for example, an arithmetic logic unit (arithmetic logic unit, ALU).

Specifically, the error detection module 210 sends instructions for detecting processor errors (such as internal detection instructions) to the instruction execution module 220 . The instruction execution module 220 is used to execute internal detection instructions to obtain the first execution result. The instruction execution module 220 sends the first execution result to the error detection module 210 . The error detection module 210 is configured to determine whether the processor stores an error based on the expected result corresponding to the first execution result and the internal detection instruction.

For example, if the first execution result matches the expected result of the internally detected instruction, error detection module 210 determines that there is no processor error. If the first execution result does not match the expected result of the internally detected instruction, the error detection module 210 determines that there is an error in the processor.

In the embodiment of the present application, the error detection module 210 and the instruction execution module 220 in the processor 200 can cooperate to implement error detection of the processor 200 without resorting to external inspection tools, and there is no need for the processor 200 to decode program instructions. As well as sending execution results to the inspection tool, etc., it is helpful to reduce the processing load of the processor, and also helps to save the resource overhead of the processor.

In a possible implementation, when the remaining space of the buffer queue of the processor 200 is greater than or equal to the threshold, the error detection module 210 sends an internal detection instruction to the instruction execution module 220 . The buffer queue is used to store instructions to be processed (or not processed) by the processor 200 . The threshold may be preconfigured in the error detection module 210.

The smaller the remaining space in the cache queue, the more instructions the processor 200 needs to process, which means the load on the processor 200 is greater; the larger the remaining space in the cache queue, the fewer instructions the processor 200 needs to process. This means that the load on the processor 200 is smaller.

In this embodiment, it can be avoided that when the load of the processor 200 is heavy, sending internal detection instructions to the instruction execution module 220 and increasing the processing load of the processor 200 can be avoided, which is conducive to rational utilization of the resources of the processor 200 .

In addition to executing instructions from the error detection module 210, the instruction execution module 220 may also execute instructions from external programs. Accordingly, the instruction execution module 220 will not only obtain the execution results of the internal detection instructions, but also obtain the execution results corresponding to the program instructions. . External program instructions refer to instructions that do not belong to the processor 200 . Therefore, in order to facilitate the error detection module 210 to identify the first execution result corresponding to the internal detection instruction, in a possible implementation, the error detection module 210 may add a mark to the internal detection instruction. The error detection module 210 obtains the first execution result of the internal detection instruction corresponding to the tag from the instruction execution module 220 according to the tag.

The expected results corresponding to the internal detection instructions may be preconfigured in the error detection module 210 . Alternatively, the expected results corresponding to the internal detection instructions may be preconfigured in the register 260 of the processor 200 . Subsequently, the error detection module 210 can read the expected result corresponding to the internal detection instruction from the register 260 .

As an example, processor 200 also includes control module 250. The control module 250 is used to control various modules of the processor 200 (including the error detection module 210 and the instruction execution module 220, etc.). The control module 250 is, for example, a control unit (CU).

As an example, the processor 200 further includes a first storage module 230 and/or a second storage module 240. The first storage module 230 and the second storage module 240 can be understood as internal storage modules of the processor 200 . The first storage module 230 is, for example, a read only memory (ROM) or a memory. The embodiment of the present application does not limit the specific implementation forms of the first storage module 230 and the second storage module 240 . The second storage module 240 is, for example, a memory.

Specifically, the first storage module 230 is used to store instructions. The first storage module 230 may be allowed to be read by the processor 200 (specifically, the error detection module 210 in the processor 200). For example, the error detection module 210 is used to read internal detection instructions from the first storage module 230 .

The second storage module 240 is used to store instructions. The second storage module 240 may be allowed to be read and written by the processor 200 (specifically, the error detection module 210 in the processor 200). For example, the external device can write instructions to the second storage module 240 through the processor 200, and the error detection module 210 can also read internal detection instructions from the second storage module 240. In this way, it is helpful to expand the number and type of instructions used to detect errors in the processor 200 .

As an example, the error detection module 210 may also read internal detection instructions from instructions that have been executed by the instruction execution module 220 .

In the embodiment of the present application, the error detection module 210 can read the internal detection instructions from the instructions that have been executed by the first storage module 230, the second storage module 240 or the instruction execution module 220 inside the processor 200, providing the ability to obtain internal Multiple ways to detect instructions.

In a possible implementation, the instruction execution module 220 can also be used to process external program instructions. The external program instructions refer to programs from devices other than the processor. For example, the instruction execution module 220 can decode the external program instruction, obtain the decoded result, and execute the decoded result to obtain the second execution result. Decoding the external program instructions can be understood as converting the external program instructions into instructions that the instruction execution module 220 can directly operate.

The external program instructions are, for example, instructions stored in an external memory. For example, the external program instructions may be instructions formed after the operating system loads the application.

Please refer to FIG. 3 , which is a schematic structural diagram of another processor provided by an embodiment of the present application. FIG. 3 is, for example, a schematic structural diagram of a multi-core processor. As shown in FIG. 3 , the processor 300 includes multiple processor cores, an error detection module 301 and an instruction execution module 302 . In FIG. 3 , multiple processor cores including a first processor core 310 and a second processor core 320 are taken as an example. A processor core can also be called a physical processor core, a physical processor core, or a processor core.

Among them, the function and implementation form of the error detection module 301 can refer to the content of the error detection module 210 discussed in Figure 2 above, and the function and implementation form of the instruction execution module 302 can refer to the content of the instruction execution module 220 discussed in Figure 2 above. .

The structures of the first processor core 310 and the second processor core 320 may be the same. The first processor core 310 is taken as an example for introduction below.

The first processor core 310 includes an instruction execution module 302 . The content of the instruction execution module 302 may refer to the content discussed above. The first processor core 310 also includes a control module 307 . The content of the control module 307 may refer to the content discussed above.

In the processor 300 involved in the embodiment of FIG. 3, the error detection module 301 can perform error detection on multiple processor cores of the processor 300 to determine which processor core specifically has an error.

For example, the error detection module 301 can send an internal detection instruction to the instruction execution module 302 in the first processor core 310, and obtain the execution result of the internal detection instruction sent by the instruction execution module 302 in the first processor core 310. If the execution result of the internal detection instruction does not match the expected result, the error detection module 301 determines that there is an error in the first processor core 310 . If the execution result of the internal detection instruction matches the expected result, the error detection module 301 determines that there is no error in the first processor core 310 . Similarly, the error detection module 301 can detect whether there is an error in the second processor core 320 .

In this implementation, the processor 300 can perform error detection on the processor core in the processor 300 , which is equivalent to performing more accurate error detection on the processor 300 .

Optionally, the processor 300 also includes one or more of a register 304, a first storage module 305, and a second storage module 306.

The function of the register 304 may refer to the contents of the register 260 discussed in FIG. 2 discussed above. The function and implementation form of the first storage module 305 may refer to the content of the first storage module 230 discussed in FIG. 2 discussed above. The function and implementation form of the second storage module 306 may refer to the content of the second storage module 240 discussed in FIG. 2 discussed above.

Please refer to FIG. 4 , which is a schematic structural diagram of another processor provided by an embodiment of the present application. As shown in FIG. 4 , the processor 400 includes an instruction execution module 410 and an error detection module 420 . The error detection module 420 includes an instruction acquisition sub-module 421, an instruction identification sub-module 422 and an error judgment sub-module 423.

Optionally, the instruction acquisition sub-module 421, the instruction identification sub-module 422 and the error judgment sub-module 423 can all be implemented by hardware. For example, the instruction acquisition sub-module 421 can be implemented by a register or a memory, and the instruction identification sub-module 422 can be implemented by a comparator. Implementation, the error judgment sub-module 423 can be implemented through a comparator.

Specifically, the instruction acquisition sub-module 421 is used to provide internal detection instructions for the instruction execution module 410. Among them, the content of the internal detection instructions obtained by the instruction acquisition sub-module 421 may refer to the content of the internal detection instructions obtained by the error detection module mentioned above, which will not be described again here. The instruction identification sub-module 422 identifies the execution results corresponding to the internal detection instructions from the execution results executed by the instruction execution module 410 . The error judgment sub-module 423 determines whether the execution result corresponding to the internal detection instruction is the same as the expected result of the internal detection instruction, thereby determining whether there is an error in the processor 400 .

Optionally, the processor 400 also includes a load determination sub-module 424, which is illustrated by a dotted box in FIG. 4 . The load determination sub-module 424 may be used to determine whether the remaining space of the buffer queue of the processor 400 is greater than or equal to the threshold. For example, the load determination sub-module 424 determines that the remaining space of the buffer queue of the processor 400 is greater than or equal to a threshold, triggering the instruction acquisition sub-module 421 to send an internal detection instruction to the instruction execution module 410 .

Any processor involved in various embodiments of the present application may be disposed in any type of computing device. Computing equipment generally refers to equipment with processing capabilities, such as servers or terminal equipment. Terminal devices such as mobile phones, tablets, computers with wireless transceiver functions, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms or smart home devices, etc.

Please refer to FIG. 5 , which is a schematic structural diagram of a computing device provided by an embodiment of the present application. As shown in Figure 5, computing device 500 includes software layers and hardware layers.

The software layer includes an operating system 510, a firmware system 520, a baseboard management controller (BMC) 530, etc. The baseboard management controller 530 is, for example, a small operating system independent of the computing device 500 . Operating system 510, firmware system 520, and baseboard management controller 530 may all be used to manage computing device 500. In the embodiment of the present application, one or more of the operating system 510, the firmware system 520, and the baseboard management controller 530 can be regarded as a management module.

The hardware layer includes external storage module 540, processor 550, network card 560, etc. The external storage module 540 is, for example, the memory of the computing device 500 . The structure of the processor 550 may refer to the structure shown in FIG. 2, FIG. 3 or FIG. 4. Only one processor 550 is illustrated in FIG. 5 . In fact, the number of processors 550 may be one or more.

Processor 550 may be used to process requests from outside computing device 500 and/or requests generated internally by computing device 500 . Network card 560 is used by computing device 500 to communicate with other devices.

In addition, computing device 500 may also include a bus, which may be used for communication between components of computing device 500 .

Optionally, the computing device 500 may also include a power supply circuit, which is used to power the processor 550 .

In a possible implementation, the processor 550 detects that there is an error in the processor 550 and can provide alarm information to the management module. The alarm information is used to indicate that there is an error in the processor 550 so that the user can learn the status of the processor 550 in a timely manner. condition.

In a possible implementation, in addition to executing internal detection instructions, the processor 550 is also configured to execute external program instructions in the external storage module 540 .

Specifically, the processor 550 reads the external program instructions from the external storage module 540 and decodes the external program instructions to obtain the decoded results. The processor 550 executes the decoded result to obtain a second execution result. The processor 550 may write the second execution result into the external storage module 540 to facilitate the operating system of the computing device 500 and the like to obtain the second execution result.

The computing device involved in the embodiments of this application can be applied in any scenario, such as in a cloud data center. Cloud data centers can be used to provide users with business services, including storage services and/or computing services.

Please refer to FIG. 6 , which is a schematic diagram of the deployment of a cloud data center provided by an embodiment of the present application. Alternatively, FIG. 6 can be understood as a schematic diagram of an application scenario of an error detection method provided by an embodiment of the present application. As shown in Figure 6, this scenario includes running on multiple terminal devices 610, multiple clients 611 and a cloud data center 620. One client 611 of the plurality of clients 611 is run in each terminal device 610 of the plurality of terminal devices 610 . Each client 611 in the plurality of clients 611 may be a software module or application. Cloud data center 620 includes one or more computing devices.

For example, the client 611 can remotely access the cloud data center 620, and then use the business services provided by the cloud data center 620.

The structure of the cloud data center is introduced below with reference to the schematic diagram of a cloud data center architecture shown in Figure 7. In Figure 7, the computing device included in the cloud data center is a server as an example.

As shown in Figure 7, the cloud data center 700 includes a cloud management platform 710 and at least one server 730. In FIG. 7 , the number of at least one server 730 is two. Wherein, the cloud management platform 710 communicates with each of the at least one server 730 through the cloud data center internal network 720.

The cloud management platform 710 is used to provide an access interface (such as an interface or an application programming interface (API)). For example, the tenant can operate the client remote access API to register a cloud account and password on the cloud management platform 710 and log in to the cloud management platform 710 . The client is, for example, client 611 in Figure 6 .

After the cloud management platform 710 successfully authenticates the cloud account and password, the tenant can further select and purchase a virtual machine with specific specifications (processor, memory, disk) on the cloud management platform 710 for a fee. Among them, virtual machines can also be called cloud servers (elastic compute service, ECS) or elastic instances. After the tenant successfully purchases the virtual machine, the cloud management platform 710 provides the tenant with the remote login account and password of the purchased virtual machine. The client can log in to the virtual machine remotely and install and run tenant applications in the virtual machine.

The logical functions of the cloud management platform 710 may include user console, computing management service, network management service, storage management service, authentication service, image management service, etc. Among them, the user console provides an interface or API to interact with tenants. Compute management services are used to manage servers running virtual machines and containers, as well as bare metal servers. Network management services are used to manage network services (such as gateways, firewalls, etc.). The storage management service is used to manage storage services (such as data bucket services). The authentication service is used to manage tenant accounts and passwords. Image management service is used to manage virtual machine images.

The structure of any two servers 730 in the at least one server 730 may be the same. The structure of one server 730 is taken as an example for description below.

Server 730 includes hardware layers and software layers. The hardware layer of server 730 includes memory 734, processor 735, network card 736 and disk 737. Among them, the contents of the memory 734, the processor 735 and the network card 736 can refer to the contents discussed in Figure 5 above. Optionally, the server 730 may also include a power supply circuit, which is used to power the processor 735 . Among them, the memory 734 can be regarded as an example of an external storage module.

The software layer of the server 730 includes an operating system installed and running on the server 730 (the operating system relative to the virtual machine can be called a host operating system). The operating system is provided with a virtual machine manager (virtual machine manager, VMM) 732 and Multiple virtual machines 731. The virtual machine manager 732 may be used to implement computing virtualization, network virtualization, and storage virtualization of the virtual machine, as well as manage the virtual machine 731 . Among them, computing virtualization refers to providing part of the processor 735 and memory 734 of the server 730 to the virtual machine; network virtualization refers to providing part of the functions (such as bandwidth) of the network card 736 to the virtual machine; and storage virtualization refers to providing part of the processor 735 and memory 734 of the server 730 to the virtual machine. Part of the disk 737 is provided to the virtual machine; the virtual machine 731 is managed, for example, creating a virtual machine 731, simulating virtual hardware for the virtual machine according to the hardware layer (hardware emulation function), deleting the virtual machine 731, forwarding and/or processing the data running on the server 730. Network packets between all virtual machines 731 or forward network packets between the virtual machine 731 on the server 730 and the external network (virtual switching function), and process input/output generated by the virtual machine 731, I/O) etc.

Among them, the running environments (such as virtual machine applications, operating systems, and virtual hardware) in different virtual machines 731 are completely isolated, and different virtual machines 731 can communicate with each other through the virtual machine manager 732 . Each virtual machine 731 may run an operating system, a firmware system, a baseboard management controller, etc.

The virtual machine manager 732 also includes a cloud platform management client 733. The cloud platform management client 733 is used to receive control plane commands sent by the cloud management platform 710, create on the server 730 according to the control plane control commands, and conduct full life management of the virtual machine. Cycle management, so that tenants can create, manage, log in and operate virtual machines 731 in the cloud data center 700 through the cloud management platform 710.

The methods provided by the embodiments of the present application will be introduced below with reference to the accompanying drawings.

In the drawings corresponding to various embodiments of the present application, all steps indicated by dotted lines are optional steps.

Please refer to FIG. 8 , which is a schematic flowchart of a method for detecting processor errors provided by an embodiment of the present application. The structure of the processor involved in the embodiment shown in Figure 8 is, for example, the processor 200 in Figure 2, the processor 300 in Figure 3, or the processor 400 in Figure 4, and the structure of the processor involved in the embodiment shown in Figure 8 The processor may be implemented, for example, in the computing device shown in FIG. 5 . The processor involved in the embodiment shown in Figure 8 includes an instruction execution module and an error detection module.

S801. The error detection module adds a mark to the internal detection instruction. The error detection module involved in the embodiment of the present application is, for example, the error detection module 210 in Figure 2, the error detection module 301 in Figure 3, or the error detection module 420 in Figure 4.

The error detection module can determine the instruction used to detect processor errors. In the embodiment of the present application, an internal detection instruction is an instruction used to detect processor errors is introduced as an example.

When the processor is applied to a computing device, such as the computing device in FIG. 5 , the instruction execution module will execute instructions from the error detection module and may also execute external program instructions from the external storage module. The instruction execution module is, for example, the instruction execution module 220 in FIG. 2 , the instruction execution module 302 in FIG. 3 , or the instruction execution module 410 in FIG. 4 . In order to facilitate subsequent differentiation of instructions sent by the error detection module to the instruction execution module, in the embodiment of the present application, the error detection module can add a mark to the internal detection instruction. The mark is used to indicate that the internal detection instruction is used to detect processor errors. instruction. The specific form of this mark can be a label.

The external storage module is not provided in the processor. The external storage module is, for example, a ROM or a memory. The external storage module is, for example, the external storage module 540 in FIG. 5 . Since the instructions in the external storage module are external program instructions, the meaning of the external program instructions can be referred to the above. The external program instructions are, for example, instructions from an external application.

Among them, there are many ways for the error detection module to obtain internal detection instructions, which are introduced below.

In the first method, the error detection module determines the internal detection instructions from the instructions that have been executed by the processor.

The instruction execution module in the processor executes multiple instructions, such as instructions from the error detection module, and Instructions from external memory modules. For ease of description, in the embodiment of this application, an instruction that has been executed by the instruction execution module is called a historical instruction, and all instructions that have been executed by the instruction execution module are called a historical instruction set. The error detection module may select at least one historical instruction from the historical instruction set for detecting whether there is an error in the processor. The error detection module may determine one of the at least one historical instructions as an internally detected instruction. Correspondingly, in mode 1, the internal detection instructions belong to instructions that have been executed by the processor, which are historical instructions.

For example, the error detection module may randomly determine an instruction from at least one historical instruction as an internal detection instruction.

For another example, the error detection module may use an instruction with the greatest execution complexity among at least one historical instruction as an internal detection instruction. Execution complexity can be characterized by the time required to execute instructions before the instruction execution module. The longer the time, the higher the execution complexity. Since the processor is more likely to make errors when executing instructions with high complexity, it is easier to detect processor errors by selecting instructions with high complexity to detect whether there are errors in the processor.

Optionally, if the processor is a multi-core processor, for example, the processor is the processor 300 in FIG. 3 , the error detection module may sample historical instruction sets from multiple instruction execution modules corresponding to multiple processor cores. In other words, the historical instruction set includes instructions that have been executed by multiple instruction execution modules.

In a possible implementation, when the error detection module obtains at least one historical instruction from the instruction execution module, the error detection module can also write the result corresponding to the execution of the at least one historical instruction by the instruction execution module into a preset in the processor. in the register. The result corresponding to at least one historical instruction can be regarded as the expected result corresponding to at least one historical instruction. The register is, for example, the register 260 in Figure 2 or the register 304 in Figure 3 .

In order to facilitate distinguishing at least one historical instruction, the error detection module can also generate an identifier of each historical instruction in the at least one historical instruction, and store the identifier of the at least one historical instruction and the expected result corresponding to the at least one historical instruction in the register.

For example, please refer to Table 1 below for the identification of at least one historical instruction stored in register association, and the expected result corresponding to at least one historical instruction.

Table 1

As shown in Table 1 above, the expected result of the instruction corresponding to instruction 0 is 11, and the expected result of the instruction corresponding to instruction 1 is 00.

In the second method, the error detection module reads the internal detection instructions from the first storage module. The first storage module in the embodiment of the present application is, for example, the first storage module 230 in FIG. 2, or the first storage module 305 in FIG. 3, for example.

The first storage module may be pre-stored with at least one instruction. For example, the at least one instruction may be manually configured in the first storage module. For example, the processor is manually configured in the first storage module before the processor leaves the factory. Correspondingly, in mode 2, the internal detection instruction belongs to an instruction in the first storage module.

The processor may perform a read operation on the first storage module. For example, the error detection module in the processor may read an instruction from at least one instruction stored in the first storage module as an internal detection instruction.

For example, the error detection module may randomly read an instruction from at least one instruction as an internal detection instruction.

As an example, at least one instruction prestored in the first storage module may be an instruction with a probability of an error executed by the processor greater than or equal to the first probability. In other words, at least one instruction prestored in the first storage module may be an instruction that is prone to errors in execution by the processor. Among them, the probability of processor execution error can be determined based on experience, or the processing obtained through multiple tests.

In a possible implementation, the first storage module may also store an expected result corresponding to at least one instruction. For example, when configuring at least one instruction in the first storage module, the staff can manually configure the expected result corresponding to the at least one instruction in the first storage module. The expected result corresponding to at least one instruction may be obtained by executing at least one instruction respectively on other processors. Among others, processors are different.

Alternatively, the identifier of at least one instruction and the expected result corresponding to the at least one instruction may be pre-stored in a register, and the register is as discussed above. For example, the staff can manually configure the expected result corresponding to at least one instruction in the register. The method for obtaining the expected result corresponding to at least one instruction may refer to the content discussed above.

In the third method, the error detection module reads the internal detection instructions from the second storage module. The second storage module in the embodiment of the present application is, for example, the second storage module 240 in Figure 2, or, for example, the second storage module 306 in Figure 3.

Wherein, the processor can perform write operations and read operations on the second storage module.

For example, at least one instruction in the second storage module may be written by the processor. For example, the external device may access the processor, and the processor may write instructions in the second storage module. Correspondingly, in mode three, the internal detection instructions belong to instructions in the second storage module. Furthermore, the error detection module in the processor can read an instruction from the second storage module as an internal detection instruction.

In the third method, the second storage module can support external writing, which facilitates subsequent addition of instructions for detecting processor errors.

In a possible implementation, the first storage module may also store an expected result corresponding to at least one instruction. For example, when the external device writes at least one instruction into the first storage module, it can also write the expected result corresponding to the at least one instruction into the first storage module. Among them, the expected result corresponding to at least one instruction may be obtained through execution by another processor.

Alternatively, the identifier of at least one instruction and the expected result corresponding to at least one instruction are pre-stored in a register, and the register is as discussed above. For example, the external device may write the expected result corresponding to at least one instruction into a register. The method for obtaining the expected result corresponding to at least one instruction may refer to the content discussed above.

If the instruction execution module only needs to execute instructions from the error detection module, then the error detection module does not need to perform step S801, that is, S801 is an optional step, which is illustrated by a dotted line in Figure 8 .

S802. The error detection module sends an internal detection instruction to the instruction execution module. Correspondingly, the instruction execution module receives internal detection instructions from the error detection module.

When the processor in the embodiment of FIG. 8 is a multi-core processor, the error detection module sends an internal detection instruction to the instruction execution module corresponding to one processor core (for example, the first processor core) in the multi-core processor. The first processor core is, for example, the first processor core 310 shown in FIG. 3 .

For example, the error detection module sends instructions for detecting processor errors to the instruction execution module according to the first cycle. The duration of the first period may be pre-configured in the error detection module, and the duration of the first period may be, for example, 5 hours.

For another example, the error detection module sends instructions for detecting processor errors to the instruction execution module from time to time.

Or, for example, when the load on the processor is small, the error detection module sends an internal detection instruction to the instruction execution module.

For example, the error detection module may characterize the load of the processor in terms of remaining space in a buffer queue in the processor. In this way, it can be avoided that the process of detecting processor errors occupies processor resources when the processor load is heavy, which is conducive to the smooth execution of instructions from the external storage module by the processor.

Specifically, if the remaining space of the buffer queue in the processor is greater than or equal to the threshold, the error detection module determines that the load of the processor is small; if the remaining space of the buffer queue of the processor is less than the threshold, the error detection module determines that the load of the processor is small. big. Wherein, the threshold value may be pre-configured in the error detection module, and the threshold value is, for example, 1M.

As an example, if the processor in the embodiment of FIG. 8 is a multi-core processor, then the error detection module can send the error detection module to the instruction execution module corresponding to the first processor core when the load of the first processor core is small. Send internal detection command. The method of determining that the load of the first processor core is small may refer to the previous content of determining that the load of the processor is small.

In the case where the processor in FIG. 8 is applied to a computing device, the user can flexibly control the process of performing processor error detection. The management module includes detection switches. Among them, the detection switch is used to indicate whether to perform error detection on the processor. The management module determines whether the detection switch is on or off according to the user's operation. In a possible embodiment, the error detection module may also determine that the detection switch in the management module is on, and send an internal detection instruction to the instruction execution module. Wherein, the detection switch is in the on state, indicating that error detection is performed on the processor; the detection switch is in the off state, indicating that error detection on the processor is not performed.

The management module includes one or more operating systems, baseboard management controllers, or firmware systems in the computing device. When the management module includes two or more of the operating system, the baseboard management controller or the firmware system, the error detection module can only determine that the detection switch of one of the operating system, the baseboard management controller or the firmware system is in an open state, This is equivalent to confirming that the detection switch in the management module is on.

For example, if the error detection module determines that the detection switch is on and the processor load is small, it sends an internal detection instruction to the instruction execution module; or if the error detection module determines that the detection switch is on, it sends an internal detection instruction to the instruction execution module. .

For example, please refer to FIG. 9 , which is a schematic diagram of a detection switch of a management module provided by the present application. As shown in Figure 9, the detection switch in the management module (specifically the button where the processor error is detected in Figure 9) is displayed as "√", indicating that the detection switch in the management module is on.

S803. The instruction execution module executes the internal detection instruction and obtains the first execution result.

Since the internal detection instruction is sent to the instruction execution module by the error detection module in the processor, there is no need to decode the internal detection instruction. The instruction execution module can directly execute the internal detection instruction to obtain the execution result of the first execution. For convenience of description, the embodiment of the present application refers to the execution result of the internal detection instruction as the first execution result.

Optionally, when the error detection module performs S801 (ie, adds a mark to the internal detection instruction), the error detection module can cache the mark of the internal detection instruction and add the mark to the first execution result.

S804. The error detection module determines the first execution result according to the mark.

For example, when the error detection module performs S801, the error detection module may obtain the execution results of all instructions (for example, including the first execution result and the second execution result) from the instruction execution module. The error detection module can identify the first execution result according to the mark, which is equivalent to the error detection module determining the first execution result.

For another example, the error detection module may send a first request to the instruction execution module. The first request is used to request an execution result corresponding to the internal detection instruction, and the first request may include (or indicate) a flag of the internal detection instruction. The instruction execution module receives the first request and feeds back the first execution result to the error detection module, which is equivalent to the error detection module determining the first execution result.

For another example, the error detection module may obtain the first execution result corresponding to the internal detection instruction from the instruction execution module according to the identification of the internal detection instruction. Among them, the content of the identification of the internal detection instruction can be referred to the previous article. In this case, the error detection module does not need to determine the first execution result according to the flag, so S804 is an optional step.

S805. The error detection module determines whether there is an error in the processor based on the matching result between the first execution result and the expected result of the internal detection instruction.

In the case where the expected result of the internal detection instruction is pre-stored in a register of the processor, the error detection module may read the expected result of the internal detection instruction from the register. Alternatively, in the case where the expected result of the internal detection instruction is pre-stored in the first storage module of the processor, the error detection module may read the expected result of the internal detection instruction from the first storage module. Alternatively, in the case where the expected result of the internal detection instruction is pre-stored in the second storage module of the processor, the error detection module may read the expected result of the internal detection instruction from the second storage module.

The error detection module determines whether the first execution result matches the expected result of the internally detected instruction. If the first execution result matches the expected result of the internal detection instruction, the error detection module determines that there is no error in the processor, the error detection module can discard the first execution result, and the processor can execute the embodiment shown in Figure 8 again, Perform error detection on the processor. If the first execution result does not match the expected result of the internal detection instruction, the error detection module determines that there is an error in the processor.

For example, the error detection module determines whether the first execution result is the same as the expected result of the internal detection instruction. If the first execution result is the same as the expected result of the internal detection instruction, it means that the first execution result matches the expected result of the internal detection instruction; if the first execution result is the same as the expected result of the internal detection instruction; An execution result is different from the expected result of the internal detection instruction, indicating that the first execution result does not match the expected result of the internal detection instruction.

S806. The instruction execution module reads external program instructions from the external storage module.

The external storage module is, for example, the external storage module 540 shown in FIG. 5 . The meaning of external program instructions can refer to the content discussed above and will not be repeated here.

S807. The instruction execution module decodes the external program instruction, obtains the decoded result, and executes the decoded result to obtain the second execution result.

S808. The instruction execution module writes the second execution result into the external storage module.

Optionally, the operating system can obtain the second execution result from the external storage module, and then present the second execution result to the user.

As an example, S806 to S808 are optional steps.

For example, please refer to FIG. 10 , which is a schematic diagram of a process for processing internal detection instructions and external program instructions according to an embodiment of the present application.

As shown in Figure 10, the path for processing internal detection instructions includes: error detection module → instruction execution module → error detection module. The path for processing external program instructions includes: application→external storage module→instruction execution module→external storage module→application. It can be seen that the path for processing internal detection instructions in the embodiment of the present application is different from the path for processing external program instructions, and is simpler than the processing path for external program instructions.

In order to avoid continuous errors of the processor, optionally, the control module in the processor can control to shut down the processor. Alternatively, where the processor of FIG. 8 is applied to a computing device, the operating system of the computing device may control turning off the processor.

When the processor in Figure 8 is applied to a computing device, in order to facilitate the user to check errors of the processor, optionally, the error detection module can provide an alarm to the management module in the computing device when it determines that there is an error in the processor. information. This alarm information is used to indicate that there is an error in the processor. Furthermore, the management module can display the alarm information. In this way, users can be notified of processor errors in time.

In a possible implementation, when the processor in FIG. 8 is a multi-core processor, the internal detection instruction may be executed by an instruction corresponding to one processor core (such as the first processor core) in the processor. module is executed. Correspondingly, the error detection module may determine that there is an error in the first processor core. In this way, the processor can pinpoint exactly which A processor core failed.

Optionally, when the error detection module determines that there is an error in the first processor core, the error detection module can generate alarm information and send the alarm information to the management module. This alarm information is used to indicate that there is an error in the processor.

Optionally, when the error detection module determines that there is an error in the first processor core, the control module corresponding to the first processor core may control to shut down the first processor core. Alternatively, in the case where the processor in FIG. 8 is applied to a computing device, the operating system of the computing device may control turning off the first processor core. In this way, other processor cores of the processor can still work normally.

In the embodiment of the present application, the processor can detect whether there is an error in the processor according to the instructions in the processor. Since there is no need for the processor to decode the program instructions and send the execution results of the program instructions to an external inspection tool, it can Reducing the instructions generated by the processor will help reduce the processing load of the processor. Moreover, in the embodiment of the present application, the processor can perform error detection when the load of the processor is small, which can reduce the impact of the processor error detection process on the execution process of external program instructions. Moreover, when the processor is a multi-core processor, the processor can detect which processor core in the processor has an error to accurately determine the processor core in which the error occurred. In addition, when an error occurs in the processor, an alarm message can be reported and/or the processor can be shut down to handle the error in a timely manner to avoid greater impact. Moreover, in the process of executing internal detection instructions, applications can be loaded without the help of the operating system, thus reducing the processing load of the operating system. In other words, a computing device can perform processor error detection without installing an operating system. The computing device in the cloud scenario may not have an operating system installed. In other words, the processor error detection method in the embodiment of the present application can be better applied to cloud scenarios, such as the cloud computing and/or cloud scenarios mentioned above. Specific examples of storage and cloud scenarios include the cloud data center mentioned above.

Please refer to FIG. 11 , which is a schematic flowchart of a method for detecting processor errors provided by an embodiment of the present application. In the embodiment shown in FIG. 11 , the processor in FIG. 8 is specifically the processor 400 shown in FIG. 4 as an example. The processor in the embodiment shown in Figure 11 includes an error detection module and an instruction execution module. The error detection module includes an instruction acquisition sub-module, an instruction identification sub-module and an instruction judgment sub-module.

S1101. The instruction acquisition submodule adds a mark to the internal detection instruction.

Among them, the specific content of tags and adding tags can refer to the content discussed above.

Optionally, the instruction acquisition sub-module may send the tag to the instruction identification sub-module, so that the instruction identification sub-module subsequently identifies instructions for detecting processor errors based on the tag.

S1102. The instruction acquisition sub-module sends an internal detection instruction to the instruction execution module. Correspondingly, the instruction execution module receives internal detection instructions from the instruction acquisition sub-module.

For example, the instruction acquisition sub-module may send an internal detection instruction to the instruction execution module when it is determined that the detection switch is in an on state and/or the load on the processor is small.

Among them, the content of detecting the switch and determining that the detection switch is in the on state may refer to the above discussion.

As an example, the processor in the embodiment shown in FIG. 11 also includes a load judgment sub-module, which is, for example, the load judgment sub-module 424 in FIG. 4 . The load judgment sub-module determines that when the load of the processor is small, the load judgment sub-module sends the first indication information to the instruction acquisition sub-module. The first indication information is used to indicate that the load of the processor is small. The instruction acquisition sub-module receives the first instruction information and executes step S1102.

When the load of the processor is large, the load judgment sub-module may send second indication information to the instruction acquisition sub-module. The second indication information is used to indicate that the remaining space in the buffer queue of the processor is less than the threshold. The instruction acquisition sub-module receives the second instruction information and does not execute step S1102; or, when the load of the processor is large, the load judgment sub-module does not need to send any instruction information to the instruction acquisition sub-module. The instruction acquisition sub-module defaults to only The touch of the first instruction message Send, then execute step S1102.

S1103. The instruction execution module executes the internal detection instruction and obtains the first execution result.

The content of the first execution result may refer to the content discussed above.

When the instruction acquisition sub-module performs S1101, the instruction execution module may add a mark to the first execution result.

S1104. The instruction execution module sends the first execution result to the instruction identification sub-module. Correspondingly, the instruction identification sub-module receives the first execution result from the instruction execution module.

S1105. The instruction identification submodule determines the first execution result according to the mark.

S1106. The instruction identification sub-module sends the first execution result to the instruction execution module. Correspondingly, the instruction execution module receives the first execution result from the instruction identification sub-module.

For example, the instruction execution module sends all execution results to the instruction identification sub-module, and the instruction identification sub-module identifies the first execution result according to the mark of the first execution result.

For another example, the instruction execution module can directly send the first execution result to the instruction identification sub-module according to the mark of the first execution result, which is equivalent to the instruction identification sub-module determining the first execution result.

S1107. The instruction judgment submodule determines whether there is an error in the processor based on the matching result between the first execution result and the expected result of the internal detection instruction.

The instruction judgment sub-module determines whether there is an error in the processor by referring to the content discussed above.

Optionally, if the instruction judgment sub-module determines that there is an error in the processor, it can provide alarm information to the management module. The content of the management module and alarm information can refer to the content discussed above.

S1108. The instruction execution module obtains external program instructions from the external storage module.

The meaning of external program instructions can refer to the content discussed above.

S1109. The instruction execution module decodes the external program instruction, obtains the decoded result, and executes the decoded result to obtain the second execution result.

S1110. The instruction execution module sends the second execution result to the external storage module.

As an example, S1108-S1110 are optional steps.

For example, please refer to FIG. 12 , which is a schematic diagram of a process for processing internal detection instructions and external program instructions according to an embodiment of the present application.

As shown in Figure 12, the path for processing internal detection instructions includes: instruction acquisition sub-module → instruction execution module → instruction identification sub-module → error judgment sub-module. The path for processing external program instructions includes: application→external storage module→instruction execution module→application. It can be seen from this that the path for processing internal detection instructions in the embodiment of the present application is different from the path for processing external program instructions, and the path for processing the internal detection instructions in the embodiment of the present application is simpler.

The embodiment of the present application can be applied to the processor shown in Figure 4. In this embodiment, the error detection module can include an instruction acquisition sub-module, a load judgment sub-module, an instruction identification sub-module and an error judgment sub-module, providing an A scheme for detecting processor errors. Moreover, in this embodiment, the instruction acquisition sub-module, load judgment sub-module, instruction identification sub-module, error judgment sub-module and instruction execution unit in the processor can work together to detect processor errors without processor compilation. Program instructions, as well as sending execution results of program instructions to external inspection tools, etc., are beneficial to reducing the processing load of the processor. In addition, the instruction acquisition sub-module can send internal detection instructions to the instruction execution module when the load of the processor is small, so as to avoid increasing the processing load of the processor when the load of the processor is large.

An embodiment of the present application provides a computing device cluster. Please refer to Figure 13, which is a computing device cluster provided by an embodiment of the present application. The computing device cluster includes at least one computing device 1300, and any two computing devices 1300 communicate through a communication network.

As shown in Figure 13, computing device 1300 includes a processor 1301 and a power supply circuit 1302. The power supply circuit 1302 is used to provide power to the processor 1301. The processor 1301 in the computing device 1300 may be used to implement any of the above methods for detecting processor errors, for example, the method for detecting processor errors in the embodiment shown in FIG. 8 or FIG. 11 . It can also implement the functions of any of the previous processors. The structure of the processor 1301 may refer to the structure of the processor in Figure 2, Figure 3 or Figure 4 mentioned above.

Optionally, the computing device 1300 also includes a memory 1303 and a communication interface 1304. The memory 1303 and the communication interface 1304 are shown as dotted boxes in FIG. 13 .

Among them, the processor 1301 and the communication interface 1304 are coupled to each other. It can be understood that the communication interface 1304 may be a transceiver or an input-output interface.

The memory 1303 may be used to store external program instructions executed by the processor 1301 or input data required by the processor 1301 to run external program instructions or data generated after the processor 1301 executes the instructions.

As an example, the computing device cluster shown in Figure 13 can be used to implement the functions of the cloud data center in Figure 6 or Figure 7.

Embodiments of the present application provide a chip system, which includes: a processor and an interface. Wherein, the processor is used to call and run instructions from the interface, and when the processor executes the instructions, implement any of the previous methods of detecting processor errors, for example, the detection in the embodiment shown in Figure 8 or Figure 11 Handler error method.

Embodiments of the present application provide a computer-readable storage medium. The computer-readable storage medium is used to store computer programs or instructions. When the computer program or instructions are executed, any one of the above methods for detecting processor errors is implemented. For example, FIG. 8 or A method of detecting processor errors in the embodiment shown in FIG. 11 .

Embodiments of the present application provide a computer program product containing instructions that, when run on a computer, implement any of the foregoing methods for detecting processor errors, for example, the detection processing in the embodiments shown in Figure 8 or Figure 11 The wrong way to do it.

The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. Software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory In memory, register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage media may be located in an ASIC. Additionally, the ASIC can be located in the base station or terminal. Of course, the processor and the storage medium may also exist as discrete components in the base station or terminal.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer program or instructions may be transmitted from a website, computer, A server or data center transmits via wired or wireless means to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media, such as floppy disks, hard disks, and magnetic tapes; they can also be optical media, such as digital video optical disks; they can also be semiconductor media, such as solid-state media. harddisk. The computer-readable storage medium may be volatile or nonvolatile storage media, or may include both volatile and nonvolatile types of storage media.

In the various embodiments of this application, if there is no special explanation or logical conflict, the terms and/or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments are based on their inherent Logical relationships can be combined to form new embodiments.

It can be understood that the various numerical numbers involved in the embodiments of the present application are only for convenience of description and are not used to limit the scope of the embodiments of the present application. The size of the serial numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic.

Claims

A processor, characterized by including an error detection module and an instruction execution module, wherein:

The error detection module is used to send internal detection instructions to the instruction execution module;

The instruction execution module is used to execute the internal detection instruction, obtain a first execution result, and send the first execution result to the error detection module;

The error detection module is configured to determine whether there is an error in the processor based on the expected result corresponding to the first execution result and the internal detection instruction.
The processor according to claim 1, characterized in that the instruction execution module is also used to:

Read external program instructions from the external storage module;

Decode the external program instructions and obtain the decoded results;

Execute the decoded result to obtain a second execution result;

Write the second execution result into the external storage module.
The processor according to claim 1 or 2, characterized in that the error detection module is also used to:

Before sending an internal detection instruction to the instruction execution module, it is determined that the remaining space in the buffer queue of the processor is greater than or equal to a threshold, and the buffer queue is used to cache instructions to be processed by the processor.
The processor according to any one of claims 1-3, characterized in that,

The error detection module is also configured to add a mark to the internal detection instruction, where the mark represents an instruction for detecting an error in the processor;

The instruction execution module is also configured to add the mark to the first execution result;

The error detection module is further configured to identify the first execution result corresponding to the internal detection instruction according to the mark in the first execution result.
The processor according to any one of claims 1-4, characterized in that the processor further includes a register, and the register stores expected results corresponding to the internal detection instructions;

The error detection module is also used to read the expected result corresponding to the internal detection instruction from the register.
The processor according to any one of claims 1 to 5, wherein the error detection module is further configured to obtain the internal detection instructions from instructions that have been executed by the processor; or,

The processor also includes a first storage module that stores the internal detection instructions, the first storage module is allowed to be read by the processor, and the error detection module is also used to read from the first storage module Read the internal detection instructions; or,

The processor further includes a second storage module that stores the internal detection instructions, the second storage module is allowed to be read and written by the processor, and the error detection module is also used to read from the third Read the internal detection instructions from the second storage module.
The processor according to any one of claims 1 to 6, characterized in that the processor further includes at least one processor core, and one of the at least one processor core corresponds to the instruction execution module ;The error detection module is specifically used for:

According to the expected result corresponding to the first execution result and the internal detection instruction, it is determined whether there is an error in the processor core corresponding to the instruction execution module.
The processor according to any one of claims 1-7, characterized in that the error detection module is also used to:

Determine that the detection switch in the management module is in an on state, and the detection switch is used to indicate whether the processor The management module includes one or more of a baseboard management controller, a firmware system corresponding to the processor, or an operating system.
The processor according to any one of claims 1 to 8, wherein the error detection module is further configured to provide alarm information to a management module when it is determined that there is an error in the processor, and the management module includes One or more of the baseboard management controller, the firmware system or the operating system corresponding to the processor, the alarm information is used to indicate that there is an error in the processor; and/or,

The processor further includes the control module, which is configured to shut down the processor when the error detection module determines that there is an error in the processor.
A method for detecting processor errors, characterized by including:

The processor executes the internal detection instruction and obtains the first execution result;

The processor determines whether there is an error in the processor based on the expected result corresponding to the first execution result and the internal detection instruction.
The method of claim 10, further comprising:

The processor reads external program instructions from the external storage module;

The processor decodes the external program instructions and obtains the decoded results;

The processor executes the decoded result to obtain a second execution result;

The processor writes the second execution result into the external storage module.
The method according to claim 10 or 11, characterized in that the method further includes:

The processor determines that the remaining space in the buffer queue is greater than or equal to a threshold, and the buffer queue is used to cache instructions to be processed by the processor.
The method according to any one of claims 10-12, characterized in that the method further includes:

The processor adds a flag to the internal detection instruction, the flag representing an instruction for detecting an error in the processor;

The processor adds the mark to the first execution result;

The processor identifies the first execution result corresponding to the internal detection instruction according to the mark in the first execution result.
The method according to any one of claims 10 to 13, characterized in that the processor includes a register, and the register stores expected results corresponding to the internal detection instructions; the method further includes:

The processor reads the expected result corresponding to the internal detection instruction from the register.
The method according to any one of claims 10-14, characterized in that the method further includes:

The processor obtains the internal detection instructions from instructions that have been executed by the processor; or,

The processor further includes a first storage module that stores the internal detection instructions, the first storage module is allowed to be read by the processor, and the processor reads the first storage module from the first storage module. Internal testing instructions; or,

The processor also includes a second storage module that stores the internal detection instructions. The second storage module allows the processor to read and write. The processor reads from the second storage module. Get the internal detection instructions.
The method according to any one of claims 10 to 15, characterized in that the processor includes at least one processor core; the processor determines the expected result corresponding to the first execution result and the internal detection instruction. , determine whether there are errors in the processor, including:

The processor determines whether there is an error in the processor core used to obtain the first execution result based on the expected result corresponding to the first execution result and the internal detection instruction.
The method according to any one of claims 10-16, characterized in that the method further includes:

The processor determines that the detection switch in the management module is in an on state. The detection switch is used to indicate whether to detect errors of the processor. The management module includes a baseboard management controller and firmware corresponding to the processor. One or more of the systems or operating systems.
The method according to any one of claims 10-17, characterized in that the method further includes:

When the processor determines that there is an error in the processor, the processor provides alarm information to the management module. The management module includes one or more of a baseboard management controller, a firmware system corresponding to the processor, or an operating system, The alarm information is used to indicate that there is an error in the processor; and/or,

When the processor determines that there is an error in the processor, the processor shuts down the processor.
A computing device, characterized by comprising the processor according to any one of claims 1-9.
A computing device, characterized in that it includes a processor and a power supply circuit, the power supply circuit supplies power to the processor, and the processor is used to execute the method according to any one of claims 10-18.
A computing device cluster, characterized by including at least one computing device, each computing device executing the method according to any one of claims 10-18.
A computer program product containing instructions, characterized in that, when the instructions are executed by a computing device, the computing device performs the method according to any one of claims 10-18.
A computer-readable storage medium, characterized in that a computer program or instructions are stored in the storage medium. When the computer program or instructions are executed, the method according to any one of claims 10-18 is implemented.