WO2024050705A1 - 一种qfn封装结构、射频收发模组结构及电子设备 - Google Patents

一种qfn封装结构、射频收发模组结构及电子设备 Download PDF

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Publication number
WO2024050705A1
WO2024050705A1 PCT/CN2022/117396 CN2022117396W WO2024050705A1 WO 2024050705 A1 WO2024050705 A1 WO 2024050705A1 CN 2022117396 W CN2022117396 W CN 2022117396W WO 2024050705 A1 WO2024050705 A1 WO 2024050705A1
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Prior art keywords
pin
radio frequency
chip
qfn
capacitor
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PCT/CN2022/117396
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English (en)
French (fr)
Inventor
谢浩
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2022/117396 priority Critical patent/WO2024050705A1/zh
Priority to CN202223330170.5U priority patent/CN219322393U/zh
Publication of WO2024050705A1 publication Critical patent/WO2024050705A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Definitions

  • This application relates to the field of packaging, and in particular to a QFN packaging structure, a radio frequency transceiver module structure and electronic equipment.
  • embodiments of the present application provide a QFN packaging structure, a radio frequency transceiver module structure and electronic equipment.
  • the first aspect of the embodiment of the present application provides a QFN packaging structure, including a substrate, an EPAD welding area, a chip, and a QFN package pin.
  • the EPAD welding area is disposed on the surface of the substrate, and the chip is disposed on the surface of the EPAD welding area;
  • the QFN package pins surround the EPAD welding area and are arranged on the surface of the substrate; the QFN package pins are used to connect to external devices of the QFN package structure; the QFN package pins are connected to the chip;
  • the chip is arranged on the non-center surface of the EPAD welding area
  • the radio frequency transmitting pin of the chip is connected to the radio frequency transmitting pin of the QFN package pin through at least three first bonding wires.
  • the radio frequency receiving pin of the chip is connected to the radio frequency receiving pin of the QFN package pin through a second binding wire;
  • the length of the first binding line is less than or equal to the length of the second binding line.
  • the number of second binding wires is 1.
  • the arc height of the first binding wire is greater than or equal to 70um and less than or equal to 80um, and the length of the first binding wire is less than or equal to the length of the second binding wire. length.
  • the radio frequency transmitting ground pin of the chip is connected to the radio frequency transmitting ground pin of the QFN package pin through a third binding wire, and the radio frequency receiving ground pin of the chip is connected to the radio frequency transmitting ground pin through a fourth binding wire.
  • the bonding wire is connected to the RF receiving ground pin of the QFN package pin;
  • the RF transmitting pin of the chip is adjacent to the RF transmitting ground pin of the chip and the RF receiving pin of the chip; the RF receiving pin of the chip is adjacent to the RF receiving ground pin of the chip;
  • the RF transmitting pin of the QFN package pin is adjacent to the RF transmitting ground pin of the QFN package pin and the RF receiving pin of the chip; the RF receiving pin of the QFN package pin is adjacent to the RF receiving ground pin of the QFN package pin. Feet adjacent.
  • the distance between the first binding line and the third binding line is greater than or equal to 30um and less than or equal to 100um, and the arc height of the third bonding line is equal to The arc height of the first binding line;
  • the length of the first binding line is less than or equal to the lengths of the third binding line and the fourth binding line.
  • a filter capacitor is provided in the chip, and the filter capacitor is connected to the radio frequency transmitting ground pin of the chip and the radio frequency transmitting pin of the chip.
  • the second aspect of the embodiment of the present application provides a QFN packaging structure, including a substrate, an EPAD welding area, a chip and a QFN package pin.
  • the EPAD welding area is arranged on the surface of the substrate, and the chip is arranged on the surface of the EPAD welding area;
  • the QFN package pins surround the EPAD welding area and are arranged on the surface of the substrate; the QFN package pins are used to connect to external devices of the QFN package structure; the QFN package pins are connected to the chip;
  • the chip is arranged on the non-center surface of the EPAD welding area
  • the radio frequency transceiver pins of the chip are connected to the radio frequency transceiver pins of the QFN package pins through at least three first bonding wires.
  • the arc height of the first binding wire is greater than or equal to 70um and less than or equal to 80um.
  • the radio frequency transmitting ground pin of the chip is connected to the radio frequency transmitting ground pin of the QFN package pin through a third binding wire, and the radio frequency receiving ground pin of the chip is connected to the radio frequency transmitting ground pin through a fourth binding wire.
  • the bonding wire is connected to the RF receiving ground pin of the QFN package pin;
  • the RF transceiver pins of the chip are adjacent to the RF transmitting ground pins of the chip and the RF receiving ground pins of the chip;
  • the radio frequency transceiver pin of the QFN package pin is adjacent to the radio frequency transmitting ground pin of the QFN package pin and the radio frequency receiving ground pin of the QFN package pin.
  • the distance between the first binding line and the third binding line is greater than or equal to 30um and less than or equal to 100um, and the arc height of the third bonding line is equal to The arc height of the first binding line is high; the length of the first binding line is less than or equal to the length of the third binding line and the fourth binding line.
  • a filter capacitor is provided in the chip, and the filter capacitor is connected to the radio frequency transmitting ground pin of the chip and the radio frequency transmitting and receiving pin of the chip.
  • the third aspect of the embodiment of the present application provides a radio frequency transceiver module structure, including an antenna, a matching network circuit, a first inductor, and a QFN packaging structure of any one of the first aspects.
  • the antenna is connected to the matching network circuit, and the matching
  • the network circuit is connected to the radio frequency transmitting pin of the QFN package pin; the first inductor is respectively connected to the matching network circuit and the radio frequency receiving pin of the QFN package pin.
  • the matching network circuit includes a first capacitor, a second capacitor, a third capacitor and a second inductor;
  • the antenna is connected to the first end of the first capacitor
  • the second terminal of the first capacitor is connected to the first terminal of the second capacitor and the first terminal of the second inductor respectively;
  • the second terminal of the second capacitor is connected to ground
  • the second end of the second inductor is respectively connected to the first end of the third capacitor, the radio frequency transmitting pin of the QFN package pin, and the first inductor;
  • the second terminal of the third capacitor is connected to ground.
  • the fourth aspect of the embodiments of the present application provides a radio frequency transceiver module structure, including an antenna, a matching network circuit and the QFN packaging structure of any one of the second aspect, the antenna is connected to the matching network circuit, and the matching network circuit is connected to the QFN The RF transceiver pin connections of the package pins.
  • the matching network circuit includes a first capacitor, a second capacitor, a third capacitor and a second inductor;
  • the antenna is connected to the first end of the first capacitor
  • the second terminal of the first capacitor is connected to the first terminal of the second capacitor and the first terminal of the second inductor respectively;
  • the second terminal of the second capacitor is connected to ground
  • the second end of the second inductor is respectively connected to the first end of the third capacitor and the RF transceiver pin of the QFN package pin;
  • the second terminal of the third capacitor is connected to ground.
  • a fifth aspect of the embodiments of the present application provides an electronic device, including a housing and the radio frequency transceiver module structure of any one of the third and fourth aspects, and the radio frequency transceiver module structure is disposed in the housing.
  • the beneficial effect of the embodiment of the present application is that the radio frequency transmitting pin of the chip is connected to the radio frequency transmitting pin of the QFN package pin through at least three first binding wires, so that the first binding wire
  • the parasitic capacitance of the EPAD welding area is large, thereby enhancing the filtering effect on harmonics, thereby reducing the external radiation of harmonics, and improving the problem of excessive radiation at a lower cost.
  • Figure 1 is a schematic diagram of a three-element matching network circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of the harmonic characteristics of a three-element matching network circuit provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of a five-element matching network circuit provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of a QFN packaging structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another QFN packaging structure provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of yet another QFN packaging structure provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of yet another QFN packaging structure provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of yet another QFN packaging structure provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of yet another QFN packaging structure provided by an embodiment of the present application.
  • Figure 10 is a schematic diagram of the structure of a radio frequency transceiver module provided by an embodiment of the present application.
  • FIG 11 is a schematic diagram of the structure of another radio frequency transceiver module provided by an embodiment of the present application.
  • Table 1 shows the global radiation regulations for Bluetooth modules. Different countries have requirements for the energy of harmonics beyond 2.4GHz, and these requirements are becoming increasingly stringent.
  • BLE Bluetooth of Low Energy
  • the radiated energy of BLE chips currently on the market easily exceeds the standard and it is difficult to pass international standard certification.
  • the Bluetooth chip needs to emit 15dBm power
  • the measured radiation exceeds the standard by 20dB.
  • the radiation exceeds the standard because the BLE chip itself will produce out-of-band interference due to nonlinear distortion and other reasons, so it can easily affect other devices.
  • nonlinear distortion will increase the proportion of harmonics. This phenomenon is called THD (Total Harmonic Distortion).
  • THD Total Harmonic Distortion
  • Figure 1 illustrates a matching network circuit for the transmit pin (TX) to achieve impedance matching.
  • the matching network circuit is also used to filter the transmitted energy.
  • a three-element matching network (3elements C-L-C matching network) circuit can be used. solution for impedance matching.
  • Figure 2 shows the harmonic characteristics of the three-element matching network circuit shown in Figure 1. It can be seen that the cut-off depth of the three-element matching network circuit shown in Figure 1 is not enough for the second and above harmonics. The cut-off depth is also called the stop-band suppression degree.
  • the stop-band suppression degree is an important indicator to measure the performance of filter selection. The higher the indicator, the better the suppression of out-of-band interference signals.
  • the function of the matching network circuit is to match the impedance of the PA (Power Amplifier) of the chip to be the same as the antenna (Antenna). Therefore, the matching network circuit has higher requirements on the values of the inductor and capacitor.
  • a 50-ohm impedance matching design network can be integrated inside the PA.
  • the matching network circuit can be set outside the integrated chip to reduce the chip area.
  • the output impedance of a high-power PA is, for example, 10 ⁇
  • the output impedance of a low-power PA is, for example, 25 ⁇ .
  • an impedance matching of 50 ohms can be achieved through a ⁇ -type matching circuit.
  • the characteristic impedance of the PA affects the value of the peripheral matching circuit. .
  • the following embodiment uses a QFN packaging structure to form capacitors and inductors. Therefore, the matching network circuit has much looser requirements on the values of capacitors and inductors.
  • the following embodiment uses the QFN packaging structure to form parasitic capacitance and parasitic inductance, which can also be understood as forming a low-pass filter in the QFN packaging structure to filter harmonics.
  • the following embodiments introduce parasitic capacitance and parasitic inductance by optimizing the QFN packaging structure.
  • the QFN packaging structure can also be combined with a three-element matching network circuit outside the QFN packaging structure to form a five-element matching network (5elements) as shown in Figure 3.
  • the C-L-C matching network circuit scheme can improve the suppression strength of harmonics, thereby reducing harmonic radiation energy.
  • the five-element matching network circuit shown in Figure 3 can be applied to Bluetooth chips that need to emit 15dBm power.
  • the chip may include a PA with an output impedance of approximately 10 ⁇ at a transmit power of 15dBm.
  • Figure 4 shows the harmonic characteristics of the five-element matching network circuit shown in Figure 3. It can be seen that the filter has more orders, the transition band (2.4GHz-4.8GHz) decreases faster, and the gain curve The slope is larger, so that the harmonic energy can be suppressed lower at 4.8GHz.
  • the welding area 51 is disposed on the surface of the substrate 56
  • the chip 52 is disposed on the surface of the EPAD welding area 51
  • the QFN package pin 53 is connected to the chip 52
  • the QFN package pin 53 includes a radio frequency transmitting ground pin VSS_TX and a radio frequency receiving ground pin VSS_RX.
  • radio frequency receiving pin RX and radio frequency transmitting pin TX radio frequency transmitting pin TX.
  • the QFN package pin 53 surrounds the EPAD welding area 51 and is arranged at the edge position of the surface of the substrate 56.
  • the QFN package pin 53 is used for electrical connection with the external device of the QFN package structure. Connection, for example, with a matching network circuit outside the QFN package structure, or the QFN package pin 53 is also used to connect with other chips to achieve user-preset functions.
  • the chip 52 is disposed on the non-center surface of the EPAD welding area 51 , that is, the chip 52 is disposed at a position offset from the center of the EPAD welding area 51 . As shown in FIG. 5 , the chip 52 is disposed closer to the radio frequency transmitting pin TX of the QFN package pin than to other pins of the QFN package pin.
  • the EPAD welding area 51 can be understood as a metal exposed pad.
  • the center of the EPAD welding area 51 coincides with the center of the QFN packaging structure.
  • the EPAD welding area 51 is located below the substrate 56 and the chip 52 is located below the EPAD welding area 51.
  • the center of the EPAD welding area 51 coincides with the center of the substrate 56.
  • the EPAD welding area can be a piece of copper provided in the central area of the QFN package structure.
  • the EPAD welding area is generally used as GND.
  • the EPAD welding area is connected to GND and can be used For heat dissipation, for example, the EPAD pad can be connected to the GND on the peripheral PCB (Printed Circuit Board).
  • At least three radio frequency transmitting pins 521, 522, and 523 of the chip 52 are connected to the radio frequency transmitting pin TX of the QFN package pin through first binding lines 541, 542, and 543 respectively.
  • ESR Equivalent Series Resistance
  • the insertion loss Insertion Loss
  • the transmit power is reduced. It can be understood that the more first binding wires connected in parallel, the smaller the resistance introduced by the first binding wires, and therefore the smaller the insertion loss.
  • the embodiment of the present application sets up two or more binding lines of radio frequency transmitting pins, and reduces the insertion loss by connecting at least three first binding lines in parallel.
  • setting the number of first binding wires between the RF transmitting pin of the chip and the RF transmitting pin of the QFN package pin to at least 3 can increase the parasitic capacitance to enhance the protection against harmonics.
  • the filter effect avoids the need to add additional filter components or chip shields, which can improve the problem of excessive radiation at low cost and avoid increasing the chip volume.
  • the more bonding wires the smaller the insertion loss at the 2.4GHz operating frequency for the chip's RF transmit pin.
  • there will be insertion loss outside the chip such as the insertion loss caused by bonding wires, the insertion loss caused by peripheral PCB traces, and the insertion loss caused by the inductors used in matching devices.
  • TX because it is a clean signal of a specific frequency emitted by the chip and the transmission power is high, the key is to reduce the loss of the signal transmitted through TX.
  • the QFN packaging structure also includes a substrate 56 , the EPAD welding area is provided on the surface of the substrate, and the QFN package pins are provided on the edge of the surface of the substrate.
  • the arc height of the first binding wire is greater than or equal to 50um and less than 100um.
  • the parasitic capacitance of TX is formed by the first bonding line and the EPAD welding area 51, which is similar to the principle of plate capacitance. As shown in FIG. 6 , the closer the first bonding line 542 is to the EPAD welding area 51 , the greater the parasitic capacitance formed between the first bonding line and the EPAD welding area.
  • the bonding arc height H1 of the first binding wire 542 in Figure 5 is set as small as possible, so that the first binding wire 542 is as close as possible to the EPAD welding area 51, so that the parasitic capacitance is as large as possible for better Filter harmonics.
  • H1 is set to be greater than or equal to 50um and less than 100um.
  • H1 can be designed to be greater than or equal to 70um and less than or equal to 80um. Setting H1 to be greater than or equal to 70um and less than or equal to 80um can increase the parasitic capacitance formed between the first bonding line and the EPAD welding pad 51 and facilitate process implementation.
  • the QFN packaging structure has better reliability.
  • H1 should be made as small as possible, and H1 can be set to 70um.
  • the bonding wire itself has parasitic inductance.
  • the parasitic inductance at TX is determined by the length of the bonding wire itself.
  • a 1mm length bonding wire corresponds to a parasitic inductance of 1nH. Therefore, harmonics can be filtered by introducing parasitic capacitance and parasitic inductance within the QFN packaging structure and working with the matching network circuit outside the QFN packaging structure.
  • the radio frequency transmitting ground pins 525, 526, and 527 of the chip are connected to the QFN package pins through the third binding wires 545, 546, and 547 respectively.
  • the radio frequency transmitting ground pin VSS_TX, and the radio frequency receiving ground pins 528, 529, and 530 of the chip are connected to the radio frequency receiving ground pin VSS_RX of the QFN package pin through the fourth binding wires 548, 549, and 550.
  • the first binding wire and the third binding wire in order to Increasing the parasitic capacitance and parasitic inductance formed by the first binding wire and the third binding wire can also make the distance d1 between the first binding wire and the third binding wire as small as possible.
  • the first binding wire The distance d1 between the line 542 and the third binding line 545 is less than or equal to 100um, and the arc height of the third binding line is equal to the arc height of the first binding line, so that the first binding line and The distance d1 between the third binding lines should be as small as possible. Because the distance between the bonding lines is too close to facilitate process implementation, please refer to Figure 6.
  • the distance d1 between the first bonding line 542 and the third bonding line 545 can be configured to be greater than or equal to 30um and less than or equal to 30um. Equal to 100um, for example 50um, to increase the parasitic capacitance formed by the first bonding line and the third bonding line, so that the parasitic capacitance formed by the first bonding line and the third bonding line satisfies 1pF ⁇ C ⁇ 7pF, For example, it is 3.6pF.
  • the value of the parasitic inductance satisfies: 1nH ⁇ L ⁇ 5nH, for example, 2.4nH.
  • the bonding arc height H2 of the second bonding line and the bonding arc height H2 of the fourth bonding line can be set to be equal to H1.
  • the chip 52 is disposed on the non-center surface of the EPAD welding area 51. Specifically, the RF transmitting pins 521, 522, and 523 of the chip 52 are close to the QFN. The RF transmit pin TX of the package pin. Compared with other pins of the chip 52, the radio frequency transmitting pins 521, 522, and 523 of the chip 52 are closest to the radio frequency transmitting pin TX of the QFN package pin. Therefore, compared with other binding lines, the third The length of one binding wire 521, 522, 523 is less than or equal to the length of other binding wires.
  • the length of the first binding wire is less than or equal to the second binding wire 544 and the third binding wire 545, 546, 547. , the length of the fourth binding lines 548, 549, and 550.
  • the chip is disposed on the non-center surface of the EPAD welding area so that the length of the first bonding line is as short as possible.
  • the radio frequency transmitting pin TX of the QFN package pin can be made to face the radio frequency transmitting pin of the chip 52 foot.
  • the length of the bonding wire can constrain the parasitic inductance.
  • a 1mm bonding wire has a parasitic inductance of 1nH, and the parasitic inductance introduced by the bonding wire is 2.4nH.
  • This embodiment can use a binding wire length within 3 mm, and the length of the first binding wire can be set to a minimum to reduce insertion loss.
  • the key is to reduce the loss of the signal transmitted through TX, that is, reducing the insertion loss is particularly important for the radio frequency transmission performance. important.
  • the RF receiving pin of the chip and the RF receiving pin of the QFN package pin are connected only through a second binding wire.
  • the purpose is to pass a
  • the second bonding line forms a larger parasitic inductance to suppress harmonics, thereby improving the SNR (SIGNAL-NOISE RATIO, signal-to-noise ratio) when the chip receives radio frequency signals.
  • SNR SIGNAL-NOISE RATIO, signal-to-noise ratio
  • the parasitic inductance formed by the RX bonding line can suppress interference other than 2.4G and improve SNR. Therefore, in this embodiment, the parasitic inductance of the RX bonding line can Set it slightly larger, because the inductance is doubled after multiple sets of binding wires are connected in parallel, so there is no need to connect multiple sets of binding wires in parallel. In addition, an increase in the number of bonding wires will also lead to an increase in cost, so the RF receiving pin of the chip and the RF receiving pin of the QFN package pin can be connected only through a second bonding wire. As shown in FIG.
  • the radio frequency receiving pin 524 of the chip 52 is connected to the radio frequency receiving pin RX of the QFN package pin through a second binding wire 544, and the number of the second binding wire is 1.
  • the radio frequency receiving performance of the chip is greatly affected by the parasitic inductance.
  • the radio frequency receiving performance of the chip mainly includes receiving sensitivity. Parasitic inductance can be introduced to prevent high-frequency noise, thereby achieving higher transmission power even at high transmission power. High receiving sensitivity.
  • the RF emission performance of the chip is greatly affected by parasitic capacitance.
  • the harmonics of the RF emission pin of the chip can be transmitted to the RF emission ground pin of the chip through the parasitic capacitance.
  • the most important parameter is SNR.
  • the receiving sensitivity is low.
  • the receiving sensitivity is -99dBm.
  • the receiving sensitivity is -99dBm.
  • the RF transmitting ground pins 525, 526, 527 of the chip and the RF receiving ground pin 524 of the chip are respectively arranged at the RF transmitting pin 521 of the chip.
  • the RF transmitting ground pin VSS_TX of the QFN package pin and the RF receiving ground pin RX of the QFN package pin are respectively set on both sides of the RF transmitting pin TX of the QFN package pin.
  • the RF transmitting pin of the chip is adjacent to the RF transmitting ground pin of the chip and the RF receiving pin of the chip respectively.
  • the RF receiving pin 524 of the chip is adjacent to the RF receiving ground pin 528 of the chip.
  • the radio frequency transmitting pin TX of the QFN package pin is adjacent to the radio frequency transmitting ground pin VSS_TX of the QFN package pin and the radio frequency receiving pin RX of the QFN package pin respectively.
  • the radio frequency receiving pin RX of the QFN package pin is adjacent to the radio frequency receiving ground pin VSS_RX of the QFN package pin.
  • the pin arrangement it is easy to introduce high-order harmonics from the RF transmitting pin of the chip to the RF transmitting ground pin of the chip through the parasitic capacitance introduced by the multiple first binding wires, so that the high-order harmonics Harmonics are not easily transmitted to the radio frequency path outside the QFN packaging structure to reduce external radiation, so that it can pass various regulations on radiation energy testing requirements.
  • the size of C4 can be 1 to 8pF, and high-order harmonics can also be introduced from the RF transmit pin of the chip to the RF transmitter of the chip through capacitor C4.
  • a radio frequency transmitting ground pin and a radio frequency receiving ground pin are provided at both ends of the radio frequency transmitting pin.
  • the harmonics of the radio frequency transmitting pin are more easily transmitted to the radio frequency transmitting ground pin and the radio frequency receiving ground pin, reducing the The harmonics radiate energy to the outside.
  • the upper and lower ends of TX are surrounded by VSS_RX and VSS_TX, so that the harmonic energy can be conducted inside the QFN package structure through the closed ground loop formed by VSS_RX or VSS_TX, thereby reducing external radiation.
  • a filter capacitor may also be added inside the chip 52 between the RF transmitting pin 521 of the chip and the RF transmitting ground pin 526 of the chip.
  • C4 that is, adding filter capacitor C4 inside the chip
  • filter capacitor C4 is connected to the RF transmitting ground pin 526 of the chip and the RF transmitting pin 521 of the chip respectively
  • the filter capacitor C4 is connected to the binding line of the chip and the QFN package pin.
  • the introduced parasitic inductance together forms a filter circuit, which has a filtering effect on high-order harmonics.
  • this embodiment proposes another QFN packaging structure.
  • the radio frequency receiving pin of the chip in the QFN packaging structure of this embodiment is shared with the radio frequency transmitting pin of the chip.
  • a pin, its shared pin is called the radio frequency transceiver pin.
  • the radio frequency transceiver pin Please refer to the bottom view of the QFN package structure shown in Figure 8, which includes an EPAD welding area 81, a chip 82 and a QFN package pin 83.
  • the chip 82 is disposed on the surface of the EPAD welding area 81, and the QFN package pin 83 is connected to the chip 82.
  • the QFN package pins 83 include a radio frequency transceiver pin TRX, a radio frequency transmitter ground pin VSS_TX, and a radio frequency receive ground pin VSS_RX.
  • the chip 82 is disposed on the non-center surface of the EPAD welding area 81 .
  • the radio frequency transceiver pins 821, 822, and 823 of the chip 82 are respectively connected to the radio frequency transceiver pin TRX of the QFN package pin through at least three first binding wires 841, 842, and 843.
  • the QFN package structure also includes a substrate 86.
  • the EPAD welding area 81 is disposed on the surface of the substrate 86.
  • the QFN package pins 83 surround the EPAD welding area 81 and are disposed on the edge of the surface of the substrate 86.
  • the QFN package pins 83 are used to communicate with the QFN package structure. external device connections.
  • the arc height H1 of the first binding wire is greater than or equal to 50um and less than 100um.
  • the parasitic capacitance of TRX is formed by the first bonding line and the EPAD welding area 51, which is similar to the principle of plate capacitance. As shown in FIG. 9 , the closer the first bonding line 821 is to the EPAD welding area 81 , the greater the parasitic capacitance formed between the first bonding line 821 and the EPAD welding area 81 . Therefore, the arc height H1 of the first binding line 821 in Figure 9 is set as small as possible so that the first binding line 821 is as close as possible to the EPAD welding area 81.
  • H1 is too small and is not conducive to process implementation. Therefore, setting H1 Is greater than or equal to 50um and less than 100um.
  • H1 can be designed to be greater than or equal to 70um and less than or equal to 80um. Setting H1 to be greater than or equal to 70um and less than or equal to 80um can increase the parasitic capacitance formed between the bonding line and the EPAD pad 81 and facilitate process implementation. In addition, the reliability of the QFN packaging structure is better. When the process allows and does not increase the cost, H1 should be made as small as possible, and H1 can be set to 70um.
  • the bonding wire itself has parasitic inductance, and the parasitic inductance at the TRX is determined by the length of the bonding wire itself.
  • a 1mm length bonding wire corresponds to a parasitic inductance of 1nH. Therefore, the harmonics can be filtered by introducing parasitic capacitance and parasitic inductance within the QFN packaging structure, and together with the matching network circuit outside the QFN packaging structure.
  • the RF transmitting ground pins 825, 826, and 827 of the chip are respectively connected to the RF transmitting pins of the QFN package through third binding wires 845, 846, and 847.
  • the transmitting ground pin VSS_TX and the chip's radio frequency receiving ground pins 828, 829 and 830 are respectively connected to the radio frequency receiving ground pin VSS_RX of the QFN package pin through fourth binding lines 848, 849 and 850.
  • the RF transceiver pins of the chip are adjacent to the RF transmitter ground pins of the chip and the RF receive ground pins of the chip respectively.
  • the RF transceiver pins TRX of the QFN package pins are respectively connected to the RF transmitter ground pins VSS_TX and VSS_TX of the QFN package pins.
  • the RF receiving ground pin VSS_RX of the QFN package pin is adjacent to it.
  • a radio frequency transmitting ground pin and a radio frequency receiving ground pin are provided at both ends of the radio frequency transmitting and receiving pins.
  • the harmonics of the radio frequency transmitting and receiving pins are more easily transmitted to the radio frequency transmitting ground pins and the radio frequency receiving ground pins, reducing the The harmonics radiate energy to the outside.
  • the upper and lower ends of TRX are surrounded by VSS_RX and VSS_TX, so that the harmonic energy can form a closed ground loop through the VSS_RX or VSS_TX inside the package, reducing external radiation.
  • the relationship between the first bonding line and the third bonding line can also be The distance d1 between them should be as small as possible.
  • the distance d1 between the first binding line 842 and the third binding line 845 is less than or equal to 100um, and the arc height of the third binding line is equal to The arc of the first binding line is high so that the distance d1 between the first binding line and the third binding line is as small as possible.
  • the distance between the first bonding line 842 and the third bonding line 845 is greater than or equal to 30um and less than or equal to 100um, for example, 50um.
  • the parasitic capacitance formed by the first bonding line and the third bonding line is increased so that the parasitic capacitance formed by the first bonding line and the third bonding line satisfies 1pF ⁇ C ⁇ 7pF, for example, 3.6pF.
  • the lengths of the first binding wires 841, 842, and 843 are less than or equal to the lengths of other binding wires.
  • the lengths of the first binding wires 841, 842, and 843 are less than or equal to the lengths of the third binding wires 845, 846, 847, The length of the fourth binding wires 848, 849, and 850.
  • the value of the bonding arc height H2 of the fourth bonding line can be set equal to H1.
  • the filter capacitor C4 disposed between the RF transceiver pin 822 of the chip and the RF transmitter ground pin 825 of the chip can also be added inside the chip 82, that is, the filter capacitor C4 can be added inside the chip. Both ends of the filter capacitor C4 are connected to the RF transmitting ground pin 825 of the chip and the RF transceiver pin 822 of the chip respectively, and the filter capacitor C4 forms a filter circuit together with the parasitic inductance introduced by the bonding wire between the chip and the QFN package pin. , which has a filtering effect on high-order harmonics.
  • the embodiments of this application propose a package-level solution, which can be applied to Bluetooth chips and can better solve the problem of excessive radiation to support higher transmission power.
  • the solutions of the embodiments of this application can also be applied to the field of the Internet of Things. Application scenarios that require radio frequency transceiver.
  • this embodiment proposes a radio frequency transceiver module structure, as shown in Figure 10, including a QFN packaging structure 101, an antenna 102, a matching network circuit 103 and a first inductor L1, the antenna 102 and the matching network circuit 103
  • the matching network circuit 103 is connected to the QFN package pin, and the radio frequency transmitting pin TX of the QFN package pin is connected to the radio frequency receiving pin RX of the QFN package pin through the first inductor L1.
  • the QFN packaging structure in this embodiment is the same as or similar to the previous embodiment. Reference can be made to the QFN packaging structure in the previous embodiment. Therefore, the QFN packaging structure 101 will not be described again here.
  • the parasitic capacitance and parasitic inductance formed by the QFN packaging structure are combined with the matching network circuit outside the QFN packaging structure to form a multi-order filter circuit.
  • the harmonic suppression effect can be improved, thereby reducing the harmonics.
  • the TX bonding line is set between the VSS_RX bonding line and the VSS_TX bonding line. It can be understood that the TX bonding line is surrounded by the two.
  • the traces connected to TX are set between the traces connected to VSS_RX and the traces connected to VSS_TX.
  • the traces connected to TX are surrounded by the two. This can reduce the external radiation of TX harmonics, because after the trace connected to TX is surrounded by the trace connected to VSS_RX and the trace connected to VSS_TX, its energy is more concentrated and will not diverge.
  • the matching network circuit 103 includes a first capacitor C1, a second capacitor C2, a third capacitor C3 and a second inductor L2, wherein the antenna 102 and the The first end of a capacitor C1 is connected, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2 and the first end of the second inductor L2 respectively, and the second end of the second capacitor C2 is connected to ground.
  • the second end of the second inductor L2 is connected to the first end of the third capacitor C3, the radio frequency transmitting pin of the QFN package pin and the first inductor L1 respectively, and the second end of the third capacitor C3 is connected to the ground.
  • the 3-element matching network circuit outside the QFN packaging structure 101 can form a second-order low-pass filter.
  • the parasitic inductance and parasitic capacitance formed by the QFN packaging structure can also be regarded as a second-order low-pass filter. Therefore, Figure 10
  • the RF transceiver module structure shown overall forms a fourth-order low-pass filter, which has a better suppression effect on high-order harmonics. In this embodiment, the more orders, the better the harmonic suppression effect, but the more orders, the greater the insertion loss.
  • the 4th order low-pass filter shown in Figure 10 can ensure harmonic suppression. The wave suppression effect is achieved while controlling the insertion loss within a certain limit.
  • this embodiment proposes another radio frequency transceiver module structure, as shown in Figure 11, including a QFN packaging structure 111, an antenna 112 and a matching network circuit 113.
  • the antenna 112 is connected to the matching network circuit 113.
  • the matching network circuit 103 is connected to the radio frequency transceiver pin TRX of the QFN package pin.
  • the QFN packaging structure in this embodiment is the same as or similar to the previous embodiment. You can refer to the QFN packaging structure in the previous embodiment.
  • the RF transmitting pin and the RF receiving pin in the QFN packaging structure 111 in this embodiment share the same one. RF transceiver pins, the QFN package structure 111 will not be described in detail here.
  • the parasitic capacitance and parasitic inductance formed by the QFN packaging structure are combined with the matching network circuit outside the QFN packaging structure to form a multi-order filter circuit.
  • the harmonic suppression effect can be improved, thereby reducing the harmonics. Wave energy radiation intensity.
  • the matching network circuit 113 includes a first capacitor C1, a second capacitor C2, a third capacitor C3 and a second inductor L2, wherein the antenna 112 and the The first end of a capacitor C1 is connected, and the second end of the first capacitor C1 is connected to the first end of the second capacitor C2 and the first end of the second inductor L2 respectively.
  • the second end of the second capacitor C2 is connected to ground.
  • the second end of the inductor L2 is connected to the first end of the third capacitor C3 and the radio frequency transceiver pin of the QFN package pin respectively, and the second end of the third capacitor C3 is connected to the ground.
  • the 3-element matching network circuit outside the QFN packaging structure 101 can form a second-order low-pass filter.
  • the parasitic inductance and parasitic capacitance formed by the QFN packaging structure can also be regarded as a second-order low-pass filter. Therefore, Figure 11
  • the RF transceiver module structure shown overall forms a fourth-order low-pass filter, which has a better suppression effect on high-order harmonics. In this embodiment, the more orders, the better the harmonic suppression effect, but the more orders, the greater the insertion loss.
  • the 4th order low-pass filter shown in Figure 11 can ensure harmonic suppression. The wave suppression effect is achieved while the insertion loss is controlled within a certain limit.
  • the electronic device provided in this embodiment includes any of the radio frequency transceiver module structures in the previous embodiments, and also includes a housing.
  • the housing is further provided with a screen, and the radio frequency transceiver module structure is disposed in the housing.
  • B corresponding to A means that B is associated with A, and B can be determined based on A.
  • determining B based on A does not mean determining B only based on A.
  • B can also be determined based on A and/or other information.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

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Abstract

本申请涉及封装领域，尤其涉及一种QFN封装结构、射频收发模组结构及电子设备。QFN封装结构包括基板、EPAD焊接区、芯片和QFN封装引脚，EPAD焊接区设置于基板的表面，芯片设置于EPAD焊接区的表面；QFN封装引脚围绕EPAD焊接区并且设置于基板的表面；QFN封装引脚用于与QFN封装结构的外部的器件连接；QFN封装引脚与芯片连接；芯片设置于EPAD焊接区的非中心位置的表面；芯片的射频发射引脚通过至少三根第一绑定线连接至QFN封装引脚的射频发射引脚。芯片的射频发射引脚通过至少三根第一绑定线连接至所述QFN封装引脚的射频发射引脚，使得第一绑定线与EPAD焊接区的寄生电容较大，从而增强对谐波的滤波作用，从而减少谐波对外的辐射。

Description

一种QFN封装结构、射频收发模组结构及电子设备 技术领域
本申请涉及封装领域，尤其涉及一种QFN封装结构、射频收发模组结构及电子设备。
背景技术
目前很多芯片在大发射功率的条件下容易产生辐射超标的问题，一般来说，当芯片支持15dBm的发射功率时，可能超出FCC(Federal Communications Commission，国联邦通信委员会)规定的对谐波辐射的限制20dB以上。目前市面上产品为了解决该问题，一般通过额外增加滤波器件，或增加芯片屏蔽罩，但这些方案都会大幅度增加成本或者使得芯片体积增加，因此，如何更低成本地解决辐射超标成为亟待解决的技术问题。
发明内容
针对辐射超标的问题，本申请实施例提供了一种QFN封装结构、射频收发模组结构及电子设备。
本申请的实施例的第一方面提供了一种QFN封装结构，包括基板、EPAD焊接区、芯片和QFN封装引脚，EPAD焊接区设置于基板的表面，芯片设置于EPAD焊接区的表面；
QFN封装引脚围绕EPAD焊接区并且设置于基板的表面；QFN封装引脚用于与QFN封装结构的外部的器件连接；QFN封装引脚与芯片连接；
芯片设置于EPAD焊接区的非中心位置的表面；
芯片的射频发射引脚通过至少三根第一绑定线连接至QFN封装引脚的射频发射引脚。
根据第一方面，在一种可能的实现方式中，芯片的射频接收引脚通过第二绑定线连接至QFN封装引脚的射频接收引脚；
第一绑定线的长度小于或者等于第二绑定线的长度。
根据第一方面，在一种可能的实现方式中，第二绑定线的数量为1。
根据第一方面，在一种可能的实现方式中，第一绑定线的打线弧高大于 或者等于70um并且小于或者等于80um，第一绑定线的长度小于或者等于第二绑定线的长度。
根据第一方面，在一种可能的实现方式中，芯片的射频发射地引脚通过第三绑定线连接至QFN封装引脚的射频发射地引脚，芯片的射频接收地引脚通过第四绑定线连接至QFN封装引脚的射频接收地引脚；
芯片的射频发射引脚分别与芯片的射频发射地引脚、芯片的射频接收引脚相邻；芯片的射频接收引脚与芯片的射频接收地引脚相邻；
QFN封装引脚的射频发射引脚分别与QFN封装引脚的射频发射地引脚、芯片的射频接收引脚相邻；QFN封装引脚的射频接收引脚与QFN封装引脚的射频接收地引脚相邻。
根据第一方面，在一种可能的实现方式中，第一绑定线与第三绑定线之间的距离大于或者等于30um并且小于或者等于100um，第三绑定线的打线弧高等于第一绑定线的打线弧高；
第一绑定线的长度小于或者等于第三绑定线、第四绑定线的长度。
根据第一方面，在一种可能的实现方式中，芯片内设置有滤波电容，滤波电容与芯片的射频发射地引脚与芯片的射频发射引脚连接。
本申请的实施例的第二方面提供了一种QFN封装结构，包括基板、EPAD焊接区、芯片和QFN封装引脚，EPAD焊接区设置于基板的表面，芯片设置于EPAD焊接区的表面；
QFN封装引脚围绕EPAD焊接区并且设置于基板的表面；QFN封装引脚用于与QFN封装结构的外部的器件连接；QFN封装引脚与芯片连接；
芯片设置于EPAD焊接区的非中心位置的表面；
芯片的射频收发引脚通过至少三根第一绑定线连接至QFN封装引脚的射频收发引脚。
根据第二方面，在一种可能的实现方式中，第一绑定线的打线弧高大于或者等于70um并且小于或者等于80um。
根据第二方面，在一种可能的实现方式中，芯片的射频发射地引脚通过第三绑定线连接至QFN封装引脚的射频发射地引脚，芯片的射频接收地引脚通过第四绑定线连接至QFN封装引脚的射频接收地引脚；
芯片的射频收发引脚分别与芯片的射频发射地引脚、芯片的射频接收地引脚相邻；
QFN封装引脚的射频收发引脚与QFN封装引脚的射频发射地引脚、QFN封装引脚的射频接收地引脚相邻。
根据第二方面，在一种可能的实现方式中，第一绑定线与第三绑定线之间的距离大于或者等于30um并且小于或者等于100um，第三绑定线的打线弧高等于第一绑定线的打线弧高；第一绑定线的长度小于或者等于第三绑定线、第四绑定线的长度。
根据第二方面，在一种可能的实现方式中，芯片内设置有滤波电容，滤波电容与芯片的射频发射地引脚与芯片的射频收发引脚连接。
本申请的实施例的第三方面提供了一种射频收发模组结构，包括天线、匹配网络电路、第一电感和第一方面中任一项的QFN封装结构，天线与匹配网络电路连接，匹配网络电路与QFN封装引脚的射频发射引脚连接；第一电感分别连接匹配网络电路与QFN封装引脚的射频接收引脚连接。
根据第三方面，在一种可能的实现方式中，匹配网络电路包括第一电容、第二电容、第三电容以及第二电感；
天线与第一电容的第一端连接；
第一电容的第二端分别连接至第二电容的第一端与第二电感的第一端；
第二电容的第二端接地；
第二电感的第二端分别连接第三电容的第一端、QFN封装引脚的射频发射引脚以及第一电感；
第三电容的第二端接地。
本申请的实施例的第四方面提供了一种射频收发模组结构，包括天线、匹配网络电路与第二方面中任一项的QFN封装结构，天线与匹配网络电路连接，匹配网络电路与QFN封装引脚的射频收发引脚连接。
根据第四方面，在一种可能的实现方式中，匹配网络电路包括第一电容、第二电容、第三电容以及第二电感；
天线与第一电容的第一端连接；
第一电容的第二端分别连接至第二电容的第一端与第二电感的第一端；
第二电容的第二端接地；
第二电感的第二端分别连接第三电容的第一端与QFN封装引脚的射频收发引脚；
第三电容的第二端接地。
本申请的实施例的第五方面提供了一种电子设备，包括外壳和第三方面和第四方面中任一项的射频收发模组结构，射频收发模组结构设置于外壳内。
与现有技术相比，本申请实施例的有益效果在于，芯片的射频发射引脚通过至少三根第一绑定线连接至所述QFN封装引脚的射频发射引脚，使得第一绑定线与EPAD焊接区的寄生电容较大，从而增强对谐波的滤波作用，从而减少谐波对外的辐射，成本较低的改善了辐射超标的问题。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一三元素匹配网络电路的示意图；
图2为本申请实施例提供的一三元素匹配网络电路的谐波特性的示意图；
图3为本申请实施例提供的一五元素匹配网络电路的示意图；
图4为本申请实施例提供的一QFN封装结构的示意图；
图5为本申请实施例提供的又一QFN封装结构的示意图；
图6为本申请实施例提供的再一QFN封装结构的示意图；
图7为本申请实施例提供的再一QFN封装结构的示意图；
图8为本申请实施例提供的再一QFN封装结构的示意图；
图9为本申请实施例提供的再一QFN封装结构的示意图；
图10为本申请实施例提供的一射频收发模组结构的示意图；
图11为本申请实施例提供的又一射频收发模组结构的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的部分实施例采用举例的方式进行详细的阐述。然而，本领域的普通技术人员可以理解，在各例子中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修 改，也可以实现本申请所要求保护的技术方案。
以蓝牙的辐射法规为例进行说明，表1为全球针对蓝牙模组的辐射法规，不同国家均对2.4GHz以外的谐波的能量有要求，并且该要求日益严苛。
表1：辐射法规
Figure PCTCN2022117396-appb-000001
以BLE(Bluetooth of Low Energy，低功耗蓝牙)芯片为例，目前市面上的BLE芯片的辐射能量容易超标，不容易通过国际标准认证。例如，当蓝牙芯片需要发射15dBm功率时，测试得到的辐射超标20dB。辐射超标是因为BLE芯片本身会因为非线性失真等原因产生带外的干扰，因此容易影响其他设备。简单来说，非线性失真会使得谐波的占比提高，这种现象称之为THD(Total Harmonic Distortion，总谐波失真)。BLE芯片的发射功率增加，谐波能量也会增加，因而导致BLE芯片的谐波辐射超出规定的谐波辐射限制。
图1示意了发射引脚(TX)的一种匹配网络电路以用于实现阻抗匹配，该匹配网络电路还用于对发射能量进行滤波处理，可以采用三元素匹配网络(3elements C-L-C matching network)电路的方案进行阻抗匹配。如图2所示为图1所示的三元素匹配网络电路的谐波特性，可以看出，图1所示的三元素匹配网络电路针对二次及以上谐波的截止深度不太够。截止深度又称之为 阻带抑制度，阻带抑制度是衡量滤波器选择性能好坏的重要指标，该指标越高说明对带外干扰信号抑制的越好。本申请实施例中，匹配网络电路的作用是把芯片的PA(Power Amplifier,功率放大器)的阻抗匹配到和天线(Antenna)一样，因此，匹配网络电路对电感和电容的取值要求较高。在一些实施例中，PA内部可以集成50欧姆的阻抗匹配设计网络，对于一些高功率PA，可以将匹配网络电路设置在集成芯片的外部，以减小芯片面积。高功率PA的输出阻抗例如为10Ω，小功率PA的输出阻抗例如为25Ω，对于高功率PA来说，可以通过π型匹配电路实现50欧姆的阻抗匹配，PA的特性阻抗影响外围匹配电路的值。
下面的实施例通过QFN封装结构形成电容和电感，因此，匹配网络电路对电容和电感的取值要求宽松了很多。下面的实施例通过QFN封装结构形成寄生电容和寄生电感，也可以理解为是在QFN封装结构内形成了低通滤波器以实现对谐波的过滤。下面的实施例通过优化QFN封装结构以引入寄生电容和寄生电感，另外QFN封装结构还可以跟QFN封装结构外部的三元素匹配网络电路组合起来以形成如图3所示的五元素匹配网络(5elements C-L-C matching network)电路的方案，可以提升对谐波的抑制强度，从而降低谐波辐射能量，图3所示的五元素匹配网络电路可以适用于需要发射15dBm功率的蓝牙芯片，本实施例中的芯片可以包括PA，该PA在15dBm的发射功率下的输出阻抗大约为10Ω。如图4所示为图3所示的五元素匹配网络电路的谐波特性，可以看出，滤波器的阶数更多，过渡带(2.4GHz-4.8GHz)的下降速度更快，增益曲线的斜率更大，这样在4.8GHz的时候对谐波的能量可以抑制得更低。
如图5所示的QFN封装(Quad Flat No-leads Package，方形扁平无引脚封装)结构的底视图，包括EPAD(Exposed pad)焊接区51、芯片52和QFN封装引脚53，其中，EPAD焊接区51设置于基板56的表面，芯片52设置于EPAD焊接区51的表面，QFN封装引脚53与芯片52连接，QFN封装引脚53包括射频发射地引脚VSS_TX、射频接收地引脚VSS_RX、射频接收引脚RX和射频发射引脚TX，QFN封装引脚53围绕EPAD焊接区51并且设置于基板56的表面的边缘位置，QFN封装引脚53用于与QFN封装结构的外部的器件电连接，例如，与QFN封装结构外部的匹配网络电路连接，或者QFN封装引脚53还用于与其他芯片连接以实现用户预设的功能。芯片52设置于 EPAD焊接区51的非中心位置的表面，即芯片52设置于偏离EPAD焊接区51的中心位置。如图5所示，相比于QFN封装引脚的其他引脚，芯片52设置于更靠近QFN封装引脚的射频发射引脚TX。EPAD焊接区51可以理解为金属的裸露焊盘，一般来说，EPAD焊接区51的中心与QFN封装结构的中心重合，EPAD焊接区51处于基板56的下方，芯片52处于EPAD焊接区51的下方，EPAD焊接区51的中心与基板56的中心重合，EPAD焊接区可以为设置于QFN封装结构的中心区域的一块铜皮，EPAD焊接区一般用作GND，EPAD焊接区与GND相连，可以用来散热，例如，EPAD焊接区可以连接到外围PCB(Printed Circuit Board，印制电路板)上的GND。芯片52的至少三个射频发射引脚521、522、523分别通过第一绑定(Bounding)线541、542、543连接至QFN封装引脚的射频发射引脚TX。本实施例通过增加第一绑定线的数目，可以减小等效电阻(Equivalent Series Resistance，ESR)，从而可以减小第一绑定线对发射功率形成插损(Insertion Loss)，避免导致芯片的发射功率降低。可以理解的是并联的第一绑定线越多，第一绑定线引入的电阻越小，因此，插损越小。本申请实施例设置了2根以上的射频发射引脚的绑定线，通过并联至少三根第一绑定线来减小插损。
本实施例中，一方面，芯片的射频发射引脚与QFN封装引脚的射频发射引脚之间的第一绑定线的数目设置为至少3根可以增加寄生电容，以增强对谐波的滤波器效果，避免了额外增加滤波器件或增加芯片屏蔽罩，可以低成本的改善辐射超标的问题，同时也避免了增加芯片体积。
另外一方面，绑定线越多，对芯片的射频发射引脚来说，2.4GHz工作频率下的插损越小。一般来说，芯片之外都会存在插损，比如绑定线带来的插损，比如外围PCB走线带来的插损，以及匹配器件用到的电感带来的插损。对于TX而言，因为是芯片发出的干净的特定频率的信号，而且发射功率大，所以关键的是减小通过TX发射的信号的损失。
基于上述实施例公开的内容，本实施例中，如图5所述，QFN封装结构还包括基板56，EPAD焊接区设置于基板的表面，QFN封装引脚设置于基板的表面的边缘。
基于上述实施例公开的内容，本实施例中，第一绑定线的打线弧高大于或者等于50um并且小于100um。TX的寄生电容是第一绑定线和EPAD焊接区51共同形成，类似极板电容原理。如图6所示，第一绑定线542越靠近EPAD 焊接区51，第一绑定线和EPAD焊接区之间形成的寄生电容就越大。因此，图5中第一绑定线542的打线弧高H1设置得尽可能小，使得第一绑定线542尽量靠近EPAD焊接区51，以使得寄生电容尽可能大，以便于更好的过滤谐波。但是H1太小不利于工艺实现，因此，H1设置为大于或者等于50um并且小于100um。例如，H1可以设计为大于或者等于70um并且小于或者等于80um，H1设置为大于或者等于70um并且小于或者等于80um可以增加第一绑定线和EPAD焊接区51之间形成的寄生电容并且便于工艺实现，另外，QFN封装结构的可靠性较好。在工艺允许且不增加成本的情况下，H1尽量取小，H1可以设置为70um。另外，绑定线本身具备寄生电感，TX处的寄生电感由自身绑定线的长度决定，一般情况下，1mm长度的绑定线对应有1nH的寄生电感。因此，可以通过在QFN封装结构内引入寄生电容和寄生电感，并且与QFN封装结构外部的匹配网络电路一起对谐波进行滤波。
基于上述实施例公开的内容，本实施例中，如图5所示，芯片的射频发射地引脚525、526、527分别通过第三绑定线545、546、547连接至QFN封装引脚的射频发射地引脚VSS_TX，芯片的射频接收地引脚528、529、530通过第四绑定线548、549、550连接至QFN封装引脚的射频接收地引脚VSS_RX。根据平行板电容器的电容的计算公式C＝ε*S/d，其中，ε为极板间介质的介电常数，S为极板面积，d为极板间的距离，本实施例中，为了增加第一绑定线与第三绑定线形成的寄生电容和寄生电感，还可以使得第一绑定线与和第三绑定线之间的距离d1尽量小，具体的，第一绑定线542与第三绑定线545之间距离d1小于或者等于100um，并且，第三绑定线的打线弧高等于第一绑定线的打线弧高，使得第一绑定线与和第三绑定线之间的距离d1尽量小。又因为绑定线之间的距离太近不便于工艺实现，因此，请参考图6，第一绑定线542与第三绑定线545之间距离d1可以配置为大于或者等于30um并且小于或者等于100um，例如为50um，以增加第一绑定线与和第三绑定线形成的寄生电容，使得第一绑定线与和第三绑定线形成的寄生电容满足1pF≥C≤7pF，例如为3.6pF。本实施例中，寄生电感的取值满足：1nH≥L≤5nH,例如为2.4nH。本实施例中，为了统一封装工艺，第二绑定线的打线弧高与第四绑定线的打线弧高H2的值可以设置为与H1相等。
基于上述实施例公开的内容，本实施例中，请参考图5，芯片52设置于EPAD焊接区51的非中心位置的表面，具体的，芯片52的射频发射引脚521、 522、523靠近QFN封装引脚的射频发射引脚TX。相较于芯片52的其他引脚，芯片52的射频发射引脚521、522、523与QFN封装引脚的射频发射引脚TX的距离最近，因此，相较于其他绑定线来说，第一绑定线521、522、523的长度小于或者等于其他绑定线的长度，例如，第一绑定线的长度小于或者等于第二绑定线544、第三绑定线545、546、547、第四绑定线548、549、550的长度。芯片设置于所述EPAD焊接区的非中心位置的表面可以使得第一绑定线的长度尽可能短，例如，可以使得QFN封装引脚的射频发射引脚TX正对着芯片52的射频发射引脚。一般情况下，绑定线的长度可以约束寄生电感，比如1mm的绑定线有1nH的寄生电感，绑定线可以引入的寄生电感为2.4nH，另外，绑定线也不是越长越好，因为绑定线越长，自身寄生电阻会影响发射功率插损。本实施例可以采用3mm以内的绑定线长度，第一绑定线的长度可以设置得最小以减小插损。对于射频信号的发射来说，因为是芯片发出的干净的特定频率的信号，而且发射功率大，所以关键的是减小通过TX发射的信号的损失，即减小插损对射频的发射性能尤为重要。
基于上述实施例公开的内容，本实施例中，为了增加接收灵敏度，芯片的射频接收引脚与QFN封装引脚的射频接收引脚仅仅通过一根第二绑定线连接，目的为了通过一根第二绑定线形成较大的寄生电感从而对谐波形成抑制，进而提高芯片接收射频信号时的SNR(SIGNAL-NOISE RATIO，信噪比)。可以理解的是，绑定线的存在会导致寄生电感的产生，电感并联时，总电感量减少，因此只设置一根第二绑定线可以保证寄生电感最大从而对谐波进行抑制。对于射频信号的接收来说，较为关键的参数是SNR，RX的绑定线形成的寄生电感可以抑制2.4G以外的干扰，可以提升SNR，所以本实施例中RX的绑定线的寄生电感可以设置得稍大，因为多组绑定线并联以后电感是成倍减小的，那么就可以不用多组绑定线并联。另外绑定线数量增加也会导致成本增加，所以芯片的射频接收引脚与QFN封装引脚的射频接收引脚可以仅仅通过一根第二绑定线连接。如图5所示，芯片52的射频接收引脚524通过第二绑定线544连接至QFN封装引脚的射频接收引脚RX，第二绑定线的数量为1。本实施例中，芯片的射频接收性能受寄生电感的影响较大，芯片的射频接收性能主要包括接收灵敏度，可以通过引入寄生电感以阻止高频噪声，从而实现在高发射功率时也可以有较高的接收灵敏度。芯片的射频发射性能受寄生电容的影响较大，芯片的射频发射引脚的谐波可以通过寄生电容传输到 芯片的射频发射地引脚。对于射频信号的接收而言，最重要的参数是SNR，在有用信号的功率较小的情况下，如果接收灵敏度较低的话很难被成功接收，例如，接收灵敏度为-99dBm，在这种情况下减小输入信号的噪声是比较关键的，所以针对RX的绑定线，可以增加寄生电感，这样可以抑制2.4GHz以外的干扰，以提高SNR。
基于上述实施例公开的内容，本实施例中，如图5所示，芯片的射频发射地引脚525、526、527和芯片的射频接收地引脚524分别设置在芯片的射频发射引脚521、522、523的两旁，QFN封装引脚的射频发射地引脚VSS_TX和QFN封装引脚的射频接收地引脚RX分别设置在QFN封装引脚的射频发射引脚TX的两旁。芯片的射频发射引脚分别与芯片的射频发射地引脚、芯片的射频接收引脚相邻，芯片的射频接收引脚524与芯片的射频接收地引脚528相邻。QFN封装引脚的射频发射引脚TX分别与QFN封装引脚的射频发射地引脚VSS_TX、QFN封装引脚的射频接收引脚RX相邻。QFN封装引脚的射频接收引脚RX与QFN封装引脚的射频接收地引脚VSS_RX相邻。采用这种引脚的排布方式的话，可以便于通过多根第一绑定线引入的寄生电容将高次谐波从芯片的射频发射引脚导入到芯片的射频发射地引脚，这样高次谐波就不容易传导到QFN封装结构外的射频通路，以减少对外的辐射，从而可以通过各种法规对辐射能量的测试要求。若在芯片的内部设置有连接到TX与VSS_TX的电容C4，例如，C4的大小可以为1～8pF，也可以通过电容C4将高次谐波从芯片的射频发射引脚导入到芯片的射频发射地引脚，这样高次谐波就不容易传导到QFN封装结构外的射频通路，以减少对外的辐射。本实施例中，射频发射引脚的两端设置有射频发射地引脚和射频接收地引脚，射频发射引脚的谐波更容易传导到射频发射地引脚和射频接收地引脚，减少了谐波对外的辐射能量。本实施例通过在TX的上下端用VSS_RX和VSS_TX进行包围，这样谐波能量可以在QFN封装结构内部通过VSS_RX或VSS_TX形成的闭合地回路传导，减少对外的辐射。
基于上述实施例公开的内容，请参考图7，本实施例中，也可以通过在芯片52的内部增加设置于芯片的射频发射引脚521与芯片的射频发射地引脚526之间的滤波电容C4，即在芯片内部加入滤波电容C4，滤波电容C4分别与芯片的射频发射地引脚526、芯片的射频发射引脚521连接，并且，滤波电容C4与芯片和QFN封装引脚的绑定线引入的寄生电感一起形成滤波电路， 对高次谐波有过滤作用。
基于上述实施例公开的内容，本实施例提出另一种QFN封装结构，与前述实施例不同的是，本实施例的QFN封装结构中的芯片的射频接收引脚与芯片的射频发射引脚共用一个引脚，其共用的引脚称之为射频收发引脚。请参考图8所示的QFN封装结构的底视图，包括EPAD焊接区81、芯片82和QFN封装引脚83，芯片82设置于EPAD焊接区81的表面，QFN封装引脚83与芯片82连接，QFN封装引脚83包括射频收发引脚TRX、射频发射地引脚VSS_TX与射频接收地引脚VSS_RX，芯片82设置于EPAD焊接区81的非中心位置的表面。芯片82的射频收发引脚821、822、823分别通过至少三根第一绑定线841、842、843连接至QFN封装引脚的射频收发引脚TRX。QFN封装结构还包括基板86，EPAD焊接区81设置于基板86的表面，QFN封装引脚83围绕EPAD焊接区81并且设置于基板86的表面的边缘，QFN封装引脚83用于与QFN封装结构的外部的器件连接。
基于上述实施例公开的内容，本实施例中，请参考图9，第一绑定线的打线弧高H1大于或者等于50um并且小于100um。TRX的寄生电容是第一绑定线和EPAD焊接区51共同形成，类似极板电容原理。如图9所示，第一绑定线821越靠近EPAD焊接区81，第一绑定线821和EPAD焊接区81之间形成的寄生电容就越大。因此，图9中第一绑定线821的打线弧高H1设置得尽可能小，使得第一绑定线821尽量靠近EPAD焊接区81，但是H1太小不利于工艺实现，因此，H1设置为大于或者等于50um并且小于100um。例如，H1可以设计为大于或者等于70um并且小于或者等于80um。H1设置为大于或者等于70um并且小于或者等于80um可以增加绑定线和EPAD焊接区81之间形成的寄生电容并且便于工艺实现，另外，QFN封装结构的可靠性较好。在工艺允许且不增加成本的情况下，H1尽量取小，H1可以设置为70um。另外，绑定线本身具备寄生电感，TRX处的寄生电感由自身绑定线的长度决定，比如一般情况下1mm长度的绑定线对应有1nH的寄生电感。因此，可以通过在QFN封装结构内引入寄生电容和寄生电感，并且可以与QFN封装结构外部的匹配网络电路一起对谐波进行滤波。
基于上述实施例公开的内容，本实施例中，请参考图8，芯片的射频发射地引脚825、826、827分别通过第三绑定线845、846、847连接至QFN封装引脚的射频发射地引脚VSS_TX，芯片的射频接收地引脚828、829、830分 别通过第四绑定线848、849、850连接至QFN封装引脚的射频接收地引脚VSS_RX。芯片的射频收发引脚分别与芯片的射频发射地引脚、芯片的射频接收地引脚相邻，QFN封装引脚的射频收发引脚TRX分别与QFN封装引脚的射频发射地引脚VSS_TX、QFN封装引脚的射频接收地引脚VSS_RX相邻。本实施例中，射频收发引脚的两端设置有射频发射地引脚和射频接收地引脚，射频收发引脚的谐波更容易传导到射频发射地引脚和射频接收地引脚，减少了谐波对外的辐射能量。本实施例通过在TRX的上下端用VSS_RX和VSS_TX进行包围，这样谐波能量可以通过封装内部的VSS_RX或VSS_TX形成闭合地回路，减少对外的辐射。
基于上述实施例公开的内容，本实施例中，为了增加第一绑定线与第三绑定线形成的寄生电容和寄生电感，还可以使得第一绑定线与和第三绑定线之间的距离d1尽量小，具体的，请参考图9，第一绑定线842与第三绑定线845之间距离d1小于或者等于100um，并且，第三绑定线的打线弧高等于第一绑定线的打线弧高，使得第一绑定线与和第三绑定线之间的距离d1尽量小。又因为绑定线之间的距离太近不便于工艺实现，因此，第一绑定线842与第三绑定线845之间的距离大于或者等于30um并且小于或者等于100um，例如为50um，以增加第一绑定线与和第三绑定线形成的寄生电容，使得第一绑定线与和第三绑定线形成的寄生电容满足1pF≥C≤7pF，例如为3.6pF。第一绑定线841、842、843的长度小于或者等于其他绑定线的长度，例如，第一绑定线841、842、843的长度小于或者等于第三绑定线845、846、847、第四绑定线848、849、850的长度。本实施例中，为了统一封装工艺，第四绑定线的打线弧高H2的值可以设置为与H1相等。
另外，本实施例中，也可以通过在芯片82的内部增加设置于芯片的射频收发引脚822与芯片的射频发射地引脚825之间的滤波电容C4，即在芯片内部加入滤波电容C4，滤波电容C4的两端分别与芯片的射频发射地引脚825、芯片的射频收发引脚822连接，并且，滤波电容C4与芯片和QFN封装引脚的绑定线引入的寄生电感一起形成滤波电路，对高次谐波有过滤作用。
本申请实施例提出了封装级的解决方案，可以应用于蓝牙芯片中，能够更好的解决辐射超标的问题，以支持更高的发射功率，本申请实施例的方案也可以应用于物联网领域需要射频收发的应用场景。
基于上述实施例公开的内容，本实施例提出射频收发模组结构，如图10 所示，包括QFN封装结构101、天线102、匹配网络电路103和第一电感L1，天线102与匹配网络电路103连接，匹配网络电路103与QFN封装引脚连接，QFN封装引脚的射频发射引脚TX与QFN封装引脚的射频接收引脚RX通过第一电感L1连接。本实施例中的QFN封装结构与前述实施例相同或者近似，可以参考前述实施例中的QFN封装结构，因此，此处对QFN封装结构101不再赘述。QFN封装结构形成的寄生电容和寄生电感与QFN封装结构外部的匹配网络电路相结合，形成了多阶滤波电路，可以通过加大滤波电路的阶数，提高对谐波的抑制效果，从而降低谐波能量辐射强度。在QFN封装结构内，TX的绑定线设置在VSS_RX的绑定线与VSS_TX的绑定线之间，可以理解为TX的绑定线被二者包围。对于射频收发模组结构的QFN封装结构之外的走线，连接TX的走线设置在连接VSS_RX的走线与连接VSS_TX的走线之间，可以理解为连接TX的走线被二者包围，这样可以减小TX谐波对外的辐射，因为连接TX的走线被连接VSS_RX的走线与连接VSS_TX的走线包围以后，其能量更为集中，不会发散。
基于上述实施例公开的内容，本实施例中，如图10所示，匹配网络电路103包括第一电容C1、第二电容C2、第三电容C3以及第二电感L2，其中，天线102与第一电容C1的第一端连接，第一电容C 1的第二端分别连接至第二电容C 2的第一端与第二电感L2的第一端，第二电容C2的第二端接地，第二电感L2的第二端分别连接第三电容C3的第一端、QFN封装引脚的射频发射引脚以及第一电感L1，第三电容C3的第二端接地。本实施例中，QFN封装结构101外部的3元素匹配网络电路可以形成2阶低通滤波器，QFN封装结构形成的寄生电感和寄生电容也可以看成为二阶低通滤波器，因此，图10所示的射频收发模组结构整体形成4阶的低通滤波器，从而对高次谐波有更好的抑制效果。本实施例中，阶数越多，对谐波的抑制效果越好，但是阶数越多，插损也会越多，图10所示的形成4阶的低通滤波器可以在保证对谐波抑制效果的同时将插损控制在一定限度内。
基于上述实施例公开的内容，本实施例提出另一种射频收发模组结构，如图11所示，包括QFN封装结构111、天线112和匹配网络电路113，天线112与匹配网络电路113连接，匹配网络电路103与QFN封装引脚的射频收发引脚TRX连接。本实施例中的QFN封装结构与前述实施例相同或者近似，可以参考前述实施例中的QFN封装结构，本实施例中的QFN封装结构111 中的射频发射引脚和射频接收引脚共用同一个射频收发引脚，此处对QFN封装结构111不再赘述。QFN封装结构形成的寄生电容和寄生电感与QFN封装结构外部的匹配网络电路相结合，形成了多阶滤波电路，可以通过加大滤波电路的阶数，提高对谐波的抑制效果，从而降低谐波能量辐射强度。
基于上述实施例公开的内容，本实施例中，如图11所示，匹配网络电路113包括第一电容C1、第二电容C2、第三电容C3以及第二电感L2，其中，天线112与第一电容C1的第一端连接，第一电容C1的第二端分别连接至第二电容C2的第一端与第二电感L2的第一端，第二电容C2的第二端接地，第二电感L2的第二端分别连接第三电容C3的第一端与QFN封装引脚的射频收发引脚，第三电容C3的第二端接地。本实施例中，QFN封装结构101外部的3元素匹配网络电路可以形成2阶低通滤波器，QFN封装结构形成的寄生电感和寄生电容也可以看成为二阶低通滤波器，因此，图11所示的射频收发模组结构整体形成4阶的低通滤波器，从而对高次谐波有更好的抑制效果。本实施例中，阶数越多，对谐波的抑制效果越好，但是阶数越多，插损也会越多，图11所示的形成4阶的低通滤波器可以在保证对谐波抑制效果的同时将插损控制在一定限度内。
本实施例提供的电子设备包括前述实施例中的任意一种射频收发模组结构，还包括一个外壳，外壳还设置有屏幕，射频收发模组结构设置于所述外壳内。本申请实施例提供的QFN封装结构的具体实现方式及有益效果上述参见上述实施例，此处不再赘述。
应理解，在本申请实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
另外，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和 方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种QFN封装结构，其特征在于，包括基板、EPAD焊接区、芯片和QFN封装引脚，所述EPAD焊接区设置于所述基板的表面，所述芯片设置于所述EPAD焊接区的表面；
    所述QFN封装引脚围绕所述EPAD焊接区并且设置于所述基板的表面；所述QFN封装引脚用于与所述QFN封装结构的外部的器件连接；所述QFN封装引脚与所述芯片连接；
    所述芯片的射频发射引脚通过至少三根第一绑定线连接至所述QFN封装引脚的射频发射引脚。
  2. 根据权利要求1所述的QFN封装结构，其特征在于，所述芯片的射频接收引脚通过第二绑定线连接至所述QFN封装引脚的射频接收引脚；
    所述第一绑定线的长度小于或者等于所述第二绑定线的长度。
  3. 根据权利要求2所述的QFN封装结构，其特征在于，所述第二绑定线的数量为1。
  4. 根据权利要求1所述的QFN封装结构，其特征在于，所述第一绑定线的打线弧高大于或者等于70um并且小于或者等于80um，所述第一绑定线的长度小于或者等于所述第二绑定线的长度。
  5. 根据权利要求1至4中任一项所述的QFN封装结构，其特征在于，所述芯片设置于所述EPAD焊接区的非中心位置的表面。
  6. 根据权利要求1至4中任一项所述的QFN封装结构，其特征在于，所述芯片的射频发射地引脚通过第三绑定线连接至所述QFN封装引脚的射频发射地引脚，所述芯片的射频接收地引脚通过第四绑定线连接至所述QFN封装引脚的射频接收地引脚；
    所述芯片的射频发射引脚分别与所述芯片的射频发射地引脚、所述芯片的射频接收引脚相邻；所述芯片的射频接收引脚与所述芯片的射频接收地引脚相邻；
    所述QFN封装引脚的射频发射引脚分别与所述QFN封装引脚的射频发射地引脚、所述芯片的射频接收引脚相邻；所述QFN封装引脚的射频接收引脚与所述QFN封装引脚的射频接收地引脚相邻。
  7. 根据权利要求6所述的QFN封装结构，其特征在于，所述第一绑定 线与所述第三绑定线之间的距离大于或者等于30um并且小于或者等于100um，所述第三绑定线的打线弧高等于所述第一绑定线的打线弧高；
    所述第一绑定线的长度小于或者等于所述第三绑定线、所述第四绑定线的长度。
  8. 根据权利要求6所述的QFN封装结构，其特征在于，所述芯片内设置有滤波电容，所述滤波电容与所述芯片的射频发射地引脚与所述芯片的射频发射引脚连接。
  9. 一种QFN封装结构，其特征在于，包括基板、EPAD焊接区、芯片和QFN封装引脚，所述EPAD焊接区设置于所述基板的表面，所述芯片设置于所述EPAD焊接区的表面；
    所述QFN封装引脚围绕所述EPAD焊接区并且设置于所述基板的表面；所述QFN封装引脚用于与所述QFN封装结构的外部的器件连接；所述QFN封装引脚与所述芯片连接；
    所述芯片的射频收发引脚通过至少三根第一绑定线连接至所述QFN封装引脚的射频收发引脚。
  10. 根据权利要求9所述的QFN封装结构，其特征在于，所述第一绑定线的打线弧高大于或者等于70um并且小于或者等于80um。
  11. 根据权利要求9所述的QFN封装结构，其特征在于，所述芯片设置于所述EPAD焊接区的非中心位置的表面。
  12. 根据权利要求9至11中任一项所述的QFN封装结构，其特征在于，所述芯片的射频发射地引脚通过第三绑定线连接至所述QFN封装引脚的射频发射地引脚，所述芯片的射频接收地引脚通过第四绑定线连接至所述QFN封装引脚的射频接收地引脚；
    所述芯片的射频收发引脚分别与所述芯片的射频发射地引脚、所述芯片的射频接收地引脚相邻；
    所述QFN封装引脚的射频收发引脚与所述QFN封装引脚的射频发射地引脚、所述QFN封装引脚的射频接收地引脚相邻。
  13. 根据权利要求12所述的QFN封装结构，其特征在于，所述第一绑定线与所述第三绑定线之间的距离大于或者等于30um并且小于或者等于100um，所述第三绑定线的打线弧高等于所述第一绑定线的打线弧高；所述第一绑定线的长度小于或者等于所述第三绑定线、所述第四绑定线的长度。
  14. 根据权利要求12所述的QFN封装结构，其特征在于，所述芯片内设置有滤波电容，所述滤波电容与所述芯片的射频发射地引脚与所述芯片的射频收发引脚连接。
  15. 一种射频收发模组结构，其特征在于，包括天线、匹配网络电路、第一电感和权利要求1至8中任一项所述的QFN封装结构，所述天线与所述匹配网络电路连接，所述匹配网络电路与所述QFN封装引脚的射频发射引脚连接；所述第一电感分别连接所述匹配网络电路与所述QFN封装引脚的射频接收引脚连接。
  16. 根据权利要求15所述的射频收发模组结构，其特征在于，所述匹配网络电路包括第一电容、第二电容、第三电容以及第二电感；
    所述天线与所述第一电容的第一端连接；
    所述第一电容的第二端分别连接至所述第二电容的第一端与所述第二电感的第一端；
    所述第二电容的第二端接地；
    所述第二电感的第二端分别连接所述第三电容的第一端、所述QFN封装引脚的射频发射引脚以及所述第一电感；所述第三电容的第二端接地。
  17. 一种射频收发模组结构，其特征在于，包括天线、匹配网络电路与权利要求9至14中任一项所述的QFN封装结构，所述天线与所述匹配网络电路连接，所述匹配网络电路与所述QFN封装引脚的射频收发引脚连接。
  18. 根据权利要求17所述的射频收发模组结构，其特征在于，所述匹配网络电路包括第一电容、第二电容、第三电容以及第二电感；
    所述天线与所述第一电容的第一端连接；
    所述第一电容的第二端分别连接至所述第二电容的第一端与所述第二电感的第一端；
    所述第二电容的第二端接地；
    所述第二电感的第二端分别连接所述第三电容的第一端与所述QFN封装引脚的射频收发引脚；
    所述第三电容的第二端接地。
  19. 一种电子设备，其特征在于，包括外壳和权利要求15至18中任一项所述的射频收发模组结构，所述射频收发模组结构设置于所述外壳内。
PCT/CN2022/117396 2022-09-06 2022-09-06 一种qfn封装结构、射频收发模组结构及电子设备 Ceased WO2024050705A1 (zh)

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CN202223330170.5U CN219322393U (zh) 2022-09-06 2022-12-09 Qfn封装结构和射频收发模组结构

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US20040104456A1 (en) * 2002-11-12 2004-06-03 Duffy Thomas P. Methods and apparatus for reducing parasitic inductance using inter-digitated bond, wires
US20070158797A1 (en) * 2006-01-11 2007-07-12 Sheng-Yuan Lee Circuit board and electronic assembly
CN102709264A (zh) * 2012-05-16 2012-10-03 南京国博电子有限公司 一种射频收发前端模块及其制备方法
US9252767B1 (en) * 2010-06-28 2016-02-02 Hittite Microwave Corporation Integrated switch module
CN210578437U (zh) * 2019-12-13 2020-05-19 苏州华太电子技术有限公司 低成本高集成度的射频芯片封装结构及射频功率放大器

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040104456A1 (en) * 2002-11-12 2004-06-03 Duffy Thomas P. Methods and apparatus for reducing parasitic inductance using inter-digitated bond, wires
US20070158797A1 (en) * 2006-01-11 2007-07-12 Sheng-Yuan Lee Circuit board and electronic assembly
US9252767B1 (en) * 2010-06-28 2016-02-02 Hittite Microwave Corporation Integrated switch module
CN102709264A (zh) * 2012-05-16 2012-10-03 南京国博电子有限公司 一种射频收发前端模块及其制备方法
CN210578437U (zh) * 2019-12-13 2020-05-19 苏州华太电子技术有限公司 低成本高集成度的射频芯片封装结构及射频功率放大器

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