WO2024049769A3 - Patterned release layers, and methods of making and using them in device manufacturing - Google Patents

Patterned release layers, and methods of making and using them in device manufacturing Download PDF

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Publication number
WO2024049769A3
WO2024049769A3 PCT/US2023/031304 US2023031304W WO2024049769A3 WO 2024049769 A3 WO2024049769 A3 WO 2024049769A3 US 2023031304 W US2023031304 W US 2023031304W WO 2024049769 A3 WO2024049769 A3 WO 2024049769A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
making
device manufacturing
patterned release
release layers
Prior art date
Application number
PCT/US2023/031304
Other languages
French (fr)
Other versions
WO2024049769A2 (en
Inventor
Matthew Robinson
Original Assignee
Terecircuits Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Terecircuits Corporation filed Critical Terecircuits Corporation
Publication of WO2024049769A2 publication Critical patent/WO2024049769A2/en
Publication of WO2024049769A3 publication Critical patent/WO2024049769A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Laminated Bodies (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

Patterned assemblies with a patterned release layer, methods of making, and methods of using are described herein. The assemblies with a patterned release layer may include donor plates, wafers, components (e.g. microelectronic components), and combinations thereof. The patterned assemblies may be used for transferring components.
PCT/US2023/031304 2022-08-30 2023-08-28 Patterned release layers, and methods of making and using them in device manufacturing WO2024049769A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202263373900P 2022-08-30 2022-08-30
US63/373,900 2022-08-30

Publications (2)

Publication Number Publication Date
WO2024049769A2 WO2024049769A2 (en) 2024-03-07
WO2024049769A3 true WO2024049769A3 (en) 2024-04-18

Family

ID=88188873

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2023/031304 WO2024049769A2 (en) 2022-08-30 2023-08-28 Patterned release layers, and methods of making and using them in device manufacturing

Country Status (1)

Country Link
WO (1) WO2024049769A2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190189496A1 (en) * 2017-12-19 2019-06-20 Pixeled Display Co., Ltd. Carrier structure and micro device structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190189496A1 (en) * 2017-12-19 2019-06-20 Pixeled Display Co., Ltd. Carrier structure and micro device structure

Also Published As

Publication number Publication date
WO2024049769A2 (en) 2024-03-07

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