WO2024045436A1 - 图形化高层次综合电路性能分析方法、系统、装置及介质 - Google Patents

图形化高层次综合电路性能分析方法、系统、装置及介质 Download PDF

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WO2024045436A1
WO2024045436A1 PCT/CN2022/141008 CN2022141008W WO2024045436A1 WO 2024045436 A1 WO2024045436 A1 WO 2024045436A1 CN 2022141008 W CN2022141008 W CN 2022141008W WO 2024045436 A1 WO2024045436 A1 WO 2024045436A1
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hardware
simulation
level
simulation model
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French (fr)
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陈弟虎
黄铚聪
黄羽霄
郑智杰
王自鑫
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中山大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/337—Design optimisation

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  • the present invention relates to the field of circuit simulation technology, in particular to graphical high-level integrated circuit performance analysis methods, systems, devices and media.
  • High-level synthesis is to automatically convert behavioral-level functions described in high-level languages into hardware description languages.
  • High-level languages refer to programming languages with a high degree of abstraction. Common high-level languages include C++, C, Python, etc.
  • Hardware description languages generally refer to Verilog HDL, VHDL, SystemVerilog, etc., which are characterized by being able to be directly used to analyze hardware. Circuit modeling. During the conversion process, in addition to using hardware circuits to implement corresponding behavioral-level functions, designers often also need to care about the timing performance of the final result, such as the delay of each module in the circuit, the arrangement of the pipeline, and the overall hardware design. throughput, etc.
  • the purpose of embodiments of the present invention is to provide a graphical high-level integrated circuit performance analysis method to improve the efficiency and stability of hardware development; in addition, the embodiments Systems, devices and storage media capable of implementing this method are also provided.
  • Co-simulation is performed according to the software description code and the hardware simulation description code, and the performance data of the simulation results and the simulation process are visually displayed.
  • the steps of obtaining the target circuit requirements and determining the test stimulus program code and hardware module code according to the target circuit requirements include:
  • function encapsulation is performed through keywords and control statements in high-level programming languages to obtain the hardware module code.
  • the step of compiling and converting the hardware module code to obtain a hardware description code, and performing forward compilation according to the hardware description code to obtain a register conversion level code includes:
  • the data flow and the control structure are integrated to obtain the register conversion level code.
  • the steps of inserting sampling code into the hardware simulation model, performing simulation compilation on the hardware simulation model after inserting the sampling code, and obtaining the hardware simulation description code include:
  • the starting position of the sampling function is determined, and the sampling function is inserted into the hardware simulation model according to the starting position.
  • inserting sampling code into the hardware simulation model, performing simulation compilation on the hardware simulation model after inserting the sampling code, and obtaining the hardware simulation description code also includes the following steps: one:
  • performing co-simulation based on the software description code and the hardware simulation description code to visually display the performance data of the simulation results and the simulation process includes at least one of the following steps: one:
  • the timing relationship is determined based on the delay overlap between the hardware modules, and the timing relationship is visually displayed.
  • performing collaborative simulation according to the software description code and the hardware simulation description code, and visually displaying the performance data of the simulation results and the simulation process also includes:
  • the graphical high-level comprehensive circuit performance analysis system includes:
  • a demand acquisition unit used to obtain the target circuit demand, and determine the test stimulus program code and hardware module code according to the target circuit demand;
  • a software coding unit used to compile and convert the test stimulus program code to obtain a software description code
  • a forward encoding unit used to compile and convert the hardware module code to obtain a hardware description code, and perform forward compilation according to the hardware description code to obtain a register conversion level code;
  • a reverse compilation unit used to reverse compile according to the register conversion level code to obtain a hardware simulation model
  • a model building unit configured to insert sampling code into the hardware simulation model, perform simulation compilation on the hardware simulation model after inserting the sampling code, and obtain a hardware simulation description code
  • a visualization unit is configured to perform collaborative simulation according to the software description code and the hardware simulation description code, and visually display the performance data of the simulation results and the simulation process.
  • the technical solution of this application also provides a graphical high-level comprehensive circuit performance analysis device, which includes:
  • At least one memory for storing at least one program
  • the at least one processor When the at least one program is executed by the at least one processor, the at least one processor is caused to run the graphical high-level integrated circuit performance analysis method as described in any one of the first aspects.
  • the technical solution of the present application also provides a storage medium in which a processor-executable program is stored. When executed by the processor, the processor-executable program is used to perform any one of the first aspects.
  • the graphical high-level integrated circuit performance analysis method is used to perform any one of the first aspects.
  • the technical solution of this application provides a graphical high-level comprehensive circuit performance analysis method, system, equipment and media; the method is based on the requirements of the target circuit to construct the test stimulus program code and hardware module code, and then compile them separately through compilation tools, and target the hardware
  • the module code part is forward compiled to obtain the register conversion level code, and the RTL code is reverse compiled to obtain the hardware simulation model.
  • the sampling code is inserted into the value model through code instrumentation, and finally through hardware simulation Description code and software description code are simulated, and the simulation results are visualized; the solution is converted between codes and simulated based on the code description of hardware and software, which greatly reduces the cost consumption caused by manual analysis.
  • Improve the design efficiency of high-level synthesis based on the characteristics of the simulation model.
  • Figure 1 is a step flow chart of the graphical high-level comprehensive circuit performance analysis method provided in the technical solution of this application;
  • Figure 2 is a step flow chart of another graphical high-level comprehensive circuit performance analysis method provided in the technical solution of this application;
  • Figure 3 is a schematic diagram of the performance data graphical interface in the technical solution of this application.
  • Figure 4 is a flow chart of the steps of graphical performance analysis based on the SHANG high-level synthesis tool in the technical solution of this application.
  • High-level synthesis refers to the process of automatically converting logical structures described in high-level languages into circuit models described in low-level abstract languages. HLS tools can reduce hardware engineers' design time while also allowing software engineers to complete hardware design.
  • LLVM Low Level Virtual Machine
  • LLVM Low Level Virtual Machine
  • LLVM needs to be supported by various functional modules. Both clang and lld can be regarded as components of LLVM. According to the characteristics of their framework, you can develop your own modules based on the functions provided by LLVM and integrate them in On the LLVM system, add its functions, or use LLVM to support the underlying implementation during the development of software tools.
  • the embodiment of the present invention first proposes a graphical high-level comprehensive circuit performance analysis method, which includes steps S100-S600:
  • the target circuit refers to the hardware circuit that requires high-level comprehensive performance analysis.
  • the core code of a double-precision floating-point adder can be generated through a general programming language, such as C language, as the hardware simulation model code in the embodiment; at the same time, a test program is generated, which includes the test Incentive program code.
  • step S100 of the embodiment method obtains target circuit requirements, and determining the test stimulus program code and hardware module code according to the target circuit requirements may include steps S110-S120:
  • test stimulus program code and hardware module code based on high-level languages, such as C, C++, and Python.
  • the generation process of the hardware module code is to model the hardware functions that the target circuit needs to implement.
  • the modeling Keywords and control statements provided by high-level languages can be used in the process.
  • the top-level hardware module is encapsulated in the form of a function.
  • the input and output of the function correspond to the input and output of the hardware module.
  • the designed test stimulus program code needs to include the following steps: generate test vectors, call the hardware module and send test vectors, and verify whether the returned results are correct.
  • test stimulus program code is generated through step S100, it is compiled through the front-end compilation tool of LLVM; the compilation and conversion process in the embodiment mainly relies on the automatic implementation of the tool.
  • the intermediate representation (IR) of the test stimulus program code part is obtained; in the embodiment, the LLVM-IR description form uses the underlying instruction set (LLVM-specific assembly instruction set), which can keep the code form relatively simple. Under the premise, high-level information is provided for subsequent analysis and optimization.
  • the process of converting from high-level language to Register Transfer Level (RTL) code is called forward compilation.
  • RTL Register Transfer Level
  • the embodiment compiles through the front-end compilation tool of LLVM, and generates a hardware part intermediate representation IR for the input hardware module code. In the middle of getting the hardware part, it means that the IR gets the RTL code through the conversion of the compiled language.
  • simulation is performed based on the RTL code obtained in step S300; first of all, the embodiment requires decompiling the RTL code, with the purpose of obtaining a hardware simulation model described in a high-level language. More specifically, in embodiments, reverse compilation can be performed through hardware code compilation tools, such as Verilator, v2c, etc.; for example, RTL code can be compiled back to the C++ model through hardware code compilation tools.
  • hardware code compilation tools such as Verilator, v2c, etc.
  • the code in the simulation model is instrumented to track the operation of each module during the simulation process; wherein, code instrumentation refers to Add additional event sampling code to the program.
  • S600 Perform collaborative simulation according to the software description code and the hardware simulation description code, and visually display the performance data and simulation process of the simulation results;
  • the hardware simulation model code that completes instrumentation is compiled by LLVM of the simulation tool to generate the IR file of the hardware simulation model, and is sent to the software and hardware co-simulation platform together with the software IR for simulation;
  • the programs that need to be set up in the software and hardware co-simulation platform include: simulation process control program, performance data collection program, simulation result display program and performance data visualization program.
  • the simulation process control program is written based on TCL script, and its main functions include: controlling the environment variables of the simulator, declaring input files, declaring output files, jumping to sub-project directories, and controlling the simulation process.
  • the simulation result display program is implemented based on QT. Its main functions include: printing the execution status of each step in the simulation process in the result window, and displaying the results output in the test stimulus program at the same time.
  • step S300 of the embodiment method the hardware module code is compiled and converted to obtain a hardware description code, and forward compilation is performed according to the hardware description code to obtain a register conversion level code, which may include step S310 and step S320:
  • the LLVM IR file of the hardware module code needs to first go through a high-level synthesis optimization process.
  • the high-level synthesis tool creates the corresponding data flow and control structure based on the results of the scheduling and resource binding process, and finally the synthesis is described.
  • RTL code for hardware circuit is described.
  • step S500 in the embodiment method is to insert sampling code into the hardware simulation model, perform simulation compilation on the hardware simulation model after inserting the sampling code, and obtain the hardware simulation description code, which may include steps S510- S520:
  • S510 Determine the high-level programming language of the hardware module code, and determine the sampling function declared in the high-level programming language according to the writing format of the high-level programming language;
  • S520 Determine the starting position of the sampling function, and insert the sampling function into the hardware simulation model according to the starting position;
  • the process of code instrumentation is: read the C++ code of the hardware module, determine all the functions declared in the code according to the writing format of the function in C++; determine the starting position of each function according to the key characters, And insert the code block of the event sampling function at this location; search the entire code file and modify each function; save the modified code to the hard disk.
  • step S500 of the embodiment method is to insert sampling code into the hardware simulation model, perform simulation compilation on the hardware simulation model after inserting the sampling code, and obtain the hardware simulation description code, which may also include step S530. -S550:
  • the instrumentation of the code will not affect the specific behavioral functions of the hardware simulation model.
  • the content recorded by the event sampling function includes but is not limited to the following:
  • the hierarchical structure of hardware circuit modules is very critical to performance analysis.
  • the data dependencies within the circuit can be analyzed, which is conducive to building a suitable pipeline and conducting targeted analysis of the circuit. optimization.
  • Types of hardware circuit modules when using high-level synthesis tools to generate hardware modules, many different types of modules will be automatically generated, such as reading data modules, calculation modules, and writing back data modules.
  • Clock cycle count at running time the timing of hardware circuits generally uses the number of clock cycles as the calculation unit. Therefore, when the program calls the current module, it only needs to record the clock cycle at the current running time to determine that the module is on the timeline. The specific location is used for subsequent sequential logic analysis.
  • step S600 in the embodiment method, performing collaborative simulation according to the software description code and the hardware simulation description code, and visually displaying the performance data of the simulation results and the simulation process may include steps S610- S630:
  • the embodiment in order to facilitate developers to analyze the hardware involved, the embodiment also provides a presentation method based on a graphical interface, the schematic diagram of which is shown in Figure 3 .
  • the graphical interface is implemented based on QT's QtableWidget.
  • the first row in the plug-in is set to the number of clock cycles, such as C0, C1...Cn.
  • the first column on the left is used to present the hierarchical structure of the module.
  • the plug-in The main part is used to present the execution of each module in different clock cycles.
  • the content that can be displayed in the graphical interface 301 includes but is not limited to:
  • Timeline 302 In the graphical interface of performance data, the basic unit of the timeline is one clock cycle. Furthermore, the timeline does not need to show all clock cycles executed during the simulation. Because the visualization results only show developers the front-to-back delay relationship between hardware modules, the timeline only needs to meet a complete data transfer process.
  • Program hierarchy 303 In the hardware code generated by high-level synthesis, a large module is often spliced into several small modules. Developers need to understand the module hierarchy of the hardware as much as possible in order to perform targeted optimization of the circuit. Furthermore, in the graphical interface, the hierarchical structure of modules should be arranged from coarse to fine, and the delay of the upper module is composed of the delay of each lower module.
  • Timing relationship visualization area 304 mainly displays the timing relationship of each module. Furthermore, since parallel execution often exists in hardware circuits, that is, the previous module has not finished executing, but the latter module has started executing, therefore, the delay between modules allows overlap.
  • step S600 in the embodiment method, performing collaborative simulation according to the software description code and the hardware simulation description code, and visually displaying the performance data and simulation process of the simulation results may also include step S640. :
  • the performance data collection program can be a text processing program written based on C. Its main function is to automatically process the log files generated by the event sampling function, and extract the hierarchical structure and structure of each module from it. type, as well as the start time and end time of module operation. After the collection is completed, the performance data is saved in the local hard disk in the form of a text file.
  • the Clang front-end is a C/C++/Objective-C compiler based on LLVM.
  • Shang high-level synthesis tool is a high-level synthesis system developed by the EDA research group of the School of Electronics and Information Engineering at Sun Yat-sen University.
  • Verilator is a cycle-accurate open source simulator supporting Verilog HDL/SystemVerilog.
  • the Verilator compilation tool is used to synthesize the RTL code of the adder circuit into a C++ simulation model.
  • code instrument the hardware simulation model (C++)
  • C++ code instrument the hardware simulation model
  • a front-end compiler of the simulation program is developed based on Clang, and the simulation model code of the instrumented adder is compiled into a hardware simulation model IR.
  • the generated hardware simulation model IR and the test program IR are sent to the software and hardware co-simulation platform for simulation.
  • the simulation platform is built based on Python, which includes a simulation process control program, a performance data collection program, a simulation result display program, and a performance data visualization program.
  • the simulation process control program first further compiles the input IR file into an executable file. It will be checked during the compilation process. If the interface does not match or the compilation error occurs, the designer will be reminded to make modifications.
  • the performance data collection program thread is first started, and then another thread is started to execute the simulation program, and the co-simulation program is gradually executed in the order of clock cycles. During this period, the performance data collection program keeps running and obtains the collected data from the memory.
  • the simulation process control program closes the performance data collection program thread and loads all collected data into the memory to prepare for visualization.
  • the visual interface is built using pyside, and the performance data presentation window is drawn using QT.
  • the execution sequence and delay time of each module in the double-precision floating-point adder are described on the graphical interface.
  • embodiments of the present invention also provide a graphical high-level integrated circuit performance analysis system.
  • the system includes:
  • a demand acquisition unit used to obtain the target circuit demand, and determine the test stimulus program code and hardware module code according to the target circuit demand;
  • a software coding unit used to compile and convert the test stimulus program code to obtain a software description code
  • a forward encoding unit used to compile and convert the hardware module code to obtain a hardware description code, and perform forward compilation according to the hardware description code to obtain a register conversion level code;
  • a reverse compilation unit used to reverse compile according to the register conversion level code to obtain a hardware simulation model
  • a model building unit configured to insert sampling code into the hardware simulation model, perform simulation compilation on the hardware simulation model after inserting the sampling code, and obtain a hardware simulation description code
  • a visualization unit is configured to perform collaborative simulation according to the software description code and the hardware simulation description code, and visually display the performance data of the simulation results and the simulation process.
  • the technical solution of this application also provides a graphical high-level comprehensive circuit performance analysis device; which includes:
  • At least one processor at least one memory, the memory is used to store at least one program; when at least one program is executed by at least one processor, at least one processor runs the graphical high-level integrated circuit performance analysis method as in the first aspect .
  • Embodiments of the present invention also provide a storage medium that stores a corresponding execution program, and the program is executed by the processor to implement the graphical high-level comprehensive circuit performance analysis method in the first aspect.
  • logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered a sequenced list of executable instructions for implementing the logical functions, and may be embodied in any computer-readable medium, For use by, or in combination with, instruction execution systems, devices or devices (such as computer-based systems, systems including processors or other systems that can fetch instructions from and execute instructions from the instruction execution system, device or device) or equipment.

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Abstract

本发明提供的图形化高层次综合电路性能分析方法、系统、装置及介质，方法包括以下步骤：获取目标电路需求，根据目标电路需求确定测试激励程序代码以及硬件模块代码；对测试激励程序代码进行编译转换得到软件描述代码；对硬件模块代码进行编译转换得到硬件描述代码，根据硬件描述代码进行正向编译得到寄存器转换级代码；根据寄存器转换级代码进行反向编译，得到硬件仿真模型；进行代码插桩，对插桩后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码；进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示；极大地减少了人为分析所带来的成本消耗，同时根据仿真模型的特性提高高层次综合的设计效率，可广泛应用于电路仿真技术领域。

Description

图形化高层次综合电路性能分析方法、系统、装置及介质 技术领域
本发明涉及电路仿真技术领域，尤其是图形化高层次综合电路性能分析方法、系统、装置及介质。
背景技术
高层次综合的核心功能是将高级语言描述的行为级功能，自动转换成硬件描述语言。高级语言指的是具有较高的抽象度的编程语言，常见的高级语言包括C++、C、Python等；而硬件描述语言一般指Verilog HDL、VHDL、SystemVerilog等，其特点是能够直接用于对硬件电路建模。在转换的过程中，除了使用硬件电路实现对应的行为级功能之外，设计者往往还需要关心最终结果的时序性能，如电路中各个模块的时延情况、流水线的排列情况、以及整体硬件设计的吞吐量等。
为了确保电路性能达到设计人员的预期，在获得高层次综合生成的硬件代码后，往往需要对电路进行性能分析。传统的性能分析方法一般是人为地对高层次综合产生的硬件代码进行推理和分析。这种方法通常需要设计激励信号，然后搭建仿真平台对代码进行测试，并对仿真产生的接口信号(波形)进行分析。然而，对于电路结构复杂和逻辑门数量较多的电路，人为分析不仅费时费力，而且容易产生遗漏和错误；同时，在硬件设计过程中，当发现某项性能不达标，或电路功能不完备时，往往还需要对高层次代码和硬件电路进行反复调整。
因此，如果只依赖人力对电路进行分析，会导致高层次综合的设计效率非常低，同时极大地增加了人力成本和时间成本。
发明内容
有鉴于此，为至少部分解决上述技术问题或者缺陷之一，本发明实施例的目的在于提供一种图形化高层次综合电路性能分析方法，以提高硬件开发的效率和稳定性；此外，实施例还提供了能够实现这一方法的系统、装置以及存储介质。
一方面，本申请技术方案提供了图形化高层次综合电路性能分析方法，包括以下步骤：
获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码；
对所述测试激励程序代码进行编译转换得到软件描述代码；
对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码；
根据所述寄存器转换级代码进行反向编译，得到硬件仿真模型；
在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码；
根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示。
在本申请方案的一种可行的实施例中，所述获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码这一步骤，包括：
确定所述目标电路需求中的硬件功能需求；
根据所述硬件功能需求，通过高级编程语言中的关键字、控制语句进行函数封装，得到所述硬件模块代码。
在本申请方案的一种可行的实施例中，所述对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码这一步骤，包括：
对所述硬件描述代码进行高层次综合优化，根据优化结果创建数据流和控制结构；
将所述数据流以及所述控制结构进行整合得到所述寄存器转换级代码。
在本申请方案的一种可行的实施例中，所述在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码这一步骤，包括：
确定所述硬件模块代码的高级编程语言，根据所述高级编程语言的书写格式确定所述高级编程语言中所声明的采样函数；
确定所述采样函数的起始位置，根据所述起始位置，将所述采样函数插入至所述硬件仿真模型。
在本申请方案的一种可行的实施例中，所述在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码，还包括以下步骤至少之一：
通过所述采样函数，记录所述硬件仿真模型中硬件模块的层次结构；
通过所述采样函数，记录所述硬件仿真模型中硬件模块的类型；
通过所述采样函数，记录所述硬件仿真模型所对应硬件电路的时钟周期计数。
在本申请方案的一种可行的实施例中，所述根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示，包括以下步骤 至少之一：
根据所述硬件模块之间的前后延时关系构建时间轴，对所述时间轴进行可视化展示；
对所述硬件仿真模型的模块层次结构进行可视化展示；
根据所述硬件模块之间的延时交叠确定时序关系，对所述时序关系进行可视化展示。
在本申请方案的一种可行的实施例中，所述根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示，还包括：
获取所述采样函数产生的日志文件，从所述日志文件中获取所述性能数据，并将所述性能数据进行可视化展示。
另一方面，图形化高层次综合电路性能分析系统，包括：
需求获取单元，用于获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码；
软件编码单元，用于对所述测试激励程序代码进行编译转换得到软件描述代码；
正向编码单元，用于对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码；
反向编译单元，用于根据所述寄存器转换级代码进行反向编译，得到硬件仿真模型；
模型构建单元，用于在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码；
可视化单元，用于根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示。
另一方面，本申请技术方案还提供一种基于图形化高层次综合电路性能分析装置，该装置包括：
至少一个处理器；
至少一个存储器，用于存储至少一个程序；
当所述至少一个程序被所述至少一个处理器执行，使得所述至少一个处理器运行如第一方面中任一项所述的图形化高层次综合电路性能分析方法。
另一方面，本申请技术方案还提供一种存储介质，其中存储有处理器可执行的程序，所述处理器可执行的程序在由处理器执行时用于执行如第一方面中任一项所述的图形化高层次综合电路性能分析方法。
本发明的优点和有益效果将在下面的描述中部分给出，其他部分可以通过本发明的具体实施方式了解得到：
本申请技术方案提供了图形化高层次综合电路性能分析方法、系统、设备以及介质；方法基于目标电路的需求构建得到测试激励程序代码以及硬件模块代码，然后通过编译工具分别进行编译，并针对硬件模块代码部分先后进行正向编译得到寄存器转换级代码，对RTL代码进行反向编译，得到硬件仿真模型，在构建仿真模型的过程中通过代码插桩将采样代码插入值模型中，最后通过硬件仿真描述代码以及软件描述代码进行仿真，并将仿真得到的结果进行可视化；方案通过代码间的转换，并基于硬件以及软件的代码描述进行仿真，极大地减少了人为分析所带来的成本消耗，同时根据仿真模型的特性提高高层次综合的设计效率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请技术方案中所提供的图形化高层次综合电路性能分析方法的步骤流程图；
图2为本申请技术方案中所提供另一种的图形化高层次综合电路性能分析方法的步骤流程图；
图3为本申请技术方案中性能数据图形化界面示意图；
图4为本申请技术方案中基于SHANG高层次综合工具的图形化性能分析的步骤流程图。
具体实施方式
下面详细描述本发明的实施例，实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。对于以下实施例中的步骤编号，其仅为了便于阐述说明而设置，对步骤之间的顺序不做任何限定，实施例中的各步骤的执行顺序均可根据本领域技术人员的理解来进行适应性调整。
首先对本申请技术方案中部分技术名词进行解释：
高层次综合(High-level Synthesis)简称HLS，指的是将高层次语言描述的逻辑结构，自动转换成低抽象级语言描述的电路模型的过程。HLS工具能够减少硬件工程师设计的时间，同时也让软件工程师完成硬件设计。
LLVM(Low Level Virtual Machine)是一个编译器框架。LLVM作为编译器框架，是需要各种功能模块支撑起来的，可以将clang和lld都看作是LLVM的组成部分，根据其框架的 特性，可以基于LLVM提供的功能开发自己的模块，并集成在LLVM系统上，增加它的功能，或者在开发软件工具的过程中，利用LLVM来支撑底层实现。
针对说明书背景中所指出的，在相关技术方案中存在着过度依赖人工分析的方式导致高层次综合的设计效率非常低，同时极大地增加了人力成本和时间成本的问题；首先，在第一方面，如图1所示，本发明实施例首先提出了一种图形化高层次综合电路性能分析方法，方法包括步骤S100-S600：
S100、获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码；
其中，目标电路是指需要进行高层次综合性能分析的硬件电路。具体在实施例中，实施例中可以通过通用程序设计语言，例如C语言生成一个双精度浮点加法器的核心代码作为实施例中的硬件仿真模型代码；同时生成一个测试程序，其中包含了测试激励程序代码。
在一些可行的实施例方式中，实施例方法的步骤S100获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码可以包括步骤S110-S120：
S110、确定所述目标电路需求中的硬件功能需求；
S120、根据所述硬件功能需求，通过高级编程语言中的关键字、控制语句进行函数封装，得到所述硬件模块代码；
具体在实施例中，首先需要基于高级语言，例如C、C++、Python，生成测试激励程序代码和硬件模块代码，其中硬件模块代码的生成过程是对目标电路需要实现的硬件功能建模，建模过程中可以使用高级语言提供的关键字和控制语句，顶层硬件模块以函数的形式进行封装，函数的输入输出对应硬件模块的输入和输出。除此之外，设计的测试激励程序代码需要包括如下步骤：生成测试向量、调用硬件模块并发送测试向量、验证返回的结果是否正确。
S200、对所述测试激励程序代码进行编译转换得到软件描述代码；
如图2所示，具体在实施例中，在通过步骤S100生成得到测试激励程序代码之后，通过LLVM的前端编译工具进行编译；实施例中的编译转换的过程主要依赖于该工具的自动实现，转换完成之后，得到测试激励程序代码部分的中间表示(Intermediate Representation,IR)；实施例中，LLVM-IR描述形式使用了底层的指令集(LLVM专用汇编指令集)，能够在保持代码形式相对简单的前提下，提供高层次信息，用于后续的分析优化。
S300、对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码；
其中，从高级语言转换为寄存器转换级(Register Transfer Level，RTL)代码的过程称为 正向编译。如图2所示，具体在实施例中，与测试激励程序代码编译的过程相类似地，实施例通过LLVM的前端编译工具进行编译，对于输入的硬件模块代码生成硬件部分中间表示IR。在得到硬件部分中间表示IR通过编译语言的转换得到RTL代码。
S400、根据所述寄存器转换级代码进行反向编译，得到硬件仿真模型；
具体在实施例中，根据步骤S300得到的RTL代码进行仿真；首先实施例需要对RTL代码进行反向编译，其目的在于获得使用高级语言描述的硬件仿真模型。更为具体地，实施例中可以通过硬件代码编译工具进行反向编译，例如Verilator、v2c等；例如，可以通过硬件代码编译工具将RTL代码编译回到C++模型。
S500、在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码；
具体在实施例中，在通过步骤S400获取得到仿真模型的高级语言描述后，对仿真模型中的代码进行插桩，用于在仿真过程中跟踪各个模块的运行情况；其中，代码插桩是指在程序中加入额外的事件采样代码。
S600、根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示；
如图2所示，具体在实施例中，完成插桩的硬件仿真模型代码经过仿真工具的LLVM编译，生成硬件仿真模型的IR文件，和软件IR被一起送入软硬件协同仿真平台进行仿真；其中，软硬件协同仿真平台中需要设置的程序包括：仿真流程控制程序、性能数据收集程序、仿真结果显示程序和性能数据可视化程序。实施例中，仿真流程控制程序基于TCL脚本编写，主要功能包括：控制仿真器的环境变量、声明输入文件、声明输出文件、跳转到子工程目录、以及控制仿真的流程。此外，仿真结果显示程序基于QT实现，主要功能包括：在结果窗口中打印仿真过程中每一步的执行情况，同时显示测试激励程序中输出的结果。
在一些可行的实施方式中，实施例方法中步骤S300、对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码，其可以包括步骤S310和步骤S320：
S310、对所述硬件描述代码进行高层次综合优化，根据优化结果创建数据流和控制结构；
S320、将所述数据流以及所述控制结构进行整合得到所述寄存器转换级代码；
具体在实施例中，硬件模块代码的LLVM IR文件需要首先需要经过高层次综合的优化流程，高层次综合工具根据调度和资源绑定流程的结果创建相应的数据流和控制结构，最后综合得到描述硬件电路的RTL代码。
在一些可行的实施方式中，实施例方法中步骤S500、在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码，可以包括步骤S510-S520：
S510、确定所述硬件模块代码的高级编程语言，根据所述高级编程语言的书写格式确定所述高级编程语言中所声明的采样函数；
S520、确定所述采样函数的起始位置，根据所述起始位置，将所述采样函数插入至所述硬件仿真模型；
具体在实施例中，进行代码插桩的过程为：读取硬件模块的C++代码，根据C++中函数的书写格式，确定代码中声明的所有函数；根据关键字符确定每个函数的起始位置，并在该位置插入事件采样函数的代码块；搜索整个代码文件，对每个函数都进行修改；将修改后的代码保存到硬盘。
在一些可行的实施方式中，实施例方法中步骤S500、在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码，还可以包括步骤S530-S550：
S530、通过所述采样函数，记录所述硬件仿真模型中硬件模块的层次结构；
S540、通过所述采样函数，记录所述硬件仿真模型中硬件模块的类型；
S550、通过所述采样函数，记录所述硬件仿真模型所对应硬件电路的时钟周期计数；
具体在实施例中，对代码的插桩不会影响到硬件仿真模型的具体行为功能，事件采样函数所记录的内容包括但不限于如下：
硬件电路模块的层次结构；硬件电路的层次结构对于性能分析非常关键，通过分析每个模块内部的层次结构，能够分析电路内部的数据依赖关系，有利于构建合适的流水线，对电路进行针对性的优化。
硬件电路模块的类型；在使用高层次综合工具生成硬件模块的时候，会自动产生多种不同类型的模块，如读取数据模块、计算模块、写回数据模块。
运行时刻的时钟周期计数；硬件电路的计时一般是以时钟周期数量作为计算单位，因此当程序调用到当前模块的时候，只需要记录下当前运行时刻的时钟周期，就能确定该模块位于时间线的具体位置，用于后续的时序逻辑分析。
在一些可行的实施方式中，实施例方法中步骤S600、根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示，可以包括步骤S610-S630：
S610、根据所述硬件模块之间的前后延时关系构建时间轴，对所述时间轴进行可视化展示；
S620、对所述硬件仿真模型的模块层次结构进行可视化展示；
S630、根据所述硬件模块之间的延时交叠确定时序关系，对所述时序关系进行可视化展示；
具体在实施例中，为了便于开发人员对硬件涉及进行分析，实施例还提供了一种基于图形化界面的呈现方法，其示意图如图3所示。如图3所示，该图形化界面基于QT的QtableWidget实现，将插件中的第一行设置为时钟周期数，如C0、C1…Cn，左侧第一列用于呈现模块的层次结构，插件的主体部分用于呈现各个模块在不同时钟周期的执行情况。图形化界面301中能够显示的内容包括但不限于：
时间轴302；性能数据的图形化界面中，时间轴的基本单位为一个时钟周期。进一步，时间轴并不需要显示仿真过程中执行的所有时钟周期。因为可视化结果只是向开发人员展示了硬件模块之间的前后延时关系，因此时间轴只需要满足一次完整地数据传递过程即可。
程序层次结构303；在高层次综合生成的硬件代码中，一个大模块往往是由若干个小模块拼接而成，开发人员需要尽可能了解硬件的模块层次结构，才能对电路进行针对性优化。进一步，图形化界面中，模块的层次结构应该从粗到细排列，上层模块的延时由下层每个模块的延时构成。
时序关系可视化区304；主要展示各个模块的时序关系。进一步地，由于硬件电路中经常存在并行执行的情况，即前一模块还未执行完，后一模块已经开始执行，因此，模块与模块之间的延时允许存在交叠的情况。
在一些可行的实施方式中，实施例方法中步骤S600、根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示，还可以包括步骤S640：
S640、获取所述采样函数产生的日志文件，从所述日志文件中获取所述性能数据，并将所述性能数据进行可视化展示；
具体在实施例中，可视化过程中，性能数据收集程序可以是一个基于C编写的文本处理程序，其主要功能是自动处理事件采样函数产生的日志文件，从中提取出各个模块的层次结构、各个模块的种类、以及模块运行的开始时间和结束时间。收集完成后，将性能数据以文本文件的形式保存在本地硬盘中。
结合说明书附图4，对本申请技术方案的实施过程进行完整的实施过程描述：
首先，使用C语言设计一个双精度浮点加法器的核心代码和测试程序，然后通过Clang前端工具，将C语言设计的代码文件编译并转换为加法器IR和测试程序IR。Clang前端是一款基于LLVM的C/C++/Objective-C编译器。
基于高层次综合工具SHANG，对加法器的IR进行多层级优化，最后综合生成加法器的RTL代码实现。Shang高层次综合工具是由中山大学电子与信息工程学院EDA研究组开发的高层次综合系统。
Verilator是一个支持Verilog HDL/SystemVerilog的周期精确的开源仿真器。本实施例中使用Verilator编译工具将加法器电路的RTL代码综合为C++仿真模型。
之后对硬件仿真模型(C++)进行代码插桩，使用预先设计好的代码读取程序解析仿真模型代码，然后在加法器中的每个模块插入事件采样函数，最后再重新保存到新的工程代码路径。
本实施例中基于Clang开发了仿真程序的前端编译器，将完成插桩的加法器的仿真模型代码编译为硬件仿真模型IR。将生成的硬件仿真模型IR和测试程序IR一起送入软硬件协同仿真平台中进行仿真。仿真平台基于python搭建，其中包括仿真流程控制程序，性能数据收集程序，仿真结果显示程序，性能数据可视化程序。
仿真流程控制程序首先将输入的IR文件进一步编译为可执行文件，编译的过程中会进行检查，若接口不匹配，或编译错误，则提醒设计人员进行修改。
编译通过后，首先启动性能数据收集程序线程，然后开启另一线程用于执行仿真程序，按照时钟周期的顺序，逐步执行协同仿真程序。期间性能数据收集程序一直保持运行，并从内存中获取到采集到的数据。
仿真结束后，仿真流程控制程序关闭性能数据收集程序线程，并将收集到的所有数据全部载入到内存中，准备进行可视化。可视化界面使用pyside搭建，其中性能数据呈现窗口使用QT绘制，将双精度浮点加法器中的每个模块的执行顺序和延迟时间在图形化界面进行描述。
另一方面，本发明实施例还提供了一种图形化高层次综合电路性能分析系统，系统包括：
需求获取单元，用于获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码；
软件编码单元，用于对所述测试激励程序代码进行编译转换得到软件描述代码；
正向编码单元，用于对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码；
反向编译单元，用于根据所述寄存器转换级代码进行反向编译，得到硬件仿真模型；
模型构建单元，用于在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码；
可视化单元，用于根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示。
另一方面，本申请的技术方案还提供一种图形化高层次综合电路性能分析装置；其包括：
至少一个处理器；至少一个存储器，该存储器用于存储至少一个程序；当至少一个程序被至少一个处理器执行，使得至少一个处理器运行如第一方面中的图形化高层次综合电路性能分析方法。
本发明实施例还提供了一种存储介质，其存储有对应的执行程序，程序被处理器执行，实现第一方面中的图形化高层次综合电路性能分析方法。
从上述具体的实施过程，可以总结出，本发明所提供的技术方案相较于现有技术存在以下优点或优势：
此外，虽然在功能性模块的背景下描述了本发明，但应当理解的是，除非另有相反说明，功能和/或特征中的一个或多个可以被集成在单个物理装置和/或软件模块中，或者一个或多个功能和/或特征可以在单独的物理装置或软件模块中被实现。还可以理解的是，有关每个模块的实际实现的详细讨论对于理解本发明是不必要的。更确切地说，考虑到在本文中公开的装置中各种功能模块的属性、功能和内部关系的情况下，在工程师的常规技术内将会了解该模块的实际实现。因此，本领域技术人员运用普通技术就能够在无需过度试验的情况下实现在权利要求书中所阐明的本发明。还可以理解的是，所公开的特定概念仅仅是说明性的，并不意在限制本发明的范围，本发明的范围由所附权利要求书及其等同方案的全部范围来决定。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
尽管已经示出和描述了本发明的实施例，本领域的普通技术人员可以理解：在不脱离本发明的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由权利要求及其等同物限定。
以上是对本发明的较佳实施进行了具体说明，但本发明并不限于上述实施例，熟悉本领域的技术人员在不违背本发明精神的前提下还可做作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (10)

  1. 图形化高层次综合电路性能分析方法，其特征在于，包括以下步骤：
    获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码；
    对所述测试激励程序代码进行编译转换得到软件描述代码；
    对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码；
    根据所述寄存器转换级代码进行反向编译，得到硬件仿真模型；
    在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码；
    根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示。
  2. 根据权利要求1所述的图形化高层次综合电路性能分析方法，其特征在于，所述获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码这一步骤，包括：
    确定所述目标电路需求中的硬件功能需求；
    根据所述硬件功能需求，通过高级编程语言中的关键字、控制语句进行函数封装，得到所述硬件模块代码。
  3. 根据权利要求1所述的图形化高层次综合电路性能分析方法，其特征在于，所述对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码这一步骤，包括：
    对所述硬件描述代码进行高层次综合优化，根据优化结果创建数据流和控制结构；
    将所述数据流以及所述控制结构进行整合得到所述寄存器转换级代码。
  4. 根据权利要求1所述的图形化高层次综合电路性能分析方法，其特征在于，所述在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码这一步骤，包括：
    确定所述硬件模块代码的高级编程语言，根据所述高级编程语言的书写格式确定所述高级编程语言中所声明的采样函数；
    确定所述采样函数的起始位置，根据所述起始位置，将所述采样函数插入至所述硬件仿真模型。
  5. 根据权利要求4所述的图形化高层次综合电路性能分析方法，其特征在于，所述在所 述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码，还包括以下步骤至少之一：
    通过所述采样函数，记录所述硬件仿真模型中硬件模块的层次结构；
    通过所述采样函数，记录所述硬件仿真模型中硬件模块的类型；
    通过所述采样函数，记录所述硬件仿真模型对应的硬件电路的时钟周期计数。
  6. 根据权利要求5所述的图形化高层次综合电路性能分析方法，其特征在于，所述根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示，包括以下步骤至少之一：
    根据所述硬件模块之间的前后延时关系构建时间轴，对所述时间轴进行可视化展示；
    对所述硬件仿真模型的模块层次结构进行可视化展示；
    根据所述硬件模块之间的延时交叠确定时序关系，对所述时序关系进行可视化展示。
  7. 根据权利要求6所述的图形化高层次综合电路性能分析方法，其特征在于，所述根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示，还包括：
    获取所述采样函数产生的日志文件，从所述日志文件中获取所述性能数据，并将所述性能数据进行可视化展示。
  8. 图形化高层次综合电路性能分析系统，其特征在于，包括：
    需求获取单元，用于获取目标电路需求，根据所述目标电路需求确定测试激励程序代码以及硬件模块代码；
    软件编码单元，用于对所述测试激励程序代码进行编译转换得到软件描述代码；
    正向编码单元，用于对所述硬件模块代码进行编译转换得到硬件描述代码，根据所述硬件描述代码进行正向编译得到寄存器转换级代码；
    反向编译单元，用于根据所述寄存器转换级代码进行反向编译，得到硬件仿真模型；
    模型构建单元，用于在所述硬件仿真模型中插入采样代码，对插入采样代码后的硬件仿真模型进行仿真编译，得到硬件仿真描述代码；
    可视化单元，用于根据所述软件描述代码以及所述硬件仿真描述代码进行协同仿真，对仿真结果的性能数据以及仿真流程进行可视化展示。
  9. 图形化高层次综合电路性能分析装置，其特征在于，包括：
    至少一个处理器；
    至少一个存储器，用于存储至少一个程序；
    当所述至少一个程序被所述至少一个处理器执行，使得所述至少一个处理器运行如权利要求1-7任一项所述的图形化高层次综合电路性能分析方法。
  10. 一种存储介质，其中存储有处理器可执行的程序，其特征在于，所述处理器可执行的程序在由处理器执行时用于运行如权利要求1-7中任一项所述的图形化高层次综合电路性能分析方法。
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