WO2024040744A1

WO2024040744A1 - Semiconductor device and forming method therefor

Info

Publication number: WO2024040744A1
Application number: PCT/CN2022/129024
Authority: WO
Inventors: 曾以志
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-24
Filing date: 2022-11-01
Publication date: 2024-02-29
Also published as: CN115346919A

Abstract

Provided is a forming method for a semiconductor device. The forming method comprises: providing a substrate, wherein the substrate comprises a plurality of active regions (411) and a plurality of word line structures (415) extending in a first direction (D1); and forming on the substrate a plurality of bit line structures (412) extending in a second direction (D2), wherein each bit line structure (412) comprises first substructures (413) and second substructures (414) alternating with each other in the second direction, the size (W5) of each first substructure (413) in the first direction being less than the size (W6) of each second substructure (414) in the first direction, the projection of each second substructure (414) on the substrate being located within the projection of each word line structure (415) on the substrate, and the second direction and the first direction being perpendicular.

Description

Semiconductor device and method of forming same

Cross-references to related applications

This disclosure is based on a Chinese patent application with application number 202211020699.9, the filing date is August 24, 2022, and the invention name is "A semiconductor device and its formation method", and claims the priority of the Chinese patent application. The Chinese patent The entire contents of this application are hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor device and a method of forming the same.

Background technique

Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in computers and is composed of several storage units. With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. However, as the density of semiconductor devices increases and their sizes shrink, the manufacturing process of semiconductor devices becomes more difficult, and the performance of the formed semiconductor devices becomes worse.

Contents of the invention

In view of this, the main purpose of the present disclosure is to provide a semiconductor device and a method for forming the same.

In order to achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

An embodiment of the present disclosure provides a method for forming a semiconductor device. The forming method includes:

providing a substrate, the substrate including a plurality of active regions and a plurality of word line structures extending along a first direction;

A plurality of bit line structures extending along the second direction are formed on the substrate, each of the bit line structures includes first substructures and second substructures alternating with each other in the second direction, wherein the The size of the first substructure in the first direction is smaller than the size of the second substructure in the first direction; the projection of the second substructure on the substrate is located where the word line structure is. In the projection on the substrate, the second direction and the first direction are perpendicular to each other.

In the above solution, a plurality of bit line structures extending along the second direction are formed on the substrate, including:

sequentially forming a first sacrificial body layer, a bottom mask layer and a patterned top mask layer on the substrate;

using the patterned top mask layer to form a patterned bottom mask structure on the bottom mask layer;

Forming a first sacrificial body layer having a first pattern using the patterned bottom mask structure;

forming a patterned first mask layer on the first sacrificial body layer with a first pattern, and using the patterned first mask layer to form a second sacrificial body layer with a second pattern;

Using the second sacrificial body layer with the second pattern, a bit line structure is formed.

In the above solution, using the patterned bottom mask structure to form a first sacrificial body layer with a first pattern includes:

Using the patterned bottom mask structure to etch part of the first sacrificial body layer to form a plurality of first sacrificial body parts extending in the second direction;

A first fixed layer is filled between the first sacrificial body parts, and the first sacrificial body part and the first fixed layer together form a first sacrificial body layer with a first pattern.

In the above solution, using the patterned first mask layer to form a second sacrificial body layer with a second pattern includes:

The patterned first mask layer has a plurality of openings extending along the second direction, each of the openings having first sub-openings and second sub-openings of different widths;

Using the patterned first mask layer to etch part of the first fixed layer to form a second fixed layer;

removing the first sacrificial body portion in the first sacrificial body layer with the first pattern to form a second fixed layer with a third pattern;

forming a second sacrificial body layer filling the third pattern gap;

The second fixed layer is removed to form the second sacrificial body layer with a second pattern; the second pattern is complementary to the third pattern.

In the above solution, the first sub-opening of the opening corresponds to the first sub-structure of the bit line structure, and the second sub-opening of the opening corresponds to the second sub-structure of the bit line structure.

In the above solution, using the second sacrificial body layer with the second pattern to form a bit line structure includes:

Form a fixed structural layer on the side wall of the second sacrificial body layer;

removing the second sacrificial body layer having the second pattern to form a fixed structure layer having a fourth pattern;

Bit line material is filled in the gaps of the fourth pattern to form a bit line structure.

In the above solution, the forming method further includes:

A first lining layer, a first insulating layer and a second lining layer are sequentially formed on the surface of the second sacrificial body layer to form a fixed structure layer, and the spaces between adjacent fixed structure layers are filled with the second insulating layer.

In the above solution, the gaps of the fourth pattern include first sub-gaps and second sub-gaps that alternate with each other in the second direction, and the size of the first sub-gaps in the first direction is smaller than the The size of the second sub-gap in the first direction;

Filling the gaps of the fourth pattern with bit line material to form a bit line structure includes:

Bit line materials are sequentially filled in the first sub-gap and the second sub-gap of the fourth pattern to form a first sub-structure of the bit line structure in the first sub-gap, and in the second sub-gap A second substructure is formed in the gap.

In the above solution, the first sacrificial body layer and the second sacrificial body layer are made of polysilicon.

In the above solution, the first substructure and the second substructure alternate with each other in the first direction.

In the above solution, the size of the second substructure in the second direction is smaller than or equal to the size of the word line structure in the second direction.

An embodiment of the present disclosure also provides a semiconductor device, including:

A substrate, the substrate including a plurality of active regions and a plurality of word line structures extending along a first direction;

A plurality of bit line structures located on the substrate and extending along a second direction, each of the bit line structures including first substructures and second substructures alternating with each other in the second direction , wherein the size of the first substructure in the first direction is smaller than the size of the second substructure in the first direction; the projection of the second substructure on the substrate is located at Within the projection of the word line structure on the substrate, the second direction and the first direction are perpendicular to each other.

In the above solution, in the second direction, the adjacent second substructures of the same bit line structure are arranged spaced apart from the word line structure.

In the technical solution provided by the embodiment of the present disclosure, a method for forming a semiconductor device is provided. The bit line structure of the semiconductor device prepared by the formation method includes first substructures and second substructures that alternate with each other in the extending direction. , the size of the first substructure in the first direction is smaller than the size of the second substructure in the first direction, and the overall area of the bit line structure with this shape is increased, thereby reducing the resistance of the bit line structure and realizing the Optimizing the read and write performance of semiconductor devices effectively improves the reliability of semiconductor devices. In addition, the projection of the second substructure on the substrate is located within the projection of the word line structure on the substrate, so the resistance of the bit line structure is reduced without occupying additional area, making it possible for semiconductor devices to achieve higher integration levels.

Description of drawings

Figure 1A is a schematic plan view of a substrate provided by an embodiment of the present disclosure;

Figure 1B is a schematic cross-sectional view along the tangent line AA' shown in Figure 1A;

1C to 1I are schematic diagrams of a bit line preparation process provided by embodiments of the present disclosure;

Figure 1J is an enlarged schematic diagram of the dotted box area in Figure 1I;

Figure 1K is a schematic plan view of the semiconductor device corresponding to Figure 1I;

Figure 2 is a schematic flowchart of a specific implementation process of a method for forming a semiconductor device provided by an embodiment of the present disclosure;

3A to 3P are schematic diagrams of the preparation process of another semiconductor device provided by embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a semiconductor device provided by an embodiment of the present disclosure.

Detailed ways

The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described in more detail, by way of example, in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present disclosure.

It should be understood that spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., are used here It may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

It should be noted that the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily as long as there is no conflict.

FIG. 1A is a schematic plan view of a substrate provided by an embodiment of the present disclosure. As shown in FIG. 1A , the substrate 100 includes a plurality of active areas 111 arranged in an array and a plurality of word line structures 120 extending along the first direction D1. Multiple active areas 111 are isolated by isolation structures 110 . For example, the material of the isolation structure 110 may be silicon oxide, silicon oxynitride, or other suitable insulating materials, and the isolation structure 110 may be a shallow trench isolation (shallow trench isolation, STI) structure.

In some embodiments, the plurality of active areas 111 are alternately arranged at intervals along the third direction D3, and the angle between the third direction D3 and the first direction D1 is greater than 30 degrees. The plurality of word line structures 120 are arranged at intervals along the second direction D2, where the second direction D2 and the first direction D1 are perpendicular to each other.

It should be noted that the word line structure in FIG. 1A is a perspective effect, which facilitates observation of the positional relationship between the word line structure and the active area.

1B is a schematic cross-sectional view along the tangent line AA' shown in FIG. 1A . As shown in FIG. 1B , the substrate 100 includes a substrate 101 , a word line structure 120 and an isolation structure 110 . The isolation structure 110 includes a first isolation structure 1101 and a third isolation structure 110 . Two isolation structures 1102. The word line structure 120 includes a gate oxide layer 121, a metal conductive layer 122, a gate conductive layer 123 and a first isolation layer 124.

Specifically, the above-mentioned substrate may be a single substance semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (such as a silicon germanium substrate, etc.), or a silicon on insulator substrate (Silicon on Insulator). Insulator (SOI), germanium on insulator (GeOI) substrate, etc.

1C to 1I are schematic diagrams of a bit line preparation process provided by embodiments of the present disclosure. As shown in Figure 1C, a target layer 130, a second mask layer 141, a stop layer 142 and a third mask layer 150 are sequentially formed on the substrate 100 shown in Figure 1B. The target layer 130 includes a silicon oxide layer 131, a nitride layer Silicon layer 132, titanium nitride layer 133, tungsten layer 134 and second isolation layer 135. The third mask layer 150 includes a sub-mask layer 151 and a sub-stop layer 152 .

As shown in FIG. 1D , the third mask layer 150 is etched using a patterned photoresist layer (not shown) to form a patterned third mask layer 153 .

Figures 1E to 1G are process diagrams of the Self-Aligned Double Patterning (SADP) process. As shown in FIG. 1E , a first dielectric layer 154 is formed, and the first dielectric layer 154 covers the patterned third mask layer 153 .

As shown in FIG. 1F , the first dielectric layer 154 on top of the patterned third mask layer 153 is removed by etching. While the first dielectric layer 154 on top of the patterned third mask layer 153 is etched away, the first dielectric layer 154 on the stop layer 142 is also removed, and then the patterned third mask layer 153 is removed, leaving The first dielectric layer 154 of the pattern sidewalls in the patterned third mask layer 153 is used to form a spacer structure 155 (spacer).

As shown in FIGS. 1F and 1G , the stop layer 142 and the second mask layer 141 are etched using the spacer structure 155 as a mask, the stop layer 142 is removed, and a patterned second mask layer 156 is formed.

As shown in FIGS. 1G and 1H , the target layer 130 is etched using the patterned second mask layer 156 as a mask to form a patterned target layer 157 .

As shown in FIGS. 1I and 1J , a first nitride layer 159 , an oxide layer 160 , and a second nitride layer 161 are sequentially deposited on the patterned target layer 157 to form a bit line structure 158 . Insulating material 162 is filled between 158 . It should be noted that FIG. 1J is an enlarged schematic diagram of the dotted frame area in FIG. 1I.

1K is a schematic plan view of the semiconductor device corresponding to FIG. 1I, and FIG. 1I is a schematic cross-sectional view along the tangent line AA' shown in FIG. 1K. As shown in FIG. 1K , the semiconductor device includes a plurality of active regions 111 and a plurality of word line structures 120 extending along the first direction D1. The plurality of active regions 111 are isolated by isolation structures 110. The plurality of bit line structures 158 formed by the above method extend along the second direction D2, and due to the one-step preparation process, the sizes of the bit line structures 158 are uniform.

However, as the size of dynamic random access memory continues to shrink and the integration level continues to increase, the characteristic size and unit area of dynamic random access memory will decrease. The size of data transmission lines also needs to be reduced. The size of data lines (such as bit lines) will also decrease. Small causes the resistance of the data line to increase. When the resistance of the bit line is too high, most of the applied voltage is consumed by the bit line and dissipated in the form of heat. Therefore, semiconductor devices with higher bitline resistance will require higher voltages to operate. Higher voltage means greater power consumption and more heat generation, which will hinder further increases in semiconductor device density. Therefore, in manufacturing high-density semiconductor devices, it is very important to maintain low bit line resistance.

The area of the bit line structure 158 shown in FIG. 1K will decrease accordingly as the density of semiconductor devices increases, so that the contact resistance between the bit line structure 158 and the corresponding bit line contact structure becomes larger, resulting in flow through the bit line structure. The current of 158 is too small, which reduces the read and write performance of the dynamic random access memory and seriously affects the reliability of the semiconductor device. Therefore, how to improve the performance of semiconductor devices has become an urgent problem that needs to be solved.

To this end, embodiments of the present disclosure provide a semiconductor device and a method of forming the same. FIG. 2 is a schematic flowchart of a specific implementation process of a method for forming a semiconductor device provided by an embodiment of the present disclosure. As shown in Figure 2, the specific steps of the method for forming the semiconductor device include:

Step S210: Provide a substrate, the substrate including a plurality of active areas and a plurality of word line structures extending along a first direction;

Step S220: Form a plurality of bit line structures extending along the second direction on the substrate, each of the bit line structures including first substructures and second substructures alternating with each other in the second direction, wherein , the size of the first substructure in the first direction is smaller than the size of the second substructure in the first direction; the projection of the second substructure on the substrate is located on the word line Within the projection of the structure on the substrate, the second direction and the first direction are perpendicular to each other.

FIGS. 3A to 3P are schematic cross-sectional structural diagrams of the formation process of a semiconductor device according to an embodiment of the present disclosure. The specific structure of the substrate 100 shown in FIGS. 3A to 3P can be referred to FIGS. 1A and 1B . The method for forming the semiconductor device of this embodiment will be described below with reference to FIG. 2 and FIGS. 3A to 3P.

As shown in FIG. 3A , a first sacrificial body layer 310 , a bottom mask layer 320 and a top mask layer 330 are sequentially formed on the substrate 100 . The material of the first sacrificial body layer 310 includes but is not limited to polysilicon (poly). The bottom mask layer 320 includes a bottom sub-mask layer 321 and a bottom stop layer 322. The material of the bottom sub-mask layer 321 includes but is not limited to amorphous carbon (Amorphous Carbon Layer, ACL), silicon oxynitride (SiON) or oxide. (Oxide) etc. The material of the bottom stop layer 322 includes, but is not limited to, silicon oxynitride, silicon oxide, and silicon nitride. The top mask layer 330 includes a top sub-mask layer 331 and a top stop layer 332. The material of the top sub-mask layer 331 includes but is not limited to Spin On Hardmask (SOH), which can be coated by spin coating. Craft formation. Materials of the top stop layer 332 include, but are not limited to, silicon oxynitride, silicon oxide, silicon nitride, and polysilicon. In some embodiments, top stop layer 332 and bottom stop layer 322 are made of the same material.

As shown in FIG. 3B , the top mask layer 330 is etched using a patterned photoresist layer (not shown) to form a patterned top mask layer 340 . In some embodiments, the formation process of the patterned top mask layer 340 includes: first forming a photoresist layer (not shown) on the top mask layer 330, and then exposing and developing the photoresist layer. To form a patterned photoresist layer, the patterned photoresist layer has a plurality of photolithography openings. Finally, the patterned photoresist layer is used as a mask to etch the top mask layer 330 exposed by the photolithography openings. A plurality of openings are thus formed on the top mask layer 330 . In a specific embodiment, the top mask layer 330 may be dry etched (eg, reactive ion etching (RIE)) using a patterned photoresist layer to form a patterned top mask. Layer 340.

3C to 3E illustrate a process of forming a patterned bottom mask structure through a self-alignment process using a patterned top mask layer. Self-aligned processes include Self-Aligned Double Patterning (SADP) process, Self-Aligned Reverse Patterning (SARP) process, Self-Aligned Quadruple Patterning (Self-Aligned Reverse Patterning, SARP) process One or more of the Aligned Quadruple Patterning (SAQP) processes. It should be noted that the embodiment of the present disclosure takes the SADP process as an example for description.

As shown in FIG. 3C , a first dielectric layer 350 is deposited and covers the patterned top mask layer 340 . The material of the first dielectric layer 350 includes but is not limited to oxide. One or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), any other suitable process, or a combination thereof may be used. A variety of thin film deposition processes are used to deposit and form the first dielectric layer 350 .

As shown in FIG. 3D , the first dielectric layer 350 on top of the patterned top mask layer 340 is removed by etching. Grind the first dielectric layer 350 to expose the top mask layer 340, and then use a wet etching process to remove the patterned top mask layer 340, retaining the first dielectric layer 350 on the sidewalls of the patterned top mask layer 340, A side wall structure 351 (spacer) is formed.

As shown in FIG. 3E , the bottom mask layer 320 is etched using the spacer structure 351 as a mask, and the bottom stop layer 322 is removed to form a patterned bottom mask structure 352 . For example, the spacer structure 351 may be used to dry-etch (eg, reactive ion etching (RIE)) the bottom mask layer 320 to form a patterned bottom mask structure 352.

3F to 3G illustrate a process of forming a first sacrificial body layer with a first pattern using the patterned bottom mask structure.

As shown in FIG. 3F , the patterned bottom mask structure 352 is used to etch part of the first sacrificial body layer 310 to form a plurality of first sacrificial body portions 360 extending along the second direction. The plurality of first sacrificial body portions are There are multiple gaps 361 between 360. In some embodiments, there are a plurality of equally spaced gaps 361 between the plurality of first sacrificial body parts 360 .

In some embodiments, since the first sacrificial body layer 310 has a single-layer structure, the etching process is simple, and the etching profile can be better controlled when forming multiple first sacrificial body portions 360 extending in the second direction. , the process window is increased, and the sidewalls of the plurality of first sacrificial body parts 360 extending in the second direction formed by wet etching and/or dry etching the first sacrificial body layer 310 are relatively smooth.

As shown in FIG. 3G , a first fixed layer 362 is filled between the first sacrificial body portions 360 . The first sacrificial body portion 360 and the first fixed layer 362 together form a first sacrificial body layer with a first pattern. . The first fixing layer 362 enables the first sacrificial body layer with the first pattern to have greater firmness to avoid problems such as collapse or tilt of the first sacrificial body portion 360 . The material of the first fixed layer 362 includes but is not limited to oxide. The first fixed layer 362 may be deposited using one or more thin film deposition processes such as CVD, PVD, ALD, any other suitable process, or a combination thereof.

3H to 3L illustrate a process of forming a second sacrificial body layer with a second pattern using a patterned first mask layer.

As shown in FIG. 3H , a patterned first mask layer 364 is formed on the first sacrificial body layer with the first pattern. Specifically, a first stop layer 363 is deposited to cover the first fixed layer 362 , and the first stop layer 363 and the bottom stop layer 322 are made of the same material. The first stop layer 363 may be deposited using one or more thin film deposition processes such as CVD, PVD, ALD, any other suitable process, or a combination thereof. A patterned first mask layer 364 is formed on the first stop layer 363. As shown in FIG. 3H, the patterned first mask layer 364 has a plurality of holes along the second direction that expose the first stop layer 363. Extended openings 365, each opening 365 having a first sub-opening and a second sub-opening of different widths.

In some embodiments, the first sub-opening of the opening 365 corresponds to the first sub-structure of the bit line structure, and the second sub-opening of the opening 365 corresponds to the second sub-structure of the bit line structure.

As shown in FIG. 3I , the patterned first mask layer 364 is used to etch part of the first fixed layer 362 to form a second fixed layer 366 . In a specific implementation, an anisotropic plasma etching process may be used to etch the first fixed layer 362 .

As shown in FIG. 3J , the first sacrificial body portion 360 of the first sacrificial body layer with the first pattern is removed to form a second fixed layer 367 with a third pattern. In some embodiments, in the process of removing the first sacrificial body layer 360 with the first pattern, a wet etching process with high selectivity is used instead of the plasma-assisted dry etching process, which further reduces the impact on the first sacrificial body layer 360 with the first pattern. Damage to the second fixation layer 366 and the substrate 100. Specifically, an etching solvent including tetramethylammonium hydroxide (TMAH) may be used to remove the first sacrificial body portion 360 in the first sacrificial body layer having the first pattern.

In some embodiments, a plurality of second fixed layers 367 having a third pattern extending along the second direction have first gaps 368 and alternating with each other in the first direction. The size of the second gap 369 in the first direction of the first gap 368 is smaller than the size of the second gap 369 in the first direction.

As shown in FIG. 3K , a second sacrificial body layer 370 filling the third pattern gap is formed. In some embodiments, the second sacrificial body layer 370 and the first sacrificial body layer 310 are made of the same material, and one or more thin film deposition processes such as CVD, PVD, ALD, any other suitable process, or a combination thereof may be used. The second sacrificial body layer 370 is deposited.

As shown in FIG. 3L , the second fixing layer 367 is removed to form the second sacrificial body layer 371 with a second pattern, the second pattern is complementary to the third pattern, and the second sacrificial body layer 371 with the second pattern is formed. The second sacrificial body layer 371 has a plurality of gaps 372 .

3M to 3P illustrate a process of forming a bit line structure using the second sacrificial body layer with a second pattern.

As shown in FIG. 3M , a fixed structure layer 373 is formed on the side wall of the second sacrificial body layer. The fixed structural layer 373 makes the second sacrificial body layer 371 with the second pattern have greater firmness to avoid problems such as collapse or tilt. Specifically, a first lining layer 374, a first insulating layer 375 and a second lining layer 376 are sequentially formed on the surface of the second sacrificial body layer to form a fixed structure layer 373, and adjacent layers are filled with the second insulating layer 377. between the fixed structural layers 373. In some embodiments, the material of the first liner 374 includes silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof, and the material of the second liner 376 includes silicon oxide, silicon oxynitride, A high dielectric constant (high k) dielectric or any combination thereof, and the materials of the first insulating layer 375 and the second insulating layer 377 include silicon nitride, silicon oxynitride, or any combination thereof. The materials of the first lining layer 374 and the second lining layer 375 may be the same or different. The first liner layer 374 , the first insulating layer 375 and the second liner layer 376 may be deposited using one or more thin film deposition processes such as CVD, PVD, ALD, any other suitable process, or a combination thereof.

As shown in FIG. 3N , the fixed structure layer 373 is planarized through a chemical mechanical polishing (CMP) process, so that the surface of the fixed structure layer 373 is consistent with the surface of the second sacrificial body layer 371 having the second pattern. Flush.

As shown in FIG. 3O , the second sacrificial body layer 371 with the second pattern is removed to form the fixed structure layer 380 with the fourth pattern. In some embodiments, in the process of removing the second sacrificial body layer 371 with the second pattern, a wet etching process with high selectivity is used instead of the plasma-assisted dry etching process, which further reduces the need for fixation. Damage to structural layer 373 and substrate 100. Specifically, an etching solvent including tetramethylammonium hydroxide may be used to remove the second sacrificial body layer 371 with the second pattern.

In some embodiments, the gaps of the fourth pattern include first sub-gaps 381 and second sub-gaps 382 that alternate with each other in the second direction, and the first sub-gaps 381 are in the first direction. The size is smaller than the size of the second sub-gap 382 in the first direction.

As shown in FIG. 3P , bit line material is filled in the gaps of the fourth pattern to form a bit line structure. In a specific implementation, bit line materials are sequentially filled in the first sub-gap 381 and the second sub-gap 382 of the fourth pattern to form a third part of the bit line structure in the first sub-gap 381 . A substructure 383 forms a second substructure 384 in the second subgap 382 . The bit line material includes a first conductive layer 385, a first connection layer 386, a second conductive layer 387 and a third isolation layer 388 that are filled in sequence. In some embodiments, the material of the first conductive layer 385 includes but is not limited to polysilicon, the material of the first connection layer 386 includes but is not limited to titanium nitride, and the material of the second conductive layer 387 includes but is not limited to tungsten, tantalum, and titanium. , the material of the third isolation layer 388 includes silicon nitride, silicon oxynitride, silicon carbonitride or other suitable materials.

In an embodiment of the present disclosure, the first substructure and the second substructure alternate with each other in the first direction.

In an embodiment of the present disclosure, the size of the second substructure in the second direction is less than or equal to the size of the word line structure in the second direction, that is, the second substructure and the word line structure are in The second direction has the same width, so that the formation of the second substructure does not occupy additional area, making it possible for the semiconductor device to achieve higher integration.

In an embodiment of the present disclosure, the ratio of the size of the second substructure in the first direction to the size of the first substructure in the first direction ranges from 1.5 to 3. Please refer to FIG. 3P for details. W1 is the width of the first substructure 383 in the first direction, W2 is the width of the second substructure 384 in the first direction, and the ratio of W2 to W1 ranges from 1.5 to 3. Since the second substructure 384 has a width in the first direction that is greater than the width of the first substructure 383 in the first direction, the overall area of the bit line structure is increased, thereby reducing the resistance of the bit line structure.

An embodiment of the present disclosure also provides a semiconductor device. The semiconductor device 400 includes: a substrate including a plurality of active regions 411 and a plurality of word line structures 415 extending along the first direction D1;

A plurality of bit line structures 412 are located on the substrate and extend along the second direction D2. Each of the bit line structures 412 includes first substructures alternating with each other in the second direction D2. 413 and a second substructure 414, wherein the size of the first substructure 413 in the first direction is smaller than the size of the second substructure 414 in the first direction D1; The projection of the structure 414 on the substrate is located within the projection of the word line structure 415 on the substrate; the second direction D2 and the first direction D1 are perpendicular to each other.

In some embodiments, multiple active areas 411 are alternately arranged at intervals along the third direction D3, and the multiple active areas 411 are isolated by isolation structures 410. The angle between the third direction D3 and the first direction D1 is greater than 30 degrees. The plurality of word line structures 415 are arranged at intervals along the second direction D2.

In an embodiment of the present disclosure, a size of the second substructure in the second direction is less than or equal to a size of the word line structure in the second direction. Please refer to FIG. 4 for details. W3 is the width of the word line structure 415 in the second direction D2. W4 is the width of the second substructure 414 in the second direction D2. W4 is less than or equal to W3. In this way, the second substructure Formation does not take up additional area.

In some embodiments, in the second direction D2, the adjacent second substructures 414 of the same bit line structure 412 are arranged apart from the word line structure 415. In this way, the second substructure can be avoided from being too dense, thereby reducing the short circuit between the second substructure and the capacitor contact plug in subsequent processes.

In an embodiment of the present disclosure, the ratio of the size of the second substructure in the first direction to the size of the first substructure in the first direction ranges from 1.5 to 3. Specifically, please refer to FIG. 4 . W5 is the width of the first substructure 413 in the first direction D1 . W6 is the width of the second substructure 414 in the first direction D1 . The ratio of W6 to W5 ranges from 1.5 to 3. Since the second substructure 414 has a greater width in the first direction D1 than the first substructure 413 in the first direction D1, the overall area of the bit line structure 412 is increased, thereby reducing the resistance of the bit line structure.

In some embodiments, a source region and a drain region are formed in the active regions on both sides of the word line structure, and the word line structure is connected or itself serves as a gate, together with the source region and the drain region, constitutes a transistor of the memory cell. (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). Further, the source region is connected to the bit line structure, a storage capacitor is formed above the drain region, and the lower plate of the storage capacitor is electrically connected to the drain region, thereby forming a semiconductor memory, such as a DRAM. Of course, it can also be formed Other types of memory.

It will be understood that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present disclosure. The implementation process constitutes any limitation. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure.

Industrial applicability

Claims

A method of forming a semiconductor device, the forming method comprising:

providing a substrate, the substrate including a plurality of active regions and a plurality of word line structures extending along a first direction;

A plurality of bit line structures extending along the second direction are formed on the substrate, each of the bit line structures includes first substructures and second substructures alternating with each other in the second direction, wherein the The size of the first substructure in the first direction is smaller than the size of the second substructure in the first direction; the projection of the second substructure on the substrate is located where the word line structure is. In the projection on the substrate, the second direction and the first direction are perpendicular to each other.
The forming method according to claim 1, wherein forming a plurality of bit line structures extending along the second direction on the substrate includes:

sequentially forming a first sacrificial body layer, a bottom mask layer and a patterned top mask layer on the substrate;

using the patterned top mask layer to form a patterned bottom mask structure on the bottom mask layer;

Forming a first sacrificial body layer having a first pattern using the patterned bottom mask structure;

forming a patterned first mask layer on the first sacrificial body layer with a first pattern, and using the patterned first mask layer to form a second sacrificial body layer with a second pattern;

Using the second sacrificial body layer with the second pattern, a bit line structure is formed.
The formation method according to claim 2, wherein the forming the first sacrificial body layer with the first pattern using the patterned bottom mask structure includes:

Using the patterned bottom mask structure to etch part of the first sacrificial body layer to form a plurality of first sacrificial body parts extending in the second direction;

A first fixed layer is filled between the first sacrificial body parts, and the first sacrificial body part and the first fixed layer together form a first sacrificial body layer with a first pattern.
The formation method according to claim 3, wherein the forming a second sacrificial body layer with a second pattern using the patterned first mask layer includes:

The patterned first mask layer has a plurality of openings extending along the second direction, each of the openings having first sub-openings and second sub-openings of different widths;

Using the patterned first mask layer to etch part of the first fixed layer to form a second fixed layer;

removing the first sacrificial body portion in the first sacrificial body layer with the first pattern to form a second fixed layer with a third pattern;

forming a second sacrificial body layer filling the third pattern gap;

The second fixed layer is removed to form the second sacrificial body layer with a second pattern; the second pattern is complementary to the third pattern.
The forming method according to claim 4, wherein the first sub-opening of the opening corresponds to the first sub-structure of the bit line structure, and the second sub-opening of the opening corresponds to the second sub-opening of the bit line structure. structure.
The formation method according to claim 4, wherein the forming a bit line structure using the second sacrificial body layer with the second pattern includes:

Form a fixed structural layer on the side wall of the second sacrificial body layer;

removing the second sacrificial body layer having the second pattern to form a fixed structure layer having a fourth pattern;

Bit line material is filled in the gaps of the fourth pattern to form a bit line structure.
The forming method according to claim 6, wherein the forming method further includes:

A first lining layer, a first insulating layer and a second lining layer are sequentially formed on the surface of the second sacrificial body layer to form a fixed structure layer, and the spaces between adjacent fixed structure layers are filled with the second insulating layer.
The forming method according to claim 6, wherein the gaps of the fourth pattern include first sub-gaps and second sub-gaps that alternate with each other in the second direction, the first sub-gaps are in the first sub-gap. The size in one direction is smaller than the size of the second sub-gap in the first direction;

Filling the gaps of the fourth pattern with bit line material to form a bit line structure includes:

Bit line materials are sequentially filled in the first sub-gap and the second sub-gap of the fourth pattern to form a first sub-structure of the bit line structure in the first sub-gap, and in the second sub-gap A second substructure is formed in the gap.
The formation method according to claim 2, wherein the first sacrificial body layer and the second sacrificial body layer are made of polysilicon.
The forming method of claim 1, wherein the first substructure and the second substructure alternate with each other in the first direction.
The forming method of claim 1, wherein a size of the second substructure in the second direction is less than or equal to a size of the word line structure in the second direction.
A semiconductor device including:

A substrate, the substrate including a plurality of active regions and a plurality of word line structures extending along a first direction;

A plurality of bit line structures located on the substrate and extending along a second direction, each of the bit line structures including first substructures and second substructures alternating with each other in the second direction , wherein the size of the first substructure in the first direction is smaller than the size of the second substructure in the first direction; the projection of the second substructure on the substrate is located at Within the projection of the word line structure on the substrate, the second direction and the first direction are perpendicular to each other.
The semiconductor device of claim 12, wherein the first substructure and the second substructure alternate with each other in the first direction.
The semiconductor device according to claim 12, wherein in the second direction, adjacent second sub-structures of the same bit line structure are arranged spaced apart from the word line structure.
The semiconductor device of claim 12 , wherein a size of the second substructure in the second direction is less than or equal to a size of the word line structure in the second direction.