WO2024038568A1

WO2024038568A1 - Physical encryption device, physical encryption method, physical decryption device, and physical decryption method

Info

Publication number: WO2024038568A1
Application number: PCT/JP2022/031285
Authority: WO
Inventors: 剛吉田
Original assignee: 三菱電機株式会社
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2024-02-22
Also published as: WO2024038633A1

Abstract

A physical encryption device according to the present disclosure comprises: a probabilistic shaping encoding unit (101) that executes probabilistic shaping on a plurality of bits inputted from the outside; an error correction encoding unit (102) that executes error correction encoding on error correction information bits sent from the probabilistic shaping encoding unit (101); a provisional symbol generation unit (103) that generates a provisional symbol from a bit string composed of the error correction information bits and error correction redundant bits; an encryption bit string generation unit (111) that generates an encryption bit string on the basis of a shared key; an encryption matrix generation unit (112) that determines an encryption matrix on the basis of at least a part of the encryption bit string; and an encryption symbol generation unit (104) that generates an encryption symbol from the provisional symbol by using the encryption matrix.

Description

Physical encryption device, physical encryption method, physical decryption device, and physical decryption method

The disclosed technology relates to a physical encryption device, a physical encryption method, a physical decryption device, and a physical decryption method.

In the technical field of optical transmission systems, probabilistic shaping (also referred to as probabilistic constellation shaping, hereinafter referred to as "probabilistic shaping" in this specification) has been attracting attention. Simply put, probability shaping is a digital signal processing technique that shapes the probability distribution of a modulated signal. More specifically, probability shaping can be said to be a technique for mapping the position of a signal with a high frequency of occurrence, that is, a high probability of occurrence, to a position close to the origin on the complex plane, that is, a position that can be realized with low energy. For this reason, stochastic shaping has come to be recognized as a technology that can bring communication efficiency as close as possible to the theoretical limit known as the Shannon limit, and is being studied around the world.

For example, Patent Document 1 discloses a technique for improving communication performance by combining probability shaping and error correction coding.

JP2020-48188A

By the way, in communication systems such as optical transmission systems, it is also required to encrypt signals to improve the confidentiality of communication. One of the encryption methods that can be considered most intuitively is a bit-level mathematical encryption method in which a pseudo-random bit string is prepared and exclusive ORed with the bit string of the signal to be encoded.
However, applying such mathematical encryption essentially equalizes the probability of occurrence of each signal point, so it should be used in conjunction with the above-mentioned probability shaping, which biases the probability of occurrence of each signal point and improves performance. The problem is that it cannot be done.

In view of the above-mentioned problems, the present technology aims to provide a physical encryption device that achieves both probability shaping and physical encryption in a communication system.

The physical encryption device according to the disclosed technique includes a probability shaping coding unit that performs probability shaping on a plurality of bits input from the outside, and a probability shaping coding unit that performs probability shaping on error correction information bits sent from the probability shaping coding unit. An error correction encoding unit that performs error correction encoding; a temporary symbol generation unit that generates temporary symbols from a bit string consisting of error correction information bits and error correction redundant bits; and a temporary symbol generation unit that generates an encrypted bit string based on a shared key. an encrypted bit string generator that determines an encryption matrix based on at least a portion of the encrypted bit string; and an encryption matrix generator that generates an encrypted symbol from a temporary symbol using the encryption matrix. The symbol generator includes a symbol generator.

Since the physical encryption device according to the disclosed technology has the above configuration, it is possible to achieve both probability shaping and physical encryption.

FIG. 1 is a block diagram showing the functional configuration of a physical encryption device according to the first embodiment. FIG. 2 is a block diagram showing the functional configuration of the physical decoding device according to the first embodiment. FIG. 3 is an explanatory diagram showing an example of generating one 8-value PAM symbol from 3 bits. FIG. 4 is an explanatory diagram showing the operation of the physical encryption device according to the first embodiment using a specific numerical example. FIG. 5 is an explanatory diagram showing the processing contents of the temporary symbol termination unit 203 configuring the physical decoding device according to the first embodiment using a specific numerical example. FIG. 6 is a block diagram showing the functional configuration of an optical transmission system that is an application example of the disclosed technology. FIG. 7 is a configuration diagram showing the hardware configuration of the physical encryption device according to the second embodiment. FIG. 8 is a configuration diagram showing the hardware configuration of the physical decoding device according to the second embodiment.

Mathematical cryptography and physical cryptography are known as types of cryptography. Generally speaking, physical cryptography refers to cryptography whose implementation is based on fundamental laws of physics, such as quantum cryptography. For example, quantum cryptography is based on the physics of quantum mechanics.
The difference between mathematical cryptography and physical cryptography is also explained by the difference in security. Mathematical cryptography is said to be a cryptography based solely on computational security. Computational security is a concept related to security that focuses on the computational complexity of the algorithm required for cryptanalysis. On the other hand, physical cryptography is said to be a cipher that can implement information-theoretic security rather than computational security. Information-theoretical security is a concept that guarantees the confidentiality of communications from an attacker (called Eve) who has unlimited computing power.
In this specification, we will not focus on whether physical laws are used or not, and the level of cryptography that handles

bits

0 and 1 is mathematical cryptography, and the level of cryptography that introduces the concept of "symbol". The ciphers are respectively referred to as physical ciphers. Furthermore, in this specification, a layer that handles symbols is referred to as a physical layer.

Embodiment 1.
FIG. 1 is a block diagram showing the functional configuration of a physical encryption device 100 according to the first embodiment. As shown in FIG. 1, the physical encryption device 100 according to the first embodiment includes a probability shaping coding section 101, an error correction coding section 102, a temporary symbol generation section 103, and an encrypted symbol generation section 104. , an encrypted bit string generation section 111, an encryption matrix generation section 112, a digital-to-analog conversion section 121, an optical modulation section 122, and an optical amplification section 123.

FIG. 2 is a block diagram showing the functional configuration of physical decoding device 200 according to the first embodiment. As shown in FIG. 2, the physical decoding device 200 according to the first embodiment includes a probability shaping decoding section 201, an error correction decoding section 202, a temporary symbol termination section 203, an encrypted symbol termination section 204, and an encryption symbol termination section 204. It includes a bit string generation section 211, an encryption matrix generation section 212, an analog-to-digital conversion section 221, and a light detection section 222.

<<Probability shaping encoding unit 101 configuring the physical encryption device 100>>
The probability shaping encoding unit 101 configuring the physical encryption device 100 is a component that performs probability shaping on a plurality of bits input from the outside. The bits that have been probability-shaped by the probability-shaping encoding unit 101 are referred to as "probability-shaped bits" in this specification.
The probability-shaped bits generated in probability-shaping encoding section 101 are sent to error-correction encoding section 102 .

<<Error correction encoding unit 102 configuring the physical encryption device 100>>
First, the error correction encoding section 102 constituting the physical encryption device 100 collects a plurality of probability-shaped bits sent from the probability shaping encoding section 101. The bits obtained by this first processing are referred to as "error correction information bits" in this specification.
Second, error correction encoding section 102 performs error correction encoding on the error correction information bits. The bits obtained by this second processing are referred to as "error correction redundant bits" in this specification.
The error correction code employed by the error correction encoding unit 102 may be, for example, a BCH code, a low density parity check code, a turbo code, or the like.
The error correction information bits and error correction redundant bits generated in error correction encoding section 102 are sent to temporary symbol generation section 103.

<<Temporary symbol generation unit 103 configuring the physical encryption device 100>>
The temporary symbol generation unit 103 configuring the physical encryption device 100 is a component that generates N temporary symbols from a bit string consisting of error correction information bits and error correction redundant bits sent from the error correction encoding unit 102. . Hereinafter, in this specification, N represents the number of temporary symbols generated by the temporary symbol generation unit 103.
The term "temporary" in the prefix of the name "temporary symbol" means that only probability shaping has been performed on the bit string, and that it is temporary and not the final form. Note that the final form obtained by the physical encryption device 100 according to the disclosed technique is referred to as an "encrypted symbol" in this specification. Details of the encryption symbol will become clear from the explanation below.
Each temporary symbol is a one-dimensional symbol. The temporary symbol assumed by the technology of the present disclosure may be, for example, a symbol related to one-dimensional pulse amplitude modulation (PAM). Further, the temporary symbol assumed by the presently disclosed technique may be, for example, a one-dimensional projection of a multidimensional symbol related to two-dimensional quadrature amplitude modulation (Quadrature Amplitude Modulation).
The disclosed technology performs probability shaping in the most upstream probability shaping encoding unit 101 and introduces the concept of an encryption matrix, thereby changing the probability distribution of temporary symbols in the temporary symbol generation unit 103 to a discretized Gaussian distribution. This has the excellent effect of being able to approximate . In other words, the disclosed technology performs probability shaping before encryption, introduces the concept of an encryption matrix, and performs encryption without affecting the probability of occurrence of signal points. It is possible to achieve both high performance and high secrecy through encryption.
The N temporary symbols generated by the temporary symbol generation section 103 are sent to the encrypted symbol generation section 104.

<<Encrypted bit string generation unit 111 configuring the physical encryption device 100>>
The encrypted bit string generation unit 111 configuring the physical encryption device 100 is a component that generates an encrypted bit string based on a shared encryption key input from the outside. Note that AES (Advanced Encryption Standard) and the like are generally known as common key encryption algorithms.
The encrypted bit string generated by the encrypted bit string generator 111 is sent to the encrypted matrix generator 112.

<<Encryption matrix generation unit 112 configuring the physical encryption device 100>>
The encryption matrix generation unit 112 configuring the physical encryption device 100 is a component that determines an encryption matrix based on at least a portion of the encrypted bit string sent from the encrypted bit string generation unit 111.
The encryption matrix generation unit 112 may be configured to hold a plurality of encryption matrix candidates (hereinafter referred to as "encryption matrix candidates"). All of the encryption matrix candidates are matrices with a size of N×N, and each has an inverse matrix. It is desirable that the encryption matrix candidate is an orthonormal matrix.
The method of determining an encryption matrix by the encryption matrix generation unit 112 may be to select and determine one encryption matrix from candidate encryption matrices.
The encryption matrix determined by encryption matrix generation section 112 is sent to encryption symbol generation section 104.

L encryption matrices (L is an integer of 1 or more) constitute one "physical encryption block." Each of the encryption matrices constituting the physical cipher block is selected from at least two encryption matrix candidates.
The encryption matrix candidate may be realized, for example, by cyclically shifting matrix elements.
The physical cipher block is composed of encryption matrices related to at least 2 to the L power of combinations.

<<Encrypted symbol generation unit 104 configuring physical encryption device 100>>
The encrypted symbol generation unit 104 configuring the physical encryption device 100 is a component that generates an encrypted symbol using the encryption matrix sent from the encryption matrix generation unit 112. Specifically, the encrypted symbol generation unit 104 multiplies the first to Nth temporary symbols sent from the temporary symbol generation unit 103 by an encryption matrix from the left, thereby generating the first to Nth temporary symbols. Generate cryptographic symbols up to.
The first to Nth encrypted symbols generated in the encrypted symbol generator 104 are sent to the digital-to-analog converter 121 in the form of digital signals.

《About specific numerical examples》
FIG. 3 is an explanatory diagram showing an example of generating one 8-value PAM symbol from 3 bits.

FIG. 4 is an explanatory diagram showing the operation of the physical encryption device 100 according to the first embodiment using a specific numerical example. Specifically, FIG. 4 shows the numerical values when N=2, L=2, and the temporary symbol is an 8-value PAM symbol that takes one of ±1, ±3, ±5, and ±7. This is an example.

In FIG. 4, the table labeled "bit string" is an example of a plurality of bits output from the error correction encoding section 102. Note that the probability shaping encoding section 101 and the error correction encoding section 102 are sometimes referred to as a PS encoder and an FEC encoder. PS is an acronym for Probabilistic Shaping. Further, FEC is an acronym for Forward Error Correction.
The bit string shown in FIG. 4 shows an example in which 3 bits are treated as one unit. In the table shown in FIG. 4, the left side represents the beginning. In the table shown in FIG. 4, the leftmost column (“0, 1, 1” arranged vertically) is the first three bits output from the error correction encoding section 102. As shown in FIG. 3, three bits consisting of "0, 1, 1" correspond to "5" of the output symbol. In the table shown in FIG. 4, the second column from the left (“1, 1, 0” arranged vertically) is the second three bits output from the error correction encoding section 102. As shown in FIG. 3, three bits consisting of "1, 1, 0" correspond to "-7" of the output symbol.

In FIG. 4, "first temporary symbol string X _p1 =5, 3, -1, 1, -3..." and "second temporary symbol string X _p2 = -7, 1, -1, -1, 3... ” each represents N temporary symbols generated by the temporary symbol generation unit 103 via the error correction encoding unit 102.
The first temporary symbol string (X _p1 ) may be considered to correspond to the real axis of the complex plane. Similarly, the second temporary symbol sequence (X _p2 ) may be considered to correspond to the imaginary axis of the complex plane. As described above, probability shaping maps the position of a signal with a high frequency of occurrence, that is, a high probability of occurrence, to a position close to the origin on the complex plane. ``0, 0, 0'' and ``0, 0, 0'', which are six consecutive 0s, are mapped to (1, 1) on the complex plane, but the design is such that a position close to the origin is selected. be done.
The first three bits (“0, 1, 1”) of the bit string are converted to the output symbol “5” based on the conversion table shown in FIG. 3, and are allocated to the beginning of the first temporary symbol string (X _p1 ). It will be done. The second three bits (“1, 1, 0”) of the bit string are converted to the output symbol “-7” based on the conversion table shown in _FIG . will be allocated to Thereafter, output symbols are sequentially and alternately allocated to the first provisional symbol string (X _p1 ) and the second provisional symbol string (X _p2 ) in the same manner.

In FIG. 4, the portion described as "shared key 11001..." is a shared key for encryption that is input to the encrypted bit string generation unit 111 from the outside.
In FIG. 4, the portion described as "encrypted bit string 10001..." represents the encrypted bit string generated by the encrypted bit string generation unit 111. The encrypted bit string is a bit string generated only from shared key information. The encrypted bit string may be generated based on the above-mentioned AES algorithm, for example.

In FIG. 4, the portion described as “2×2 matrix candidates E ₀ =…, E ₁ =…” represents the encryption matrix candidates (E ₀ , E ₁ ) held by the encryption matrix generation unit 112. It is something. The encryption matrix (E ₀ , E ₁ ) illustrated in FIG. 4 is shown below.

What should be noted in particular is that the encryption matrices (E ₀ , E ₁ ) shown in equation (1) are all orthogonal matrices. There are various ways to define an orthogonal matrix, but one definition is that the column vectors that make up the orthogonal matrix form an orthonormal basis. Here, in orthonormality, the length of all vectors is 1, and the inner product of the vectors is equal to Kronecker's delta, that is, when two different lines are extracted (when i≠j), the inner product is 0. It has the following properties.
In the encryption matrix (E ₀ , E ₁ ) shown in equation (1), the whole is divided by the square root of 2, which is the column vector of the encryption matrix (E ₀ , E ₁ ) that becomes the base vector. This is for normalizing the size of 1 to 1.

The most important technical feature of the physical encryption device 100 according to the disclosed technology is that it implements encryption by introducing the concept of "encryption matrix." More specifically, the most important feature of the technology disclosed herein is that it has realized the idea of preparing a plurality of encryption matrix candidates (for example, E ₀ and E ₁ ) and switching between them as appropriate. Furthermore, the technology of the present disclosure has a technical feature in that the encryption matrix candidates are composed of a plurality of different orthogonal matrices.
The encryption matrix, which is an orthogonal matrix, has the property of linear mapping, in that the distribution characteristics when the temporary symbol string, which is the mapping source, is plotted on a complex plane are maintained at the mapping destination.
In the specific numerical example shown in FIG. 4, _E1 of the encryption matrix can be interpreted as follows.

However, the bold R that appears in equation (2) represents a two-dimensional rotation matrix. That is, the encryption matrix _E1 is nothing but a rotation matrix that rotates 45 degrees around the origin. Therefore, E ₁ of the encryption matrix maintains the distribution characteristics when the temporary symbol string, which is the mapping source, is plotted on the complex plane even in the mapping destination.
Furthermore, E ₀ of the encryption matrix shown in FIG. 4 can be interpreted as follows.

However, the matrix described as Y-axis mirror that appears in equation (3) can be interpreted as a matrix that provides a mapping that implements line symmetry about the Y axis. That is, the encryption matrix E ₀ is nothing but a matrix that provides a mapping that first performs line symmetry around the Y axis and then performs a 45 degree rotation around the origin. Therefore, E ₀ of the encryption matrix also maintains the distribution characteristics in the mapping destination when the temporary symbol string that is the mapping source is plotted on the complex plane.

An encryption matrix candidate consisting of a plurality of different orthogonal matrices may be generated by combining rotation and line symmetry in this way. Note that in the numerical example shown in FIG. 4, the encryption matrix candidate is created by 45-degree rotation and line symmetry about the Y-axis, but the disclosed technology is not limited to this. The angle of rotation may be other than 45 degrees, and the center of line symmetry may be at the Y-axis level.

An encryption matrix candidate consisting of a plurality of different orthogonal matrices can also be generated by randomly generating "1" or "-1". This method is particularly effective when N in the size (N×N) of the encryption matrix is an even number.
The following is a simple numerical example when N=2 to explain the generation procedure of the encryption matrix (E). Assume that "1, 1" is obtained as a result of randomly generating "1" or "-1". The vertical vector of "1, 1" is considered to be the first basis vector (e ₁ ) and is set as the leftmost column vector of the encryption matrix (E in equation (1) ₀ , see _E1 ). The condition for E to be an orthogonal matrix when N=2 is given by the following equation.

The next step is to further randomly generate "1" or "-1" and use it as a candidate for the second basis vector (e ₂ ). In order for E to be an orthogonal matrix, the inner product of the first basis vector (e ₁ ) and the second basis vector (e ₂ ) must be zero. That is, the equation shown at the bottom of equation (4) must hold true. For example, assume that as a result of randomly generating "1" or "-1", the second basis vector (e ₂ ) is "1, -1". At this time, since the inner product of the vectors becomes 0, it can be said that the encryption matrix (E) has been successfully generated (see E ₀ in equation (1)).
If one encryption matrix (E) is successfully generated, the procedure from there is, for example, fixing the first basis vector (e ₁ ) and creating a new second basis vector (e ₂ ) may be found using a similar method. Furthermore, if one encryption matrix (E) is successfully generated, the procedure from there may use line symmetry or rotation such as the Y-axis mirror described above to generate multiple encryption matrix candidates. .
Note that since orthogonal matrices have the property that the value of the determinant is 1 or -1, this property may be used to check whether the encryption matrix candidate has been successfully generated. E ₀ shown in equation (1) has a determinant value of −1. E ₁ shown in equation (1) has a determinant value of 1.

The following is a simple numerical example regarding an encryption matrix candidate when N=4, obtained by a method of randomly generating "1" or "-1".

Here, a square matrix whose elements are either 1 or -1 and whose columns (and rows) are orthogonal is called a Hadamard matrix. Sylvester's generation method is known as a method for generating Hadamard matrices. _E2 of the matrix shown in the upper part of equation (5) is the Hadamard matrix when N=4 obtained by Sylvester's generation method. In addition, in the matrix shown in equation (5), the subscript 2 in E ₂ and the subscript 3 in E3 are distinguished from the matrix (E ₀ , E ₁ ) shown in equation (1). Different numbers are selected for the purpose.

When N in the encryption matrix size (N×N) is an odd number, a Hadamard matrix cannot be created. When the first basis vector is set to "1, 1, 1" (strictly speaking, it is divided by the root 3 for normalization, see equation (6)), the orthogonal matrix that can be generated is, for example, as follows. It is given to

In this way, when N in the size (N×N) of the encryption matrix is an odd number, it is easy to generate the encryption matrix by combining rotation and symmetry.

In FIG. 4, the portions described as “2×2 matrices E ₁ , E ₀ , E ₀ , E ₀ , E ₁ , . . . ” indicate that the encryption matrix generation unit 112 sequentially generates one of the encryption matrix candidates. This represents the selected encryption matrix. The arrangement of the encryption matrix “E ₁ , E ₀ , E ₀ , E ₀ , E ₁ ,…” (pay attention to the subscript numbers) corresponds to the arrangement of the encrypted bits in “Encrypted bit string 10001…” .

As shown in FIG. 4, the encryption and decryption operations are given by the following equation using the encryption matrix (E _b[i] ).

Here, i appearing in formula (7) is a variable that specifies the number of the symbol in the symbol string. Furthermore, b[i], which is a subscript added to the letter E representing the encryption matrix, indicates the value of the i-th bit in the bit string after encryption. Therefore, in the example shown in FIG. 4, the specific values are b[1]=1, b[2]=0, b[3]=0, b[4]=0, b[5]= 1.

In FIG. 4, the parts described as "first encrypted symbol string..." and "second encrypted symbol string..." refer to the first to Nth encrypted symbols generated in the encrypted symbol generation unit 104. It represents a symbol.
For example, the encrypted symbol for i=1 is calculated through the calculation shown in the following equation.

<<Digital-to-analog converter 121 that constitutes the physical encryption device 100>>
The digital-to-analog conversion unit 121 configuring the physical encryption device 100 is a component that converts the encrypted symbol sent from the temporary symbol generation unit 103 as a digital signal into an electrical analog signal. The digital-to-analog conversion unit 121 performs digital-to-analog conversion for each physical lane of the encrypted symbol sent from the temporary symbol generation unit 103. For example, if the optical transmission system performs orthogonal polarization multiplexing to generate orthogonal amplitude modulation, then Four physical lanes are prepared: axis. Note that in this specification, the in-phase axis is referred to as the I-axis. Further, the orthogonal phase axis shall be referred to as the Q axis. The letter I on the I axis comes from the initial letter In-phase. The letter Q on the Q-axis comes from the initial letter Quadrature.

<<Light modulation section 122 configuring physical encryption device 100>>
The optical modulator 122 configuring the physical encryption device 100 is a component that modulates light, which is a carrier wave, based on the electrical analog signal sent from the digital-to-analog converter 121. If the electrical analog signal sent from the digital-to-analog converter 121 is of four systems: The section 122 performs four modulations and generates one modulated optical signal.
The optical signal generated by the optical modulation section 122 is sent to the optical amplification section 123.

<<Optical amplification unit 123 configuring the physical encryption device 100>>
The optical amplifying section 123 configuring the physical encryption device 100 is a component that amplifies the optical signal sent from the optical modulating section 122.
The optical signal amplified by the optical amplification section 123 is sent to an optical transmission system (not shown) consisting of an optical fiber or the like.

A device that is a subcombination of the physical encryption device 100 is the physical decryption device 200 shown in FIG. As shown in FIGS. 1 and 2, the components of the physical encryption device 100 and the components of the physical decryption device 200 have a corresponding relationship.

<<Photodetector 222 configuring physical decoding device 200>>
The optical detection unit 222 that constitutes the physical decoding device 200 is a component that detects an optical signal from an optical transmission system made of an optical fiber or the like. In the photodetector 222, the optical signal is converted into electrical analog signals of four systems: X polarization-I-axis, X-polarization-Q-axis, Y-polarization-I-axis, and Y-polarization-Q-axis. The four electrical analog signals are sent to an analog-to-digital converter 221.

<<Analog-to-digital converter 221 configuring physical decoding device 200>>
The analog-to-digital converter 221 configuring the physical decoding device 200 is a component that converts an electrical analog signal sent from the photodetector 222 into a digital signal.
The digital signal converted by the analog-to-digital converter 221 is sent as an encrypted symbol to the encrypted symbol termination section 204.

<<Encrypted bit string generation unit 211 configuring the physical decryption device 200>>
The encrypted bit string generation unit 211 configuring the physical decryption device 200 is a component that generates the same encrypted bit string based on the same shared key that the physical encryption device 100 has. The common key encryption algorithm used by the encrypted bit string generator 211 is the same as that used by the encrypted bit string generator 111 of the physical encryption device 100.
The encrypted bit string generated by the encrypted bit string generator 211 is sent to the encrypted matrix generator 212.

<<Encryption matrix generation unit 212 configuring the physical decryption device 200>>
The encryption matrix generation unit 212 configuring the physical decryption device 200 is a component that determines an encryption matrix based on at least a part of the encrypted bit string sent from the encrypted bit string generation unit 211.
The way the encryption matrix generation unit 212 determines the encryption matrix is the same as the way the encryption matrix generation unit 112 in the physical encryption device 100 determines the encryption matrix.
The encryption matrix determined by the encryption matrix generation section 212 is sent to the encryption symbol termination section 204.

<<Encrypted symbol termination section 204 configuring physical decoding device 200>>
The encrypted symbol termination unit 204 configuring the physical decoding device 200 is a component that decodes encrypted symbols into temporary symbols using the encryption matrix sent from the encryption matrix generation unit 212. Specifically, the encrypted symbol termination unit 204 multiplies the first to Nth encrypted symbols sent from the analog-to-digital converter 221 by the inverse matrix of the encryption matrix from the left. Decoding into the 1st to Nth temporary symbols is performed.
The first to Nth temporary symbols decoded by the encrypted symbol termination section 204 are sent to the temporary symbol termination section 203.

<<Temporary symbol termination section 203 configuring physical decoding device 200>>
The temporary symbol termination section 203 configuring the physical decoding device 200 is a component that decodes the first to Nth temporary symbols sent from the encrypted symbol termination section 204 into a bit string.
FIG. 5 is an explanatory diagram showing the processing contents of temporary symbol termination section 203 configuring physical decoding device 200 according to the first embodiment using a specific numerical example. In FIG. 5, the table shown on the left side of the leftward arrow is a numerical example of the bit string decoded in the temporary symbol termination section 203. As shown in FIG. 5, the bit string decoded in the temporary symbol termination unit 203 includes "hard decision bits" (bits displayed in bold) that are decoded based on the conversion table shown in FIG. , "reliability information (example of 2 bits)" (2 bits displayed in non-bold).

<<Error correction decoding unit 202 that constitutes the physical decoding device 200>>
The error correction decoding section 202 configuring the physical decoding device 200 is a component that performs error correction decoding on the bit string sent from the temporary symbol termination section 203. The error correction decoding performed by the error correction decoding section 202 corresponds to the error correction encoding performed in the error correction encoding section 102 of the physical encryption device 100, and has the opposite effect.
The bit string subjected to error correction decoding in the error correction decoding section 202 is sent to the probability shaping decoding section 201.

<<Probability shaping decoding unit 201 configuring the physical decoding device 200>>
The probability shaping decoding unit 201 configuring the physical decoding device 200 is a component that performs a reverse probability shaping operation on the bit string sent from the error correction decoding unit 202.
Physical decoding processing is realized by the actions of the respective components constituting the physical decoding device 200 described above.

FIG. 6 is a block diagram showing the functional configuration of an optical transmission system that is an application example of the disclosed technology. The physical encryption device 100 according to the disclosed technology is installed on the left side of the optical transmission system shown in FIG. It can be applied to the functional blocks described as "optical multiplexing" and "optical amplification." Further, the physical decoding device 200 according to the disclosed technology is located on the right side of the optical transmission system shown in FIG. It can be applied to the part of the functional block that has been created.

One of the excellent effects of the physical encryption device 100 according to the first embodiment is that it is possible to achieve both probability shaping and physical encryption in this way.

Embodiment 2.
The physical encryption device 100 and the physical decryption device 200 according to the second embodiment are the physical encryption device 100 and the physical decryption device 200 according to the presently disclosed technology in terms of hardware configuration.
In the second embodiment, the same symbols used in the first embodiment are used unless otherwise specified. Further, in the second embodiment, explanations that overlap with those in the first embodiment will be omitted as appropriate.

FIG. 7 is a configuration diagram showing the hardware configuration of the physical encryption device 100 according to the second embodiment. Each function of the physical encryption device 100 is realized by a processing circuit. Even if the processing circuit is dedicated hardware, it is also called a CPU (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP) that executes a program stored in memory. ).

FIG. 7A is a configuration diagram showing the hardware configuration of physical encryption device 100 according to the second embodiment, and shows a case where the processing circuit is dedicated hardware. As shown in FIG. 7A, the physical encryption device 100 in this case includes a transmission side input interface 152, a transmission side processing circuit 154, and a transmission side output interface 158.
The dedicated hardware transmitter processing circuit 154 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof. Each function of the physical encryption device 100 may be realized by a separate transmission side processing circuit 154 for each function, or may be realized all by one transmission side processing circuit 154.

FIG. 7B is a configuration diagram showing the hardware configuration of the physical encryption device 100 according to the second embodiment, and shows a case where the processing circuit is a CPU. In this case, the functions of each part of the physical encryption device 100 are executed by software. As shown in FIG. 7B, the physical encryption device 100 in this case includes a sending side input interface 152, a sending side processor 155, a sending side memory 156, and a sending side output interface 158.
The transmitting side processor 155, which is a processing circuit realized by a CPU, realizes the functions of each part by reading and executing a program stored in the transmitting side memory 156. That is, the physical encryption device 100 includes a transmitting side memory 156 for storing a program that, when executed by the transmitting side processor 155, results in the processing steps related to the functions of each unit being executed. It can also be said that these programs cause the sending processor 155, which is a computer, to execute the procedures and methods of the physical encryption device 100. Here, the transmitting side memory 156 may be a non-volatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, etc., for example. Further, the transmitting side memory 156 may include a disk such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, or the like. Further, the transmitting side memory 156 may be in the form of an HHD or an SSD.

Note that the physical encryption device 100 may have some functions realized by dedicated hardware and the remaining functions realized by software or firmware. In this manner, the functions of each part of the processing circuit related to the physical encryption device 100 can be realized by hardware, software, firmware, or a combination thereof.

FIG. 8 is a configuration diagram showing the hardware configuration of the physical decoding device 200 according to the second embodiment. Each function of the physical decryption device 200 is realized by a processing circuit different from that of the physical encryption device 100. As with the physical encryption device 100, the processing circuit related to the physical decryption device 200 may be dedicated hardware or a CPU that executes a program stored in memory.

FIG. 8A is a configuration diagram showing the hardware configuration of the physical decoding device 200 according to the second embodiment, and as shown in FIG. 8A in which the processing circuit is dedicated hardware, in this case, The physical decoding device 200 includes a receiving side input interface 252, a receiving side processing circuit 254, and a receiving side output interface 258.
The dedicated hardware receiver processing circuit 254 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof. Each function of the physical decoding device 200 may be realized by a separate receiving side processing circuit 254 for each function, or may be realized all by one receiving side processing circuit 254.

FIG. 8B is a configuration diagram showing the hardware configuration of physical decoding device 200 according to the second embodiment, and shows a case where the processing circuit is a CPU. In this case, the functions of each part of the physical decoding device 200 are executed by software. As shown in FIG. 7B, the physical decoding device 200 in this case includes a receiving side input interface 252, a receiving side processor 255, a receiving side memory 256, and a receiving side output interface 258.
The receiving processor 255, which is a processing circuit implemented by a CPU, implements the functions of each section by reading and executing a program stored in the receiving memory 256. That is, the physical decoding device 200 includes a receiving side memory 256 for storing a program that, when executed by the receiving side processor 255, results in the processing steps related to the functions of each unit being executed. It can also be said that these programs cause the receiving processor 255, which is a computer, to execute the procedures and methods of the physical decoding device 200. Here, the receiving side memory 256 may be a non-volatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, etc., for example. Further, the receiving side memory 256 may be of a mode including a disk such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, or the like. Further, the receiving side memory 256 may be in the form of an HHD or an SSD.

Note that the physical decoding device 200 may have some functions realized by dedicated hardware and the remaining functions realized by software or firmware. In this way, the processing circuit related to the physical decoding device 200 can realize the functions of each part using hardware, software, firmware, or a combination thereof.

As described above, in the physical encryption device 100 and the physical decryption device 200 according to the second embodiment, the functions of each part can be realized by hardware, software, firmware, or a combination thereof. The physical encryption device 100 and the physical decryption device 200 according to the second embodiment realized in this way have the same effects as those described in the first embodiment.

The disclosed technology can be applied, for example, to encryption of optical transmission systems, particularly on the backbone network side, and has industrial applicability.

100 Physical encryption device, 101 Probability shaping coding unit, 102 Error correction coding unit, 103 Temporary symbol generation unit, 104 Encrypted symbol generation unit, 111 Encrypted bit string generation unit, 112 Encryption matrix generation unit, 121 Digital analog Conversion unit, 122 Optical modulation unit, 123 Optical amplification unit, 152 Transmission side input interface, 154 Transmission side processing circuit, 155 Transmission side processor, 156 Transmission side memory, 158 Transmission side output interface, 200 Physical decoding device, 201 Stochastic shaping decoding 202 Error correction decoding unit, 203 Temporary symbol termination unit, 204 Encrypted symbol termination unit, 211 Encrypted bit string generation unit, 212 Encryption matrix generation unit, 221 Analog-to-digital conversion unit, 222 Photodetection unit, 252 Receiving side input Interface, 254 Receiving side processing circuit, 255 Receiving side processor, 256 Receiving side memory, 258 Receiving side output interface.

Claims

a probability shaping encoder that performs probability shaping on a plurality of bits input from the outside;
an error correction encoding unit that performs error correction encoding on the error correction information bits sent from the probability shaping encoding unit;
a temporary symbol generation unit that generates a temporary symbol from the bit string consisting of the error correction information bits and the error correction redundant bits;
an encrypted bit string generator that generates an encrypted bit string based on the shared key;
an encryption matrix generation unit that determines an encryption matrix based on at least a portion of the encrypted bit string;
an encrypted symbol generation unit that uses the encryption matrix to generate an encrypted symbol from the temporary symbol;
including,
Physical encryption device.
A physical encryption device for a physical encryption device including a probability shaping coding unit, an error correction coding unit, a temporary symbol generation unit, an encrypted bit string generation unit, an encryption matrix generation unit, and an encrypted symbol generation unit. A method of
The probability shaping encoding unit performs probability shaping on a plurality of bits input from the outside,
The error correction encoding unit performs error correction encoding on the error correction information bits sent from the probability shaping encoding unit,
The temporary symbol generation unit generates a temporary symbol from the bit string consisting of the error correction information bits and the error correction redundant bits,
The encrypted bit string generation unit generates an encrypted bit string based on a shared key,
the encryption matrix generation unit determines an encryption matrix based on at least a portion of the encrypted bit string;
the encrypted symbol generation unit generates an encrypted symbol from the temporary symbol using the encryption matrix;
Physical encryption method.
an encrypted bit string generator that generates an encrypted bit string based on the shared key;
an encryption matrix generation unit that determines an encryption matrix based on at least a portion of the encrypted bit string;
an encrypted symbol termination unit that decodes the encrypted symbol into a temporary symbol using the encryption matrix;
a temporary symbol termination unit that decodes the temporary symbol into a bit string;
an error correction decoding unit that performs error correction decoding on the bit string sent from the temporary symbol terminal part;
a probability shaping decoding unit that performs an inverse probability shaping operation on the bit string sent from the error correction decoding unit;
including,
Physical decoding device.
A physical decoding method for a physical decoding device including an encrypted bit string generation section, an encrypted matrix generation section, an encrypted symbol termination section, a temporary symbol termination section, an error correction decoding section, and a probability shaping decoding section. hand,
The encrypted bit string generation unit generates an encrypted bit string based on a shared key,
the encryption matrix generation unit determines an encryption matrix based on at least a portion of the encrypted bit string;
the encrypted symbol termination unit decodes the encrypted symbol into a temporary symbol using the encryption matrix;
The temporary symbol termination unit decodes the temporary symbol into a bit string,
The error correction decoding unit performs error correction decoding on the bit string sent from the temporary symbol terminal part,
The probability shaping decoding unit performs a reverse probability shaping operation on the bit string sent from the error correction decoding unit.
Physical decoding method.