WO2024037163A1

WO2024037163A1 - Storage array and preparation method therefor, and memory and electronic device

Info

Publication number: WO2024037163A1
Application number: PCT/CN2023/100031
Authority: WO
Inventors: 黄凯亮; 景蔚亮; 孙莹; 王正波; 廖恒
Original assignee: 华为技术有限公司
Priority date: 2022-08-19
Filing date: 2023-06-13
Publication date: 2024-02-22
Also published as: CN117651421A

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Disclosed are a storage array and a preparation method therefor, and a memory and an electronic device, wherein the storage array comprises: a substrate and storage unit sub-arrays; each storage unit sub-array comprises: a stack structure, a first channel layer, a first gate dielectric layer, and a first gate electrode; the stack structure comprises a conductive layer and a storage function layer, wherein the conductive layer comprises conductive blocks, the storage function layer being arranged between two adjacent conductive blocks, and the two adjacent conductive blocks and the storage function layer forming a storage unit; the first channel layer corresponds to the storage unit, and at least part of the first channel layer is located on a side wall of the stack structure and is in contact with the two adjacent conductive blocks and the storage function layer, which are in the storage unit; the two adjacent conductive blocks, the first channel layer, the first gate dielectric layer and the first gate electrode form a first transistor; and the storage array is of a 3D architecture, and the first transistor is a field effect transistor of a vertical channel structure, such that the number of storage units and the number of first transistors can be increased, thereby increasing the storage density.

Description

Storage array and preparation method thereof, memory, electronic equipment

This application claims priority to the Chinese patent application submitted to the State Intellectual Property Office on August 19, 2022, with application number 202211003741.6 and the application name "Storage Array and Preparation Method, Memory, and Electronic Equipment", the entire content of which is incorporated by reference. incorporated in this application.

Technical field

The present application relates to the field of semiconductor technology, and in particular, to a memory array and its preparation method, memory, and electronic equipment.

Background technique

With the continuous evolution of integrated circuit technology, the number of transistors per unit area on the chip in various electronic products (such as computers, mobile phones, etc.) continues to increase, resulting in the continuous optimization of the performance of electronic products. Taking chip memory as an example, as the number of transistors per unit area increases, the storage density of chip memory also continues to increase, thus being able to meet people's needs for data processing in the information age.

However, due to the differences in structure and process between the logic unit in the chip processor and the memory unit in the chip memory, there is a gap in the degree of performance improvement between the two. That is to say, the storage density of chip memory cannot keep up with the computing speed of chip processors, resulting in a "storage wall" phenomenon, resulting in limited overall performance of the system including chip processors and chip memories.

Contents of the invention

Embodiments of the present application provide a storage array, a preparation method thereof, a memory, and an electronic device for improving storage density.

In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, a memory array is provided. The memory array includes: a substrate and a plurality of memory cell sub-arrays located on the substrate. The memory cell subarray includes: a stacked layer structure, a first channel layer, a first gate dielectric layer and a first gate electrode. The laminated structure includes a plurality of conductive layers and a plurality of storage function layers stacked along a first direction. The conductive layer includes a plurality of conductive blocks spaced apart along a second direction. A storage function layer is disposed between two adjacent conductive blocks. , two adjacent conductive blocks and the storage functional layer located between the two adjacent conductive blocks form a memory unit. The first direction is perpendicular to the substrate and the second direction is parallel to the substrate. The first channel layer corresponds to the memory cell, and at least part of the first channel layer is located on the sidewall of the stacked structure and is in contact with two adjacent conductive blocks and the memory function layer in the memory cell. The first gate dielectric layer covers the first channel layer. The first gate electrode is located on a side of the first gate dielectric layer away from the first channel layer. The two adjacent conductive blocks, the first channel layer, the first gate dielectric layer, and the first gate electrode form a first transistor.

In the memory array provided by some embodiments of the present application, a storage functional layer is arranged between two adjacent conductive blocks to form a memory unit for storing data, and the two adjacent conductive blocks in the memory unit The first transistor is formed with the first channel layer, the first gate dielectric layer and the first gate electrode, and the first transistor is used to change the state of the storage function layer in the corresponding memory unit to realize data storage. In embodiments of the present application, a conductive layer including a plurality of conductive blocks and a storage functional layer are stacked to form a stacked structure, and the first channel layer, the first gate dielectric layer and the first gate electrode in the first transistor are Arranged on the side walls of the stacked structure, the entire storage array can have a 3D architecture. This is conducive to increasing the number of storage units per unit area, which in turn is conducive to increasing the size of the storage array. storage density. Moreover, the first transistor in the implementation of this application is a vertical channel structure field effect transistor. The orthogonal projection area of the vertical channel structure field effect transistor on the substrate is relatively small, which is beneficial to disposing more first transistors on the substrate. , which is conducive to further improving the storage density of the storage array.

In a possible implementation manner of the first aspect, two adjacent conductive blocks in the memory unit are located on the same conductive layer. Along the second direction, the storage function layer in the memory unit is located between two adjacent conductive blocks. In this way, two conductive blocks in each memory cell can be simultaneously prepared and formed in one patterning process, which is beneficial to simplifying the manufacturing process of the memory array. In addition, a certain contact area between the storage function layer and the conductive block can enable the storage unit to have the required functions. This will help reduce the alignment accuracy between each conductive block and the storage function layer in the same storage unit, and reduce Difficulty of preparing storage arrays.

In a possible implementation manner of the first aspect, in the same conductive layer, conductive blocks and storage functional layers are alternately arranged along the second direction. Two adjacent memory cells located on the same layer can share a conductive block and are electrically connected to each other through the shared conductive block. This is conducive to simplifying the structure of multiple memory cells located on the same layer (or the same row), improving the integration of multiple memory cells located on the same layer, and facilitating the placement of more memory cells in the same conductive layer, which is beneficial to Further improve the integration density, storage capacity and storage density of storage arrays.

In a possible implementation manner of the first aspect, the stacked structure further includes a plurality of first insulating layers. Along the first direction, multiple conductive layers and multiple first insulating layers are alternately arranged. By providing the first insulating layer, two adjacent conductive layers can be separated to form an insulating isolation between the two adjacent conductive layers to avoid short circuits between the two adjacent conductive layers and ensure good performance of the memory array. electrical properties.

In a possible implementation of the first aspect, two adjacent conductive blocks in the memory unit are respectively located on two adjacent conductive layers, and the orthographic projections of the two adjacent conductive blocks on the substrate overlap. Along the first direction, the storage function layer in the memory unit is located between two adjacent conductive blocks. This is beneficial to increasing the contact area between the storage functional layer and the adjacent conductive block and improving the performance of the storage unit.

In a possible implementation of the first aspect, among two adjacent conductive layers, the conductive block located on one of the conductive layers is the first conductive block, and the conductive block located on the other conductive layer is the second conductive block. In the orthographic projection of two adjacent conductive layers on the substrate, along the second direction, a plurality of first conductive blocks and a plurality of second conductive blocks are alternately arranged. Along the first direction, one first conductive block and two second conductive blocks overlap, and one first conductive block and two storage function layers overlap. In this way, two adjacent conductive layers and multiple memory functional layers located between the two adjacent conductive layers form a row of memory cells. The multiple memory cells in the row of memory cells are arranged in sequence along the second direction, and the row In the memory unit, two adjacent memory units share a first conductive block or a second conductive block, and are electrically connected to each other through the shared conductive block. By sharing the first conductive block or sharing the second conductive block, the orthogonal projection area of the first conductive block or the shared second conductive block on the substrate can be increased, which is beneficial to reducing the difficulty of preparing the conductive layer, and thus is beneficial to reducing the cost of the memory array. difficulty of preparation.

In a possible implementation manner of the first aspect, the stacked structure further includes a plurality of first insulating blocks. In the same conductive layer, along the second direction, a plurality of conductive blocks and a plurality of first insulating blocks are alternately arranged. By arranging the first insulating block, two adjacent conductive blocks in the same conductive layer can be separated, and an insulating isolation is formed between the two adjacent conductive blocks to prevent the two adjacent conductive blocks from interfering with each other. A short circuit is formed between them to ensure that the storage array has good electrical performance.

In a possible implementation manner of the first aspect, the memory cell sub-array includes multiple rows of memory cells, and each row of memory cells includes multiple memory cells arranged along the second direction. The stacked structure also includes multiple second insulating layers, and the second insulating layers are located between two adjacent rows of memory cells. By providing a second insulating layer, two adjacent rows of memory cells can be separated. Insulating isolation is formed between two adjacent rows of memory cells to avoid short circuits between two adjacent rows of memory cells and ensure that the memory array has good electrical performance.

In a possible implementation manner of the first aspect, the memory cell sub-array includes multiple rows of memory cells, and each row of memory cells includes multiple memory cells arranged along the second direction. The stacked structure also includes a plurality of second insulating blocks. In the same row of memory cells, the storage function layers of the plurality of memory units and the plurality of second insulating blocks are alternately arranged. Alternatively, in the same row of storage units, the storage function layers of multiple storage units are connected and form an integrated structure. By arranging a plurality of second insulating blocks, two adjacent memory functional layers located on the same conductive layer can be separated to facilitate more clear definition of memory cells. By connecting the storage functional layers of multiple memory cells in the same row of memory cells and forming an integrated structure, it is possible to avoid etching the storage functional layers of multiple memory cells in the same row of memory cells and effectively reduce the number of photomasks. times, which is conducive to simplifying the preparation process of the storage functional layer, which in turn is conducive to simplifying the preparation process of the storage array and reducing costs.

In a possible implementation manner of the first aspect, the memory cell sub-array includes multiple columns of memory cells, and each column of memory cells includes multiple memory cells stacked along the first direction. In the same column of memory cells, the orthographic projections of the storage function layers of any two memory cells on the substrate at least partially overlap. This is beneficial to improving the arrangement regularity of the memory cells in each memory cell sub-array, thereby improving the arrangement regularity of the first transistors corresponding to each memory unit, and reducing the wiring and preparation difficulties of the memory array.

In a possible implementation manner of the first aspect, a plurality of stacked structures are arranged sequentially along a third direction, and the third direction is parallel to the substrate and perpendicular to the second direction. The laminated structure has first and second opposing side walls. The plurality of stacked structures includes at least one stacked structure pair. The stacked structure pair includes an adjacent first stacked structure and a second stacked structure. The first sidewall of the first stacked structure is located away from the second stacked structure. On one side of the second laminated structure, the second side wall is located on the side away from the first laminated structure. The first channel layer, the first gate dielectric layer and the first gate electrode of the first transistor corresponding to the memory cell in the first stacked structure are located on the first sidewall of the first stacked structure and are in contact with the second stacked layer. The first channel layer, first gate dielectric layer and first gate electrode of the first transistor corresponding to the memory unit in the structure are located on the second sidewall of the second stacked structure.

In a possible implementation of the first aspect, the stacked structure has opposite first side walls and second side walls. In the first transistor corresponding to the memory cell in the stacked structure, a part of the first channel layer, a part of the first gate dielectric layer and a part of the first gate electrode are located on the first sidewall, and the first channel layer Another portion, another portion of the first gate dielectric layer and another portion of the first gate electrode are located on the second sidewall. This is equivalent to each first transistor including two conductive channels, which is equivalent to increasing the effective channel width, and can effectively increase the reading speed of the memory array.

In a possible implementation manner of the first aspect, the memory unit sub-array includes multiple columns of memory cells, and each column of memory units includes multiple memory cells arranged sequentially along the first direction. Along the first direction and the second direction, the first channel layers of two adjacent first transistors are separated from each other. The first gate dielectric layers of the plurality of first transistors corresponding to the same column of memory cells are connected and located on the sidewalls of the stacked structure. The first gates of the plurality of first transistors corresponding to the same column of memory cells are connected and located on the sidewalls of the stacked structure. By separating the first channel layers of two adjacent first transistors from each other, short circuits between different first transistors through the first channel layers can be avoided, ensuring good electrical performance of each first transistor. By connecting the first gate dielectric layers of the plurality of first transistors corresponding to the same column of memory cells, the first gate dielectric layers of the plurality of first transistors can be formed into an integrated structure. By connecting the first gate dielectric layers of the plurality of first transistors corresponding to the same column of memory cells, Connecting the first gates of corresponding first transistors can make the first gates of the plurality of first transistors form an integrated structure, which is beneficial to reducing the difficulty of preparing and forming the first transistors and the memory array. and Moreover, after the first gates of the plurality of first transistors corresponding to the same column of memory cells are connected, the first gates of the plurality of first transistors can be electrically connected to the same word line, which is beneficial to reducing the number of words. The number of lines simplifies the structure of the storage array.

In a possible implementation manner of the first aspect, in the first transistor farthest from the substrate along the first direction, the first channel layer, the first gate dielectric layer and the first gate electrode also cover the top wall of the stacked structure. In this way, during the process of preparing the first transistor that is farthest from the substrate along the first direction, it is possible to avoid etching the first channel layer, the first gate dielectric layer and the portion of the first gate covering the top wall of the stacked structure. , which is beneficial to reducing the difficulty of preparing and forming the first transistor and the memory array.

In a possible implementation of the first aspect, in the first transistor corresponding to each memory unit, the cross-sectional pattern of the first channel layer, the first gate dielectric layer and the first gate electrode is along the first direction and along the third direction. In the shape of a ring, the first channel layer surrounds the memory cell, the first gate dielectric layer surrounds the first channel layer, and the first gate electrode surrounds the first gate dielectric layer. The third direction is parallel to the substrate and perpendicular to the second direction. In this way, the structure of each first transistor is a full-gate structure, which effectively increases the overlapping area of the first gate and the first channel layer, thereby effectively improving the ability of the first gate to control the first channel layer. Improve the performance of the first transistor and the memory array.

In a possible implementation manner of the first aspect, the memory cell sub-array includes multiple columns of memory cells, and each column of memory cells includes multiple memory cells stacked along the first direction. The first gates of the plurality of first transistors corresponding to the same column of memory cells are connected and located between the sidewalls of the stacked structure and two adjacent first gate dielectric layers. In this way, the first gates of the plurality of first transistors can be electrically connected to the same word line, which is beneficial to reducing the number of word lines and simplifying the structure of the memory array.

In a possible implementation manner of the first aspect, at least two memory cell sub-arrays are arranged in sequence along the second direction, and at least two memory cell sub-arrays are arranged in sequence along the third direction. The third direction is parallel to the substrate and perpendicular to the second direction. This can avoid increasing the thickness of the storage array while improving the storage density of the storage array.

In a possible implementation manner of the first aspect, at least two memory cell sub-arrays are arranged sequentially along the first direction. The memory array also includes an encapsulation layer, and the encapsulation layer is located between two adjacent memory cell sub-arrays along the first direction. By arranging the memory cell sub-arrays in the first direction, it is possible to increase the storage density of the memory array and at the same time improve the space utilization and reduce the area of the memory array. The encapsulation layer can separate two adjacent memory cell sub-arrays along the first direction, thereby improving the structural stability of the upper memory cell sub-array.

In a possible implementation manner of the first aspect, the memory cell sub-array includes multiple rows of memory cells, and each row of memory cells includes multiple memory cells arranged along the second direction. The memory cell subarray also includes: a plurality of second transistors, the second transistors are located at the ends of a row of memory cells, and the plurality of second transistors are arranged in a column along the first direction; the second transistors include a second source and a second drain. , a second channel layer, a second gate dielectric layer and a second gate electrode. Two adjacent conductive blocks located at the end of a row of memory cells respectively form a second source electrode and a second drain electrode, and a third insulating block is disposed between the second source electrode and the second drain electrode. At least part of the second channel layer is located on the sidewall of the stacked structure and is in contact with the second source electrode, the second drain electrode, and the third insulating block. The second gate dielectric layer covers the second channel layer. The second gate electrode is located on a side of the second gate dielectric layer away from the second channel layer. By arranging the second transistor, the operation of a certain row of memory cells in the memory cell sub-array can be selectively controlled. When the first gates of the first transistors corresponding to the memory cells in the same column are connected to form an integrated structure, interference between memory cells in different rows can be avoided, ensuring that the memory array can operate normally. In addition, the second transistor is a vertical channel structure field effect transistor, and its front projection area on the substrate is smaller, which can avoid affecting the storage density of the storage array.

In a possible implementation manner of the first aspect, the storage function layer includes a ferroelectric material layer, a resistive switching layer material or a phase change material layer. In the case where the memory function layer is a ferroelectric material layer, the memory array is a ferroelectric memory array. When the memory function layer is a resistive switching material layer, the memory array is a resistive switching memory array. In the case where the storage function layer is a phase change material layer, the memory array is a phase change memory array.

In a second aspect, a method of manufacturing a memory array is provided, which method includes: providing a substrate. An initial stacked layer structure is formed on the substrate to form a first channel layer, a first gate dielectric layer and a first gate electrode. The initial stacked structure includes multiple conductive layers and multiple storage function layers stacked along the first direction; the conductive layer includes a plurality of conductive blocks sequentially spaced along the second direction, and a storage layer is disposed between two adjacent conductive blocks. The functional layer, two adjacent conductive blocks and the storage functional layer located between the two adjacent conductive blocks form a memory unit. The first direction is perpendicular to the substrate and the second direction is parallel to the substrate. The first channel layer corresponds to the memory cell, and at least a part of the first channel layer is located on the sidewall of the initial stacked structure and is in contact with two adjacent conductive blocks and the memory function layer in the memory cell. The first gate dielectric layer covers the first channel layer. The first gate electrode is located on a side of the first gate dielectric layer away from the first channel layer. The two adjacent conductive blocks, the first channel layer, the first gate dielectric layer, and the first gate electrode form a first transistor.

In a possible implementation manner of the second aspect, forming an initial stacked structure on the substrate includes: alternately forming a first composite layer and a first sacrificial layer on the substrate. Forming the first composite layer includes: forming a first conductive film; etching the first conductive film to form a plurality of conductive blocks arranged at intervals along the second direction to obtain a conductive layer. A storage functional layer is formed between two adjacent conductive blocks, and the two adjacent conductive blocks in the same memory unit are located in the conductive layer of the first composite layer.

In a possible implementation of the second aspect, forming the first channel layer, the first gate dielectric layer and the first gate electrode includes: forming a channel film that covers at least the sidewalls of the initial stacked structure; forming a gate dielectric film, the gate dielectric film covers the channel film; forming a gate film, the gate dielectric film covers the gate dielectric film; etching the gate film, the gate dielectric film and the channel film to form an initial layer extending along the first direction the gate electrode, the initial gate dielectric layer and the initial channel layer; removing the first sacrificial layer through the sidewalls in the initial stacked structure that are not covered by the initial gate electrode, the initial gate dielectric layer and the initial channel layer to form the first gap; The initial channel layer is etched through the first slit to remove the portion of the initial channel layer opposite to the first slit.

In a possible implementation manner of the second aspect, the initial gate electrode, the initial gate dielectric layer and the initial channel layer are all located on at least two opposite sidewalls of the initial stacked structure. Through the partial sidewalls in the initial stacked structure that are not covered by the initial gate, the initial gate dielectric layer and the initial channel layer, before removing the first sacrificial layer, it also includes: along the first direction and along the second direction, at least for the initial The stacked layer structure is etched to form a first initial stacked layer structure and a second initial stacked layer structure that are oppositely arranged. The initial gate electrode, the initial gate dielectric layer and the initial channel layer are divided into two parts. One part is located on the side wall of the first initial stacked structure, and the other part is located on the side wall of the second initial stacked structure.

In a possible implementation manner of the second aspect, after forming the first channel layer, the first gate dielectric layer and the first gate electrode, the preparation method further includes: filling the first gap with an insulating material to form a first insulating layer.

In a possible implementation of the second aspect, the initial gate, the initial gate dielectric layer and the initial channel layer are all located on at least two opposite sidewalls of the initial stacked structure; the initial channel layer is carved through the first gap. After etching, the first channel pattern is obtained. Forming the first channel layer, the first gate dielectric layer and the first gate further includes: etching the initial gate dielectric layer through the first slit, removing a portion of the initial gate dielectric layer opposite to the first slit, forming a first gate dielectric pattern; depositing the material of the first channel layer in the first gap to form a second channel pattern, the first channel pattern and the second channel pattern forming the first channel layer; along the first direction and Along the third direction, the cross-section of the first channel layer The pattern is annular, the first channel layer surrounds the memory unit, and the third direction is parallel to the substrate and perpendicular to the second direction; the material of the first gate dielectric layer is deposited in the first gap to form a second gate dielectric pattern. A gate dielectric pattern and a second gate dielectric pattern form a first gate dielectric layer; along the first direction and along the third direction, the cross-sectional pattern of the first gate dielectric layer is annular, and the first gate dielectric layer surrounds the first channel layer; Deposit the material of the first gate electrode in the first gap to form a first gate electrode pattern. The first gate electrode pattern and the parts of the initial gate electrode located on opposite sides of the same memory cell form the first gate electrode; along the first direction and Along the third direction, the cross-sectional pattern of the first gate is annular, and the first gate surrounds the first gate dielectric layer.

In a possible implementation manner of the second aspect, forming an initial stacked structure on the substrate includes: alternately forming a second composite layer and a second sacrificial layer on the substrate. Forming the second composite layer includes: forming a second conductive film; etching the second conductive film to form a plurality of conductive blocks arranged at intervals along the second direction to obtain a conductive layer; forming memory on the plurality of conductive blocks. Functional layer; forming a third conductive film on the storage functional layer; etching the third conductive film to form a plurality of conductive blocks arranged at intervals along the second direction to obtain a conductive layer; along the first direction, the same memory unit Two adjacent conductive blocks in are respectively located on two adjacent conductive layers in the second composite layer, and the orthographic projections of the two adjacent conductive blocks on the substrate overlap.

In a possible implementation manner of the second aspect, forming the storage function layer on the plurality of conductive blocks includes: forming a plurality of second insulating blocks sequentially spaced along the second direction on the plurality of conductive blocks; A storage function layer is formed between the second insulating blocks, and a plurality of storage function layers are arranged at intervals along the second direction. Among the two adjacent conductive layers in the second composite layer, the conductive block located in one of the conductive layers is the first conductive block, and the conductive block located in the other conductive layer is the second conductive block. In the orthographic projection of two adjacent conductive layers on the substrate, along the second direction, multiple first conductive blocks and multiple second conductive blocks are alternately arranged; along the first direction, one first conductive block and two second conductive blocks are arranged alternately. Two conductive blocks overlap, and a first conductive block and two storage function layers overlap.

In a possible implementation of the second aspect, forming the first channel layer, the first gate dielectric layer and the first gate electrode includes: forming a channel film that covers at least the sidewalls of the initial stacked structure; forming a gate dielectric film, the gate dielectric film covers the channel film; forming a gate film, the gate dielectric film covers the gate dielectric film; etching the gate film, the gate dielectric film and the channel film to form an initial gate extending along the first direction , the initial gate dielectric layer and the initial channel layer; through the sidewalls in the initial stacked structure that are not covered by the initial gate, the initial gate dielectric layer and the initial channel layer, remove the second sacrificial layer to form a second gap; Second gap, etching the initial channel layer to remove the part of the initial channel layer opposite to the second gap to form a plurality of first channel layers spaced apart in the first direction; filling the second gap with insulation material to form the second insulating layer.

A third aspect provides a memory, which includes: a controller, and a storage array as in any implementation of the first aspect.

In a fourth aspect, an electronic device is provided. The electronic device includes: a processor, and a memory as in any embodiment of the third aspect. Among them, the memory is used to store data generated by the processor.

For the technical effects brought about by the preparation method of the storage array in the second aspect, the memory in the third aspect, and the electronic device in the fourth aspect, please refer to the technical effects brought about by different design methods in the first aspect, here No longer.

Description of drawings

Figure 1a is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

Figure 1b is a schematic structural diagram of a memory provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of an array unit in a ferroelectric memory array provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of a storage array provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 5a is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 5b is a front view of the memory array shown in Figure 5a;

Figure 5c is a cross-sectional view of the memory array shown in Figure 5a along the second direction and along the third direction;

Figure 5d is a cross-sectional view of the memory array shown in Figure 5a along the first direction and along the third direction;

Figure 6 is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 7 is an equivalent circuit diagram of a memory array provided by an embodiment of the present application;

Figure 8a is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 8b is a front view of the memory array shown in Figure 8a;

Figure 8c is a cross-sectional view of the memory array shown in Figure 8a along the second direction and along the third direction;

Figure 8d is a cross-sectional view of the memory array shown in Figure 8a along the first direction and along the third direction;

Figure 9a is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 9b is a front view of the memory array shown in Figure 9a;

Figure 9c is a cross-sectional view of the memory array shown in Figure 9a along the second direction and along the third direction;

Figure 9d is a cross-sectional view of the memory array shown in Figure 9a along the first direction and along the third direction;

Figure 10a is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 10b is a front view of the memory array shown in Figure 10a;

Figure 10c is a cross-sectional view of the memory array shown in Figure 10a along the second direction and along the third direction;

Figure 10d is a cross-sectional view of the memory array shown in Figure 10a along the first direction and along the third direction;

Figure 11a is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 11b is a front view of the memory array shown in Figure 11a;

Figure 11c is a cross-sectional view of the memory array shown in Figure 11a along the second direction and along the third direction;

Figure 11d is a cross-sectional view of the memory array shown in Figure 11a along the first direction and along the third direction;

Figure 12a is a schematic structural diagram of another storage array provided by an embodiment of the present application;

Figure 12b is a front view of the memory array shown in Figure 12a;

Figure 12c is a cross-sectional view of the memory array shown in Figure 12a along the second direction and along the third direction;

Figure 12d is a cross-sectional view of the memory array shown in Figure 12a along the first direction and along the third direction;

Figure 13 is a flow chart of a method for preparing a memory array provided by an embodiment of the present application;

Figures 14a to 14k are flow charts for preparing a memory array provided by embodiments of the present application;

Figures 15a to 15d are flow charts for preparing another storage array provided by embodiments of the present application;

Figures 16a to 16e are yet another preparation flow chart of a memory array provided by an embodiment of the present application;

Figures 17a to 17g are yet another preparation flow chart of a memory array provided by an embodiment of the present application;

Figures 18a to 18d are yet another preparation flow chart of a memory array provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments.

Among them, in the description of this application, unless otherwise stated, "plurality" means two or more than two. "to "One less item (items)" or similar expressions refer to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one of a, b, or c (a), can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

"And/or" describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship.

In addition, in order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as “first” and “second” are used to distinguish identical or similar items with basically the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the number and execution order, and words such as "first" and "second" do not limit the number and execution order. At the same time, in the embodiments of this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner that is easier to understand.

In the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to being defined relative to the schematically placed directions of the components in the drawings. It should be understood that these directional terms may be relative. Concepts, which are used for relative description and clarification, may change accordingly depending on the orientation in which components are placed in the drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity, and the dimensional proportions between the various parts in the illustrations do not reflect actual dimensional proportions.

Example embodiments are described herein with reference to cross-sectional illustrations and/or plan illustrations that are idealized illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated. Therefore, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

In addition, the architecture and scenarios described in the embodiments of the present application are for the purpose of explaining the technical solutions of the embodiments of the present application more clearly, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art will know that as the architecture With the evolution of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

An embodiment of the present application provides an electronic device. The electronic device can be a mobile phone (mobile phone), tablet computer (pad), television, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, As well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, smart wearable devices (such as , smart watches, smart bracelets), vehicle-mounted equipment, smart home equipment and/or smart city equipment. The embodiments of this application do not place special restrictions on the specific types of electronic equipment.

FIG. 1a is an architectural schematic diagram of an electronic device provided by an exemplary embodiment of the present application. As shown in Figure 1a, the electronic device 1000 includes: a memory 500, a processor 200, an input device 300, an output device 400 and other components. pieces. Those skilled in the art can understand that the structure of the electronic device shown in Figure 1a does not constitute a limitation on the electronic device 100. The electronic device 100 may include more or fewer components than those shown in Figure 1a. Either some of the components shown in Figure 1a may be combined, or the components may be arranged differently than that shown in Figure 1a.

Memory 500 is used to store software programs and modules. The memory 500 mainly includes a storage program area and a storage data area. The storage program area can store an operating system, at least one application program required for a function (such as a sound playback function, an image playback function, etc.), etc.; the storage data area can store an electronic program according to the electronic program. Data created by the use of the device (such as audio data, image data, phone book, etc.), etc. In addition, the memory 500 includes an external memory 510 and an internal memory 520 . Data stored in the external memory 510 and the internal memory 520 can be transferred to each other. The external memory 510 includes, for example, a hard disk, a USB disk, a floppy disk, etc. The internal memory 520 includes, for example, static random access memory (static random access memory, SRAM), dynamic random access memory (dynamic random access memory, DRAM), read-only memory, etc.

The processor 200 is the control center of the above-mentioned electronic device 1000. It uses various interfaces and lines to connect various parts of the entire electronic device 1000, by running or executing software programs and/or modules stored in the memory 500, and by calling the software programs and/or modules stored in the memory 500. The electronic device 1000 performs various functions and processes data based on the data in the electronic device 1000, thereby overall monitoring the electronic device 1000. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (artificial intelligence, AI) processor, a digital signal processor (DSP), a neural network processor, or other processors. Application specific integrated circuit (ASIC), etc. In FIG. 1a, the processor 200 is a CPU as an example. The CPU may include a calculator 210 and a controller 220. The arithmetic unit 210 obtains the data stored in the internal memory 520 and processes the data stored in the internal memory 520. The processed results are usually sent back to the internal memory 520. The controller 220 can control the arithmetic unit 210 to process data, and the controller 220 can also control the external memory 510 and the internal memory 520 to store data or read data. Memory 500 may store data generated by processor 200.

The input device 300 is used to receive input numeric or character information and generate key signal input related to user settings and function control of the electronic device 1000 . By way of example, the input device 300 may include a touch screen and other input devices. The touch screen, also known as the touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operations on or near the touch screen using fingers, stylus, or any suitable objects or accessories), and perform operations based on preset settings. The program drives the corresponding connection device. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact point coordinates, and then sends it to the touch controller. to the processor 200, and can receive commands sent by the processor 200 and execute them. In addition, touch screens can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control keys, power switch keys, etc.), trackballs, mice, joysticks, etc. The controller 220 in the above-mentioned processor 200 can also control the input device 300 to receive the input signal or not to receive the input signal. In addition, input numeric or character information received by the input device 300 and key signal input generated related to user settings and function control of the electronic device may be stored in the internal memory 520 .

The output device 400 is used to output the input of the input device 300 and store the data corresponding to the internal memory 520 signal of. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the above-mentioned processor 200 can also control the output device 400 to output a signal or not to output a signal.

It should be noted that the thick arrow in Figure 1a is used to indicate data transmission, and the direction of the thick arrow indicates the direction of data transmission. For example, a one-way arrow between the input device 300 and the internal memory 520 indicates that data received by the input device 300 is transmitted to the internal memory 520 . For another example, the bidirectional arrow between the operator 210 and the internal memory 520 indicates that the data stored in the internal memory 520 can be transferred to the operator 210 , and the data processed by the operator 210 can be transferred to the internal memory 520 . The thin arrows in Figure 1a indicate components that controller 220 can control. For example, the controller 220 can control the external memory 510, the internal memory 520, the operator 210, the input device 300, the output device 400, etc.

Optionally, the electronic device 1000 shown in FIG. 1a may also include various sensors. For example, gyroscope sensor, hygrometer sensor, infrared sensor, magnetometer sensor, etc., which will not be described in detail here. Optionally, the electronic device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which will not be described again here.

It can be understood that the memory provided by the embodiment of the present application can be used as the memory 500 in the above-mentioned electronic device 1000. For example, the memory provided by the embodiment of the present application can be used as the external memory 510 in the above-mentioned memory 500, or can be used as the internal memory 520 in the above-mentioned memory 500.

The memories provided by the embodiments of the present application include, but are not limited to, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), or phase change memory (PCM), etc. Among them, ferroelectric random access memory can be referred to as ferroelectric memory, and resistive random access memory can be referred to as resistive switching memory.

In some examples, as shown in Figure 1b, the above-mentioned memory 500 includes: a controller 600 and a storage array 100. The controller 600 and the storage array 100 can be provided independently of each other or integrated together. The number of storage arrays 100 is one or more. Figure 1b illustrates four memory arrays 100.

For example, the controller 600 may be coupled to the storage array 100 and used to control the storage array 100 to store data. For example, the above-described controller 600 can manage data stored in the storage array 100 and communicate with external devices (eg, a host). As another example, the controller 600 can also control operations of the storage array 100, such as read operations or write operations. Of course, the controller 600 can also perform any other suitable functions, and is not limited to the two examples.

Illustratively, the memory cells of the memory provided by the embodiments of the present application include: two adjacent conductive blocks, and a storage functional layer disposed between the two conductive blocks. Along the stacking direction of the two conductive blocks and the storage function layer, the two conductive blocks are arranged oppositely. The memory functional layer includes but is not limited to a ferroelectric material layer, a resistive material layer or a phase change material layer. In the case where the storage function layer is a ferroelectric material layer, the above-mentioned memory is a ferroelectric memory. In the case where the storage function layer is a resistive switching material layer, the above memory is a resistive switching memory. In the case where the storage function layer is a phase change material layer, the above memory is a phase change memory.

The principles of data storage in the above types of memories are basically similar. For example, the two conductive blocks in the above memory unit can serve as two electrodes respectively. By forming an electric field between the two conductive blocks, the state of the storage functional layer can be changed. Data storage can be achieved by utilizing changes in the status of the storage function layer.

Take, for example, that the storage function layer is a ferroelectric material layer and the above-mentioned memory is a ferroelectric memory. The ferroelectric material layer includes ferroelectric material. The ferroelectric material layer can serve as an insulating medium, so that the two electrodes and the ferroelectric material layer in the memory unit Able to form ferroelectric capacitors. Ferroelectric memory utilizes the characteristics of ferroelectric materials that can undergo spontaneous polarization and that the polarization state can be reoriented with the action of an external electric field for data storage.

For example, the above two conductive blocks are a first conductive block and a second conductive block respectively. When a positive voltage is applied to the first conductive block and a negative voltage is applied to the second conductive block, an electric field will be formed between the first conductive block and the second conductive block. Under the action of this electric field, the ferroelectricity in the ferroelectric layer will The polarity of the material is directed towards the first conductive mass. When a negative voltage is applied to the first conductive block and a positive voltage is applied to the second conductive block, an electric field will be formed between the first conductive block and the second conductive block. Under the action of this electric field, the ferroelectricity in the ferroelectric layer will The polarity of the material points towards the second conductive mass.

Specifically, when an electric field is applied to a ferroelectric material, its central atom stays in a low-energy state along the electric field. Conversely, when an electric field flip is applied to the same ferroelectric material, its central atom follows the direction of the electric field. Move within the crystal and stay in another lower energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains. The ferroelectric domains form polarization charges (also called flip charges) under the action of an electric field.

The flipping charge formed by the flipping of ferroelectric domains under the action of electric field is high, and the flipping charge formed by ferroelectric domains not flipping under the action of electric field is low. This binary stable state of ferroelectric materials allows ferroelectric materials to be used as The memory uses the difference in the direction of the residual polarization intensity and applies an electric field in the same direction to generate different flip charges, which can be used to store data "0" and "1".

When an electric field is added to a ferroelectric material crystal, the central atom moves in the crystal along the direction of the electric field. When the atom moves, it passes through an energy barrier, causing charge breakdown. After the electric field is removed, the central atom can remain The position does not change and the polarization state can be maintained. Therefore, the ferroelectric memory formed of ferroelectric materials has the characteristics of non-volatile, that is, the ferroelectric memory will not lose the stored data when the power is turned off.

As a kind of non-volatile memory, ferroelectric memory has the advantages of high speed, high density, low power consumption and radiation resistance. Specifically, ferroelectric memory can perform write operations at the speed of the bus. There is basically no write delay during data transmission. There are no restrictions on the amount of data transmission and write delay. The system can complete the write operation on the entire chip memory in an instant. In other words, ferroelectric memory has fast read and write speeds. In addition, since ferroelectric capacitors are used as storage media, the writing operation of ferroelectric memory only needs to be performed under the operating voltage. Therefore, the operating current and quiescent current of ferroelectric memory are very low, which makes the power consumption required by ferroelectric memory very low. Low.

Exemplarily, a ferroelectric memory includes a plurality of array units arranged in an array, and the structures of the array units mainly include four structures as shown in Figure 2.

(a) in Figure 2 illustrates a transistor Tr and a ferroelectric capacitor C. In (a) of FIG. 2 , the ferroelectric capacitor C is electrically connected to the gate of the transistor Tr. During the operation of the ferroelectric memory, the gate voltage of the transistor Tr can be adjusted by controlling the flipping of the ferroelectric domain in the ferroelectric capacitor C, and then the storage state of the ferroelectric memory can be determined by detecting the current of the transistor Tr. Therefore, the structure shown in (a) of Figure 2 can also be called a 1T1C current sensing structure.

(b) in Figure 2 illustrates a transistor Tr and n ferroelectric capacitors C in parallel, n≥2, and n is an integer. In (b) of FIG. 2 , each ferroelectric capacitor C is electrically connected to the gate of the transistor Tr. During the operation of the ferroelectric memory, one ferroelectric capacitor C can be selected from multiple ferroelectric capacitors C connected in parallel, and then the gate voltage of the transistor Tr can be controlled by the flipping of the ferroelectric domain in the selected ferroelectric capacitor C. High or low, the storage state of the selected ferroelectric capacitor C is determined by detecting the current of the transistor Tr, that is, the storage state of the ferroelectric memory is determined. Therefore, the structure shown in (b) of Figure 2 can also be called 1TnC current sensing structure.

(c) in Figure 2 illustrates a transistor Tr and a ferroelectric capacitor C. In (c) of FIG. 2 , the ferroelectric capacitor C is electrically connected to the source or drain of the transistor Tr. During the operation of the ferroelectric memory, the storage state of the ferroelectric capacitor C can be determined by detecting the current direction of the transistor Tr, that is, the storage state of the ferroelectric memory can be determined. Therefore, the structure shown in (c) of Figure 2 can also be called a 1T1C charge sensing structure. This structure is understood as replacing the capacitors in the traditional 1T1C DRAM with ferroelectric capacitors.

(d) in Figure 2 illustrates a transistor Tr and n ferroelectric capacitors C connected in parallel. In (d) of FIG. 2 , each ferroelectric capacitor C is electrically connected to the source of the transistor Tr, or is electrically connected to the drain of the transistor Tr. During the operation of the ferroelectric memory, one ferroelectric capacitor C can be selected from multiple ferroelectric capacitors C connected in parallel, and then the storage state of the selected ferroelectric capacitor C can be determined by detecting the current direction of the transistor Tr. That is, determining the storage status of the ferroelectric memory. Therefore, the structure shown in (c) of Figure 2 can also be called a 1TnC charge sensing structure.

Since each ferroelectric capacitor C can be used to store 1 bit of data, each array unit of the above-mentioned 1TnC structure can store n bits of data, which is beneficial to realizing high-density storage based on ferroelectric memory.

The ferroelectric memories of the various structures mentioned above usually have a 2D structure, that is, a planar structure, and the transistor Tr is a horizontal channel transistor. Limited by the preparation process of ferroelectric memories, it is difficult to further increase the storage density of ferroelectric memories. For example, limited by the accuracy of the photolithography process, it is difficult to significantly reduce the area of the transistor Tr and ferroelectric capacitor C in the ferroelectric memory. This makes it difficult to install more transistors Tr and ferroelectric capacitor C per unit area, and thus It is difficult to increase the storage density of ferroelectric memory.

Based on this, embodiments of the present application provide a storage array, which has a 3D architecture. As shown in FIGS. 3 and 4 , the memory array 100 includes a substrate 1 and a plurality of memory cell sub-arrays 2 located on the substrate 1 . The memory cell sub-array 2 is used to store data.

The above-mentioned plurality of memory cell sub-arrays 2 can be arranged in various ways, and can be selected and arranged according to actual needs. The memory array 100 has a first direction Z, a second direction X and a third direction Y. The first direction Z is perpendicular to the substrate 1 , the second direction X is parallel to the substrate 1 , and the third direction Y is parallel to the substrate 1 , and the second direction X and the third direction Y are perpendicular.

In some examples, as shown in FIG. 3 , at least two memory cell sub-arrays 2 are arranged in sequence along the second direction X, and at least two memory cell sub-arrays 2 are arranged in sequence along the third direction Y. That is, the plurality of memory cell sub-arrays 2 in the memory array 100 are arranged in an array and arranged in multiple rows and multiple columns. In other words, the multiple memory cell sub-arrays 2 in the memory array 100 include multiple columns of memory cell sub-arrays 2 arranged along the second direction X, and each column of the memory cell sub-array 2 includes multiple memory cells arranged along the third direction Y. subarray2.

For example, FIG. 3 illustrates twelve memory cell sub-arrays 2 arranged in three columns along the second direction X, and each column of the memory cell sub-arrays 2 includes memory cells arranged along the third direction Y. Four memory cell sub-arrays2.

In this way, the scale of the memory array can be increased and the storage density of the memory array 100 can be increased while avoiding an increase in the thickness of the memory array 100 .

In other examples, as shown in FIG. 4 , at least two memory cell sub-arrays 2 are arranged in sequence along the second direction X, at least two memory cell sub-arrays 2 are arranged in sequence along the third direction Y, and at least two memory cells The sub-arrays 2 are arranged sequentially along the first direction Z. That is, the plurality of memory cell sub-arrays 2 in the memory array 100 are They are arranged in an array in the plane, and also arranged in a layer in the first direction Z. In other words, the plurality of memory cell sub-arrays 2 in the memory array 100 are arranged along the first direction Z into a multi-layer memory cell sub-array 2. A plurality of memory cell sub-arrays 2 are arranged in the direction X. Each column of the memory cell sub-array 2 includes a plurality of memory cell sub-arrays 2 arranged in the third direction Y.

For example, FIG. 4 illustrates twenty-four memory cell sub-arrays 2. The twenty-four memory cell sub-arrays 2 are arranged in two layers along the first direction Z. Each layer of the memory cell sub-array 2 has twelve memory cells. subarray2. For each layer of memory unit sub-arrays 2, the twelve memory unit sub-arrays 2 are arranged in three columns along the second direction X, and each column of memory unit sub-arrays 2 includes four memory unit sub-arrays 2 arranged along the third direction Y. Array 2.

Exemplarily, the memory array 100 further includes an encapsulation layer 7 . Along the first direction Z, the encapsulation layer 7 is located between two adjacent memory cell sub-arrays 2 . The encapsulation layer 7 can separate two adjacent memory cell sub-arrays 2 along the first direction Z, thereby improving the structural stability of the upper memory cell sub-array 2 . FIG. 4 only illustrates the partial structure of the encapsulation layer 7 and does not limit the overall structure of the encapsulation layer 7 .

In this way, the scale of the storage array and the storage density of the storage array 100 can be increased, while the space utilization rate can be improved and the area of the storage array 100 can be reduced.

Figure 5a illustrates a structure of a memory cell sub-array 2. Each of the above-mentioned memory cell sub-arrays 2 includes a stacked structure 21, a first channel layer 22, a first gate dielectric layer 23 and a first gate electrode 24. There are multiple first channel layers 22 , first gate dielectric layers 23 and first gate electrodes 24 .

By way of example, the material of the first channel layer 22 includes, but is not limited to, semiconductor materials and metal oxide materials. For example, the material of the first channel layer 22 includes but is not limited to silicon-based semiconductor materials such as Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), or, In2O3 (indium oxide), ZnO (zinc oxide), Ga2O3 (gallium oxide), ITO (indium tin oxide), TiO2 (titanium dioxide) and other metal oxide materials, In-Ga-Zn-O (IGZO, indium gallium zinc oxide ), In-Sn-Zn-O (ISZO, indium tin zinc oxide) and other multi-component compound materials, or two-dimensional semiconductor materials such as graphene, MoS2 (molybdenum disulfide), black phosphorus, or any combination thereof. The materials of the first gate dielectric layer 23 include but are not limited to SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide) , Si3N4 (silicon nitride) and other insulating materials or any combination thereof. The structure of the first gate dielectric layer 23 is a single-layer structure, a stacked structure or a stacked structure composed of combined materials. The material of the first gate 24 includes metal material or other conductive materials. For example, the materials of the first gate 24 include TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Conductor materials such as Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) or any combination thereof.

In some examples, as shown in FIGS. 5a and 5b , the above-described stacked structure 21 includes multiple conductive layers 211 stacked along the first direction Z. The material of the conductive layer 211 includes metal materials or other conductive materials. For example, the material of the conductive layer 211 includes conductive materials such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), Al, Cu, Ru, Ag, or any combination thereof.

In the above-mentioned laminated structure 21, the thickness of each conductive layer 211 may be the same or different, and may be set according to actual needs. In addition, in the production process of the laminated structure 21, different stacking layer numbers will correspond to different stacking heights. For example, the number of film layers stacked in the laminated structure 21 can be dozens or even hundreds of layers (for example, 32 layers, 64 layers or 128 layers, etc.), the more layers the stacked structure 21 includes, the higher the integration level of the storage array 100 and the larger the storage capacity. The specific design can be based on actual storage requirements or preparation process conditions. stack The number of stacked layers and stacking height of the layer structure 21 are not limited in this application.

Illustratively, each of the above-mentioned conductive layers 211 includes a plurality of conductive blocks 211a spaced apart along the second direction X. The plurality of conductive blocks 211a are sequentially arranged along the second direction X and arranged in a row. For example, in each conductive layer 211, there is a certain distance between two adjacent conductive blocks 211a, and they are insulated.

In some examples, as shown in FIGS. 5b to 5d , the above-mentioned stacked structure 21 further includes a plurality of storage function layers 212 . Each storage function layer 212 has a block shape, for example. A memory function layer 212 is disposed between two adjacent conductive blocks 211a, and the two adjacent conductive blocks 211a and the memory function layer 212 located between the two adjacent conductive blocks 211a form a memory cell MC.

By forming an electric field between the two conductive blocks 211a in each memory cell MC, the state of the storage function layer 212 located between the two conductive blocks 211a can be changed, and then the change in the state of the storage function layer 212 can be utilized, Implement data storage.

For example, one memory cell MC is used to store 1 bit of data. Multiple conductive layers 211 and multiple storage functional layers 212 in each stacked structure 21 can constitute multiple memory cells MC, so that each stacked structure 21 can store multiple bits of data. Multiple memory cells MC in each stacked structure 21 are arranged sequentially in the second direction X and stacked in the first direction Z to form a 3D architecture. Compared with a planar architecture (or 2D architecture), it is beneficial Increasing the number of memory cells MC per unit area is beneficial to increasing the storage density of the memory array 100 .

For example, the stacked structure 21 has two opposite side walls A, and the two opposite side walls are a first side wall A1 and a second side wall A2 respectively. For example, the side wall A of the laminated structure 21 is perpendicular to the plane of the substrate 1 , or, considering the influence of the preparation process, there is a certain angle between the side wall A of the laminated structure 21 and the plane of the substrate 1 . In this case, , it can be considered that the side wall A of the stacked structure 21 is substantially perpendicular to the plane where the substrate 1 is located. That is, the third direction Y is perpendicular or substantially perpendicular to the side wall A.

For example, the sizes of the conductive block 211a and the memory function layer 212 in the third direction Y are equal or substantially equal. The side surfaces of the conductive block 211a and the storage function layer 212 that are perpendicular or substantially perpendicular to the third direction Y form a part of the side wall A of the stacked structure 21 .

In some examples, at least part of the first channel layer 22 is located on the sidewall A of the stacked structure 21 , the first gate dielectric layer 23 covers the first channel layer 22 , and the first gate electrode 24 is located on the first gate dielectric layer 22 . The layer 23 is on a side away from the first channel layer 22 . That is to say, along the third direction Y and away from the sidewall A, the first channel layer 22 , the first gate dielectric layer 23 and the first gate electrode 24 are stacked in sequence. The first gate dielectric layer 23 separates the first gate electrode 24 and the first channel layer 22 to form electrical isolation to avoid contact between the first gate electrode 24 and the first channel layer 22. At the same time, the first gate electrode 24 and the first channel layer 22 are electrically isolated. The electrode 24 is separated from the conductive block 211a in the stacked structure 21 to avoid a short circuit between the first gate electrode 24 and the conductive block 211a.

Among them, "at least part of the first channel layer 22 is located on the sidewall A of the stacked structure 21" includes but is not limited to: a part of the first channel layer 22 is located on one sidewall A of the stacked structure 21 (such as the first On the sidewall A1), the other part is located on the other sidewall A (for example, the second sidewall A2) of the stacked structure 21; or, the first channel layer 22 is entirely located on one sidewall A (for example, the second sidewall A2) of the stacked structure 21. on the first side wall A1). The first channel layer 22 has a vertical structure, for example.

In some examples, the above-mentioned first channel layer 22 is provided corresponding to the memory cell MC. For example, one first channel layer 22 is provided corresponding to one memory cell MC. As shown in Figure 5c, the first channel layer 22 and its corresponding memory cell Two adjacent conductive blocks 211a and the storage function layer 212 in the cell MC are in contact. Among them, an ohmic contact (or electrical contact) is formed between the first channel layer 22 and the two adjacent conductive blocks 211a. The two adjacent conductive blocks 211a, the first channel layer 22, and the first gate dielectric layer 23. The first gate 24 forms the first transistor T1.

The two adjacent conductive blocks 211a in each memory cell MC can be used as two electrodes or as the source and drain of the corresponding first transistor T1, so that the memory cell MC is connected to the corresponding first transistor T1. set in parallel. During the process of storing data in the memory cell MC, for example, the first transistor T1 corresponding to the memory cell MC can be turned off, and then voltages are applied to the two conductive blocks 211a in the memory cell MC respectively to avoid the two conductive blocks 211a. The conductive block 211a forms a conductive path through the first channel layer 22, thereby forming an electric field between the two conductive blocks 211a, changing the state of the storage function layer 212, and realizing data storage.

The memory cell MC and its corresponding first transistor T1 share the two adjacent conductive blocks 211a, which is beneficial to simplifying the structure of the stacked structure 21 and reducing the orthographic projection area of the stacked structure 21 on the substrate 1, which is beneficial to More stacked structures 21 or memory cell sub-arrays 2 are provided on the substrate 1 to increase the storage density of the memory array 100 .

Based on the positional relationship between the first gate 24 and the first channel layer 22 in the first transistor T1, the structure of the first transistor T1 forms a transistor structure in which the channel is a vertical channel. Therefore, the first transistor T1 can It is called a vertical channel structure field effect transistor (Field effect transistor, FET). Compared with horizontal channel transistors, the front projection area of the first transistor T1 on the substrate 1 is smaller, which is conducive to disposing more first transistors T1 and stacked structures 21 on the substrate 1 and is conducive to further improving storage efficiency. Storage density of array 100.

Therefore, in the memory array 100 provided by some embodiments of the present application, the storage function layer 212 is disposed between two adjacent conductive blocks 211a to form a memory unit MC for storing data, and the memory unit MC The two adjacent conductive blocks 211a, the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 constitute a first transistor T1, so as to use the first transistor T1 to change the storage function in the corresponding memory cell MC. The state of layer 212 implements data storage.

In the embodiment of the present application, a conductive layer including a plurality of conductive blocks 211a and a memory functional layer 212 are stacked to form a stacked structure 21, and the first channel layer 22 and the first gate dielectric layer in the first transistor T1 are 23 and the first gate 24 are disposed on the sidewall A of the stacked structure 21, so that the entire memory array 100 has a 3D architecture. This is conducive to increasing the number of memory cells MC per unit area, which is conducive to increasing the storage density of the memory array 100 .

Moreover, the first transistor T1 in the implementation of the present application is a vertical channel structure field effect transistor. The orthogonal projection area of the vertical channel structure field effect transistor on the substrate 1 is relatively small, which is conducive to providing more transistors on the substrate 1 The first transistor T1 is conducive to further improving the storage density of the memory array 100 .

The above-mentioned storage array 100 can be applied to the back end of line (BEOL) process, which is beneficial to increasing the storage area and realizing a large-capacity non-volatile storage array through stacking.

In some embodiments, as shown in FIG. 6 , the above-mentioned memory cell sub-array 2 includes multiple rows of memory cells MC, and each row of memory cells MC includes multiple memory cells MC arranged along the second direction X. In the same row of memory cells MC, two adjacent memory cells MC are electrically connected. The equivalent circuit diagram shown in FIG. 7 illustrates a row of memory cells MC and the first transistor T1 corresponding to the row of memory cells MC.

Exemplarily, as shown in Figure 5c and Figure 6, the electrical connection method between the two adjacent memory cells MC is: a conductive block 211a in one memory cell MC and a conductive block 211a in the other memory cell MC. 211a Electrical connection. Since the two conductive blocks 211a in the memory cell MC can serve as the source and drain of the first transistor T1 corresponding to the memory cell MC, two adjacent memory cells MC in the same row of memory cells MC are electrically connected. It can also be understood that the two first transistors T1 corresponding to the two adjacent memory cells MC are electrically connected, that is, the source of one first transistor T1 and the drain of the other first transistor T1 are electrically connected.

In this way, each row of memory cells MC and the first transistor T1 corresponding to the row of memory cells MC form a chain cell structure as a whole, and the memory array 100 as a whole forms an island chain structure.

In some examples, the first gate 24 of each first transistor T1 is electrically connected to a word line WL, and one of the source and drain of the first transistor T1 is electrically connected to the plate line PL (eg, a direct electrical connection). or indirect electrical connection), the other one of the source electrode and the drain electrode of the first transistor T1 is electrically connected to the bit line BL (for example, a direct electrical connection or an indirect electrical connection). The equivalent circuit diagram shown in FIG. 7 illustrates n+1 first transistors T1. From right to left, the first gates 24 of the n+1 first transistors T1 are connected to the word lines WL0, WL1,... , WLn is electrically connected, the leftmost first transistor T1 is directly electrically connected to the plate line PL, and the remaining first transistors T1 are indirectly electrically connected to the plate line PL (that is, through the first transistor T1 located on the left electrically connected to the plate line PL); each first transistor T1 is indirectly electrically connected to the bit line BL, wherein the rightmost first transistor T1 is electrically connected to the bit line BL through the second transistor T2. Regarding the structure of the second transistor T2, please refer to the description below and will not be described again here.

The working principle of the above chain cell structure is, for example: in the "standby" state, each word line WL transmits a high-potential electrical signal to the first transistor T1 to control each first transistor T1 to turn on and select the signal line. BS transmits a high-potential electrical signal to the second transistor T2 to control the second transistor T2 to turn on, and then both the plate line PL and the bit line BL transmit a low-potential electrical signal Vss, so that the storage function layer 212 in each memory cell MC In the same state (for example, when the storage function layer 212 is a ferroelectric material layer, each ferroelectric capacitor can be in the same polarization state); during the "writing" process, correspond to the selected memory cell MC The word line WL electrically connected to the first transistor T1 transmits a low-potential electrical signal to control the first transistor T1 to turn off, the remaining first transistor T1 and the second transistor T2 are in an on-state, and the plate line PL transmits a high-potential The electrical signal Vdd, the bit line BL still transmits the low-potential electrical signal Vss, so that the storage function layer 212 in the selected memory cell MC changes (for example, when the storage function layer 212 is a ferroelectric material layer, So that the polarization direction of the selected ferroelectric capacitor is flipped), while the unselected memory cell MC maintains its original state (for example, when the memory function layer 212 is a ferroelectric material layer, the unselected ferroelectric capacitor MC remains in its original state). The capacitor maintains the original polarization state) to realize the writing of data; during the "reading" process, the word line WL electrically connected to the first transistor T1 corresponding to the selected memory cell MC transmits a low-potential voltage signal to control the first transistor T1 to turn off, the remaining first transistor T1 and the second transistor T2 to be in the on state, the plate line PL transmits a negative high-level electrical signal (-Vdd), and the bit line BL still transmits a low The potential electrical signal Vss is used to cause the storage function layer 212 in the selected memory cell MC to change (for example, in the case where the storage function layer 212 is a ferroelectric material layer, to cause the polarization of the selected ferroelectric capacitor to change. direction flips), while the unselected memory cell MC maintains its original state (for example, when the storage function layer 212 is a ferroelectric material layer, the unselected ferroelectric capacitor maintains its original polarization state), achieving Reading of data.

In some embodiments of the present application, in the same memory cell MC, the positional relationship between two adjacent conductive blocks 211a and the storage functional layer 212 includes a variety of positions, which can be selected and set according to actual needs, and this application does not limit this.

In some possible embodiments, as shown in Figures 5a to 5c and Figures 8a to 10d, the same memory unit MC Two adjacent conductive blocks 211a are located on the same conductive layer 211. That is to say, the two conductive blocks 211a in the same memory cell MC are arranged on the same layer; the conductive blocks 211a of different memory cells MC in the same row of memory cells MC are also arranged on the same layer.

Exemplarily, along the second direction . Along the second direction

Here, the "same layer arrangement" mentioned in this application refers to a layer structure formed by using the same film formation process to form a film layer with a specific pattern, and then using the same mask to form a patterning process. Depending on the specific pattern, a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses. In this way, two conductive blocks 211a in each memory cell MC can be simultaneously prepared and formed in one patterning process, which is beneficial to simplifying the manufacturing process of the memory cell sub-array 2 and the memory array 100.

In addition, the embodiment of the present application does not limit the size of the contact area between the memory function layer 212 and the conductive blocks 211a located on opposite sides of the same memory cell MC. That is to say, in the same memory cell MC, the contact area between the memory function layer 212 and the conductive blocks 211a located on opposite sides thereof can be larger or smaller. A certain contact area can make the memory unit MC have all the functions. required functions. This is beneficial to reducing the alignment accuracy between each conductive block 211a and the memory function layer 212 in the same memory cell MC, and reducing the difficulty of manufacturing the memory cell sub-array 2 and the memory array 100.

In some examples, as shown in Figures 8c, 9c and 10c, in the same conductive layer 211, along the second direction X, the conductive blocks 211a and the storage function layer 212 are alternately arranged. Among the plurality of conductive blocks 211a located on the same conductive layer 211, a storage function layer 212 is disposed between any two adjacent conductive blocks 211a. Two adjacent memory cells MC located on the same layer can share a conductive block 211a and are electrically connected to each other through the shared conductive block 211a. Or it can be understood that the two first transistors T1 corresponding to two adjacent memory cells MC located on the same layer share one source or drain.

Taking the structure shown in FIG. 9c as an example, the conductive layer 211 includes a first conductive block 211a-1, a second conductive block 211a-2 and a third conductive block 211a-3 arranged sequentially along the second direction X. The first conductive block A first storage functional layer 212-1 is provided between 211a-1 and the second conductive block 211a-2, and a second storage functional layer 212- is provided between the second conductive block 211a-2 and the third conductive block 211a-3. 2. That is, along the second direction Arranged in order. Among them, the first conductive block 211a-1, the first storage function layer 212-1 and the second conductive block 211a-2 form the first memory unit MC-1, the second conductive block 211a-2, the second storage function layer 212- 2 and the third conductive block 211a-3 form the second memory unit MC-2. The first memory unit MC-1 and the second memory unit MC-2 share the second conductive block 211a-2, and pass through the second conductive block 211a- 2 to achieve electrical connection.

This is conducive to simplifying the structure of multiple memory cells MC located on the same layer (or the same row), improving the integration of multiple memory cells MC located on the same layer, and facilitating the placement of more memory cells MC in the same conductive layer 211 , which is conducive to further improving the integration density, storage capacity and storage density of the storage array 100.

In some examples, as shown in FIGS. 8 b , 9 b and 10 b , the stacked structure 21 further includes a plurality of first insulating layers 213 . Along the first direction Z, the multi-layer conductive layers 211 and the multi-layer first insulating layers 213 are alternately arranged. Any two adjacent A first insulating layer 213 is disposed between the conductive layers 211 , and a conductive layer 211 is disposed between any two adjacent first insulating layers 213 .

Exemplarily, the material of the first insulating layer 213 includes but is not limited to SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4 and other insulating materials or any combination thereof. The structure of the first insulating layer 213 is a single-layer structure. A laminated structure or a laminated structure composed of combined materials.

By providing the first insulating layer 213, two adjacent conductive layers 211 can be separated, and an insulating isolation (or electrical isolation) can be formed between the two adjacent conductive layers 211 to avoid interference between the two adjacent conductive layers 211. A short circuit is formed between them to ensure that the storage array 100 has good electrical performance.

In other possible embodiments, as shown in Figures 11a to 12d, two adjacent conductive blocks 211a in the same memory cell MC are respectively located on two adjacent conductive layers 211. Along the first direction Z, the storage function layer 212 in the memory cell MC is located between the two adjacent conductive blocks 211a. That is to say, two adjacent conductive blocks 211a in the same memory cell MC are located on different conductive layers 211, and the memory function layer 212 is also located on a different layer than the two adjacent conductive blocks 211a. Along the first direction Z, in the same memory cell MC, a conductive block 211a, a storage functional layer 212, and another conductive block 211a are arranged in sequence. The lower surface of the storage functional layer 212 is in contact with a conductive block 211a. The upper surface is in contact with another conductive block 211a.

For example, the orthographic projections of two adjacent conductive blocks 211a in the same memory cell MC on the substrate 1 overlap. The two adjacent conductive blocks 211a are arranged in a staggered manner. In the first direction Z, the two adjacent conductive blocks 211a partially overlap. Since the storage function layer 212 is located between the two adjacent conductive blocks 211a, the storage function layer 212 and the two adjacent conductive blocks 211a partially overlap in the first direction Z, and the three overlap The part plays the role of storing data.

Adopting the above arrangement is beneficial to increasing the contact area between the memory function layer 212 and the adjacent conductive block 211a, and improving the performance of the memory cell MC.

In some examples, as shown in Figure 11b, among two adjacent conductive blocks 211a in the same memory cell MC, the conductive block 211a located in one conductive layer 211 of the two adjacent conductive layers 211 is the first conductive block. 211a-1, the conductive block 211a of the other conductive layer 211 among the two adjacent conductive layers 211 is the second conductive block 211a-2.

In the orthographic projection of the two adjacent conductive layers 211 on the substrate 1, along the second direction X, a plurality of first conductive blocks 211a-1 and a plurality of second conductive blocks 211a-2 are alternately arranged. That is, a second conductive block 211a-2 is disposed between any two adjacent first conductive blocks 211a-1, and a first conductive block 211a-1 is disposed between any two adjacent second conductive blocks 211a-2. .

Along the first direction Z, one first conductive block 211a-1 and two second conductive blocks 211a-2 overlap, and one first conductive block 211a-1 and two memory function layers 212 overlap. At this time, the first conductive block 211a-1, the two second conductive blocks 211a-2 overlapping the first conductive block 211a-1, and the two memory functions overlapping the first conductive block 211a-1 The layer 212 forms two memory cells MC arranged sequentially along the second direction X, and the two memory cells MC share the first conductive block 211a-1 and are electrically connected to each other through the first conductive block 211a-1. Or it can be understood that the two first transistors T1 corresponding to the two memory cells MC share one source or drain.

Alternatively, along the first direction Z, one second conductive block 211a-2 overlaps with two first conductive blocks 211a-1, and one second conductive block 211a-2 overlaps with two memory function layers 212. At this time, the second conductive block 211a-2, the two first conductive blocks 211a-1 overlapping the second conductive block 211a-2, and the two memory functions overlapping the second conductive block 211a-2 Layer 212 forms two memory cells MC arranged sequentially along the second direction X, and The two memory cells MC share the second conductive block 211a-2 and are electrically connected to each other through the second conductive block 211a-2. Or it can be understood that the two first transistors T1 corresponding to the two memory cells MC share one source or drain.

In this way, two adjacent conductive layers 211 and a plurality of memory function layers 212 located between the two adjacent conductive layers 211 form a row of memory cells MC, and the plurality of memory cells MC in the row of memory cells MC are along the second direction. X is arranged in sequence, and in the row of memory cells MC, two adjacent memory cells MC share the first conductive block 211a-1 or the second conductive block 211a-2, and are electrically connected to each other through the shared conductive block. By sharing the first conductive block 211a-1 or the second conductive block 211a-2, the front projection area of the first conductive block 211a-1 or the shared second conductive block 211a-2 on the substrate 1 can be increased, which is beneficial to Reducing the preparation difficulty of the conductive layer 211 is beneficial to reducing the preparation difficulty of the memory array 100 .

Moreover, the two first transistors T1 corresponding to the above two memory cells MC share a source or drain, which increases the overlapping area of the first gate 24 and the source, and increases the overlap between the first gate 24 and the drain. The overlapping area is beneficial to realizing the ohmic contact between the source electrode or the drain electrode and the first channel layer 22 .

In some examples, as shown in Figures 11b, 11c, 12b and 12c, the stacked structure 21 also includes a plurality of first insulating blocks 214. In the same conductive layer 211, along the second direction X, a plurality of conductive blocks 211a and a plurality of first insulating blocks 214 are arranged alternately.

A plurality of first insulating blocks 214 are provided in each conductive layer 211. The plurality of first insulating blocks 214 and the plurality of conductive blocks 211a in the conductive layer 211 are arranged in sequence along the second direction A conductive block 211a is disposed between the insulating blocks 214, and a first insulating block 214 is disposed between any two adjacent conductive blocks 211a.

Exemplarily, the material of the first insulating block 214 includes but is not limited to SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4 and other insulating materials or any combination thereof. The structure of the first insulating block 214 is a single-layer structure. A laminated structure or a laminated structure composed of combined materials.

By providing the first insulating block 214, two adjacent conductive blocks 211a in the same layer of conductive layer 211 can be separated, and an insulating isolation (or electrical isolation) is formed between the two adjacent conductive blocks 211a, so as to This avoids a short circuit between the two adjacent conductive blocks 211a to ensure that the memory array 100 has good electrical performance.

In some examples, as shown in FIG. 11 b and FIG. 12 b , the stacked structure 21 further includes multiple layers of second insulating layers 215 , and the second insulating layers 215 are located between two adjacent rows of memory cells MC. Along the first direction Z, multiple rows of memory cells MC and multiple layers of second insulating layers 215 are alternately arranged. A second insulating layer 215 is disposed between any two adjacent rows of memory cells MC, and a row of memory cells MC is disposed between any two adjacent second insulating layers 215 .

Since two adjacent conductive layers 211 and a plurality of memory function layers 212 located between the two adjacent conductive layers 211 form a row of memory cells MC, a second insulating layer 215 is disposed between every two conductive layers 211 .

Exemplarily, the material of the second insulating layer 215 includes but is not limited to SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4 and other insulating materials or any combination thereof. The structure of the second insulating layer 215 is a single-layer structure. A laminated structure or a laminated structure composed of combined materials.

By providing the second insulating layer 215, two adjacent rows of memory cells MC can be separated, and an insulation isolation (or electrical isolation) is formed between the two adjacent rows of memory cells MC to prevent the two adjacent rows of memory cells MC from interfering with each other. A short circuit is formed between them to ensure that the storage array 100 has good electrical performance.

In the same row of memory cells MC, the storage function layer MC can be set in a variety of ways, and the settings can be selected according to actual needs.

For example, as shown in FIGS. 11 b and 11 c , the stacked structure 21 further includes a plurality of second insulating blocks 216 . In the same row of memory cells MC, the storage function layers 212 and the plurality of second insulating blocks 216 of the plurality of memory cells MC are alternately arranged. At this time, each storage function layer 212 has a block shape.

For the plurality of storage function layers 212 and the plurality of second insulating blocks 216 located on the same conductive layer 211, along the second direction A storage function layer 212 is disposed between two adjacent second insulating blocks 216 , and a second insulating block 216 is disposed between any two adjacent storage function layers 212 .

Optionally, the material of the second insulating block 216 includes but is not limited to SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4 and other insulating materials or any combination thereof. The structure of the second insulating block 216 is a single-layer structure. A laminated structure or a laminated structure composed of combined materials.

By providing the second insulating block 216, two adjacent memory function layers 212 located on the same conductive layer 211 can be separated to facilitate more clear definition of the memory cell MC.

As another example, as shown in Figures 12a to 12c, in the same row of memory cells MC, the memory function layers 212 of multiple memory cells MC are connected and form an integrated structure. That is, the storage function layers 212 of multiple memory cells MC in the same row of memory cells MC are arranged on the same layer, and the storage function layers 212 of two adjacent memory cells MC are continuous and not disconnected. At this time, each storage function layer 212 is in a strip shape and extends along the second direction X.

This can avoid etching the storage functional layers 212 of multiple memory cells MC in the same row of memory cells MC, can effectively reduce the number of photomasks, and is conducive to simplifying the preparation process of the storage functional layer 212, which in turn is conducive to simplifying the memory unit. The manufacturing process of array 2 and storage array 100 reduces costs.

In some embodiments, as shown in Figure 8b, Figure 9b, Figure 10b, Figure 11b and Figure 12b, the above-mentioned memory cell sub-array 2 includes multiple columns of memory cells MC, and each column of memory cells MC includes stacked memory cells along the first direction Z. Multiple memory cells MC. Two adjacent memory cells MC in the same column of memory cells MC are electrically insulated (or called electrical isolation). In the same column of memory cells MC, the orthographic projections of the memory function layers 212 of any two memory cells MC on the substrate 1 at least partially overlap.

For example, the orthographic projections of the storage function layers 212 of the above two memory cells MC on the substrate 1 partially overlap and are somewhat misaligned; The projections overlap; or, among the storage function layers 212 of the two memory cells MC, the orthographic projection of one on the substrate 1 is within the range of the orthographic projection of the other on the substrate 1 .

Using the above setting method, the memory cells MC in each memory unit sub-array 2 are arranged in multiple rows and columns, which is beneficial to improving the regularity of the arrangement of the memory cells MC in each memory unit sub-array 2, which is beneficial to improving the connection with each memory unit. The regular arrangement of the first transistors T1 corresponding to the cell MC reduces the wiring difficulty and manufacturing difficulty of the memory cell sub-array 2 and the memory array 100.

In some embodiments of the present application, the first transistor T1 corresponding to each memory cell MC is provided in a variety of ways, and the setting can be selected according to actual needs, and this application does not limit this.

In some possible embodiments, the first channel layer 22 of at least one first transistor T1 is located on one sidewall A or two sidewalls A2 of the stacked structure 21 .

In some examples, as shown in FIG. 5c , the first channel layer 22 of the first transistor T1 is located on one sidewall A (for example, the first sidewall A1 ) of the stacked structure 21 , and the first channel layer 22 of the first transistor T1 The gate dielectric layer 23 and the first gate electrode 24 are also located on the sidewall A, and in the direction away from the sidewall A, the first channel layer 22 and the first gate dielectric The layer 23 and the first gate 24 are arranged in sequence. Among them, the first channel layer 22 is in contact with one side of the conductive block 211a and one side of the storage function layer 212 in the corresponding memory cell MC. This is beneficial to improving the arrangement regularity of each first transistor T1 and reducing the wiring and manufacturing difficulty of the memory cell sub-array 2 and the memory array 100.

Here, in each memory cell sub-array 2, the first transistor T1 is provided in various positions.

For example, in the same memory cell sub-array 2, the first channel layer 22, the first gate dielectric layer 23, and the first gate electrode 24 of each first transistor T1 are located on the same sidewall A of the stacked structure 21 (for example, the first On the side wall A1).

For another example, in different memory cell sub-arrays 2, the first channel layer 22, the first gate dielectric layer 23, and the first gate electrode 24 of each first transistor T1 are all located on the first sidewall A1 of the corresponding stacked structure 21. (or the second side wall A2). Alternatively, in different memory cell sub-arrays 2 , the first channel layer 22 , first gate dielectric layer 23 , and first gate electrode 24 of each first transistor T1 in a part of the memory cell sub-array 2 are located in the corresponding stacked structure 21 On the first sidewall A1 (or the second sidewall A2), the first channel layer 22, the first gate dielectric layer 23, and the first gate electrode 24 of each first transistor T1 in another part of the memory cell sub-array 2 are all Located on the second side wall A2 (or the first side wall A1) of the corresponding stacked structure 21.

Optionally, as shown in Figures 8a, 8c and 8d, multiple stacked structures 21 are arranged in sequence along the third direction Y. The plurality of stacked structures 21 includes at least one stacked structure pair, and each stacked structure pair includes two adjacent stacked structures 21 . The two adjacent stacked structures 21 included in the pair of stacked structures are respectively a first stacked structure 21-1 and a second stacked structure 21-2. The first side wall A1 of the first laminated structure 21-1 is located on the side away from the second laminated structure 21-2, and the second side wall A2 of the second laminated structure 21-2 is located on the side away from the first laminated structure 21 -1 side. Correspondingly, the second side wall A2 of the first laminated structure 21-1 and the first side wall A1 of the second laminated structure 21-2 are arranged oppositely.

The first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 of the first transistor T1 corresponding to the memory cell MC in the first stacked structure 21-1 are located in the first stacked structure 21-1. On the first sidewall A1, the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 of the first transistor T1 corresponding to the memory cell MC in the second stacked structure 21-2 are located on the second sidewall A1. On the second side wall A2 of the laminated structure 21-2.

Exemplarily, the first stacked structure 21-1 and the second stacked structure 21-2 are symmetrically arranged, and the first trench of each first transistor T1 located on the first sidewall A1 of the first stacked structure 21-1 The channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24, and the first channel layer 22 and the first transistor T1 located on the second sidewall A2 of the second stacked structure 21-2. The gate dielectric layer 23 and the first gate electrode 24 are symmetrically arranged.

In other examples, as shown in FIGS. 9a, 9c and 9d, in the first transistor T1, a part of the first channel layer 22, a part of the first gate dielectric layer 23 and a part of the first gate electrode 24 are located On the first sidewall A1 of the stacked structure 21 , another part of the first channel layer 22 , another part of the first gate dielectric layer 23 and another part of the first gate electrode 24 are located on the second sidewall of the stacked structure 21 On A2. That is, the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 of each first transistor T1 are divided into two parts, which are respectively located on the first sidewall A1 and the second side of the stacked structure 21. On wall A2.

The first channel layer 22 of each first transistor T1 is in contact with two opposite sides of the memory cell MC (including the two sides of the conductive block 211a and the two sides of the memory function layer 212). This is equivalent to each first transistor T1 including two conductive channels, which is equivalent to increasing the effective channel width, and can effectively increase the read speed of the memory array 100 .

In some further examples, as shown in FIGS. 8 b and 9 b , along the first direction Z and the second direction X, the first channel layers 22 of two adjacent first transistors T1 are separated from each other. That is to say, the first channel of the different first transistor T1 The channel layers 22 are independent and unconnected. This can prevent short circuits between different first transistors T1 through the first channel layer 22 and ensure good electrical performance of each first transistor T1.

The first gate dielectric layers 23 of the plurality of first transistors T1 corresponding to the same column of memory cells MC are connected and located on the sidewall A of the stacked structure 21 . The first gates 24 of the plurality of first transistors T1 corresponding to the same column of memory cells MC are connected and located on the sidewall A of the stacked structure 21 . For example, along the first direction Z, the first gate dielectric layers 23 of two adjacent first transistors T1 are connected to each other to form an integrated structure, and the connected parts of the two are in contact with the sidewall A of the stacked structure 21 , the first gate electrodes 24 of two adjacent first transistors T1 are connected to each other to form an integrated structure, and the portion where the two are connected to each other is located on the side surface of the first gate dielectric layer 23 away from the stacked structure 21 .

By connecting the first gate dielectric layers 23 of the plurality of first transistors T1 corresponding to the same column of memory cells MC, the first gate dielectric layers 23 of the plurality of first transistors T1 can form an integrated structure and form a vertical structure. structure, by connecting the first gates 24 of the plurality of first transistors T1 corresponding to the same column of memory cells MC, the first gates 24 of the plurality of first transistors T1 can form an integrated structure and form a vertical structure. structure, this can avoid etching the first gate dielectric layer 23 or the first gate electrode 24 of the plurality of first transistors T1 corresponding to the same column of memory cells MC, which is beneficial to reducing the preparation of the first transistor T1 and the memory array. 100 difficulty. Moreover, after the first gates 24 of the plurality of first transistors T1 corresponding to the same column of memory cells MC are connected, the first gates 24 of the plurality of first transistors T1 can be electrically connected to the same word line WL. connection, which is beneficial to reducing the number of word lines WL and simplifying the structure of the memory array 100.

In some of the above examples, as shown in FIGS. 8a and 9a , in the first transistor T1 farthest from the substrate 1 along the first direction Z, the first channel layer 22 , the first gate dielectric layer 23 and the first gate The pole 24 also covers the top wall B of the laminated structure 21 . The first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 of the first transistor T1 all have a folded surface shape.

In this way, during the process of preparing the first transistor T1 farthest from the substrate 1 along the first direction Z, it is possible to avoid covering the stacked structure 21 with the first channel layer 22 , the first gate dielectric layer 23 and the first gate electrode 24 . Etching the top wall B is helpful to reduce the difficulty of preparing and forming the first transistor T1 and the memory array 100 .

Here, as shown in FIG. 8d , in the same memory cell sub-array 2 , the first channel layer 22 , the first gate dielectric layer 23 , and the first gate electrode 24 of each first transistor T1 are located on the same side of the stacked structure 21 . In the case of one sidewall A (for example, the first sidewall A1), if the first gate dielectric layers 23 of the plurality of first transistors T1 corresponding to the same column of memory cells MC are connected, then the plurality of first transistors T1 The first gate dielectric layer 23 of T1 has a "7" shape or an inverted "L" shape as a whole; if the first gates 24 of multiple first transistors T1 corresponding to the same column of memory cells MC are connected, then the multiple first gates 24 of the first transistors T1 corresponding to the same column of memory cells MC will be connected. The first gate electrode 24 of the first transistor T1 is in a "7" shape or an inverted "L" shape as a whole.

As shown in Figure 9d, in the same memory cell sub-array 2, the first channel layer 22, the first gate dielectric layer 23, and the first gate electrode 24 of each first transistor T1 are located on both sidewalls of the stacked structure 21. In the case of A, if the first gate dielectric layers 23 of the plurality of first transistors T1 corresponding to the same column of memory cells MC are connected, the first gate dielectric layers 23 of the plurality of first transistors T1 will be inverted as a whole. "U" shape, and snaps onto the stacked structure 21; if the first gates 24 of the plurality of first transistors T1 corresponding to the same column of memory cells MC are connected, then the first gates 24 of the plurality of first transistors T1 A gate 24 is in an inverted "U" shape as a whole and is fastened to the stacked structure 21 .

In other possible embodiments, as shown in FIG. 10a , the first channel layer 22 of each first transistor T1 surrounds the memory cell MC.

In some examples, as shown in FIG. 10d , in the first transistor T1 corresponding to each memory cell MC, along the first direction Z and along the third direction Y, the first channel layer 22 , the first gate dielectric layer 23 and The cross-sectional pattern of the first gate electrode 24 is annular, the first channel layer 22 surrounds the memory cell MC, the first gate dielectric layer 23 surrounds the first channel layer 22 , and the first gate electrode 24 surrounds the first gate dielectric layer 23 .

“Along the first direction Z and along the third direction Y” refers to the extending direction of a certain plane perpendicular to the second direction X. The first channel layer 22 , the first gate dielectric layer 23 and the first gate electrode 24 The cross-sectional pattern is annular. Correspondingly, the three-dimensional patterns of the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 are all tubular. Among them, a part of each conductive block 211a in the memory cell MC is located in the tubular first channel layer 22 and is in contact with the inner wall of the first channel layer 22, and the other part extends out of the tubular first channel. The channel layer 22 is located outside the tubular first channel layer 22 . The storage function layer in the memory cell MC is located in the tubular first channel layer 22 and is in contact with the inner wall of the first channel layer 22 . The tubular first gate dielectric layer 23 is nested on the tubular first channel layer 22 , and the two are in contact with each other. The tubular first gate electrode 24 is nested on the tubular first gate dielectric layer 23 , and the two are in contact with each other.

Using the above arrangement, the structure of each first transistor T1 is a full-gate structure, which effectively increases the overlapping area of the first gate 24 and the first channel layer 22, thereby effectively improving the relationship between the first gate 24 and the first channel layer 22. The control capability of the channel layer 22 improves the performance of the first transistor T1 and the memory array 100 .

Optionally, among the plurality of first transistors T1 corresponding to the same column of memory cells MC, the first gate dielectric layers 23 of two adjacent first transistors T1 are arranged at intervals, and the first gate dielectric layers 23 of two adjacent first transistors T1 are arranged at intervals. The first gate electrodes 24 are spaced apart from each other.

Optionally, the first gates 24 of the plurality of first transistors T1 corresponding to the same column of memory cells MC are connected and located between the sidewall A of the stacked structure 21 and the two adjacent first gate dielectric layers 23. between. For example, the gap between the first gate dielectric layers 23 of two adjacent first transistors T1 is filled with the material of the first gate electrode 24, so that the first gate electrodes 24 are connected to each other and form an integrated structure. The overall structure of the first gate 24 of T1 is a honeycomb structure having a plurality of holes (the plurality of holes are arranged in a row along the first direction Z).

In this way, the first gates 24 of the plurality of first transistors T1 can be electrically connected to the same word line WL, which is beneficial to reducing the number of word lines WL and simplifying the structure of the memory array 100 .

In some embodiments of the present application, as shown in FIG. 6 , the memory cell subarray 2 further includes: a plurality of second transistors T2. The plurality of second transistors T2 are arranged in one column along the first direction Z. A second transistor T2 is located at the end of a row of memory cells MC. Along the second direction X, the first transistors T1 and the second transistors T2 corresponding to the row of memory cells MC are arranged in sequence. For example, the plurality of second transistors T2 described above correspond to the plurality of rows of memory cells MC in the memory cell sub-array 2 on a one-to-one basis.

In some examples, the second transistor T2 includes a second gate 25 , a second source 26 , and a second drain 27 . The second gate electrode 25 of each second transistor T2 is electrically connected to a selection signal line BS. One of the second source electrode 26 and the second drain electrode 27 of the second transistor T2 is located in the same row and adjacent to the second gate electrode 25 of the second transistor T2 . The first transistor T1 is electrically connected, and the other one of the second source electrode 26 and the second drain electrode 27 of the second transistor T2 is electrically connected to one bit line BL.

The equivalent circuit diagram shown in FIG. 7 illustrates a row of memory cells MC, a first transistor T1 corresponding to the row of memory cells MC, and a second transistor T2 corresponding to the row of memory cells MC. In Figure 7, the second transistor T2 is located at the right end of a row of memory cells MC and is electrically connected to the first transistor T1 located on the far right. The first transistor T1 located on the far right is electrically connected to the bit line BL through the second transistor T2. .

Here, the above-mentioned second transistor T2 can also be called a selection transistor. Among the second transistors T2 in the same column, different second transistors T2 are electrically connected to different selection signal lines BS and are electrically connected to different bit lines BL. During the operation of the memory cell sub-array 2, the operating state of the second transistor T2 in the same column can be controlled through the selection signals transmitted by different selection signal lines BS. For example, the level of the selection signal transmitted by one selection signal line BS is high level and controls the corresponding second transistor T2 to turn on. The level of the selection signal transmitted by the other selection signal lines BS is low level and controls the turning on of the corresponding second transistor T2. The corresponding second transistor T2 is turned off. In this way, when each word line WL transmits an electrical signal, the first transistor T1 and the memory cell MC of a row corresponding to each turned off second transistor T2 will not work, and the turned on second transistor T2 The corresponding first transistor T1 and memory cell MC of a row will work (for example, store data or read data).

By setting the second transistor T2, the operation of a certain row of memory cells MC in the memory cell sub-array 2 can be selectively controlled. When the first gate electrode 24 of the first transistor T1 corresponding to the memory cell MC in the same column is connected to form an integrated structure, interference between the memory cells MC in different rows can be avoided, ensuring that the memory cell sub-array 2 and the memory array 100 works fine.

In some examples, the second transistor T2 also includes a second channel layer 28 and a second gate dielectric layer. Two adjacent conductive blocks 211a located at the end of a row of memory cells MC respectively form a second source electrode 26 and a second drain electrode 27. A third insulating block 217 is disposed between the second source electrode 26 and the second drain electrode 27. . Wherein, at least part of the second channel layer 28 is located on the sidewall A of the stacked structure 21, the second gate dielectric layer covers the second channel layer 28, and the second gate electrode 25 is located on the second gate dielectric layer away from the second trench. One side of channel layer 28. That is to say, along the third direction Y and away from the sidewall A, the second channel layer 28 , the second gate dielectric layer and the second gate electrode 25 are stacked in sequence. The second gate dielectric layer separates the second gate electrode 25 and the second channel layer 28 to avoid contact between the second gate electrode 25 and the second channel layer 28. At the same time, the second gate electrode 25 and the stacked layer The conductive blocks 211a in the structure 21 are spaced apart to avoid a short circuit between the second gate 25 and the conductive block 211a.

As shown in FIG. 6 , the second channel layer 28 is in contact with the second source electrode 26 , the second drain electrode 27 and the third insulating block 217 . An ohmic contact is formed between the second channel layer 28 and the second source electrode 26 and the second drain electrode 27 .

In FIG. 6 , two adjacent conductive blocks 211a located at the rightmost end of a row of memory cells MC serve as the second source electrode 26 and the second drain electrode 27 of the second transistor T2 respectively. Here, for example, the rightmost memory cell MC can share a conductive block 211a with the second transistor T2, so that the rightmost memory cell MC (or the first transistor T1) can be electrically connected to the second transistor T2. Simplify the structure of the memory cell sub-array 2.

For example, the second channel layer 28, the second gate dielectric layer, and the second gate electrode 25 of the second transistor T2 can be respectively connected with the first channel layer 22, the first gate dielectric layer 23, and the first transistor T1. The first gate 24 is formed simultaneously, and the arrangement of the second channel 28 of the second transistor T2 may be the same as the arrangement of the first channel layer 22 of the first transistor T1. This is beneficial to simplifying the manufacturing process of the memory cell sub-array 2 and the memory array 100.

Based on the positional relationship between the second gate 25 and the second channel layer 28 in the second transistor T2, the structure of the second transistor T2 forms a transistor structure in which the channel is a vertical channel. Therefore, the second transistor T2 can It is called a vertical channel structure field effect transistor. Compared with horizontal channel transistors, the front projection area of the second transistor T2 on the substrate 1 is smaller, which can avoid affecting the storage density of the memory array 100 .

In some embodiments, the memory function layer 212 in the stacked structure 21 includes a ferroelectric material layer, a resistive switching layer material or a phase change material layer.

For example, the ferroelectric material layer includes a hafnium-based ferroelectric material (or HfO2-based ferroelectric material). Ferroelectric Material layer materials include but are not limited to ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, etc., or other elements based on this material (for example, HfO2) Doped materials and any combination thereof. The materials of the resistive material layer include but are not limited to NiOx, TaOx, TiOx, HfOx, WOx, ZrOx, AlyOx, SrTiOx, etc. The materials of the phase change material layer include but are not limited to GeTe alloy, Sb2Te5 alloy, Ge2Sb2Te5, etc.

In the above-mentioned Figures 5d, 8d, 9d, 10d, and 11d, the cross-sectional position of (a) in each drawing corresponds to the position of the memory unit MC, and the cross-section of (b) in each drawing The position corresponds to the position between two adjacent memory cells MC.

Some embodiments of the present application also provide a method for preparing a storage array. As shown in Figure 13, the preparation method includes: S100 to S300.

S100, provide substrate 1.

S200, form an initial stacked structure 21a on the substrate 1. The initial stacked structure 21a includes a plurality of conductive layers 211 and a plurality of memory function layers 212 stacked along the first direction Z. The conductive layer 211 includes a plurality of conductive blocks 211a arranged at intervals along the second direction X. A storage function layer 212 is provided between two adjacent conductive blocks 211a. The storage function layer 212 between 211a forms a storage unit. The first direction Z is perpendicular to the substrate 1 and the second direction X is parallel to the substrate 1 .

For example, the embodiment of the present application may use multiple processes such as deposition process, etching process, grinding process, etc. to form the initial stacked structure 21a. Among them, the deposition process includes but is not limited to Chemical Vapor Deposition (CVD) process, Physical Vapor Deposition (PVD) process, Atomic Layer Deposition (ALD) process or any combination thereof. thin film deposition process. The etching process includes but is not limited to photolithography process. Grinding processes include but are not limited to CMP (chemical mechanical polishing, chemical mechanical grinding or chemical mechanical polishing) processes.

Here, the structure of the initial stacked structure 21a is basically the same as the structure of the stacked structure 21 mentioned above. The initial stacked structure 21a is replaced by film layers (ie, the first sacrificial layer or the second sacrificial layer mentioned below). Then the laminated structure 21 can be obtained. Regarding the arrangement of the conductive layer 211, the conductive block 211a and the storage function layer 212 in the initial stacked structure 21a, please refer to the above description of the conductive layer 211, the conductive block 211a and the storage function layer 212 in the stacked structure 21, here No longer.

S300, form the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24. The first channel layer 22 corresponds to the memory cell MC. At least a part of the first channel layer 22 is located on the sidewall A of the initial stacked structure 21a and is connected to the two adjacent conductive blocks 211a and the memory cell MC. The functional layers 212 are in contact. The first gate dielectric layer 23 covers the first channel layer 22. The first gate electrode 24 is located on the side of the first gate dielectric layer 23 away from the first channel layer 22. The two adjacent conductive blocks 211a and the first channel layer 22. The first gate dielectric layer 23 and the first gate electrode 24 form the first transistor T1.

For example, the embodiment of the present application may use multiple processes such as deposition process and etching process to form any one of the first channel layer 22 , the first gate dielectric layer 23 and the first gate electrode 24 .

The first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 prepared in S300 have the same characteristics as the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 mentioned above. For the same structure and arrangement, please refer to the above description of the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24, and will not be described again here.

The memory array preparation method provided by the embodiments of the present application is used to prepare and form the memory array 100 described in any of the above embodiments. The beneficial effects achieved by this preparation method are the same as those achieved by the above memory array 100. The effect is the same and will not be described again here.

The above-mentioned initial stacked structure 21a corresponds to one memory cell sub-array 2. Since the memory array 100 includes a plurality of memory cell sub-arrays 2 located on the substrate 1, a plurality of initial stacked structures 21a are simultaneously formed on the substrate 1. The embodiment of the present application takes the preparation and formation of a memory cell sub-array 2 as an example to schematically illustrate the preparation method of the memory array.

In some embodiments of the present application, in the same memory cell MC, the positional relationship between two adjacent conductive blocks 211a and the memory functional layer 212 includes multiple types. Correspondingly, in the above S200, the initial stacked structure 21a is formed. The methods include many.

In some possible embodiments, two adjacent conductive blocks 211a in the same memory cell MC are located on the same conductive layer 211.

Based on this, as shown in FIGS. 14a to 14d , in the above S200 , forming an initial stacked structure 21 a on the substrate 1 includes: alternately forming the first composite layer 3 and the first sacrificial layer 4 on the substrate 1 .

Here, the film layer in contact with the substrate 1 is, for example, the first sacrificial layer 4 , and the film layer furthest away from the substrate 1 along the first direction Z is, for example, the first composite layer 3 .

For example, the first composite layer 3 and the first sacrificial layer 4 may have different etching selectivity ratios. In this way, in the subsequent process, the first composite layer 3 can be retained and the first sacrificial layer 4 can be removed to form a gap between any two adjacent first composite layers 3 to facilitate subsequent filling of the gap with insulating material.

Optionally, the material of the first sacrificial layer 4 includes, but is not limited to, silicon nitride, for example.

Exemplarily, forming the above-mentioned first composite layer 3 includes: S210a to S230a.

S210a, as shown in Figure 14a, the first conductive film D1 is formed.

For example, the embodiment of the present application may use a CVD process, a PVD process, an ALD process, or any combination thereof to form the first conductive film D1. The size of the first conductive film D1 in the second direction X is, for example, larger than the size in the third direction Y, so that the orthographic projection shape of the first conductive film D1 on the substrate 1 is a rectangle or a strip. The third direction Y is parallel to the substrate 1 , and the second direction X and the third direction Y are perpendicular.

S220a, as shown in FIG. 14b, the first conductive film D1 is etched to form a plurality of conductive blocks 211a sequentially spaced along the second direction X to obtain the conductive layer 211.

For example, the embodiment of the present application may use a photolithography process to etch the first conductive film D1 and disconnect the first conductive film D1 to obtain a plurality of conductive blocks 211a arranged at intervals. This step is called photolithography along the second direction X, for example.

S230a, as shown in FIG. 14c, a memory functional layer 212 is formed between two adjacent conductive blocks 211a. The two adjacent conductive blocks 211a in the same memory cell MC are located in the conductive layer 211 of the first composite layer 3.

For example, in the embodiment of the present application, a CVD process, a PVD process, an ALD process or any combination thereof can be used to form a storage function film on the conductive layer 211. A part of the storage function film is located on each conductive block 211a. A part is located between any two adjacent conductive blocks 211a; then the memory function film can be polished (or called surface planarization) using a grinding process such as CMP to remove the part located on each conductive block 211a, leaving the part located on any of the conductive blocks 211a. The portion between two adjacent conductive blocks 211a and the portion of the storage function film located between the two adjacent conductive blocks 211a constitute the storage function layer 212. Wherein, the conductive layer 211 can be As a stop layer for the grinding process, the surface flatness of the first composite layer 3 is improved.

Using the above preparation method, two adjacent conductive blocks 211a and the memory functional layer 212 in the same memory cell MC can be located on the same layer. In the prepared first composite layer 3, along the second direction They are electrically connected to each other through a common conductive block 211a.

In some examples, in the above S300, the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 are formed, including: S310a to S360a.

S310a, as shown in Figure 14e, the channel film E is formed. The channel film E covers at least the sidewalls of the initial stacked structure 21a.

For example, in embodiments of the present application, the channel film E may be formed using a CVD process, a PVD process, an ALD process, or any combination thereof.

For example, the channel film E has a planar shape as a whole and covers one side wall of the initial stacked structure 21a. As another example, the channel film E includes two planar parts covering two opposite side walls of the initial stacked structure 21a. As another example, as shown in (b) of FIG. 14e , the channel film E is in an inverted U shape as a whole, and the channel film E covers the two opposite side walls and the top wall of the initial stacked structure 21 a.

S320a, as shown in Figure 14f, a gate dielectric film F is formed. The gate dielectric film F covers the channel film E.

For example, in this embodiment, the gate dielectric film F may be formed using a CVD process, a PVD process, an ALD process, or any combination thereof. For example, the shape of the gate dielectric film F and the channel film E are the same, and the gate dielectric film F and the channel film E are arranged in the same manner.

Optionally, as shown in (b) in Figure 14f, the channel film E is in an inverted U-shape as a whole. Correspondingly, the gate dielectric film F is in an inverted U-shape as a whole and is located on the channel film E, covering the initial stack. The two opposite side walls and top wall of structure 21a.

S330a, as shown in Figure 14g, the gate film G is formed. The gate film G covers the gate dielectric film F.

For example, in this embodiment, the gate film G may be formed using a CVD process, a PVD process, an ALD process, or any combination thereof. For example, the shape of the gate film G is the same as the shape of the gate dielectric film F, and the gate film G and the gate dielectric film F (or the channel film E) are arranged in the same manner.

Optionally, as shown in (b) in Figure 14g, the gate dielectric film F is in an inverted U-shape as a whole. Correspondingly, the gate electrode film G is in an inverted U-shape as a whole and is located on the channel film E, covering the initial stack. The two opposite side walls and top wall of structure 21a.

The embodiment of the present application takes as an example that the shapes of the channel film E, the gate dielectric film F, and the gate film G are all inverted U shapes.

S340a, as shown in Figure 14h, the gate film G, the gate dielectric film F and the channel film E are etched to form an initial gate G1, an initial gate dielectric layer F1 and an initial channel layer extending along the first direction Z. E1.

For example, the embodiment of the present application can use a photolithography process to synchronously etch the gate film G, the gate dielectric film F and the channel film E, and disconnect the gate film G to obtain the gate film G, which is arranged at intervals along the second direction X. A plurality of initial gate electrodes G1 are cut off from the gate dielectric film F to obtain a plurality of initial gate dielectric layers F1 arranged at intervals along the second direction X. The channel film E is cut off to obtain a plurality of initial gate dielectric layers F1 arranged at intervals along the second direction X. multiple initial channel layers E1. This step is called photolithography along the second direction X, for example.

For example, the initial gate G1, initial gate dielectric layer F1 and initial channel layer E1 located at the same position have different shapes. are the same, and the orthographic projections of the three on substrate 1 coincide.

S350a, as shown in FIG. 14i, remove the first sacrificial layer 4 through the sidewalls of the initial stacked structure 21a that are not covered by the initial gate electrode G1, the initial gate dielectric layer F1, and the initial channel layer E1 to form the first gap H1. .

For example, in this embodiment of the present application, a selective wet etching process may be used to remove the first sacrificial layer 4 . After etching the gate film G, the gate dielectric film F and the channel film E, a part of the surface of the first sacrificial layer 4 will be covered by the initial channel layer E1, the initial gate dielectric layer F1 and the initial gate electrode G1. Part of the surface was exposed. The corrosive liquid can gradually corrode the first sacrificial layer 4 through the exposed part of the surface of the first sacrificial layer 4 until the first sacrificial layer 4 is completely removed, and the space occupied by the first sacrificial layer 4 forms the first gap H1.

Here, the first composite layer 3 , the initial gate G1 , the initial gate dielectric layer F1 and the initial channel layer E1 all have different etching selectivity ratios from the first sacrificial layer 4 . In this way, during the process of removing the first sacrificial layer 4, only the first sacrificial layer 4 can be removed to avoid corrosion of the first composite layer 3, the initial gate electrode G1, the initial gate dielectric layer F1 and the initial channel layer E1, and thus It is beneficial to ensure the structural integrity of the first composite layer 3, the initial gate electrode G1, the initial gate dielectric layer F1 and the initial channel layer E1.

S360a, as shown in FIG. 14j, the initial channel layer E1 is etched through the first gap H1, and the portion of the initial channel layer E1 opposite to the first gap H1 is removed.

For example, the embodiment of the present application may use a selective wet etching process to remove the portion of the initial channel layer E1 opposite to the first gap H1. The corrosive liquid can enter the first gap H1, and the portion of the initial channel layer E1 opposite to the first gap H1 can come into contact with the corrosive liquid and be removed. By controlling the etching time, removal of the portion of the initial channel layer E1 that is in contact with the first composite layer 3 can be avoided.

Here, the first composite layer 3 , the initial gate G1 and the initial gate dielectric layer F1 all have different etching selectivity ratios from the initial channel layer E1 . In this way, during the process of removing the portion of the initial channel layer E1 opposite to the first gap H1, only the initial channel layer E1 can be etched, avoiding the need to etch the first composite layer 3, the initial gate electrode G1 and the initial gate dielectric. The layer F1 forms corrosion, which is beneficial to ensuring the structural integrity of the first composite layer 3 , the initial gate electrode G1 and the initial gate dielectric layer F1 .

As shown in (b) of Figure 14j, after removing the portion of the initial channel layer E1 that is opposite to the first gap H1, the initial channel layer E1 can be disconnected to obtain multiple layers arranged at intervals along the first direction Z. a first channel pattern E2. Among them, along the first direction Z, a first channel pattern E2 farthest from the substrate 1 is located on the two opposite side and top surfaces of the first composite layer 3 farthest from the substrate 1, and the remaining first channels In the pattern E2, each first channel pattern E2 is located on one side of the corresponding first composite layer 3.

In some examples, two adjacent conductive blocks 211a in the first composite layer 3 and the memory function layer 212 located between the two adjacent conductive blocks 211a can be used as a memory unit MC, as obtained in the above step S360a. The first channel pattern E2 in contact with the memory cell MC can be used as the first channel layer 22, and the portion of the initial gate dielectric layer F1 opposite to the first channel layer 22 can be used as the first gate dielectric layer 23. , the portion of the initial gate G1 opposite to the first channel layer 22 can serve as the first gate 24 .

At this time, along the first direction Z, the first channel layer 22 farthest from the substrate 1 is located on both sides and the top surface of the memory cell MC, and the remaining first channel layers 22 include two first channel patterns. E2, each first channel pattern E2 is located on one side of the corresponding memory cell MC. The same applies to the first gate dielectric layer 23 and the first gate electrode 24 .

Moreover, along the first direction Z, the first gate dielectric layer 23 of the first transistor T1 in the same column has an integral structure, and the first gate electrode 24 has an integral structure.

Exemplarily, as shown in Figure 14k, after forming the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24, that is, after the above S360a, the preparation method further includes: in the first gap H1 is filled with insulating material to form the first insulating layer 213 .

For example, in this embodiment of the present application, the ALD process or any combination of thin film deposition processes may be used to backfill the insulating material in the first gap H1 to form the first insulating layer 213 .

After the first insulating layer 213 is formed, the structure formed by laminating the first composite layer 3 and the first insulating layer 213 is the stacked structure 21 .

In addition to occupying the space occupied by the first sacrificial layer 4, the first insulating layer 213 also occupies the space between two adjacent first channel layers 22, so as to separate the two adjacent first channel layers 22. This results in electrical insulation (or electrical isolation) between two adjacent first channel layers 22 .

In other examples, the initial gate electrode G1, the initial gate dielectric layer F1 and the initial channel layer E1 are all located on at least two opposite sidewalls of the initial stacked structure 21a. As shown in FIG. 15 a , before the above S350 , that is, through the sidewalls in the initial stacked structure 21 a that are not covered by the initial gate electrode G1 , the initial gate dielectric layer F1 and the initial channel layer E1 , the first sacrificial layer is removed. 4 before, it also includes: etching at least the initial stacked structure 21a along the first direction Z and along the second direction X to form a first initial stacked structure 21a-1 and a second initial stacked structure 21a arranged oppositely. -2. The initial gate G1, the initial gate dielectric layer F1 and the initial channel layer E1 are all divided into two parts, one part of which is located on the sidewall of the first initial stacked structure 21a-1, and the other part is located on the second on the side walls of the initial stacked structure 21a-2.

Exemplarily, the first initial stacked structure 21a-1 and the second initial stacked structure 21a-2 are symmetrical to each other, the two parts of the initial gate G1 are symmetrical to each other, the two parts of the initial gate dielectric layer F1 are symmetrical to each other, and the initial channel The two parts of layer E1 are symmetrical to each other.

As shown in Figure 15b and Figure 15c, there is a gap between the first initial stacked structure 21a-1 and the second initial stacked structure 21a-2, so that in S350, the first initial stacked layer can pass through the gap and the first initial stacked structure 21a-2. Remove the first sacrificial layer 4 from the sidewalls of the structure 21a-1 and the second initial stacked structure 21a-2 that are not covered by the initial gate electrode G1, the initial gate dielectric layer F1 and the initial channel layer E1, and remove the initial channel The portion of layer E1 opposite to the first gap H1. Among them, the contact area between the corrosive liquid and the first sacrificial layer 4 is increased, which is beneficial to increasing the removal rate of the first sacrificial layer 4 .

Exemplarily, as shown in Figure 15d, after the above S360a, the preparation method further includes: filling the first gap H1 with an insulating material to form the first insulating layer 213. In addition to occupying the space occupied by the first sacrificial layer 4 , the first insulating layer 213 also occupies the space between two adjacent channel patterns, as well as the above-mentioned gap.

After the first insulating layer 213 is formed, the first initial stacked structure 21a-1 and the second initial stacked structure 21a-2 can respectively serve as a stacked structure 21. Each first channel pattern E2 obtained in the above S360a can serve as a first channel layer 22.

At this time, along the first direction Z, the first channel layer 22 farthest from the substrate 1 is located on one side and top surface of the memory cell MC, and the remaining first channel layers 22 include a first channel pattern E2, The first channel pattern E2 is located on one side of the corresponding memory cell MC. The same applies to the first gate dielectric layer 23 and the first gate electrode 24 .

In other examples, two adjacent conductive blocks 211a in the first composite layer 3 and the memory function layer 212 located between the two adjacent conductive blocks 211a serve as a memory unit MC. In the above S300, the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 are formed, which also includes: S370a to S31000a.

S370a, as shown in FIG. 16a, the initial gate dielectric layer F1 is etched through the first slit H1, and the portion of the initial gate dielectric layer F1 opposite to the first slit H1 is removed to form a first gate dielectric pattern F2.

For example, the embodiment of the present application may use a selective wet etching process to remove the portion of the initial gate dielectric layer F1 opposite to the first gap H1. The corrosive liquid can enter the first gap H1, and the portion of the initial gate dielectric layer F1 opposite to the first gap H1 can come into contact with the corrosive liquid and be removed. By controlling the etching time, it is possible to avoid removing the portion of the initial gate dielectric layer F1 that is in contact with the first channel pattern E2.

Here, the first composite layer 3 , the initial gate electrode G1 and the first channel pattern E2 all have different etching selectivity ratios from the initial gate dielectric layer F1 . In this way, during the process of removing the portion of the initial gate dielectric layer F1 opposite to the first gap H1, only the initial gate dielectric layer F1 can be etched, avoiding the need to etch the first composite layer 3, the initial gate electrode G1 and the first trench. The channel pattern E2 forms corrosion, which is beneficial to ensuring the structural integrity of the first composite layer 3 , the initial gate electrode G1 and the first channel pattern E2 .

As shown in (b) of Figure 16a, after removing the portion of the initial gate dielectric layer F1 that is opposite to the first gap H1, the initial gate dielectric layer F1 can be disconnected to obtain a plurality of layers arranged at intervals along the first direction Z. a first gate dielectric pattern F2. The shapes of the first gate dielectric pattern F2 and the first channel pattern E2 contacting the first gate dielectric pattern F2 are the same or substantially the same, and the orthographic projection areas of the two on a plane perpendicular to the third direction Y are the same or substantially the same.

S380a, as shown in FIG. 16b, deposit the material of the first channel layer 22 in the first gap H1 to form the second channel pattern E3. The first channel pattern E2 and the second channel pattern E3 form the first channel. Layer 22. Along the first direction Z and along the third direction Y, the cross-sectional pattern of the first channel layer 22 is annular. The first channel layer 22 surrounds the memory cell MC. The third direction Y is parallel to the substrate 1 and perpendicular to the second direction Y. Direction X.

For example, the embodiment of the present application may use the ALD process or any combination of thin film deposition processes to backfill the material of the first channel layer 22 in the first gap H1 to form the second channel pattern E3.

As shown in (b) of FIG. 16b , the material of the first channel layer 22 will be deposited on the top surface and/or the bottom surface of each memory cell MC to form the second channel pattern E3, so that the material of the first channel layer 22 is located on the top surface and/or bottom surface of each memory cell MC. The two first channel layers 22 on the two side surfaces are connected to the second channel pattern E3 to form the first channel layer 22 . The first channel layer 22 has a tubular shape as a whole and surrounds the memory cell MC located inside the first channel layer 22 .

S390a, as shown in FIG. 16c, deposit the material of the first gate dielectric layer 23 in the first gap H1 to form the second gate dielectric pattern F3. The first gate dielectric pattern F2 and the second gate dielectric pattern F3 form the first gate dielectric. Layer 23. Along the first direction Z and along the third direction Y, the cross-sectional pattern of the first gate dielectric layer 23 is annular, and the first gate dielectric layer 23 surrounds the first channel layer 22 .

For example, the embodiment of the present application can use the ALD process or any combination of thin film deposition processes to backfill the material of the first gate dielectric layer 23 in the first gap H1 to form the second gate dielectric pattern F3.

As shown in (b) of FIG. 16c , the material of the first gate dielectric layer 23 will be deposited on the top and/or bottom surface of the first channel layer 22 , that is, on the surface of the second channel pattern E3 , forming the second gate dielectric pattern F3 such that the two first gate dielectric patterns F2 located on both sides of each first channel layer 22 are connected to the second gate dielectric pattern F3 to form the first gate dielectric layer 23 . The first gate dielectric layer 23 is in a tubular shape as a whole and surrounds the first channel layer 22 located inside the first gate dielectric layer 23 .

S3100a, as shown in FIG. 16d, deposit the material of the first gate 24 in the first gap H1 to form the first gate pattern G2. The first gate pattern G2 and the initial gate G1 are located on opposite sides of the same memory cell MC. The first gate electrode 24 is formed on the side portion. Along the first direction Z and along the third direction Y, the cross-sectional pattern of the first gate electrode 24 is annular, and the first gate electrode 24 surrounds the first gate dielectric layer 23 .

For example, the embodiment of the present application may use the ALD process or any combination of thin film deposition processes to backfill the material of the first gate 24 in the first gap H1 to form the first gate pattern G2.

For example, the material of the first gate electrode 24 will be deposited on the top surface and/or the bottom surface of the first gate dielectric layer 23, that is, deposited on the surface of the first gate electrode pattern G2, to form the first gate electrode pattern G2, so that The portions of the initial gate G1 located on opposite sides of the same memory cell MC are connected to the first gate pattern G2 to form the first gate 24 . The first gate electrode 24 is in a tubular shape as a whole and surrounds the first gate dielectric layer 23 located inside the first gate electrode 24 . The material of the first gate 24 does not fill the first gap H1. Further, the insulating material can be backfilled in the first gap H1.

For another example, the material of the first gate electrode 24 fills the first gap H1, and along the first direction Z, two adjacent first gate electrodes 24 share a first gate electrode pattern G2.

The first transistor T1 obtained in the above step S3100a is a transistor with a full gate structure.

As shown in Figure 16e, after the above-mentioned S3100a, the preparation method further includes: filling the first gap H1 with an insulating material to form the first insulating layer 213.

In other possible embodiments, two adjacent conductive blocks 211a in the same memory cell MC are respectively located on two adjacent conductive layers 211.

Based on this, as shown in FIG. 17 g and FIG. 18 d, in the above-mentioned S200 , forming an initial stacked structure 21 a on the substrate 1 includes: alternately forming the second composite layer 5 and the second sacrificial layer 6 on the substrate 1 .

Here, the film layer in contact with the substrate 1 is, for example, the second sacrificial layer 6 , and the film layer furthest away from the substrate 1 along the first direction Z is, for example, the second composite layer 5 .

For example, the second composite layer 5 and the second sacrificial layer 6 may have different etching selectivity ratios. In this way, in the subsequent process, the second composite layer 5 can be retained and the second sacrificial layer 6 can be removed to form a gap between any two adjacent second composite layers 5 to facilitate subsequent filling of the gap with insulating material.

Optionally, the material of the second sacrificial layer 6 includes, but is not limited to, silicon nitride, for example.

Exemplarily, forming the above-mentioned second composite layer 5 includes: S210b to S250b.

S210b, as shown in Figure 17a, a second conductive film D2 is formed.

For example, embodiments of the present application may use a CVD process, a PVD process, an ALD process, or any combination thereof to form the second conductive film D2. The size of the second conductive film D2 in the second direction X is, for example, larger than the size in the third direction Y, so that the orthographic projection shape of the second conductive film D2 on the substrate 1 is a rectangle or a strip.

S220b, as shown in FIG. 17b, the second conductive film D2 is etched to form a plurality of conductive blocks 211a arranged at intervals along the second direction X to obtain a conductive layer 211.

For example, the embodiment of the present application may use a photolithography process to etch the second conductive film D2 and break the second conductive film D2 to obtain a plurality of conductive blocks 211a arranged at intervals. This step is called photolithography along the second direction X, for example.

S230b, as shown in FIG. 17c, form a storage function layer 212 on the plurality of conductive blocks 211a.

For example, before forming the storage function layer 212, the embodiment of the present application may use a CVD process or a PVD process. The thin film deposition process of the process, ALD process or any combination thereof forms an insulating film on the above-mentioned plurality of conductive blocks 211a. A part of the insulating film is located on each conductive block 211a, and the other part is located between any two adjacent conductive blocks 211a. ;Then the insulating film can be polished (or surface planarized) using a grinding process such as CMP to remove the portion located on each conductive block 211a and retain the portion located between any two adjacent conductive blocks 211a. A portion of the storage function layer between two adjacent conductive blocks 211a constitutes the first insulating block 214; then a CVD process, a PVD process, an ALD process or any combination of thin film deposition processes can be used to deposit on the above-mentioned plurality of conductive blocks 211a. A storage function layer 212 is formed.

Among them, the conductive layer 211 can be used as a stop layer for the grinding process to improve the surface flatness of the conductive layer 211 so as to improve the flatness of the storage function layer 212. The storage function layer 212 covers the plurality of conductive blocks 211a and the plurality of first insulating blocks 214.

S240b, as shown in FIG. 17d, form a third conductive film D3 on the storage function layer 212.

For example, embodiments of the present application may use a CVD process, a PVD process, an ALD process, or any combination thereof to form the third conductive film D3. For example, the orthographic projection of the third conductive film D3 on the substrate 1 coincides with the orthographic projection of the second conductive film D2 on the substrate 1 .

S250b, as shown in Figures 17e and 18c, the third conductive film D3 is etched to form a plurality of conductive blocks 211a spaced apart in sequence along the second direction X to obtain a conductive layer 211. Along the first direction Z, two adjacent conductive blocks 211a in the same memory cell MC are respectively located in two adjacent conductive layers 211 in the second composite layer 5, and the two adjacent conductive blocks 211a are on the substrate 1. Orthographic projections overlap.

Illustratively, as shown in Figures 17f and 18c, after etching the third conductive film D3, embodiments of the present application can use a CVD process, a PVD process, an ALD process or any combination thereof to form a film deposition process on the above-mentioned multiple layers. An insulating film is formed on each conductive block 211a. Part of the insulating film is located on each conductive block 211a, and the other part is located between any two adjacent conductive blocks 211a; then the insulating film can be polished using a grinding process such as CMP (or (called surface planarization treatment), remove the part located on each conductive block 211a, and retain the part located between any two adjacent conductive blocks 211a. The part of the insulating film located between two adjacent conductive blocks 211a constitutes First insulating block 214.

Two adjacent conductive layers 211 , the memory function layer 212 located between the two adjacent conductive layers 211 , and the first insulating block 214 located in each conductive layer 211 constitute the second composite layer 5 .

The above-mentioned storage function layer 212 is in a planar shape, which can effectively reduce the number of photomasks and reduce the cost of the storage array preparation method.

In some examples, as shown in FIGS. 18a and 18b , before the above S240b, that is, before forming the third conductive film D3 on the storage function layer 212, the preparation method further includes: forming an edge on the plurality of conductive blocks 211a. A plurality of second insulating blocks 216 are arranged at intervals along the second direction X to form a storage function layer 212 between two adjacent second insulating blocks 216. The plurality of storage function layers 212 are arranged at intervals along the second direction X.

Among the two adjacent conductive layers 211 in the second composite layer 5, the conductive block 211a located in one of the conductive layers 211 is the first conductive block 211a-1, and the conductive block 211a located in the other conductive layer 211 is the second conductive block 211a-1. Conductive block 211a-2. In the orthographic projection of two adjacent conductive layers 211 on the substrate 1, along the second direction X, a plurality of first conductive blocks 211a-1 and a plurality of second conductive blocks 211a-2 are arranged alternately. Along the first direction Z, one first conductive block 211a-1 and two second conductive blocks 211a-2 overlap, and one first conductive block 211a-1 and two memory function layers 212 overlap.

For example, the embodiment of the present application can use a CVD process, a PVD process, an ALD process or any combination of film deposition processes to form an insulating film on the plurality of conductive blocks 211a, and use a photolithography process to etch the insulating film. A plurality of second insulating blocks 216 are formed; then, the embodiment of the present application can use a CVD process, a PVD process, an ALD process or a film deposition process of any combination thereof to form a storage function film on the plurality of second insulating blocks 216. The storage function A part of the film is located on each second insulating block 216, and the other part is located between any two adjacent second insulating blocks 216; the memory function film can then be polished (or called surface planarized) using a grinding process such as CMP. ), remove the part located on each second insulating block 216, and retain the part located between any two adjacent second insulating blocks 216. The part of the storage function film located between two adjacent second insulating blocks 216 constitutes Storage functional layer 212.

Regarding the arrangement of the first conductive block 211a-1, the second conductive block 211a-2 and the storage function layer 212 in the second composite layer 5, please refer to the above description and will not be described again here.

In some examples, in the above S300, the first channel layer 22, the first gate dielectric layer 23 and the first gate electrode 24 are formed, including: S310b to S370b.

S310b, form a channel film E, which covers at least the sidewalls of the initial stacked structure 21a.

S320b: Form a gate dielectric film F, and the gate dielectric film F covers the channel film E.

S330b: Form a gate film G, and the gate film G covers the gate dielectric film F.

S340b: Etch the gate film G, the gate dielectric film F, and the channel film E to form an initial gate G1, an initial gate dielectric layer F1, and an initial channel layer E1 extending along the first direction Z.

S350b: Remove the second sacrificial layer 6 through the sidewalls of the initial stacked structure 21a that are not covered by the initial gate electrode G1, the initial gate dielectric layer F1, and the initial channel layer E1 to form a second gap.

S360b, etch the initial channel layer E1 through the second slit, remove the portion of the initial channel layer E1 that is opposite to the second slit, and form a plurality of first channel layers 22 spaced apart in the first direction Z. .

The above steps in S310b to S360b are basically the same as the corresponding steps in S310a to S360a in some of the above examples. For details, please refer to the description of the corresponding steps in S310a to S360a in some of the above examples, which will not be described again here.

S370b: Fill the second gap with insulating material to form the second insulating layer 215.

For example, the embodiment of the present application may use the ALD process or any combination of thin film deposition processes to backfill the insulating material in the second gap H2 to form the second insulating layer 215 . After executing the above steps S310b to S370b, the obtained structure is as shown in Figures 11a to 12d.

In some embodiments, the second transistor T2 can be manufactured and formed simultaneously with the first transistor T1, and the manufacturing method of the second transistor T2 will not be described again.

In the above-mentioned Figures 14a to 17g, (a) in each figure represents a front view of the structure obtained by the corresponding step, and (b) in each figure represents the structure obtained by the corresponding step along the first direction Z and along the first direction Z. Cross-sectional view in the third direction Y.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that come to mind within the technical scope disclosed by the present disclosure by any person familiar with the technical field should be covered. within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A memory array, characterized in that the memory array includes: a substrate and a plurality of memory cell sub-arrays located on the substrate;

The memory cell subarray includes:

A laminated structure, the laminated structure includes a plurality of conductive layers and a plurality of storage function layers stacked along a first direction, the conductive layer includes a plurality of conductive blocks spaced apart along the second direction, two adjacent conductive blocks The storage function layer is arranged between the blocks, and the two adjacent conductive blocks and the storage function layer located between the two adjacent conductive blocks form a memory unit; the first direction is perpendicular to the substrate , the second direction is parallel to the substrate;

A first channel layer corresponding to the memory cell, at least part of the first channel layer is located on the sidewall of the stacked structure, and is connected to two adjacent conductive blocks in the memory cell and The storage function layers are in contact;

a first gate dielectric layer covering the first channel layer; and,

a first gate located on the side of the first gate dielectric layer away from the first channel layer; the two adjacent conductive blocks and the first channel layer, the first gate dielectric layer, The first gate forms a first transistor.
The memory array according to claim 1, wherein two adjacent conductive blocks in the memory unit are located on the same conductive layer;

Along the second direction, the storage function layer in the memory unit is located between the two adjacent conductive blocks.
The memory array according to claim 2, wherein in the same conductive layer, the conductive blocks and the storage functional layers are alternately arranged along the second direction.
The memory array according to claim 2, wherein the stacked structure further includes a plurality of first insulating layers, and along the first direction, the multi-layer conductive layer and the multi-layer first insulating layer Alternate settings.
The memory array according to claim 1, wherein two adjacent conductive blocks in the memory unit are respectively located on two adjacent conductive layers, and the two adjacent conductive blocks are on the substrate. orthographic projections overlap;

Along the first direction, the storage function layer in the memory unit is located between the two adjacent conductive blocks.
The memory array according to claim 5, wherein among the two adjacent conductive layers, the conductive block located on one of the conductive layers is the first conductive block, and the conductive block located on the other conductive layer is the third conductive block. two conductive blocks;

In the orthographic projection of the two adjacent conductive layers on the substrate, along the second direction, a plurality of the first conductive blocks and a plurality of the second conductive blocks are alternately arranged;

Along the first direction, one first conductive block and two second conductive blocks overlap, and one first conductive block and two storage function layers overlap.
The memory array according to claim 5, wherein the stacked structure further includes a plurality of first insulating blocks, and in the same conductive layer, along the second direction, a plurality of the conductive blocks and a plurality of first insulating blocks are The first insulating blocks are arranged alternately.
The memory array according to claim 5, wherein the memory cell sub-array includes multiple rows of memory cells, and each row of memory cells includes a plurality of the memory cells arranged along the second direction;

The stacked structure further includes a plurality of second insulating layers, and the second insulating layers are located between two adjacent rows of memory cells.
The memory array according to claim 5, wherein the memory cell sub-array includes multiple rows of memory cells, and each row of memory cells includes a plurality of the memory cells arranged along the second direction;

The stacked structure also includes a plurality of second insulating blocks. In the same row of memory units, the plurality of memory units are Storage functional layers and a plurality of second insulating blocks are alternately arranged; or,

In the same row of storage units, the storage function layers of multiple storage units are connected and form an integrated structure.
The memory array according to claim 1, wherein the memory cell sub-array includes a plurality of columns of memory cells, each column of memory cells includes a plurality of the memory cells stacked along the first direction;

In the same column of memory cells, the orthographic projections of the storage function layers of any two memory cells on the substrate at least partially overlap.
The memory array according to claim 1, wherein a plurality of the stacked structures are arranged in sequence along a third direction, the third direction is parallel to the substrate and perpendicular to the second direction; The laminated structure has opposite first side walls and second side walls;

The plurality of laminated structures includes at least one laminated structure pair, the laminated structure pair includes an adjacent first laminated structure and a second laminated structure, and the first side wall of the first laminated structure is located at A side away from the second laminated structure, the second side wall of the second laminated structure is located on a side away from the first laminated structure;

The first channel layer, the first gate dielectric layer and the first gate electrode of the first transistor corresponding to the memory cell in the first stacked structure are located on the first sidewall of the first stacked structure, and The first channel layer, first gate dielectric layer and first gate electrode of the first transistor corresponding to the memory unit in the second stacked structure are located on the second sidewall of the second stacked structure.
The memory array according to claim 1, wherein the stacked structure has opposite first sidewalls and second sidewalls;

In the first transistor corresponding to the memory cell in the stacked structure, a part of the first channel layer, a part of the first gate dielectric layer and a part of the first gate electrode are located on the first On the sidewall, another part of the first channel layer, another part of the first gate dielectric layer and another part of the first gate are located on the second sidewall.
The memory array according to any one of claims 1 to 12, wherein the memory cell sub-array includes multiple columns of memory cells, and each column of memory cells includes a plurality of the memory cells arranged sequentially along the first direction. storage unit;

Along the first direction and the second direction, the first channel layers of two adjacent first transistors are separated from each other;

The first gate dielectric layers of the plurality of first transistors corresponding to the same column of memory cells are connected and located on the sidewalls of the stacked structure;

The first gates of the plurality of first transistors corresponding to the same column of memory cells are connected and located on the sidewalls of the stacked structure.
The memory array according to claim 13, wherein in the first transistor farthest from the substrate along the first direction, the first channel layer, the first gate dielectric layer and the The first gate also covers the top wall of the stacked structure.
The memory array according to claim 1, wherein in the first transistor corresponding to each of the memory cells, along the first direction and along the third direction, the first channel layer, the third The cross-sectional pattern of a gate dielectric layer and the first gate electrode is annular, the first channel layer surrounds the memory unit, the first gate dielectric layer surrounds the first channel layer, and the first The gate electrode surrounds the first gate dielectric layer;

The third direction is parallel to the substrate and perpendicular to the second direction.
The memory array according to claim 15, wherein the memory cell sub-array includes a plurality of Column memory cells, each column of memory cells including a plurality of the memory cells stacked along the first direction;

The first gates of the plurality of first transistors corresponding to the same column of memory cells are connected and located between the sidewalls of the stacked structure and two adjacent first gate dielectric layers.
The memory array according to claim 1, wherein at least two of the memory cell sub-arrays are arranged in sequence along the second direction, and at least two of the memory cell sub-arrays are arranged in sequence along the third direction;

The third direction is parallel to the substrate and perpendicular to the second direction.
The memory array according to claim 17, wherein at least two of the memory cell sub-arrays are arranged sequentially along the first direction;

The memory array further includes an encapsulation layer, and the encapsulation layer is located between two adjacent memory cell sub-arrays along the first direction.
The memory array according to claim 1, wherein the memory cell sub-array includes multiple rows of memory cells, and each row of memory cells includes a plurality of the memory cells arranged along the second direction;

The memory cell subarray further includes: a plurality of second transistors, the second transistors are located at the ends of a row of memory cells, the plurality of second transistors are arranged in a column along the first direction; the second transistors Includes a second source electrode, a second drain electrode, a second channel layer, a second gate dielectric layer and a second gate electrode;

Two adjacent conductive blocks located at the end of the row of memory cells respectively form the second source electrode and the second drain electrode, and a third source electrode and the second drain electrode are provided between the second source electrode and the second drain electrode. insulating block;

At least part of the second channel layer is located on the sidewall of the stacked structure and is in contact with the second source electrode, the second drain electrode, and the third insulating block;

The second gate dielectric layer covers the second channel layer;

The second gate electrode is located on a side of the second gate dielectric layer away from the second channel layer.
The storage array according to claim 1, wherein the storage functional layer includes a ferroelectric material layer, a resistive switching layer material or a phase change material layer.
A method for preparing a storage array, characterized in that the preparation method includes:

provide a substrate;

An initial stacked layer structure is formed on the substrate, the initial stacked layer structure includes multiple conductive layers and multiple storage function layers stacked along a first direction; the conductive layer includes a plurality of conductive layers arranged at intervals along the second direction. A plurality of conductive blocks, the storage function layer is disposed between two adjacent conductive blocks, the two adjacent conductive blocks and the storage function layer located between the two adjacent conductive blocks form a memory unit; The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate;

Forming a first channel layer, a first gate dielectric layer and a first gate, the first channel layer corresponding to the memory cell, at least a part of the first channel layer located in the initial stacked structure on the sidewalls and in contact with two adjacent conductive blocks and the storage functional layer in the memory unit; the first gate dielectric layer covers the first channel layer; the first gate is located at the The side of the first gate dielectric layer away from the first channel layer is formed by the two adjacent conductive blocks, the first channel layer, the first gate dielectric layer and the first gate electrode. The first transistor.
The preparation method according to claim 21, characterized in that forming an initial stacked structure on the substrate includes:

alternately forming first composite layers and first sacrificial layers on the substrate;

Forming the first composite layer includes:

forming a first conductive film;

Etching the first conductive film to form a plurality of conductive blocks arranged at intervals along the second direction to obtain the conductive layer;

The memory function layer is formed between two adjacent conductive blocks, and the two adjacent conductive blocks in the same memory unit are located in the conductive layer of the first composite layer.
The preparation method according to claim 22, wherein forming the first channel layer, the first gate dielectric layer and the first gate electrode includes:

Forming a channel film that covers at least the sidewalls of the initial stacked structure;

Forming a gate dielectric film covering the channel film;

Forming a gate film that covers the gate dielectric film;

Etch the gate electrode film, the gate dielectric film and the channel film to form an initial gate electrode, an initial gate dielectric layer and an initial channel layer extending along the first direction;

Through the sidewalls in the initial stacked structure that are not covered by the initial gate, the initial gate dielectric layer and the initial channel layer, the first sacrificial layer is removed to form a first gap;

The initial channel layer is etched through the first slit to remove the portion of the initial channel layer opposite to the first slit.
The preparation method according to claim 23, characterized in that the initial gate, the initial gate dielectric layer and the initial channel layer are located at least on two opposite sidewalls of the initial stacked structure;

Before removing the first sacrificial layer through the partial sidewalls in the initial stacked structure that are not covered by the initial gate, the initial gate dielectric layer and the initial channel layer, the method further includes:

Along the first direction and along the second direction, at least the initial stacked structure is etched to form a first initial stacked structure and a second initial stacked structure oppositely arranged, the gate, the The initial gate dielectric layer and the initial channel layer are divided into two parts, one part of which is located on the sidewall of the first initial stacked structure, and the other part is located on the second initial stacked layer on the side walls of the structure.
The preparation method according to claim 23 or 24, characterized in that, after forming the first channel layer, the first gate dielectric layer and the first gate electrode, the preparation method further includes:

Fill the first gap with an insulating material to form a first insulating layer.
The preparation method according to claim 23, characterized in that the initial gate, the initial gate dielectric layer and the initial channel layer are located at least on two opposite sidewalls of the initial stacked structure; After etching the initial channel layer through the first gap, a first channel pattern is obtained;

The forming the first channel layer, the first gate dielectric layer and the first gate further includes:

Etching the initial gate dielectric layer through the first slit to remove a portion of the initial gate dielectric layer opposite to the first slit to form a first gate dielectric pattern;

Deposit the material of the first channel layer in the first gap to form a second channel pattern, and the first channel pattern and the second channel pattern form the first channel layer; along The first direction and along the third direction, the cross-sectional pattern of the first channel layer is annular, the first channel layer surrounds the memory unit, the third direction is parallel to the substrate, and perpendicular to the second direction;

Deposit the material of the first gate dielectric layer in the first gap to form a second gate dielectric pattern, and the first gate dielectric pattern and the second gate dielectric pattern form the first gate dielectric layer; along the first direction and along the In the third direction, the cross-sectional pattern of the first gate dielectric layer is annular, and the first gate dielectric layer surrounds the first channel layer;

Deposit the material of the first gate electrode in the first gap to form a first gate electrode pattern. The first gate electrode pattern and the portions of the initial gate electrode located on opposite sides of the same memory cell form the first gate electrode pattern. A first gate electrode; along the first direction and along the third direction, the cross-sectional pattern of the first gate electrode is annular, and the first gate electrode surrounds the first gate dielectric layer.
The preparation method according to claim 21, characterized in that forming an initial stacked structure on the substrate includes:

alternately forming second composite layers and second sacrificial layers on the substrate;

Forming the second composite layer includes:

forming a second conductive film;

Etching the second conductive film to form a plurality of conductive blocks arranged at intervals along the second direction to obtain a conductive layer;

forming a storage function layer on the plurality of conductive blocks;

forming a third conductive film on the storage function layer;

The third conductive film is etched to form a plurality of conductive blocks arranged at intervals along the second direction to obtain a conductive layer; along the first direction, adjacent conductive blocks in the same memory unit are formed. The two conductive blocks are respectively located on two adjacent conductive layers in the second composite layer, and the orthographic projections of the two adjacent conductive blocks on the substrate overlap.
The preparation method according to claim 27, wherein forming a storage functional layer on the plurality of conductive blocks includes:

forming a plurality of second insulating blocks sequentially spaced along the second direction on the plurality of conductive blocks;

A storage function layer is formed between two adjacent second insulating blocks, and a plurality of the storage function layers are sequentially spaced along the second direction; among the two adjacent conductive layers in the second composite layer , the conductive block located on one of the conductive layers is the first conductive block, and the conductive block located on the other conductive layer is the second conductive block; in the orthographic projection of the two adjacent conductive layers on the substrate, Along the second direction, a plurality of the first conductive blocks and a plurality of the second conductive blocks are alternately arranged; along the first direction, one first conductive block and two second conductive blocks Overlap, and one first conductive block and two storage function layers overlap.
The preparation method according to claim 27, wherein forming the first channel layer, the first gate dielectric layer and the first gate electrode includes:

Forming a channel film that covers at least the sidewalls of the initial stacked structure;

Forming a gate dielectric film covering the channel film;

Forming a gate film that covers the gate dielectric film;

Etch the gate electrode film, the gate dielectric film and the channel film to form an initial gate electrode, an initial gate dielectric layer and an initial channel layer extending along the first direction;

Through the sidewalls in the initial stacked structure that are not covered by the initial gate, the initial gate dielectric layer and the initial channel layer, remove the second sacrificial layer to form a second gap;

The initial channel layer is etched through the second slit, and a portion of the initial channel layer opposite to the second slit is removed to form a plurality of third channels spaced apart in the first direction. a channel layer;

Fill the second gap with insulating material to form a second insulating layer.
A memory, characterized in that the memory includes: a controller, and the storage array according to any one of claims 1 to 20.
An electronic device, characterized in that the electronic device includes: a processor, and a memory as claimed in claim 30;

Wherein, the memory is used to store data generated by the processor.