WO2024036517A1 - 一种交叉链接方法、装置，电子设备及存储介质 - Google Patents

一种交叉链接方法、装置，电子设备及存储介质 Download PDF

Info

Publication number
WO2024036517A1
WO2024036517A1 PCT/CN2022/113080 CN2022113080W WO2024036517A1 WO 2024036517 A1 WO2024036517 A1 WO 2024036517A1 CN 2022113080 W CN2022113080 W CN 2022113080W WO 2024036517 A1 WO2024036517 A1 WO 2024036517A1
Authority
WO
WIPO (PCT)
Prior art keywords
address
library function
register address
operation instruction
mapping table
Prior art date
Application number
PCT/CN2022/113080
Other languages
English (en)
French (fr)
Inventor
于亭亭
张珂
林舒晞
Original Assignee
芯原微电子(上海)股份有限公司
芯原微电子（成都）有限公司
芯原微电子(南京)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 芯原微电子(上海)股份有限公司, 芯原微电子（成都）有限公司, 芯原微电子(南京)有限公司 filed Critical 芯原微电子(上海)股份有限公司
Priority to EP22925229.1A priority Critical patent/EP4350504A4/en
Priority to CN202280003641.5A priority patent/CN117916710A/zh
Priority to KR1020237042129A priority patent/KR20240025509A/ko
Priority to PCT/CN2022/113080 priority patent/WO2024036517A1/zh
Publication of WO2024036517A1 publication Critical patent/WO2024036517A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/54—Link editing before load time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/47—Retargetable compilers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/76—Adapting program code to run in a different environment; Porting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G06F9/45516—Runtime code conversion or optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44536—Selecting among different versions
    • G06F9/44542—Retargetable

Definitions

  • the present application relates to the field of computer technology, specifically, to a cross-linking method, device, electronic equipment and storage medium.
  • the compilation and linking process is the process of converting a high-level language program (source code) into a program (executable code or machine code) that can be run on hardware. It includes two main steps: compilation and linking. Compilation is the process of translating high-level language source code into intermediate code (object file); linking is the process of organizing object files and used library files (including library functions) to form the final generated executable code.
  • the compiler can include a 64-bit compiler and a 32-bit compiler.
  • some programs may be generated by the 32-bit front end.
  • some programs have this kind of complexity caused by 64-bit front ends.
  • the current linker cannot solve the correctness of the machine code generated in this case during cross-linking, which makes The staff had to upgrade all library functions to 64-bit, which required that all compilers that generate library functions must be upgraded to 64-bit, which brought a huge amount of engineering work to the staff. It can be seen that the current compilation and linking process cannot achieve cross-linking of programs with different digits without upgrading library functions.
  • the purpose of the embodiments of the present application is to provide a cross-linking method, device, electronic equipment and storage medium to realize cross-linking of programs with different address digits.
  • embodiments of the present application provide a cross-linking method, which includes: when a register address in a first operation instruction of a library function hits a preset mapping table, modifying the register address in the first operation instruction. ;
  • the mapping table includes the mapping relationship between the target register address of the main program and the register address of the library function; the target register address of the main program is promoted to the first address digit; the operation of the library function
  • the register address in the instruction is the second address digit; the first address digit is greater than the second address digit; the register address in the modified first operation instruction is the target register address of the corresponding main program in the mapping table; Migrate the modified first operation instruction to the main program.
  • the operation instructions of the library function before migrating the operation instructions of the library function to the main program, it is first detected through the preset mapping table.
  • the register address in the first operation instruction hits the preset mapping table, the operation instruction is detected according to the mapping table. Modify the register address in the first operation instruction (that is, increase it to the first address digit) according to the mapping relationship, and then migrate the modified first operation instruction to the main program to ensure that the library function is transplanted into the main program.
  • This method eliminates the need for staff to upgrade all compilers that generate library functions to the first address digit, reducing staff workload and accelerating the development process of subsequent projects.
  • the method before scanning all instructions in the library function, the method further includes: renaming the register corresponding to the library function, So that each register in the library function is assigned in one instruction.
  • the registers corresponding to the library function are first renamed, so that each register in the library function is assigned a value in one instruction. By renaming, This is to prevent confusion when subsequent register digits are increased and affect the normal migration of library functions.
  • the method further includes: scanning all instructions in the library function and determining the first operation instruction; wherein the first operation instruction is an address operation instruction; and converting the first operation instruction into The register address is matched with the mapping table.
  • the method before scanning all instructions in the library function, the method further includes: obtaining the parameter transfer instruction of the main program; wherein, The parameter transfer instruction includes a target register address and a source register address; wherein, the target register address is the second address digit, and the target register address is an address used to provide input parameters for the called library function; The target register address is raised to the first address digit and is associated with the register address of the called library function; wherein the register address of the called library function is the input parameter of the called library function itself. Address; construct the mapping table based on the increased target register address and the register address of the called library function.
  • the number of digits of the parameter register address is modified based on the parameter transfer instruction of the main program to dynamically form the required mapping table without the need to build a mapping table containing all register address mapping relationships. In this way , improving link efficiency.
  • the method before obtaining the parameter transfer instruction of the main program, the method further includes: a compiler based on the number of first address digits, converting the first The main program source code of one address digit is compiled into the main program; the compiler based on the second address digit compiles the library function source code of the second address digit into the library function.
  • the compiler of the main program source code can continue to be compiled based on the first address digits, and the library function source code can be compiled based on the compiler of the second address digits, without the need for staff to upgrade all
  • the compiler that generates library functions to the first address digit reduces the workload of staff and accelerates the development process of subsequent projects.
  • the method when the first operation instruction contains a register address that hits the mapping table and a register address that misses the mapping table, the method It also includes: using a sign extension method to increase the target register of the main program corresponding to the register address that misses the mapping table to a first address digit, and updating the mapping table; based on the updated mapping table, The register address in an operation instruction is modified.
  • the target register of the main program corresponding to the register address that misses the mapping table is sign extended. Promote to the first address digit and update the mapping table.
  • the mapping table can be updated during the linking process of the library function to ensure the correctness of transplanting the library function into the main program and the uniformity of the number of address bits.
  • the first operation instruction includes any one of a read instruction, a write instruction, and an operation instruction.
  • embodiments of the present application provide a cross-linking device, including: a processing module configured to, after the register address in the first operation instruction of the library function hits a preset mapping table, The register address is modified; wherein, the mapping table includes a mapping relationship between the target register address of the main program and the register address of the library function; the target register address of the main program is raised to the first address digit; so The register address in the operation instruction of the library function is the second address digit; the register address in the modified first operation instruction is the target register address of the corresponding main program in the mapping table; the link module is used to transfer all The modified first operation instruction is transferred to the main program.
  • the device further includes: a renaming module; the renaming module is configured to, before scanning all instructions in the library function, Rename the register corresponding to the library function so that each register in the library function is assigned a value in one instruction.
  • the device further includes: a matching module; the matching module is configured to operate when the address operation instruction of the library function hits a preset mapping table Finally, before modifying the register address in the address operation instruction of the library function, scan all instructions in the library function and determine the first operation instruction; wherein the first operation instruction is an address operation Instruction: Match the register address in the first operation instruction with the mapping table.
  • the device further includes: a building module; the building module is used to obtain all instructions in the library function before scanning.
  • the parameter transfer instruction of the main program wherein the parameter transfer instruction includes a target register address and a source register address; wherein the target register address is the second address digit, and the target register address is used to provide the called
  • the library function provides the address of the input parameter; the target register address is raised to the first address digit and associated with the register address of the called library function; wherein the register address of the called library function is the The input parameter address of the called library function itself is the input parameter address of the called library function; the mapping table is constructed based on the increased target register address and the register address of the called library function.
  • the device further includes: a compilation module; the compilation module is configured to, before obtaining the parameter transfer instruction of the main program, based on the first A compiler based on one address digit compiles the main program source code of the first address digit into the main program; a compiler based on the second address digit compiles the library function source code of the second address digit into the main program. Describe library functions.
  • the device further includes: an update module; the update module is configured to when the first operation instruction contains a register that hits the mapping table address and when the register address of the mapping table is missed, the target register of the main program corresponding to the register address of the mapping table is raised to the first address digit in a sign extension manner, and the mapping table is updated; Modify the register address in the first operation instruction based on the updated mapping table.
  • the first operation instruction includes any one of a read instruction, a write instruction, and an operation instruction.
  • embodiments of the present application provide an electronic device, including: a processor and a memory, the processor is connected to the memory; the memory is used to store programs; the processor is used to call programs stored in the memory.
  • the program in executes the method provided by the above-mentioned first aspect embodiment and/or in combination with some possible implementations of the above-mentioned first aspect embodiment.
  • embodiments of the present application provide a computer-readable storage medium on which a computer program is stored.
  • the computer program executes the above-described first aspect embodiment and/or in combination with the above-described first aspect.
  • Figure 1 is a module block diagram of an electronic device provided by an embodiment of the present application.
  • Figure 2 is a step flow chart of a cross-linking method provided by an embodiment of the present application.
  • Figure 3 is a schematic flowchart of a cross-link provided by an embodiment of the present application.
  • Figure 4 is a module block diagram of a cross-link device provided by an embodiment of the present application.
  • Icons 100-electronic equipment; 110-processor; 120-memory; 200-cross-link device; 210-processing module; 220-link module.
  • FIG. 1 is a schematic structural block diagram of an electronic device 100 applying a cross-linking method and device provided by an embodiment of the present application.
  • the electronic device 100 may be a terminal or a server, and the terminal may be, but is not limited to, a personal computer (Personal Computer, PC), a smart phone, a tablet, a personal digital assistant (Personal Digital Assistant, PDA), a mobile Internet Device (Mobile Internet Device, MID), etc.
  • the server may be, but is not limited to, a network server, a database server, a cloud server, or a server integration composed of multiple sub-servers.
  • the devices listed above are only used to facilitate understanding of the embodiments of the present application, and should not be used to limit the embodiments.
  • the electronic device 100 may include a processor 110 and a memory 120 .
  • the processor 110 is electrically connected to the memory 120 directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.
  • the cross-linking device includes at least one software module that can be stored in the memory 120 in the form of software or firmware or solidified in the operating system (Operating System, OS) of the electronic device 100 .
  • the processor 110 is configured to execute executable modules stored in the memory 120, such as software function modules and computer programs included in the cross-linking device, to implement the cross-linking method.
  • the processor 110 can execute the computer program after receiving the execution instruction.
  • the processor 110 is a graphics processor (Graphics Processing Unit, GPU).
  • the compiler configured in the graphics processor supports not only high-level languages for graphics rendering, such as GLSL (OpenGL Shading Language, shading language), HLSL (High Level Shader Language, high-level shader language), etc., but also supports high-level languages for general computing such as OpenCL (Open Computing Language, open computing language), CUDA (Compute Unified Device Architecture, a computing platform), etc., and also supports intermediate code representation in binary form DXIL, SPIR-V, etc.
  • the processor 110 can also be an integrated circuit chip with signal processing capabilities.
  • the processor 110 can also be a general-purpose processor, for example, it can be a central processing unit (Central Processing Unit, CPU), a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a discrete Gate or transistor logic devices and discrete hardware components can implement or execute the methods, steps and logical block diagrams disclosed in the embodiments of this application.
  • the general-purpose processor may be a microprocessor or any conventional processor or the like.
  • the memory 120 may be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read only memory (Programmable Read-Only Memory, PROM), erasable and removable memory. Programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), and electrically erasable programmable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM).
  • RAM Random Access Memory
  • ROM read only memory
  • PROM Programmable Read-Only Memory
  • EPROM Erasable Programmable Read-Only Memory
  • EEPROM Electrically erasable programmable read-only memory
  • FIG. 1 is only illustrative.
  • the electronic device 100 provided by the embodiment of the present application may also have fewer or more components than that shown in FIG. 1 , or have a different configuration than that shown in FIG. 1 .
  • each component shown in Figure 1 can be implemented by software, hardware, or a combination thereof.
  • Figure 2 is a step flow chart of a cross-linking method provided by an embodiment of the present application. This method is applied to the electronic device 100 shown in Figure 1. It should be noted that the cross-linking method provided by the embodiment of the present application is not limited to the order shown in Figure 2 and below. The method includes: step S101-step S102.
  • Step S101 After the register address in the first operation instruction of the library function hits the preset mapping table, modify the register address in the first operation instruction.
  • the mapping table includes the mapping relationship between the target register address of the main program and the register address of the library function; the target register address of the main program is promoted to the first address digit; the register address in the operation instruction of the library function is the second address. number of bits; the register address in the modified first operation instruction is the target register address of the corresponding main program in the mapping table.
  • first address digits are greater than the second address digits.
  • the first address digits are determined by the main program source code
  • the second address digits are determined by the address digits of the library function source code. For example, if the source code of the main program is 64 bits, then the number of first address digits is 64 bits, and the number of address digits of the library function source code is 32 bits, then the number of digits of the second address is 32 bits.
  • the first address digits may be 32 bits and the second address digits may be 16 bits, or the first address digits may be 128 bits and the second address digits may be 64 bits, or it may also be The first address is 64 bits, and the second address is 16 bits, which is not limited in this application.
  • the first address digits are 64 bits and the second address digits are 32 bits.
  • the above hit can be understood as the register address in the first operation instruction of the library function is the same as one of the register addresses in the mapping table.
  • the method further includes: scanning all instructions in the library function and determining a first operation instruction; wherein the first operation instruction is an address operation instruction; changing The register address is matched with the mapping table.
  • the above-mentioned first operation instruction includes any one of a read instruction (load), a write instruction (store), and an operation instruction.
  • the operation instructions include but are not limited to: addition instruction (add), subtraction instruction (sub), multiplication instruction (mul) and division instruction (div).
  • the first instruction may also refer to all instructions in the library function, which is not limited in this application.
  • the method before performing the above action of scanning all instructions in the library function, the method further includes: renaming a register corresponding to the library function so that each register in the library function is assigned a value in one instruction.
  • 001 and 007 represent two addition instructions in the library function.
  • uint32 represents the 32-bit integer type
  • temp(*) represents the register.
  • temp(1079) represents register No. 1079.
  • temp(1079) is assigned once.
  • the same register needs to be promoted to 64 bits in some instructions, while in other instructions ( If non-address operation instructions) are not needed, temp(1079) can be renamed to an unused new register temp(1267), so the above instruction changes to:
  • the registers corresponding to the library function are first renamed, so that each register in the library function is assigned a value in one instruction. Through the renamed method to prevent confusion when subsequent registers are increased in digits.
  • the method before performing the above action of scanning all instructions in the library function, also includes: obtaining the parameter transfer instruction of the main program; raising the target register address in the parameter transfer instruction to the first address digit, and matching it with The register address of the called library function is associated; a mapping table is constructed based on the increased target register address and the register address of the called library function.
  • the parameter transfer instruction includes the target register address and the source register address;
  • the target register address is originally the second address digit, and the target register address is the address used to provide input parameters for the called library function; the register address of the called library function is the input parameter address of the called library function itself. .
  • the above instructions are the parameter transfer instructions of the main program; uint64 represents the 64-bit integer type.
  • the meaning of this instruction is to assign the value of register 34 to register 66.
  • temp(34) is the source register address; the operand of temp(34) is the source operand.
  • temp(66) is the destination register address; the operand of temp(66) is the destination operand, and temp(66) is the address used to provide input parameters for the called library function.
  • the modified instruction is:
  • target register address temp(66) is increased from 32 bits to 64 bits.
  • the register address of the called library function corresponding to the input parameter address is uint32 temp(1067). That is, uint32 temp(1067) is the register address of the called library function, and is also the input parameter address of the called library function itself.
  • the increased target register address is associated with the register address of the called library function to build a mapping table.
  • mapping relationship between the increased target register address in the mapping table and the register address of the called library function is as follows:
  • the instructions in the main program are non-address operation instructions, they can be linked directly according to the conventional link method.
  • the number of digits of the parameter register address is modified based on the parameter transfer instruction of the main program to dynamically form the required mapping table, without the need to build a mapping table containing all register address mapping relationships. This method improves link efficiency.
  • the method before obtaining the parameter transfer instruction of the main program, the method also includes: a compiler based on the first address digits, compiles the main program source code of the first address digits into the main program; based on the second address digits The compiler of the number compiles the library function source code of the second address digit into a library function.
  • the 64-bit main program source code can be compiled into the main program;
  • the 32-bit library function source code can be compiled into a library function.
  • the main program and library functions in the aforementioned embodiments are middle level intermediate codes.
  • the source code needs to be compiled by a compiler.
  • the compiler based on the first address digit can continue to compile the main program source code, and the compiler based on the second address digit can compile the library function source code, without the need for staff to upgrade all
  • the compiler generates library functions to the first address digit.
  • the first operation instruction is the following read instruction:
  • the modified first operation instruction is:
  • the method when the first operation instruction contains a register address that hits the mapping table and a register address that misses the mapping table, the method further includes: sign-extending the main program corresponding to the register address that misses the mapping table.
  • the target register is raised to the first address digit, and the mapping table is updated; the register address in the first operation instruction is modified based on the updated mapping table.
  • the first operation instruction is the following addition instruction:
  • uint32 temp(1067) hits the mapping table, corresponding to the main program uint64 temp(66), while uint32 temp(1079) and uint32 temp(1069) miss the mapping table. Therefore, in order to unify the number of address digits, the target register of the main program corresponding to uint32 temp (1079) and uint32 temp (1069) is upgraded to 64 bits, and the mapping table is updated.
  • the updated mapping table includes the following mapping relationships:
  • the modified first operation instruction is:
  • the mapping table can be updated during the linking process of the library function to ensure the correctness of transplanting the library function into the main program and the uniformity of the number of address bits.
  • the above-mentioned increase in the number of bits can also be achieved through the mapping relationship of symbols in the symbol table, which is not limited in this application.
  • Step S102 Migrate the modified first operation instruction to the main program.
  • modified first operation instruction is migrated to the main program.
  • the linked main program then performs subsequent machine-independent optimization and machine-related optimization to generate the final executable code, which is machine code.
  • the electronic device After the electronic device obtains the 64-bit main program source code and the 32-bit library function source code, it first compiles it, that is, through a 64-bit compiler , compile the 64-bit main program source code into the main program, and compile the 32-bit library function source code into library functions through a 32-bit compiler. Then, link the main program and the library function.
  • the parameter transfer instructions include the target register address and the source register address; among them, the target register address is 32 bits, and the target register address is for Provide the address of the input parameter to the called library function; promote the target register address to 64 bits and associate it with the register address of the called library function; where the register address of the called library function is the called library function itself
  • the first operation instruction is determined; wherein the first operation instruction is an address operation instruction; the register address in the first operation instruction is matched with the mapping table.
  • the register address in the first operation instruction of the library function hits the preset mapping table, the register address in the first operation instruction is modified; the register address in the modified first operation instruction is the corresponding host in the mapping table. The target register address of the program; finally, the modified first operation instruction is migrated to the main program, and then the executable code is obtained.
  • the register address in the first operation instruction hits the preset mapping table, Modify the register address in the first operation instruction according to the mapping relationship of the mapping table (that is, increase it to the first address digit), and then migrate the modified first operation instruction to the main program to ensure that the library function is transplanted to The correctness of the main program and the uniformity of address digits. In this way, there is no need for staff to upgrade all compilers that generate library functions to the first address digits, reducing the workload of staff and accelerating the development process of subsequent projects. .
  • an embodiment of the present application also provides a cross-linking device 200, which includes:
  • the processing module 210 is configured to modify the register address in the first operation instruction of the library function after it hits a preset mapping table; wherein the mapping table includes the main program's The mapping relationship between the target register address and the register address of the library function; the target register address of the main program is promoted to the first address digit; the register address in the operation instruction of the library function is the second address digit ; The first address digits are greater than the second address digits; the register address in the modified first operation instruction is the target register address of the corresponding main program in the mapping table.
  • the link module 220 is used to migrate the modified first operation instruction to the main program.
  • the device also includes: a matching module.
  • the matching module is configured to scan all instructions in the library function before modifying the register address in the address operation instruction of the library function after the address operation instruction of the library function hits the preset mapping table, and Determine the first operation instruction; wherein the first operation instruction is an address operation instruction; match the register address in the first operation instruction with the mapping table.
  • the device also includes: a renaming module.
  • a renaming module configured to rename the register corresponding to the library function before scanning all instructions in the library function, so that each register in the library function is assigned a value in one instruction.
  • the device also includes building blocks.
  • a building module configured to obtain the parameter transfer instruction of the main program before scanning all instructions in the library function; wherein the parameter transfer instruction includes a target register address and a source register address; wherein the target The register address is the second address digit, and the target register address is the address used to provide input parameters for the called library function; the target register address is raised to the first address digit, and is compared with the called The register address association of the library function; wherein, the register address of the called library function is the input parameter address of the called library function itself; based on the increased target register address and the called library function The register address constructs the mapping table.
  • the device further includes a compilation module.
  • a compilation module configured to compile the main program source code of the first address digit into the main program based on the first address digit compiler before obtaining the parameter transfer instruction of the main program; based on the second address digit A compiler with a second address digit compiles the library function source code with a second address digit into the library function.
  • the device further includes an update module.
  • An update module configured to, when the first operation instruction contains a register address that hits the mapping table and a register address that misses the mapping table, update the register address that misses the mapping table in a sign-extension manner.
  • the target register of the main program is raised to the first address digit, and the mapping table is updated; the register address in the first operation instruction is modified based on the updated mapping table.
  • embodiments of the present application also provide a computer-readable storage medium on which a computer program is stored.
  • a computer program is stored.
  • the method provided in the above embodiments is executed.
  • the storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrated with one or more available media.
  • the available media may be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as DVDs), or semiconductor media (such as solid state disks (SSD)), etc.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional module in each embodiment of the present application can be integrated together to form an independent part, each module can exist alone, or two or more modules can be integrated to form an independent part.
  • relational terms such as first, second, etc. are used merely to distinguish one entity or operation from another entity or operation and do not necessarily require or imply the existence of any such entity or operation between these entities or operations. Actual relationship or sequence.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Stored Programmes (AREA)

Abstract

本申请提供一种交叉链接方法、装置，电子设备及存储介质。该方法包括：当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将第一操作指令中的寄存器地址进行修改；其中，映射表包括主程序的目标寄存器地址与库函数的寄存器地址之间映射关系；主程序的目标寄存器地址被提升至第一地址位数；库函数的操作指令中的寄存器地址为第二地址位数；第一地址位数大于第二地址位数；修改后的第一操作指令中的寄存器地址为映射表中对应的主程序的目标寄存器地址；将修改后的第一操作指令迁移至主程序中。通过上述方式，可以无需工作人员升级所有产生库函数的编译器至第一地址位数，减少工作人员的工作量，加速后续项目的开发进程。

Description

一种交叉链接方法、装置，电子设备及存储介质 技术领域
本申请涉及计算机技术领域，具体而言，涉及一种交叉链接方法、装置，电子设备及存储介质。
背景技术
编译链接过程是把一个高级语言程序(源代码)转换成可以在硬件上运行的程序(可执行代码或机器码)的过程，其包含编译和链接两个主要步骤。其中编译就是把高级语言源代码翻译为中间代码(目标文件)的过程；链接是把目标文件和用到的库文件(包括库函数)进行组织形成最终生成的可执行代码的过程。
比如，根据地址长度位数的不同，编译器可以包括64位编译器和32位编译器，当编译器在支持多个硬件平台和多种编程语言时，会出现部分程序是由32位前端产生的，而部分程序由64位前端产生的这种复杂情况。具体的，当需要产生64位的可执行程序，而库函数是由32位编译器产生时，在交叉链接时，目前的链接器无法解决这种情况下产生的机器码的正确性，从而使得工作人员不得不升级所有的库函数到64位，这就要求必须升级所有产生库函数的编译器至64位，由此给工作人员带来极大的工程量。可见，目前的编译链接过程无法在不升级库函数的情况下，实现不同位数的程序的交叉链接。
发明内容
本申请实施例的目的在于提供一种交叉链接方法、装置，电子设备及存储介，以实现不同地址位数的程序的交叉链接。
本申请是这样实现的：
第一方面，本申请实施例提供一种交叉链接方法，包括：当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将所述第一操作指令中的寄存器地址进行修改；其中，所述映射表包括主程序的目标寄存器地址与所述库函数的寄存器地址之间映射关系；所述主程序的目标寄存器地址被提升至第一地址位数；所述库函数的操作指令中的寄存器地址为第二地址位数；第一地址位数大于第二地址位数；修改后的第一操作指令中的寄存器地址为所述映射表中对应的主程序的目标寄存器地址；将所述修改后的第一操作指令迁移至所述主程序中。
在本申请实施例中，在将库函数的操作指令迁移至主程序之前，先通过预设的映射表进行检测，当第一操作指令中的寄存器地址命中预设的映射表后，根据映射表的映射关系将第一操作指令中的寄存器地址进行修改(即提升至第一地址位数)，然后再将修改后的第一操作指令迁移至主程序中，以保证库函数移植到主程序中的正确性和地址位数的统一性，通过该方式，也无需工作人员升级所有产生库函数的编译器至第一地址位数，减少工作人员的工作量，加速后续项目的开发进程。
结合上述第一方面提供的技术方案，在一些可能的实现方式中，在所述扫描所述库函数中的所有指令之前，所述方法还包括：对所述库函数对应的寄存器进行重命名，以使所述库函数中的每个寄存器在一条指令中被赋值。
在本申请实施例中，在扫描库函数中的所有指令之前，先对库函数对应的寄存器进行重命名，以使库函数中的每个寄存器在一条指令中被赋值，通过重命名的方式，以防止后续寄存器做位数提升时产生混淆，影响库函数正常的迁移。
结合上述第一方面提供的技术方案，在一些可能的实现方式中，在所述当库函数的地址操作指令命中预设的映射表后，将所述库函数的地址操作指令中的寄存器地址进行修改之前，所述方法还包括：扫描所述库函数中的所有指令，并确定出所述第一操作指令；其中，所述第一操作指令为地址操作指令；将所述第一操作指令中的寄存器地址与所述映射表进行匹配。
在本申请实施例中，先对库函数的所有指令进行扫描，只有指令为地址操作指令时，才进行映射表匹配的动作，通过该方式，能够提高链接效率。
结合上述第一方面提供的技术方案，在一些可能的实现方式中，在所述扫描所述库函数中的所有指令之前，所述方法还包括：获取所述主程序的参数传递指令；其中，所述参数传递指令包括目标寄存器地址与源寄存器地址；其中，所述目标寄存器地址为第二地址位数，所述目标寄存器地址为用于为被调用的库函数提供输入参数的地址；将所述目标寄存器地址提升至第一地址位数，并与所述被调用的库函数的寄存器地址关联；其中，所述被调用的库函数的寄存器地址为所述被调用的库函数自身的输入参数地址；基于提升位数后的目标寄存器地址与所述被调用的库函数的寄存器地址构建所述映射表。
在本申请实施例中，基于主程序的参数传递指令对参数寄存器地址的位数进行修改，以动态的形成所需的映射表，而无需构建包含所有寄存器地址映射关系的映射表，通过该方式，提高了链接效率。
结合上述第一方面提供的技术方案，在一些可能的实现方式中，在所述获取所述主程序的参数传递指令之前，所述方法还包括：基于第一地址位数的编译器，将第一地址位数的主程序源代码编译为所述主程序；基于第二地址位数的编译器，将第二地址位数的库函数源代码编译为所述库函数。
在本申请实施例中，可以继续基于第一地址位数的编译器对主程序源代码进行编译，以及基于第二地址位数的编译器对库函数源代码进行编译，而无需工作人员升级所有产生库函数的编译器至第一地址位数，减少了工作人员的工作量，加速了后续项目的开发进程。
结合上述第一方面提供的技术方案，在一些可能的实现方式中，当所述第一操作指令中存在命中所述映射表的寄存器地址以及未命中所述映射表的寄存器地址时，所述方法还包括：以符号扩展方式将未命中所述映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新所述映射表；基于更新后的映射表对所述第一操作指令中的寄存器地址进行修改。
在本申请实施例中，当第一操作指令中存在命中映射表的寄存器地址以及未命中映射表的寄存器地址时，以符号扩展方式将未命中映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新映射表。通过上述方式，能够在库函数的链接过程中实现映射表的更新，以保证库函数移植到主程序中的正确性和地址位数的统一性。
结合上述第一方面提供的技术方案，在一些可能的实现方式中，所述第一操作指令包括读指令、写指令、运算指令中的任意一种。
第二方面，本申请实施例提供一种交叉链接装置，包括：处理模块，用于当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将所述第一操作指令中的寄存器地址进行修改；其中，所述映射表包括主程序的目标寄存器地址与所述库函数的寄存器地址之间映射关系；所述主程序的目标寄存器地址被提升至第一地址位数；所述库函数的操作指令中的寄存器地址为第二地址位数；修改后的第一操作指令中的寄存器地址为所述映射表中对应的主程序的目标寄存器地址；链接模块，用于将所述修改后的第一操作指令迁移至所述主程序中。
结合上述第二方面提供的技术方案，在一些可能的实现方式中，所述装置还包括：重命名模块；所述重命名模块，用于在所述扫描所述库函数中的所有指令之前，对所述库函数对应的寄存器进行重命名，以使所述库函数中的每个寄存器在一条指令中被赋值。
结合上述第二方面提供的技术方案，在一些可能的实现方式中，所述装置还包括：匹配模块；所述匹配模块，用于在所述当库函数的地址操作指令命中预设的映射表后，将所述库函数的地址操作指令中的寄存器地址进行修改之前，扫描所述库函数中的所有指令，并确定出所述第一操作指令；其中，所述第一操作指令为地址操作指令；将所述第一操作指令中的寄存器地址与所述映射表进行匹配。
结合上述第二方面提供的技术方案，在一些可能的实现方式中，所述装置还包括：构建模块；所述构建模块，用于在所述扫描所述库函数中的所有指令之前，获取所述主程序的参数传递指 令；其中，所述参数传递指令包括目标寄存器地址与源寄存器地址；其中，所述目标寄存器地址为第二地址位数，所述目标寄存器地址为用于为被调用的库函数提供输入参数的地址；将所述目标寄存器地址提升至第一地址位数，并与所述被调用的库函数的寄存器地址关联；其中，所述被调用的库函数的寄存器地址为所述被调用的库函数自身的输入参数地址；基于提升位数后的目标寄存器地址与所述被调用的库函数的寄存器地址构建所述映射表。
结合上述第二方面提供的技术方案，在一些可能的实现方式中，所述装置还包括：编译模块；所述编译模块，用于在所述获取所述主程序的参数传递指令之前，基于第一地址位数的编译器，将第一地址位数的主程序源代码编译为所述主程序；基于第二地址位数的编译器，将第二地址位数的库函数源代码编译为所述库函数。
结合上述第二方面提供的技术方案，在一些可能的实现方式中，所述装置还包括：更新模块；所述更新模块，用于当所述第一操作指令中存在命中所述映射表的寄存器地址以及未命中所述映射表的寄存器地址时，以符号扩展方式将未命中所述映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新所述映射表；基于更新后的映射表对所述第一操作指令中的寄存器地址进行修改。
结合上述第二方面提供的技术方案，在一些可能的实现方式中，所述第一操作指令包括读指令、写指令、运算指令中的任意一种。
第三方面，本申请实施例提供一种电子设备，包括：处理器和存储器，所述处理器和所述存储器连接；所述存储器用于存储程序；所述处理器用于调用存储在所述存储器中的程序，执行如上述第一方面实施例和/或结合上述第一方面实施例的一些可能的实现方式提供的方法。
第四方面，本申请实施例提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序在被处理器运行时执行如上述第一方面实施例和/或结合上述第一方面实施例的一些可能的实现方式提供的方法。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的一种电子设备的模块框图。
图2为本申请实施例提供的一种交叉链接方法的步骤流程图。
图3为本申请实施例提供的一种交叉链接的流程示意图。
图4为本申请实施例提供的一种交叉链接装置的模块框图。
图标：100-电子设备；110-处理器；120-存储器；200-交叉链接装置；210-处理模块；220-链接模块。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
请参阅图1，本申请实施例提供的一种应用交叉链接方法及装置的电子设备100的示意性结构框图。本申请实施例中，电子设备100可以是终端或者服务器，终端可以是，但不限于个人计算机(Personal Computer，PC)、智能手机、平板电脑、个人数字助理(Personal Digital Assistant，PDA)、移动上网设备(Mobile Internet Device，MID)等。服务器可以是但不限于网络服务器、数据库服务器、云服务器或由多个子服务器构成的服务器集成等。当然，上述列举的设备仅用于便于理解本申请实施例，其不应作为对本实施例的限定。
在结构上，电子设备100可以包括处理器110和存储器120。
处理器110与存储器120直接或间接地电性连接，以实现数据的传输或交互，例如，这些元件相互之间可通过一条或多条通讯总线或信号线实现电性连接。交叉链接装置包括至少一个可以软件或固件(Firmware)的形式存储在存储器120中或固化在电子设备100的操作系统(Operating System，OS)中的软件模块。处理器110用于执行存储器120中存储的可执行模块，例如，交叉链接装置所包括的软件功能模块及计算机程序等，以实现交叉链接方法。处理器110可以在接收到执行指令后，执行计算机程序。
于本申请实施例中，处理器110为图形处理器(Graphics Processing Unit，GPU)。配置在图形处理器中的编译器既支持图形渲染的高级语言,如GLSL(OpenGL Shading Language，着色语言)、HLSL(High Level Shader Language，高级着色器语言)等，也支持通用计算的高级语言如OpenCL(Open Computing Language，开放运算语言)、CUDA(Compute Unified Device Architecture，一种运算平台)等，同时还支持二进制形式的中间代码表示DXIL、SPIR-V等。
当然，处理器110还可以是一种集成电路芯片，具有信号处理能力。处理器110也可以是通用处理器，例如，可以是中央处理器(Central Processing Unit，CPU)、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、分立门或晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。此外，通用处理器可以是微处理器或者任何常规处理器等。
存储器120可以是，但不限于，随机存取存储器(Random Access Memory，RAM)、只读存储器(Read Only Memory，ROM)、可编程只读存储器(Programmable Read-Only Memory，PROM)、可擦可编程序只读存储器(Erasable Programmable Read-Only Memory，EPROM)，以及电可擦编程只读存储器(Electric Erasable Programmable Read-Only Memory，EEPROM)。存储器120用于存储程序，处理器110在接收到执行指令后，执行该程序。
需要说明的是，图1所示的结构仅为示意，本申请实施例提供的电子设备100还可以具有比图1更少或更多的组件，或是具有与图1所示不同的配置。此外，图1所示的各组件可以通过软件、硬件或其组合实现。
请参阅图2，图2为本申请实施例提供的交叉链接方法的步骤流程图，该方法应用于图1所示的电子设备100。需要说明的是，本申请实施例提供的交叉链接方法不以图2及以下所示的顺序为限制，该方法包括：步骤S101-步骤S102。
步骤S101：当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将第一操作指令中的寄存器地址进行修改。
其中，映射表包括主程序的目标寄存器地址与库函数的寄存器地址之间映射关系；主程序的目标寄存器地址被提升至第一地址位数；库函数的操作指令中的寄存器地址为第二地址位数；修改后的第一操作指令中的寄存器地址为映射表中对应的主程序的目标寄存器地址。
需要说明的是，第一地址位数大于第二地址位数，第一地址位数由主程序源代码所确定，第二地址位数由库函数源代码的地址位数所确定。比如，主程序源代码为64位，则第一地址位数为64位，库函数源代码的地址位数为32位，则第二地址位数为32位。当然，在其他实施例中，可以是第一地址位数为32位，第二地址位数为16位，或者第一地址位数为128位，第二地址位数为64位，还可以是第一地址为64位，第二地址位数为16位，对此，本申请不作限定。为了便于理解，后续示例中，均以第一地址位数为64位，第二地址位数为32位进行举例说明。
上述命中可以理解为库函数的第一操作指令中的寄存器地址与映射表中的其中一个寄存器地址相同。
作为一种实施方式，在步骤S101之前，该方法还包括：扫描库函数中的所有指令，并确定出第一操作指令；其中，第一操作指令为地址操作指令；将第一操作指令中的寄存器地址与映射表进行匹配。
上述的第一操作指令包括读指令(load)、写指令(store)、运算指令中的任意一种。
其中，运算指令包括但不限于：加法指令(add)、减法指令(sub)、乘法指令(mul)和除法指令(div)。
在本申请实施例中，先对库函数的所有指令进行扫描，只有指令为地址操作指令时，才进行映射表匹配的动作，通过该方式，能够提高链接效率。
当然，第一指令也可以是指的库函数中的所有指令，本申请不作限定。
可选地，在上述执行扫描库函数中的所有指令的动作之前，该方法还包括：对库函数对应的寄存器进行重命名，以使库函数中的每个寄存器在一条指令中被赋值。
示例性的：
001：uadd uint32 temp(1079)，uint32 temp(1067)，uint32 temp(1069)；
...
007:uadd uint32 temp(1079)，uint32 temp(1068)，10。
其中，001和007表示库函数中的两条加法指令。其中，uint32表示32位整数类型，temp(*)表示寄存器，比如temp(1079)表示1079号寄存器。在指令001和指令007中，均对temp(1079)进行了一次赋值，为了避免后续寄存器做位数提升时产生混淆，如同一寄存器在部分指令中需要被提升为64位，而另一部分指令(如非地址操作指令)不需要的情况，此时可以将temp(1079)重新命名为一个未使用过的新寄存器temp(1267)，于是上述指令变化为：
001：uadd uint32 temp(1079)，uint32 temp(1067)，uint32 temp(1069)
...
007:uadd uint32 temp(1267)，uint32 temp(1068)，10
可见，在本申请实施例中，在扫描库函数中的所有指令之前，先对库函数对应的寄存器进行重命名，以使库函数中的每个寄存器在一条指令中被赋值，通过重命名的方式，以防止后续寄存器做位数提升时产生混淆。
可选地，在上述执行扫描库函数中的所有指令的动作之前，该方法还包括：获取主程序的参数传递指令；将参数传递指令中的目标寄存器地址提升至第一地址位数，并与被调用的库函数的寄存器地址关联；基于提升位数后的目标寄存器地址与被调用的库函数的寄存器地址构建映射表。
其中，参数传递指令包括目标寄存器地址与源寄存器地址；
其中，目标寄存器地址原始为第二地址位数，目标寄存器地址为用于为被调用的库函数提供输入参数的地址；被调用的库函数的寄存器地址为被调用的库函数自身的输入参数地址。
示例性的：
movparam uint32 temp(66)uint64 temp(34)；
上述指令即为主程序的参数传递指令；uint64表示64位整数类型。这条指令的含义是将34号寄存器的值赋值给66号寄存器。其中，temp(34)为源寄存器地址；temp(34)的操作数为源操作数。temp(66)为目标寄存器地址；temp(66)的操作数为目的操作数，temp(66)为用于为被调用的库函数提供输入参数的地址。
由于主程序为64位，此处对指令的目标操作地址进行修改，将其提升至64位，修改后的指令为：
movparam uint64 temp(66)uint64 temp(34)；
可见，目标寄存器地址temp(66)由32位提升为64位。
示例性的，被调用的库函数对应该输入参数地址的寄存器地址为uint32 temp(1067)。即，uint32 temp(1067)为被调用的库函数的寄存器地址，也为被调用的库函数自身的输入参数 地址。
然后，将提升位数后的目标寄存器地址与被调用的库函数的寄存器地址进行关联，以构建映射表。
其中，映射表中的提升位数后的目标寄存器地址与被调用的库函数的寄存器地址的映射关系如下：
uint32 temp(1067)<—>uint64 temp(66)。
需要说明的是，若主程序中的指令为非地址操作指令时，直接按照常规链接方式进行链接即可。
可见，在本申请实施例中，基于主程序的参数传递指令对参数寄存器地址的位数进行修改，以动态的形成所需的映射表，而无需构建包含所有寄存器地址映射关系的映射表，通过该方式，提高了链接效率。
可选地，在获取主程序的参数传递指令之前，该方法还包括：基于第一地址位数的编译器，将第一地址位数的主程序源代码编译为主程序；基于第二地址位数的编译器，将第二地址位数的库函数源代码编译为库函数。
示例性的，可以基于64位编译器，将64位主程序源代码编译为主程序；基于32位编译器，将32位库函数源代码编译为库函数。
需要说明的是，前述实施例中的主程序以及库函数均为中级别中间代码(middle level intermediate code)。在链接之前，需要通过编译器将源代码进行编译。而在本申请实施例中，可以继续基于第一地址位数的编译器对主程序源代码进行编译，以及基于第二地址位数的编译器对库函数源代码进行编译，无需工作人员升级所有产生库函数的编译器至第一地址位数。
在构建预设表，以及确定出库函数的第一操作指令之后，将第一操作指令中的寄存器地址与映射表进行匹配。下面结合具体的示例进行说明，第一操作指令为如下的读指令：
load float32 temp(1079)，uint32 temp(1067)，0；
查找映射表，其中，uint32 temp(1067)映射为主程序的uint64 temp(66)，主程序的temp(66)的位数已经提升为了64位，此时，表征这条操作指令在迁移至主程序时，需要进行64位的指令提升，此处将第一操作指令进行修改，修改后的第一操作指令为：
load float32 temp(1079)，uint64 temp(66)，0。
一实施例中，当第一操作指令中存在命中映射表的寄存器地址以及未命中映射表的寄存器地址时，该方法还包括：以符号扩展方式将未命中映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新映射表；基于更新后的映射表对第一操作指令中的寄存器地址进行修改。
具体的，当第一操作指令中存在多个寄存器地址时，而此时有可能出现部分寄存器地址命中映射表，而另一部分寄存器地址未命中映射表的情况，为了实现地址位数的统一性，仅另一部分寄存器地址所对应的主程序的目标寄存器提升至第一地址位数的，并对映射表进行更新，最后，再基于更新后的映射表对第一操作指令中的寄存器地址进行修改。
由于符号扩展方式为本领域所熟知，此处不作过多说明。
下面结合具体的示例进行说明，第一操作指令为如下的加法指令：
uadd uint32 temp(1079)，uint32 temp(1067)，uint32 temp(1069)；
其中，通过查找映射表，uint32 temp(1067)命中映射表，对应主程序uint64 temp(66)，而uint32 temp(1079)和uint32 temp(1069)未命中映射表。因此，为了实现地址位数的统一，将uint32 temp(1079)及uint32 temp(1069)对应的主程序的目标寄存器提升至64位，并更新映射表。
更新后的映射表包括以下映射关系：
uint32 temp(1067)<—>uint64 temp(66)；
uint32 temp(1079)<—>uint64 temp(78)；
uint32 temp(1069)<—>uint64 temp(69)。
最后，基于更新后的映射表对第一操作指令中的寄存器地址进行修改。修改后的第一操作指令为：
uadd uint64 temp(78)，uint64 temp(66)，uint64 temp(69)。
可见，在本申请实施例中，当第一操作指令中存在命中映射表的寄存器地址以及未命中映射表的寄存器地址时，以符号扩展方式将未命中映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新映射表。通过上述方式，能够在库函数的链接过程中实现映射表的更新，以保证库函数移植到主程序中的正确性和地址位数的统一性。
在其他实施例中，还可以通过符号表中符号的映射关系实现上述位数的提升，本申请不作限定。
步骤S102：将修改后的第一操作指令迁移至主程序中。
最后，将修改后的第一操作指令迁移至主程序中。链接后的主程序再进行后续的机器无关优化和机器相关优化，进而产生最后的可执行代码，即机器码。
下面结合一个具体的示例对上述交叉链接方法进行说明，请参阅图3，电子设备在获取到64位主程序源代码以及32位库函数源代码后，先进行编译，即，通过64位编译器，将64位主程序源代码编译为主程序，以及通过32位编译器，将32位库函数源代码编译为库函数。然后，将主程序和库函数进行链接，首先，获取主程序的参数传递指令；其中，参数传递指令包括目标寄存器地址与源寄存器地址；其中，目标寄存器地址为32位，目标寄存器地址为用于为被调用的库函数提供输入参数的地址；将目标寄存器地址提升至64位，并与被调用的库函数的寄存器地址关联；其中，被调用的库函数的寄存器地址为被调用的库函数自身的输入参数地址；基于提升位数后的目标寄存器地址与所述被调用的库函数的寄存器地址构建映射表。然后，对库函数对应的寄存器进行重命名，以使库函数中的每个寄存器在一条指令中被赋值。之后，扫描库函数中的所有指令，并确定出第一操作指令；其中，第一操作指令为地址操作指令；将第一操作指令中的寄存器地址与映射表进行匹配。当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将第一操作指令中的寄存器地址进行修改；修改后的第一操作指令中的寄存器地址为映射表中对应的主程序的目标寄存器地址；最后将修改后的第一操作指令迁移至主程序中，进而得到可执行代码。
综上，在本申请实施例中，在将库函数的操作指令迁移至主程序之前，先通过预设的映射表进行检测，当第一操作指令中的寄存器地址命中预设的映射表后，根据映射表的映射关系将第一操作指令中的寄存器地址进行修改(即提升至第一地址位数)，然后再将修改后的第一操作指令迁移至主程序中，以保证库函数移植到主程序中的正确性和地址位数的统一性，通过该方式，也无需工作人员升级所有产生库函数的编译器至第一地址位数，减少工作人员的工作量，加速后续项目的开发进程。
请参阅图4，基于同一发明构思，本申请实施例还提供一种交叉链接装置200，该装置包括：
处理模块210，用于当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将所述第一操作指令中的寄存器地址进行修改；其中，所述映射表包括主程序的目标寄存器地址与所述库函数的寄存器地址之间映射关系；所述主程序的目标寄存器地址被提升至第一地址位数；所述库函数的操作指令中的寄存器地址为第二地址位数；第一地址位数大于第二地址位数；修改后的第一操作指令中的寄存器地址为所述映射表中对应的主程序的目标寄存器地址。
链接模块220，用于将所述修改后的第一操作指令迁移至所述主程序中。
可选地，该装置还包括：匹配模块。
匹配模块用于在所述当库函数的地址操作指令命中预设的映射表后，将所述库函数的地址操作指令中的寄存器地址进行修改之前，扫描所述库函数中的所有指令，并确定出所述第一操作指令；其中，所述第一操作指令为地址操作指令；将所述第一操作指令中的寄存器地址与所述映射表进行匹配。
可选地，该装置还包括：重命名模块。
重命名模块，用于在所述扫描所述库函数中的所有指令之前，对所述库函数对应的寄存器进行重命名，以使所述库函数中的每个寄存器在一条指令中被赋值。
可选地，该装置还包括构建模块。
构建模块，用于在所述扫描所述库函数中的所有指令之前，获取所述主程序的参数传递指令；其中，所述参数传递指令包括目标寄存器地址与源寄存器地址；其中，所述目标寄存器地址为第二地址位数，所述目标寄存器地址为用于为被调用的库函数提供输入参数的地址；将所述目标寄存器地址提升至第一地址位数，并与所述被调用的库函数的寄存器地址关联；其中，所述被调用的库函数的寄存器地址为所述被调用的库函数自身的输入参数地址；基于提升位数后的目标寄存器地址与所述被调用的库函数的寄存器地址构建所述映射表。
可选地，该装置还包括编译模块。
编译模块，用于在所述获取所述主程序的参数传递指令之前，基于第一地址位数的编译器，将第一地址位数的主程序源代码编译为所述主程序；基于第二地址位数的编译器，将第二地址位数的库函数源代码编译为所述库函数。
可选地，该装置还包括更新模块。
更新模块，用于当所述第一操作指令中存在命中所述映射表的寄存器地址以及未命中所述映射表的寄存器地址时，以符号扩展方式将未命中所述映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新所述映射表；基于更新后的映射表对所述第一操作指令中的寄存器地址进行修改。
需要说明的是，由于所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
基于同一发明构思，本申请实施例还提供一种计算机可读存储介质，其上存储有计算机程序，计算机程序在被运行时执行上述实施例中提供的方法。
该存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如软盘、硬盘、磁带)、光介质(例如DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
在本申请所提供的实施例中，应该理解到，所揭露装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
再者，在本申请各个实施例中的各功能模块可以集成在一起形成一个独立的部分，也可以是各个模块单独存在，也可以两个或两个以上模块集成形成一个独立的部分。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。
以上所述仅为本申请的实施例而已，并不用于限制本申请的保护范围，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种交叉链接方法，其特征在于，包括：
    当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将所述第一操作指令中的寄存器地址进行修改；其中，所述映射表包括主程序的目标寄存器地址与所述库函数的寄存器地址之间映射关系；所述主程序的目标寄存器地址被提升至第一地址位数；所述库函数的操作指令中的寄存器地址为第二地址位数；第一地址位数大于第二地址位数；修改后的第一操作指令中的寄存器地址为所述映射表中对应的主程序的目标寄存器地址；
    将所述修改后的第一操作指令迁移至所述主程序中。
  2. 根据权利要求1所述的方法，其特征在于，在所述扫描所述库函数中的所有指令之前，所述方法还包括：
    对所述库函数对应的寄存器进行重命名，以使所述库函数中的每个寄存器在一条指令中被赋值。
  3. 根据权利要求1所述的方法，其特征在于，在所述当库函数的地址操作指令命中预设的映射表后，将所述库函数的地址操作指令中的寄存器地址进行修改之前，所述方法还包括：
    扫描所述库函数中的所有指令，并确定出所述第一操作指令；其中，所述第一操作指令为地址操作指令；
    将所述第一操作指令中的寄存器地址与所述映射表进行匹配。
  4. 根据权利要求3所述的方法，其特征在于，在所述扫描所述库函数中的所有指令之前，所述方法还包括：
    获取所述主程序的参数传递指令；其中，所述参数传递指令包括目标寄存器地址与源寄存器地址；其中，所述目标寄存器地址为第二地址位数，所述目标寄存器地址为用于为被调用的库函数提供输入参数的地址；
    将所述目标寄存器地址提升至第一地址位数，并与所述被调用的库函数的寄存器地址关联；其中，所述被调用的库函数的寄存器地址为所述被调用的库函数自身的输入参数地址；
    基于提升位数后的目标寄存器地址与所述被调用的库函数的寄存器地址构建所述映射表。
  5. 根据权利要求4所述的方法，其特征在于，在所述获取所述主程序的参数传递指令之前，所述方法还包括：
    基于第一地址位数的编译器，将第一地址位数的主程序源代码编译为所述主程序；
    基于第二地址位数的编译器，将第二地址位数的库函数源代码编译为所述库函数。
  6. 根据权利要求1所述的方法，其特征在于，当所述第一操作指令中存在命中所述映射表的寄存器地址以及未命中所述映射表的寄存器地址时，所述方法还包括：
    以符号扩展方式将未命中所述映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新所述映射表；
    基于更新后的映射表对所述第一操作指令中的寄存器地址进行修改。
  7. 根据权利要求1-6中任一项所述的方法，其特征在于，所述第一操作指令包括读指令、写指令、运算指令中的任意一种。
  8. 一种交叉链接装置，其特征在于，包括：
    处理模块，用于当库函数的第一操作指令中的寄存器地址命中预设的映射表后，将所述第一操作指令中的寄存器地址进行修改；其中，所述映射表包括主程序的目标寄存器地址与所述库函数的寄存器地址之间映射关系；所述主程序的目标寄存器地址被提升至第一地址位数；所述库函数的操作指令中的寄存器地址为第二地址位数；第一地址位数大于第二地址位数；修改后的第一操作指令中的寄存器地址为所述映射表中对应的主程序的目标寄存器地址；
    链接模块，用于将所述修改后的第一操作指令迁移至所述主程序中。
  9. 根据权利要求8所述的装置，其特征在于，所述装置还包括：重命名模块；
    所述重命名模块，用于在所述扫描所述库函数中的所有指令之前，对所述库函数对应的寄存器进行重命名，以使所述库函数中的每个寄存器在一条指令中被赋值。
  10. 根据权利要求8所述的装置，其特征在于，所述装置还包括：匹配模块；
    所述匹配模块，用于在所述当库函数的地址操作指令命中预设的映射表后，将所述库函数的地 址操作指令中的寄存器地址进行修改之前，扫描所述库函数中的所有指令，并确定出所述第一操作指令；其中，所述第一操作指令为地址操作指令；将所述第一操作指令中的寄存器地址与所述映射表进行匹配。
  11. 根据权利要求10所述的装置，其特征在于，所述装置还包括：构建模块；
    所述构建模块，用于在所述扫描所述库函数中的所有指令之前，获取所述主程序的参数传递指令；其中，所述参数传递指令包括目标寄存器地址与源寄存器地址；其中，所述目标寄存器地址为第二地址位数，所述目标寄存器地址为用于为被调用的库函数提供输入参数的地址；将所述目标寄存器地址提升至第一地址位数，并与所述被调用的库函数的寄存器地址关联；其中，所述被调用的库函数的寄存器地址为所述被调用的库函数自身的输入参数地址；基于提升位数后的目标寄存器地址与所述被调用的库函数的寄存器地址构建所述映射表。
  12. 根据权利要求11所述的装置，其特征在于，所述装置还包括：编译模块；
    所述编译模块，用于在所述获取所述主程序的参数传递指令之前，基于第一地址位数的编译器，将第一地址位数的主程序源代码编译为所述主程序；基于第二地址位数的编译器，将第二地址位数的库函数源代码编译为所述库函数。
  13. 根据权利要求8所述的装置，其特征在于，所述装置还包括：更新模块；
    所述更新模块，用于当所述第一操作指令中存在命中所述映射表的寄存器地址以及未命中所述映射表的寄存器地址时，以符号扩展方式将未命中所述映射表的寄存器地址所对应的主程序的目标寄存器提升至第一地址位数，并更新所述映射表；基于更新后的映射表对所述第一操作指令中的寄存器地址进行修改。
  14. 根据权利要求8-13中任一项所述装置，其特征在于，所述第一操作指令包括读指令、写指令、运算指令中的任意一种。
  15. 一种电子设备，其特征在于，包括：处理器和存储器，所述处理器和所述存储器连接；
    所述存储器用于存储程序；
    所述处理器用于运行存储在所述存储器中的程序，执行如权利要求1-7中任一项所述的方法。
  16. 一种计算机可读存储介质，其特征在于，其上存储有计算机程序，所述计算机程序在被计算机运行时执行如权利要求1-7中任一项所述的方法。
PCT/CN2022/113080 2022-08-17 2022-08-17 一种交叉链接方法、装置，电子设备及存储介质 WO2024036517A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP22925229.1A EP4350504A4 (en) 2022-08-17 2022-08-17 CROSS-LINK METHOD AND APPARATUS, ELECTRONIC DEVICE AND STORAGE MEDIUM
CN202280003641.5A CN117916710A (zh) 2022-08-17 2022-08-17 一种交叉链接方法、装置，电子设备及存储介质
KR1020237042129A KR20240025509A (ko) 2022-08-17 2022-08-17 크로스 링크 방법, 장치, 전자 설비 및 저장 매체
PCT/CN2022/113080 WO2024036517A1 (zh) 2022-08-17 2022-08-17 一种交叉链接方法、装置，电子设备及存储介质

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/113080 WO2024036517A1 (zh) 2022-08-17 2022-08-17 一种交叉链接方法、装置，电子设备及存储介质

Publications (1)

Publication Number Publication Date
WO2024036517A1 true WO2024036517A1 (zh) 2024-02-22

Family

ID=89940459

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/113080 WO2024036517A1 (zh) 2022-08-17 2022-08-17 一种交叉链接方法、装置，电子设备及存储介质

Country Status (4)

Country Link
EP (1) EP4350504A4 (zh)
KR (1) KR20240025509A (zh)
CN (1) CN117916710A (zh)
WO (1) WO2024036517A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577268A (zh) * 2003-07-12 2005-02-09 三星电子株式会社 共享库系统及构建该系统的方法
US6968541B1 (en) * 2000-10-04 2005-11-22 International Business Machines Corporation Apparatus and method for template instantiation with a cross compiler
CN1892602A (zh) * 2005-07-01 2007-01-10 中国科学院计算技术研究所 一种二进制翻译中库函数调用的处理方法
CN112506517A (zh) * 2020-11-30 2021-03-16 天津飞腾信息技术有限公司 一种裸机系统级激励交叉编译系统及编译方法
US20210279045A1 (en) * 2020-03-05 2021-09-09 Intuit Inc. Integrated development environment for developing and compiling query language schemas for application program interfaces
CN114816417A (zh) * 2022-04-18 2022-07-29 北京凝思软件股份有限公司 一种交叉编译方法、装置、计算设备及存储介质

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6662361B1 (en) * 2000-01-14 2003-12-09 International Business Machines Corporation Method, system, program, and data structures for transforming an instruction in a first bit architecture to an instruction in a second bit architecture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6968541B1 (en) * 2000-10-04 2005-11-22 International Business Machines Corporation Apparatus and method for template instantiation with a cross compiler
CN1577268A (zh) * 2003-07-12 2005-02-09 三星电子株式会社 共享库系统及构建该系统的方法
CN1892602A (zh) * 2005-07-01 2007-01-10 中国科学院计算技术研究所 一种二进制翻译中库函数调用的处理方法
US20210279045A1 (en) * 2020-03-05 2021-09-09 Intuit Inc. Integrated development environment for developing and compiling query language schemas for application program interfaces
CN112506517A (zh) * 2020-11-30 2021-03-16 天津飞腾信息技术有限公司 一种裸机系统级激励交叉编译系统及编译方法
CN114816417A (zh) * 2022-04-18 2022-07-29 北京凝思软件股份有限公司 一种交叉编译方法、装置、计算设备及存储介质

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4350504A4 *

Also Published As

Publication number Publication date
EP4350504A4 (en) 2024-04-24
KR20240025509A (ko) 2024-02-27
EP4350504A1 (en) 2024-04-10
CN117916710A (zh) 2024-04-19

Similar Documents

Publication Publication Date Title
US9417857B2 (en) Unifying static and dynamic compiler optimizations in source-code bases
US11347489B2 (en) Accessing a migrated member in an updated type
US10303449B2 (en) Compiling non-native constants
US8881123B2 (en) Enabling symbol resolution of private symbols in legacy programs and optimizing access to the private symbols
WO2016094258A1 (en) Inter-procedural type propagation for devirtualization
JP2014002790A (ja) 高速パッチベースメソッドコール
US20180365033A1 (en) Compatible dictionary layout
JP5536593B2 (ja) 最適化装置、最適化方法およびコンパイラ・プログラム
US9298630B2 (en) Optimizing memory bandwidth consumption using data splitting with software caching
WO2024036517A1 (zh) 一种交叉链接方法、装置，电子设备及存储介质
CN114138376B (zh) 一种在应用中加载插件的方法、计算设备及存储介质
US20170083298A1 (en) Resilient format for distribution of ahead-of-time compiled code components
US11030097B2 (en) Verifying the validity of a transition from a current tail template to a new tail template for a fused object
JP2022542007A (ja) テスト・ベクタを使用した高水準コンストラクトの最適化の自動検証
US11593080B1 (en) Eliminating dead stores
US20240134666A1 (en) Hybrid just in time load module compiler with performance optimizations
US10671362B2 (en) Generating code for function calls that use multiple addressing modes
CN114185556A (zh) 一种智能合约部署方法、装置、设备以及存储介质
CN114579135A (zh) 一种安装包生成方法及装置
WO2022180594A1 (en) Hybrid just in time load module compiler with performance optimizations
CN113010207A (zh) 资源配置方法、装置、电子设备及存储介质

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280003641.5

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2022925229

Country of ref document: EP

Effective date: 20230816