WO2024036452A1

WO2024036452A1 - Processing apparatus, and related control method for low-power-consumption standby

Info

Publication number: WO2024036452A1
Application number: PCT/CN2022/112593
Authority: WO
Inventors: 杨春杰
Original assignee: 华为技术有限公司
Priority date: 2022-08-15
Filing date: 2022-08-15
Publication date: 2024-02-22

Abstract

Disclosed in the present application are a processing apparatus, and a related control method for low-power-consumption standby. The present application is characterized in that the processing apparatus comprises a power management unit, a chip system and an on-chip memory, wherein the power management unit supplies power to the chip system by means of a first power domain, and supplies power to the on-chip memory by means of a second power domain; the power management unit is used for receiving a first indication sent by the chip system, which first indication is used for indicating that the processing apparatus has entered a standby state, and the power management unit is also used for controlling the first power domain to turn off, and keeping some or all power sources of the second power domain in a power supply state; after the processing apparatus enters the standby state, the chip system is in a powered-off state and some or all devices of the on-chip memory are in a powered-on state; a first control signal is sent to the on-chip memory, and the first control signal is used for keeping the on-chip memory in a first mode, and in the first mode, the on-chip memory stores currently stored data. By using the embodiments of the present application, standby power consumption can be reduced, thereby increasing a standby duration and improving the user experience.

Description

A processing device and related low-power standby control method

Technical field

The present invention relates to the field of chip technology, and in particular, to a processing device and related low-power standby control method.

Background technique

Under conditions of limited battery capacity, when terminal devices such as smartphones or smart watches are in standby mode, that is, the terminal device is turned on but not performing any substantial work (i.e., not operating files and programs), in order to obtain longer The standby time required is getting lower and lower.

When the existing terminal equipment is in standby state, considering that the time for the terminal equipment to return from standby state to normal working state should not be too long, it is necessary to reserve at least one low-voltage normally open area for the system on chip (SoC) of the terminal equipment. (Always ON, AO) power domain and high-voltage interface power domain to ensure that some data or configurations are retained in standby state, thereby reducing power-on recovery time. In this scenario, the standby power consumption of the terminal device mainly includes SoC standby power consumption, and also includes other power consumption such as memory, power management unit and board level. However, during actual application, it was found that when the terminal device enters the standby state, the SoC standby power consumption is high and the maximum proportion of SoC standby power consumption can reach more than half of the total power consumption, which greatly shortens the standby time of the terminal device.

Therefore, how to provide a processing device and related low-power standby control method to reduce standby power consumption, increase standby time, and improve user experience is an issue that needs to be solved urgently.

Contents of the invention

Embodiments of the present invention provide a processing device and related low-power standby control method to reduce standby power consumption, increase standby time, and improve user experience.

In a first aspect, an embodiment of the present invention provides a processing device, characterized in that the processing device includes a power management unit, a system-on-chip SoC and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit. unit, the power management unit supplies power to the SoC through the first power domain, and supplies power to the internal memory through the second power domain; the power management unit is used to: receive the first instruction sent by the SoC, The first instruction is used to instruct the processing device to enter a standby state; control to disconnect the first power domain and keep part or all of the power supply of the second power domain in a power supply state; wherein the processing device is in After entering the standby state, the SoC is in a completely power-off state and some or all devices of the internal memory are in a power-on state; a first control signal is sent to the internal memory, and the first control signal is used to maintain The internal memory is in a first mode, wherein in the first mode the internal memory stores currently stored data.

In the embodiment of the present invention, when the processing device enters the standby state, the SoC can first control the internal memory to enter the self-refresh mode, and then the power management unit takes over some of the control signals of the internal memory to maintain the internal memory in the self-refresh state, and then the power management unit The unit can shut down the entire power supply to the SoC, thereby reducing the overall standby power consumption of the processing device. Furthermore, when the processing device is woken up (that is, the processing device returns to normal working status), since the data in the internal memory is not lost, there is no need to re-read relevant data from the external memory to the internal memory (that is, the processing device does not need to be powered on and initialized again). process), thereby reducing the power-on recovery time of the processing device. In the existing technology, after the processing device enters the standby state, the SoC needs to continue to control and manage the internal memory, that is, the SoC needs to maintain the internal memory in the self-refresh mode to ensure that the data currently stored in the internal memory is not lost. Therefore, in the existing It is technically impossible to completely power off the SoC. In summary, in this application, by improving the power management unit in the processing device, when the processing device enters the standby state, the power management unit can take over the internal memory after the SoC is completely powered off and maintain the internal memory in the self-refresh mode. , which not only ensures that the processing device can return to normal working status in a short period of time, but also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

In a possible implementation, the power management unit includes a status register and a first control module; the power management unit is specifically configured to: after receiving the first instruction sent by the SoC, The status register is set to a first state; in the first state, the signal output by the SoC to the internal memory is shielded through the first control module, and the first control signal is sent to the internal memory. signal to maintain the internal memory in the first mode.

In the embodiment of the present invention, the power management unit includes a status register and a first control module. When the power management unit receives the first instruction sent by the SoC, it can first set the status register to 1 (that is, the first state) , which in turn can indicate that the processing device enters a standby state, and then the power management unit can take over the internal memory. During this process, in order to avoid that after the SoC is powered off, the signal sent by the SoC to the internal memory through the power management unit becomes unstable, causing the control signal sent by the power management unit to the internal memory to be disordered and destroying the self-refresh state of the internal memory. Therefore, the power supply The first control module in the management unit will shield the signal sent by the SoC to the internal memory (for example, the signal sent by the SoC to the internal memory can be shielded before the SoC is completely powered off), and the power management unit will fully control and manage the internal memory. Furthermore, the first control module of the power management unit can send a first control signal to the internal memory to maintain the internal memory in the self-refresh mode, so that the internal memory can still save the currently stored data when the processing device is in the standby state. In summary, in this application, after the processing device enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. This ensures that the processing device can resume normal operation in a short period of time. status, it also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

In a possible implementation, the internal memory is configured to: receive the first control signal sent by the power management unit, and maintain the first mode to save currently stored data.

In the embodiment of the present invention, after the power management unit takes over the internal memory, the power management unit can control and manage the state of the internal memory. Therefore, after the internal memory receives the first control signal sent by the power management unit, it can maintain the self-refresh mode (ie, the first mode), that is, the internal memory continuously refreshes the currently stored data, so that the processing device enters the standby state. Afterwards, the internal memory can still retain the currently stored data. In summary, in this application, after the processing device enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. This ensures that the processing device can resume normal operation in a short period of time. status, it also reduces the standby power consumption of the processing device, increases the standby time, and improves the user experience.

In a possible implementation, the processing device further includes an external memory, and the power management unit is further coupled with the external memory, and the power management unit supplies power to the external memory through a third power domain; The power management unit is further configured to: after receiving the first instruction sent by the SoC, keep part or all of the power supply of the third power domain in a power supply state, wherein the processing device enters the standby state. After the state, some or all devices of the external memory are in the power-on state; a second control signal is sent to the external memory, and the second control signal is used to maintain the external memory in the second mode, wherein, in the In the second mode, the external memory retains current configuration parameters.

In the embodiment of the present invention, after the power management unit receives the first instruction sent by the SoC, in order to avoid the problem of losing the current configuration parameters of the external memory after the processing device enters the standby state, the power management unit will maintain the third power domain. In power supply state. In order to reduce the power consumed in standby, some power domains in the third power domain can also be powered off, that is, some or all devices that do not affect the storage of current configuration parameters in the external memory can be powered off. Further, when the processing device enters the standby state, the SoC can be powered off, and the power management unit takes over the internal memory and external memory. After the power management unit takes over the external memory, it can send a second control signal to the external memory to maintain the external memory in the second mode. That is, the second mode can be understood as a low power consumption mode of the external memory. In low power consumption mode, the external memory can still retain the current configuration parameters and configuration status. In summary, after the processing device in this application enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. At the same time, the external memory also retains the current configuration parameters, which ensures that the processing The device can return to normal working status in a shorter period of time, which also reduces the standby power consumption of the processing device, increases the standby time, and improves user experience.

In a possible implementation, the power management unit further includes a second control module; when the status register is set to the first state, the power management unit is specifically configured to: A second control module, shields the signal output by the SoC to the external memory, and sends the second control signal to the external memory to maintain the external memory in the second mode.

In the embodiment of the present invention, in addition to multiple power domains, a first control module and a status register, the power management unit may also include a second control module. After receiving the first instruction sent by the SoC, the power management unit can first set the status register to 1 (ie, the first state), which can indicate that the processing device enters the standby state, and then the power management unit can take over the external memory. During this process, in order to avoid that after the SoC is powered off, the signal sent by the SoC to the external memory through the power management unit becomes unstable, causing the signal sent by the power management unit to the external memory to be disordered. Therefore, the second control module in the power management unit will The signal sent by the SoC to the external memory is shielded, and the power management unit fully controls and manages the external memory. The second control module of the power management unit can then send a second control signal to the external memory, so that the external memory can be maintained at low power. consumption mode, so that the external memory can still save the current configuration parameters and configuration status when the processing device is in standby mode. In summary, after the processing device in this application enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. At the same time, the external memory also retains the current configuration parameters, which ensures that the processing The device can return to normal working status in a shorter period of time, which also reduces the standby power consumption of the processing device, increases the standby time, and improves user experience.

In a possible implementation, the external memory is configured to receive the second control signal sent by the power management unit and maintain the second mode to retain current configuration parameters.

In the embodiment of the present invention, after the power management unit takes over the external memory, the power management unit can control and manage the status of the external memory. Therefore, when the external memory receives the second control signal sent by the power management unit, it can remain in the low power consumption mode (second mode), that is, the external memory can still retain the current configuration information and data after the processing device enters the standby state. Configuration status. In summary, after the processing device in this application enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. At the same time, the external memory also retains the current configuration parameters, which ensures that the processing The device can return to normal working status in a shorter period of time, which also reduces the standby power consumption of the processing device, increases the standby time, and improves user experience.

In a possible implementation, the power management unit is further configured to: upon receiving an indication that the processing device needs to resume its working state, restore the first power domain and supply power to the SOC; receive The second instruction sent by the SOC sets the status register to a second state; in the second state, the signal output by the SoC to the internal memory is unshielded, and the signal output by the SoC to the internal memory is forwarded. The signal output by the internal memory is sent to the internal memory; or, the signal output by the SoC to the external memory is unblocked, and the signal output by the SoC to the external memory is forwarded to the external memory.

In the embodiment of the present invention, when the power management unit receives an instruction to wake up the processing device, it can restore the first power domain and continue to supply power to the SoC. After the SoC is powered on, it can continue to control and manage the internal memory and external memory. Further, after the SoC is powered on, it can send a second instruction to the power management unit. After receiving the second instruction, the power management unit can set the status register to the second state (ie, SR=0), indicating that the processing device is in normal condition. The working state can also indicate that the power management unit no longer needs to continue to control and manage the internal memory and external memory. Next, the SoC can unblock the control signals from the SoC to the power management unit by controlling the relevant logic of the power management unit, and at the same time transparently transmit the relevant control signals to the internal memory and external memory through the power management unit. Finally, the processing device returns to normal working condition. In summary, after the processing device in this application enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. At the same time, the external memory also retains the current configuration parameters, which ensures that the processing The device can return to normal working status in a shorter period of time, which also reduces the standby power consumption of the processing device, increases the standby time, and improves user experience.

In a possible implementation, the SoC is configured to: after the first power domain is turned on, determine whether the status register in the power management unit is in the first state; if the If the status register is in the first state, the second instruction is sent to the power management unit.

In the embodiment of the present invention, after the SoC is powered on again, it can first be determined whether the status register in the power management unit is in the first state. If the status register is in the first state, a second instruction can be sent to the power management unit to The relevant logic of the control power management unit unblocks the control signals sent by the SoC to the power management unit. At the same time, the SoC can transparently transmit the relevant control signals to the internal memory and external memory through the power management unit. If the status register is not in the first state, the processing device will perform a power-on restart process, which requires reconfiguring the external memory and re-reading the required data from the external memory to the internal memory. In summary, after the processing device in this application enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. At the same time, the external memory also retains the current configuration parameters, which ensures that the processing The device can return to normal working status in a shorter period of time, which also reduces the standby power consumption of the processing device, increases the standby time, and improves user experience.

In a second aspect, embodiments of the present invention provide a low-power standby control method, which is characterized in that it is applied to a processing device. The processing device includes a power management unit, a system-on-chip SoC and an internal memory, wherein the SoC and the The internal memory is coupled to the power management unit, the power management unit supplies power to the SoC through a first power domain, and supplies power to the internal memory through a second power domain; the method includes: using the power management unit A unit that receives a first instruction sent by the SoC, where the first instruction is used to instruct the processing device to enter a standby state; and controls to disconnect the first power domain through the power management unit and maintain the first power domain. Part or all of the power supplies in the second power domain are in a power supply state; wherein, after the processing device enters the standby state, the SoC is in a completely power-off state and some or all devices of the internal memory are in a power-on state; by The power management unit sends a first control signal to the internal memory. The first control signal is used to maintain the internal memory in a first mode, wherein in the first mode, the internal memory saves the current stored data.

In a possible implementation, the power management unit includes a status register and a first control module; sending a first control signal to the internal memory through the power management unit includes: upon receiving the After the first instruction is sent by the SoC, the status register is set to the first state; in the first state, the signal output by the SoC to the internal memory is shielded through the first control module, and sending the first control signal to the internal memory to maintain the internal memory in the first mode.

In a possible implementation, the method further includes: receiving the first control signal sent by the power management unit through the internal memory, and maintaining the internal memory in the first mode to Save currently stored data.

In a possible implementation, the processing device further includes an external memory, and the power management unit is further coupled with the external memory, and the power management unit supplies power to the external memory through a third power domain; The method further includes: using the power management unit, after receiving the first instruction sent by the SoC, keeping part or all of the power supply of the third power domain in a power supply state, wherein the processing device enters After the standby state, some or all components of the external memory are in a powered-on state; a second control signal is sent to the external memory through the power management unit, and the second control signal is used to maintain the external memory. The memory is in a second mode, wherein the external memory retains current configuration parameters in the second mode.

In a possible implementation, the power management unit further includes a second control module; when the status register is set to the first state, the power management unit sends a signal to the external memory through the power management unit. Sending a second control signal includes: shielding the signal output by the SoC to the external memory through the second control module, and sending the second control signal to the external memory to maintain the external memory in The second mode.

In a possible implementation, the method further includes: receiving the second control signal sent by the power management unit through the external memory, and maintaining the external memory in the second mode to Keep current configuration parameters.

In a possible implementation, the method further includes: upon receiving an indication that the processing device needs to resume its working state, restoring the first power domain and powering the SoC through the power management unit; Through the power management unit, the second instruction sent by the SoC is received, and the status register is set to the second state; in the second state, the power management unit is used to unblock the SoC to the the signal output by the internal memory, and forward the signal output by the SoC to the internal memory; or, unblock the signal output by the SoC to the external memory, and forward the signal output by the SoC to the external memory. The external memory outputs the signal to the external memory.

In a possible implementation, the method further includes: after the first power domain is turned on, determining whether the status register in the power management unit is in the first state through the SoC; If the status register is in the first state, the second indication is sent to the power management unit through the SoC.

In a third aspect, the present application provides a terminal device that has the function of implementing any of the above low-power standby control methods. This function can be implemented by hardware, or it can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

In a fourth aspect, embodiments of the present invention provide a computer program. The computer program includes instructions. When the computer program is executed by a computer, the computer can perform any one of the low-power standby control methods in the second aspect. process.

In a fifth aspect, the present application provides a semiconductor chip, characterized in that the semiconductor chip includes the processing device described in any one of the above first aspects.

In a sixth aspect, the present application provides an electronic device, characterized in that the electronic device includes the semiconductor chip described in the fifth aspect.

Description of drawings

Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention.

Figure 2 is a schematic structural diagram of a processing device provided by an embodiment of the present invention.

Figure 3 is a schematic diagram of a power domain in a power management unit provided by an embodiment of the present invention.

FIG. 4 is a schematic diagram of a user interface of an electronic device entering a standby state according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a power domain after a processing device is in a standby state according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a power management unit after a processing device enters a standby state according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a power management unit after another processing device is in a standby state according to an embodiment of the present invention.

FIG. 8 is a schematic structural diagram of another power management unit after the processing device is in a standby state according to an embodiment of the present invention.

Figure 9 is a schematic structural diagram of another processing device provided by an embodiment of the present invention.

FIG. 10 is a schematic diagram of another power management unit after another processing device is in a standby state according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of a power management unit in the working state of a processing device provided by an embodiment of the present invention.

FIG. 12 is a schematic diagram of a power management unit in the working state of another processing device provided by an embodiment of the present invention.

FIG. 13 is a schematic diagram of a user interface for waking up an electronic device according to an embodiment of the present invention.

Figure 14 is a schematic flowchart of a processing device entering a standby state according to an embodiment of the present invention.

Figure 15 is a flow chart of a low-power standby control method provided by an embodiment of the present invention.

Detailed ways

The embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.

The terms “first”, “second”, “third” and “fourth” in the description, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific sequence. . Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

Reference herein to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

The terms "component", "module", "system", etc. used in this specification are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, processor, object, executable file, thread of execution, program and/or computer running on a processor. Through the illustrations, both applications running on the computing device and the computing device may be components. One or more components can reside in a process and/or thread of execution and a component can be localized on one computer and/or distributed between 2 or more computers. Additionally, these components can execute from various computer-readable media having various data structures stored thereon. A component may, for example, be based on a signal having one or more data packets (eg, data from two components interacting with another component, a local system, a distributed system, and/or a network, such as the Internet, which interacts with other systems via signals) Communicate through local and/or remote processes.

Based on the above, an embodiment of the present invention provides an electronic device. Please refer to Figure 1. Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. The electronic device 100 may include but is not limited to a smartphone, a smart wearable device (such as a smart watch), a tablet computer, a personal digital assistant, etc. Various types of equipment that rely on battery power. The electronic device 100 may have a built-in chip or chipset or a circuit board equipped with the chip or chipset, and the chip or chipset or the circuit board equipped with the chip or chipset can work under necessary software drivers. The chip or chipset or the circuit board equipped with the chip or chipset may include a power management unit 101, a system on chip 102, an internal memory 103, an external memory 104, a battery 105, and further may also include components not shown in Figure 1 Interfaces, peripherals and other components. specific,

The power management unit 101 can manage the power supply of the electronic device 100 . The power management unit 101 can be used to connect the battery 105, the system on chip 102, the internal memory 103, the external memory 104 and other devices. The power management unit 101 can receive input from the battery 105 and/or the charge management unit to provide power to the system-on-chip 102, internal memory 103, external memory 104, etc. The power management unit 101 can also be used to monitor battery capacity, battery cycle times, battery health status (leakage, impedance) and other parameters. Batteries 105 may include rechargeable batteries, and/or lithium batteries, etc. In some embodiments, when the electronic device 100 enters the standby state, the power management unit 101 can completely power off the system-on-chip 102, and the power management unit 101 can take over the internal memory 103 and the external memory 104 to maintain the internal memory 103 in the standby state. The self-refresh state and the external memory 104 are in a low power consumption state, which not only reduces standby power consumption, increases standby time, and improves user experience, but also enables quick power-on recovery of the system-on-chip 102. How the power management unit 101 takes over the internal memory 103 and the external memory 104 in the standby state will be described in detail in subsequent embodiments, and will not be described in detail here.

System On Chip 102 (System On Chip, SoC) may include a processor 1021 and a controller 1022. When the electronic device 100 is in a normal working state, the power management unit 101 supplies power to the system-on-chip 102. The processor 1021 in the system-on-chip 102 can run an operating system, a file system (such as a flash file system) or an application program to control the connection to the system. Processor 1021 is a plurality of hardware or software elements and can process various data and perform operations. The processor 1021 can load the instructions or data stored in the external memory 104 into the internal memory 103, and transfer the instructions or data that require operation to the processor 1021 for operation. When the operation is completed, the processor 1021 temporarily stores the results. In the internal memory 103, instructions or data that require long-term storage are stored in the external memory 104 through the controller 1022. The processor 1021 may include one or more processing units (also called processing cores). For example, the processor 1021 may include a central processing unit (CPU), an application processor (application processor, AP), a modem processing unit, a graphics unit Processing unit (graphics processing unit, GPU), image signal processing unit (image signal processor, ISP), video encoding and decoding unit, digital signal processing unit (digital signal processor, DSP), baseband processing unit and neural network processing unit (neural- One or more of network processing unit, NPU), etc. Among them, different processing units can be independent devices or integrated in one or more devices. Optionally, the processor 1021 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in processor 1021 is a cache memory (Cache). The Cache can store instructions or data just used or recycled by the processor 1021. If the processor 1021 needs to use the instruction or data again, it can be directly called from the Cache. Repeated access is avoided and the waiting time of the processor 1021 is reduced, thus improving the efficiency of the system. The controller 1022 in the system-on-chip 102 can be used to manage and control the data reading and writing between the processor 1021 and the internal memory 103 and the external memory 104. Provide standardized (such as Universal Flash Storage UFS standard) interfaces for communication between In some embodiments, for instructions or data issued from the processor 1021, the controller 1022 can convert the instructions or data into data packets supporting a certain protocol through encapsulation. For data received by the processor 1021, the controller 1022 Then perform the reverse operation. In some embodiments, when the electronic device 100 is in the standby state, all devices in the system-on-chip 102 may be in a power-off state, that is, the power management unit 101 may stop powering the system-on-chip 102 .

The internal memory 103 is usually a power-off volatile memory, which will lose its stored contents when the power is off. It can also be called memory or main memory. The internal memory 103 in this application includes readable and writable running memory, which is used to temporarily store the operation data in the processor 1021, and to interact with the external memory 104 or other external memories. It can be used as an operating system or other ongoing memory. A storage medium for temporary data of running programs. For example, the operating system running on the processor 1021 transfers the data that needs to be calculated from the internal memory 103 to the processor 1021 for calculation. When the calculation is completed, the processor 1021 transmits the result. In some embodiments, when the electronic device 100 enters the standby state, the power management unit 101 will continue to supply power to the internal memory 103 and put the internal memory 103 in a self-refresh mode to ensure that the data currently stored in the internal memory 103 is not lost, thus avoiding This eliminates the need to load the required data or instructions in the external memory 104 into the internal memory 103 again after the system-on-chip 102 is powered on again, thereby reducing the power-on recovery time of the system-on-chip 102 so that the electronic device 100 can recover more quickly. to normal working condition.

The internal memory 103 may include one or more of dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and the like. Among them, DRAM also includes Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), referred to as DDR, second-generation double-rate synchronous dynamic random access memory (DDR2), and third-generation double-rate synchronous dynamic random access memory (DDR SDRAM). DDR3), the fourth generation of low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 4, LPDDR4) and the fifth generation of low power consumption double data rate synchronous dynamic random access memory (Low Power Double Data Rate 5, LPDDR5), etc. .

The external memory 104 is a non-volatile memory, and its stored contents will not be lost after power failure. The external memory 104 can be used for long-term storage of instructions and data involved in the operation of the processor 1021, such as startup programs, operating systems, application programs, and data. Since the processor 1021 cannot directly read instructions and data in the external memory 104 nor directly write instructions or data to the external memory 104, when the processor 1021 executes a read (or load) instruction, it actually passes the controller 1022. The content to be read (including instructions and/or data) stored in the external memory 104 is temporarily loaded into the internal memory 103, and then the processor 1021 reads it from the internal memory 103; while performing writing (i.e., storing) When issuing an instruction, the processor 1021 actually first temporarily writes the data to be stored (including instructions and/or data) into the internal memory 103 , and then stores the data from the internal memory 103 to the external memory 104 through the controller 1022 . In some embodiments, when the electronic device 100 enters the standby state, the power management unit 101 will continue to supply power to the external memory 104 and put the external memory 104 in a low power consumption mode to ensure that the external memory 104 retains the current configuration parameters, preventing This eliminates the need for the external memory 104 to re-perform the power-on initialization process after the system-on-chip 102 is powered on again, thereby reducing the power-on recovery time of the system-on-chip 102, so that the electronic device 100 can return to a normal working state more quickly.

The external memory 104 may include Flash memory (for example, NAND flash memory, NOR flash memory, etc.), universal flash memory (universal flash storage, UFS), embedded multimedia card eMMC, universal flash memory storage multi-chip package uMCP memory, embedded multimedia card, etc. Chip package one or more of eMCP memory, solid state drive (SSD), etc.

It can be understood that the structure of the electronic device 100 in FIG. 1 is only some exemplary implementations provided by the embodiment of the present invention. The structure of the electronic device in the embodiment of the present invention includes but is not limited to the above implementations.

Please refer to Figure 2. Figure 2 is a schematic structural diagram of a processing device provided by an embodiment of the present invention. The processing device in the embodiment of the present application will be described in detail below with reference to Figure 2. As shown in Figure 2, the processing device 200 may include but is not limited to a power management unit 201, a system on chip 202 and an internal memory 203, wherein the system on a chip SoC 202 and the internal memory 203 are coupled to the power management unit 201. Unit 201 powers the SoC 202 through a first power domain and the internal memory 203 through a second power domain. It should be noted that the processing device 200 can be built into various types of equipment that require battery power, such as the electronic equipment 100 in Figure 1 above. The functions of the power management unit 201 can include parts of the power management unit 101 in Figure 1 above. or all functions. The functions of the SoC 202 may include part or all of the functions of the system-on-chip 102 in FIG. 1 , and the internal memory 203 may include part or all of the functions of the internal memory 103 in FIG. 1 . in,

The power management unit 201 is configured to receive a first instruction sent by the SoC 202, where the first instruction is used to instruct the processing device 200 to enter a standby state.

Specifically, the power management unit 201 can manage the power supply of each module in the processing device 200. For example, as shown in Figure 3, Figure 3 is a schematic diagram of the power domain in a power management unit provided by an embodiment of the present invention. In the figure, the power management The unit 201 supplies power to the SoC 202 through the first power domain, where the first power domain may include multiple sub-power domains, such as the system interface power supply (also called IO power supply), the low-voltage normally open area (Always ON, AO) power supply of the SoC 202 , memory control signal power supply and other power supplies; the power management unit 201 supplies power to the internal memory 203 (such as LPDDR4) through the second power domain, where the second power domain can also include multiple sub-power domains, such as the IO power supply inside the DDR, Control signal power supply, etc. System On Chip (SoC) 202 can refer to the integration of a complete system on a single chip. The so-called complete system generally includes a central processing unit (CPU), peripheral circuits, etc. The internal memory 203 is usually a power-off volatile memory, and the contents stored therein will be lost when the power is off. It can also be called memory or main memory. The internal memory 203 in this application includes readable and writable running memory, which is used to temporarily store the operation data in the SoC 202, and can exchange data with external memory or other external memories, and can be used as an operating system or other running memory. A storage medium for temporary data of a program.

Optionally, when the SoC 202 receives the user's target operation on the processing device 200, or the user does not perform any operation on the processing device 200 within a preset time period, the SoC 202 may be triggered to send a first instruction to the power management unit 201, so that The processing device 200 enters a standby state. For example, as shown in Figure 4, Figure 4 is a schematic user interface diagram of an electronic device that enters a standby state according to an embodiment of the present invention. In the figure, the electronic device (such as a smart phone, a smart wearable device, a tablet computer, etc.) Battery-powered equipment) has a built-in processing device 200. The electronic device in (a) of Figure 4 can display an operation interface during normal operation. When a user's pressing operation on the electronic device is detected (such as the user pressing on both sides of the electronic device) power button), the SoC 202 can be triggered to send a first instruction to the power management unit 201, so that the processing device 200 enters the standby state, and then the electronic device will be in a black screen standby state as shown in Figure 4(b).

The power management unit 201 is also configured to control the disconnection of the first power domain and keep part or all of the power supply of the second power domain in the power supply state; wherein the processing device 200 enters the standby state. After the state is reached, the SoC 202 is in a completely powered-off state and some or all devices of the internal memory 203 are in a powered-on state.

Specifically, after the power management unit 201 receives the first instruction sent by the SoC 202, the power management unit 201 may disconnect the first power domain. For example, as shown in Figure 5, Figure 5 is a schematic diagram of a power domain after a processing device is in a standby state according to an embodiment of the present invention. In the figure, the first power domain may include multiple sub-power domains. The power management unit 201 receives After receiving the first instruction sent by the SoC 202, all sub-power supplies in the first power domain will be disconnected, so that the SoC 202 is in a completely powered off state when the processing device 200 is in the standby state. In addition, since the internal memory 202 is a volatile memory upon power-off, in order to avoid data loss in the internal memory 203 when the processing device 200 is in the standby state, the power management unit 201 will keep the second power domain in the power supply state. Further, in order to reduce the power consumed in standby, some power domains in the second power domain can be powered off, that is, some or all devices that do not affect the storage of currently stored data in the internal memory 203 can be powered off. For example, The IO power supply of the internal memory 203 is powered off (the internal memory 203 does not need to interact with other modules when the processing device 200 is in the standby state, so the IO power supply can be powered off).

The power management unit 201 is further configured to: send a first control signal to the internal memory 203, where the first control signal is used to maintain the internal memory 203 in a first mode, wherein in the first mode The internal memory 203 described below stores currently stored data.

Specifically, when the power management unit 201 disconnects the first power domain, the SoC 202 is in a power-off state and cannot continue to control and manage the internal memory 203. The power management unit 201 can take over the internal memory 203, and the power management unit 201 can send data to the internal memory 203. The first control signal is to maintain the internal memory 203 in the first mode (that is, the first mode can be understood as the self-refresh mode of the internal memory 203). The first control signal is a signal (which can be a fixed level signal) that maintains the internal memory 203 in the self-refresh mode, and can be a signal composed of multiple signals, such as a signal composed of a clock enable signal and a reset signal. When the clock enable signal sent by the power management unit 201 to the internal memory 203 is 0 and the reset signal is 1, the internal memory 203 can always remain in the self-refresh mode.

Optionally, before the SoC 202 sends the first control signal to the power management unit 201, it may first send the control signal and related control commands to the internal memory 203, so that the internal memory 203 can enter the self-refresh state.

For example, as shown in Figure 6, Figure 6 is a schematic diagram of a power management unit after a processing device enters a standby state according to an embodiment of the present invention. In the figure, a control logic module (such as a first control module) can be added to the power management unit 201. ), when the SoC 202 is in the power-off state, the first control signal can be sent to the internal memory 203 through the control logic module, that is, the reset signal is 1 and the clock enable signal is 0, so as to maintain the internal memory 203 in the self-refresh mode. Therefore, when the processing device 200 is in the standby state, the internal memory 203 can still save the currently stored data.

It should be noted that when the processing device 200 enters the standby state, the internal memory 203 can save the currently stored data to avoid the need to re-read relevant data from the external memory after the processing device 200 wakes up, thereby reducing the power-on recovery time of the processing device 200 time.

Optionally, the first control signal can also be a single signal, such as a reset signal. SoC 202 can first send a clock enable signal of 0 to the internal memory 203 before powering off. When SoC 202 is powered off, the clock enable signal can be maintained through a pull-down resistor. The power signal is always 0, and then when the power management unit 201 sends a reset signal of 1 to the internal memory 203, the internal memory 203 can remain in the self-refresh mode. For example, as shown in Figure 5, the SoC 202 and the internal memory 203 can be connected through a transmission line and a pull-down resistor. Furthermore, the SoC 202 can first send a clock enable signal of 0 to the internal memory 203 before powering off, and after the SoC 202 is powered off, The clock enable signal is maintained at 0 through a pull-down resistor. Further, when the power management unit 201 takes over the internal memory 203, it can send a reset signal of 1 to the internal memory 203 to maintain the internal memory 203 in the self-refresh mode, so that the current data can still be saved when the processing device 200 is in the standby state. stored data.

In a possible implementation, the power management unit 201 includes a status register and a first control module; the power management unit 201 is specifically configured to: after receiving the first instruction sent by the SoC 202, The status register is set to a first state; in the first state, the signal output by the SoC 202 to the internal memory is shielded through the first control module, and the first signal is sent to the internal memory. A control signal to maintain the internal memory in the first mode.

Specifically, the status register (status register, SR) in the power management unit 201 can have two states. When SR=0, it can mean that the processing device 200 is in a normal working state; when SR=1 (that is, it can be understood as The status register is set to the first state. It should be emphasized that in the first state, SR=1), which can indicate that the processing device 200 enters the standby state. The first control module in the power management unit 201 may have control logic and may send signals to the internal memory 203 .

Next, description will be made with reference to Figure 7. Figure 7 is a schematic diagram of the power management unit after another processing device is in a standby state according to an embodiment of the present invention. In the figure, a status register and a first control unit can be added to the power management unit 201. module, when the power management unit 201 receives the first instruction sent by the SoC 202, it can first set the status register to 1 (that is, the first state), which can then indicate that the processing device 200 enters the standby state, and then the power management unit 201 can take over Internal memory 203. During this process, after the power management unit 201 takes over the internal memory 203 and before the SoC 202 is completely powered off, the SoC 202 may still send signals to the internal memory 203 through the power management unit 201. Therefore, the first control of the power management unit 201 can be used. The module shields the signal sent by the SoC 202 to the power management unit 201, and the power management unit 201 completely controls and manages the internal memory 203, and then the first control module of the power management unit 201 can send a first control signal to the internal memory 203 to maintain the internal memory 203. The memory 203 may be in a self-refresh mode, so that the memory 203 can still save currently stored data when the processing device 200 is in a standby state. In addition, after the SoC 202 is completely powered off, since the signal sent by the SoC 202 to the internal memory 203 through the power management unit 201 is blocked by the power management unit 201, the power management unit 201 fully controls and manages the internal memory 203 after the SoC 202 is completely powered off.

It should be noted that before SoC 202 is powered off, SoC 202 may also send the configuration information of the first control module to the power management unit 201, so that the power management unit 201 configures the first control module based on the configuration information as when SR=1 , the first control signal can be sent to the internal memory 203 .

In a possible implementation, the internal memory 203 is configured to receive the first control signal sent by the power management unit 201 and maintain the first mode to save currently stored data.

Specifically, after the power management unit 201 takes over the internal memory 203, the power management unit 201 can manage the status of the internal memory 203. Therefore, after receiving the first control signal sent by the power management unit 201, the internal memory 203 can maintain the self-refresh mode (ie, the first mode), that is, the internal memory 203 continuously refreshes the currently stored data, so that the processing After the device 200 enters the standby state, the internal memory 203 can still retain the currently stored data. In summary, in this application, after the processing device 200 enters the standby state, the SoC 202 is completely powered off and the internal memory 203 can still retain the currently stored data. This ensures that the processing device 200 can Restoring the normal working state also reduces the standby power consumption of the processing device 200 .

Optionally, as shown in Figure 7, the SoC 202 and the internal memory 203 can be connected through a transmission line and a pull-down resistor. Further, the SoC 202 can send a clock enable signal of 0 to the internal memory 203 before powering off, and power down the SoC 202. After power-on, the clock enable signal is maintained at 0 through the pull-down resistor. Further, when the power management unit 201 takes over the internal memory 203, it can actively send a reset signal of 1 (ie, the first control signal) to the internal memory 203, and then the internal memory 203 will respond when the clock enable signal is 0 and the reset signal is 1. In the state, the self-refresh mode can always be maintained, that is, the internal memory 203 continuously refreshes the currently stored data, so that after the processing device 200 enters the standby state, the internal memory 203 can still retain the currently stored data.

Optionally, as shown in Figure 8, Figure 8 is a schematic structural diagram of a power management unit after the processing device is in a standby state according to an embodiment of the present invention. In the figure, the first control module in the power management unit 201 can The internal memory 203 sends a reset signal and can also send a clock enable signal. After the power management unit 201 takes over the internal memory 203, the power management unit 201 can actively send a reset signal of 1 and a clock enable signal of 0 to the internal memory 203 (that is, the first control signal consists of a reset signal of 1 and a clock enable signal of 0). (composed of clock enable signal), then the internal memory 203 can always maintain the self-refresh mode when the clock enable signal is 0 and the reset signal is 1, that is, the internal memory 203 continuously refreshes the currently stored data to After the processing device 200 enters the standby state, the internal memory 203 can still retain the currently stored data.

In a possible implementation, the processing device 200 further includes an external memory 204, and the power management unit 201 is also coupled to the external memory 204. The power management unit 201 provides the power management unit for the external memory 204 through a third power domain. The external memory 204 supplies power; the power management unit 201 is also configured to: after receiving the first instruction sent by the SoC 202, keep part or all of the power supply of the third power domain in the power supply state, wherein the After the processing device 200 enters the standby state, some or all devices of the external memory 204 are in the power-on state; a second control signal is sent to the external memory 204, and the second control signal is used to maintain the external memory 204. The memory 204 is in a second mode, wherein the external memory 204 retains current configuration parameters in the second mode.

Specifically, the external memory 204 is generally a non-volatile memory, and its stored contents will not be lost after a power outage. Common external memory 204 may include Flash memory (for example, NAND flash memory, NOR flash memory, etc.), universal flash memory (universal flash storage, UFS), etc. Next, description will be made with reference to Figure 9. As shown in Figure 9, Figure 9 is a schematic structural diagram of another processing device provided by an embodiment of the present invention. In the figure, the power management unit 201 can also provide external memory through the third power domain. 204 (such as EMMC or UFS), where the third power domain may include multiple sub-power domains, such as the IO power supply inside the external memory 204, the control signal power supply, etc. After the power management unit 201 receives the first instruction sent by the SoC 202, in order to avoid the problem of losing the current configuration parameters of the external memory 204 after the processing device 200 enters the standby state, the power management unit 201 will keep the third power domain in the power supply state. . In order to reduce the power consumed in standby, some power domains in the third power domain can also be powered off. That is, some or all devices that do not affect the storage of the current configuration parameters in the external memory 204 can be powered off. For example, the external memory 204 can be powered off. The IO power supply is powered off (when the processing device 200 is in the standby state, the external memory 204 does not need to interact with other modules, so the IO power supply can be powered off). Further, when the processing device 200 enters the standby state, the SoC 202 can be powered off, and the power management unit 201 takes over the internal memory 203 and the external memory 204. After the power management unit 201 takes over the external memory 204, it can send a second control signal to the external memory 204, that is, the second control signal can be a reset signal. Since the external memory 204 can always receive a reset signal of 1, the external memory 204 can remain in the second mode, that is, the second mode can be understood as a low power consumption mode of the external memory 204 . In the low power consumption mode, the external memory 204 can still retain the current configuration parameters and configuration status.

Optionally, before the SoC 202 sends the first control signal to the power management unit 201, it may first send the control signal and related control commands to the external memory 204, so that the external memory 204 can enter the low power consumption mode.

It should be noted that when the processing device 200 enters the standby state, the current configuration parameters and configuration status of the external memory 204 can be retained to avoid the need to re-configure the external memory 204 after the processing device 200 wakes up, thus reducing the power-on recovery time of the processing device 200 time.

In a possible implementation, the power management unit 201 further includes a second control module; when the status register is set to the first state, the power management unit 201 is specifically configured to: The second control module shields the signal output by the SoC 202 to the external memory 204 and sends the second control signal to the external memory 204 to maintain the external memory 204 in the second mode.

Specifically, the power management unit 201 may also include a second control module. Next, description will be made with reference to Figure 10. As shown in Figure 10, Figure 10 is a schematic diagram of another power management unit after another processing device is in a standby state according to an embodiment of the present invention. In the figure, the power management unit 201 In addition to including multiple power domains, a first control module and a status register, a second control module may also be included. When the power management unit 201 receives the first instruction sent by the SoC 202, it can first set the status register to 1 (ie, the first state), which can then indicate that the processing device 200 enters the standby state, and then the power management unit 201 can take over the external memory. 204. During this process, since the SoC 202 may still send signals to the external memory 204 through the power management unit 201 after the power management unit 201 takes over the external memory 204 and before the SoC 202 is completely powered off, the second control module in the power management unit 201 The signal sent by the SoC 202 to the external memory 204 will be shielded, and the power management unit 201 will completely control and manage the external memory 204. Then the second control module of the power management unit 201 can send a second control signal to the external memory 204 to maintain the external memory. The memory 204 can be in a low power consumption mode, so that the current configuration parameters and configuration status can still be saved when the processing device 200 is in a standby state. In addition, after the SoC 202 is completely powered off, the second control module will also block the unsteady signal output by the SoC 202 to the external memory 204 through the power management unit 201, so that the power management unit 201 can fully control and manage the external memory 204 after the SoC 202 is completely powered off. .

It should be noted that before SoC 202 is powered off, SoC 202 may also send the configuration information of the second control module to the power management unit 201, so that the power management unit 201 configures the second control module based on the configuration information as when SR=1 , the second control signal can be sent to the external memory 204.

Specifically, after the power management unit 201 takes over the external memory 204, the power management unit 201 can control and manage the status of the external memory 204. Therefore, when the external memory 204 receives the second control signal sent by the power management unit 201, it can remain in the low power consumption mode (second mode), that is, the external memory 204 can still retain the current state after the processing device 200 enters the standby state. configuration information and configuration status. In summary, in this application, after the processing device 200 enters the standby state, the SoC 202 is completely powered off and the external memory 204 can still retain the current configuration parameters and configuration status. This ensures that the processing device 200 can operate in a short period of time. The normal working state is restored within a certain period of time, which also reduces the standby power consumption of the processing device 200, increases the standby time, and improves the user experience.

In a possible implementation, the power management unit 201 is further configured to: upon receiving an indication that the processing device 200 needs to resume its working state, restore the first power domain and power the SoC 202; Receive the second instruction sent by the SoC 202, set the status register to the second state; in the second state, unblock the signal output by the SoC 202 to the internal memory 203, and forward the SoC 202 The signal output to the internal memory 203 is sent to the internal memory 203; or, the signal output by the SoC 202 to the external memory 204 is unblocked, and the signal output by the SoC 202 to the external memory 204 is forwarded to the external memory 204. External memory 204.

Specifically, when the power management unit 201 receives an instruction to wake up the processing device 200, it can restore the first power domain and continue to power the SoC 202. When the SoC 202 is powered on, it can continue to control and manage the internal memory 203 and the external memory 204. Further, after the SoC 202 is powered on, it can send a second instruction to the power management unit 201. After receiving the second instruction, the power management unit 201 can set the status register to the second state (ie, SR=0), indicating that the processing device 200 is in a normal working state, which may also indicate that the power management unit 201 does not need to continue to control and manage the internal memory 203 and the external memory 204 . Next, the SoC 202 can unblock the control signals from the SoC 202 to the power management unit 201 by controlling the relevant logic of the power management unit 201, and at the same time transparently transmit the relevant control signals to the internal memory 203 and the external memory 204 through the power management unit 201. Finally, the processing device 200 returns to normal working status.

For example, as shown in Figure 11, Figure 11 is a schematic diagram of a power management unit in the working state of a processing device provided by an embodiment of the present invention. In the figure, after the power management unit 201 receives the second control signal sent by the SoC 202, it can The status register is set to 0, indicating that the power management unit 201 does not need to continue to control the internal memory 203 and the external memory 204, that is, the first control module of the power management unit 201 does not need to continue to control the internal memory 203, and the second control module of the power management unit 201 does not need to continue to control the internal memory 203. The control module does not need to continue to control and manage the external memory 204. Further, the first control module can unblock the signal output by the SoC 202 to the internal memory 203, and forward the signal output by the SoC 202 to the internal memory 203 to the internal memory 203. For example, the first control module can directly forward the reset signal sent by the SoC 202 to the internal memory. 203; The second control module can unblock the signal output by the SoC 202 to the external memory 204, and forward the signal output by the SoC 202 to the external memory 204 to the external memory 204. For example, the second control module can directly forward the reset signal sent by the SoC 202 to the external memory 204. .

For another example, as shown in Figure 12, Figure 12 is a schematic diagram of the power management unit in the working state of another processing device provided by an embodiment of the present invention. In the figure, after the power management unit 201 receives the second control signal sent by the SoC 202, The status register can be set to 0, indicating that the power management unit 201 does not need to continue to control the internal memory 203 and the external memory 204, that is, the first control module of the power management unit 201 does not need to continue to control the internal memory 203. The second control module does not need to continue to control and manage the external memory 204 . Further, the first control module can unblock the signal output by the SoC 202 to the internal memory 203, and forward the signal output by the SoC 202 to the internal memory 203 to the internal memory 203. For example, the first control module can directly forward the reset signal and clock signal sent by the SoC 202. The signal can be sent to the internal memory 203; the second control module can unblock the signal output by the SoC 202 to the external memory 204, and forward the signal output by the SoC 202 to the external memory 204 to the external memory 204. For example, the second control module can directly forward the reset sent by the SoC 202. signal to external memory 204.

Optionally, as shown in Figure 13, Figure 13 is a schematic diagram of a user interface for waking up an electronic device according to an embodiment of the present invention. In the figure, the electronic device has a built-in processing device 200. When the processing device 200 is in a standby state, as shown in Figure The electronic device shown in (a) of 13 is in a black screen standby state. When the user's pressing operation on the electronic device is detected (such as the user pressing the power button on both sides of the electronic device), the power management unit 201 will receive The processing device 200 needs an instruction to resume the working state to wake up the processing device 200, and then the electronic device can be lit up and the operation interface can be displayed on the electronic device as shown in (b) of FIG. 13 .

In a possible implementation, the SoC 202 is configured to: after the first power domain is turned on, determine whether the status register in the power management unit 201 is in the first state; if If the status register is in the first state, the second instruction is sent to the power management unit 201.

Specifically, after the SoC 202 is powered on again, it can first determine whether the status register in the power management unit 201 is in the first state. If the status register is in the first state, a second instruction can be sent to the power management unit 201 to control the power supply. The relevant logic of the management unit 201 unblocks the control signal sent by the SoC 202 to the power management unit 201. At the same time, the SoC 202 can transparently transmit the relevant control signal to the internal memory 203 and the external memory 204 through the power management unit 201. If the status register is not in the first state, the processing device 200 will perform a power-on restart process, which requires reconfiguring the external memory 204 and re-reading the required data from the external memory 204 to the internal memory 203 .

Next, take a mobile phone as an example and illustrate from the SoC 202 side with reference to Figure 14. As shown in Figure 14, Figure 14 is a schematic flow chart of a processing device entering a standby state according to an embodiment of the present invention. In the figure, the mobile phone has a built-in processing device. 200, entering the standby state of the mobile phone may include the following steps S401 to S419. The detailed description is as follows:

S401: The phone enters normal standby mode. Specifically, SoC202 can first enter the normal standby mode after receiving the user's target operation on the mobile phone. It should be emphasized that in the normal standby mode, the power management unit 201 does not completely power off the SoC 202, and the SoC 202 still controls and manages the internal memory 203 and the external memory 204.

S402: The SOC returns to the normal working state, and the PMU exits the power saving mode. Specifically, when the time for the mobile phone to enter the normal standby mode exceeds the preset value, the SoC 202 can receive a timeout interrupt to wake up, so that the SoC 202 returns to the normal working state, and the power management unit 201 (ie, PMU) exits the power saving mode.

S403: SOC saves the DDR training sequence into FLASH. Specifically, SoC 202 saves the training sequence of internal memory 203 (ie, DDR) into external memory 204 (ie, FLASH).

S404: SOC saves on-site parameters to DDR and configures DDR to enter self-refresh mode. Specifically, the SoC 202 saves the data into the internal memory 203 and configures the internal memory 203 to enter the self-refresh mode, so that the data saved in the internal memory 203 is not lost after the mobile phone enters the super standby mode.

S405: SOC configures PMU Logic control1, shields the input signal PMU_FLASH_RST_N, and fixes the output FLASH_RST_N to 1. Specifically, before SoC 202 is completely powered off, SoC 202 can configure the logic control module in the power management unit 201 so that after SoC 202 is completely powered off, the logic control module can shield the signal output by SoC 202 to the external memory 204 and send the signal to the external memory. 204 outputs a control signal to cause the external memory 204 to enter a low power consumption mode and retain the current configuration parameters and configuration status.

S406: SOC configures PMU Logic control2, shields the input signal PMU_DDR_RST_N, and fixes the output DDR_RST_N to 1. Specifically, before SoC 202 is completely powered off, SoC 202 can configure the logic control module in the power management unit 201 so that after SoC 202 is completely powered off, the logic control module can shield the signal output by SoC 202 to the internal memory 203 and transmit the signal to the internal memory. 203 outputs a control signal to cause the internal memory 203 to enter the self-refresh mode to avoid data loss in the internal memory 203 .

S407: SOC configures PMU Super SR to 1. Specifically, before SoC 202 is completely powered off, SoC 202 can first configure the status register in the power management unit 201 so that SR=1, which can indicate that the mobile phone will enter a deep standby state, and the power management unit 201 can take over the internal memory 203 and External memory 204.

S408: SOC controls the power off of the PMU, and the PMU enters the Super SR power off process. Specifically, the SoC 202 may send a first instruction to the power management unit 201, so that the power management unit 201 completely powers off the SoC 202.

S409: The entire SOC is powered off, the DDR and FLASH parts are powered on, and the PMU enters the power saving (Economical, ECO) mode. Specifically, after receiving the first instruction sent by the SoC 202, the power management unit 201 can completely power off the SoC 202, or can power off part of the internal memory 203 and the external memory 204.

S410: SOC enters super standby mode.

S411: The mobile phone enters super standby. Specifically, when the SoC 202 is completely powered off, the mobile phone enters the super standby mode. At this time, the power management unit 201 can take over the internal memory 203 and the external memory 204 .

S412: PMU goes through the Super SR power-on process, including the clock start process. Specifically, when the power management unit 201 receives a wake-up interrupt such as the user pressing the power button of the mobile phone, the power management unit 201 can perform the Super SR power-on process including starting the clock.

S413: The SOC is powered on to run the startup code and access the PMU Super SR to see if it is 1. Specifically, the power management unit 201 can re-power the SoC 202, and after the SoC 202 resumes normal operation, it can first access whether the status register in the power management unit 201 is 1 to determine whether the mobile phone is in deep standby mode.

S414: If yes, the SOC runs the Super standby recovery process. Specifically, if the status of the status register in the power management unit 201 is 1 after the SoC 202 resumes normal operation, it indicates that the mobile phone needs to wake up from the deep standby state. If not, the SOC runs the normal power-on reset process, indicating that the phone needs to wake up from the shutdown state.

S415: SOC configures PMU Super SR to 0. Specifically, the status register in the power management unit 201 can be configured to 0 first to indicate that the mobile phone has entered a normal working state. It can also indicate that the power management unit 201 does not need to continue to control and manage the internal memory 203 and the external memory 204.

S416: SOC configures PMU Logic control1 to be in pass-through mode, that is, the signal FLAHS_RST_N is equivalent to the SOC output signal PMU_FLASH_RST_N. Specifically, the power management unit 201 no longer needs to continue to control and manage the external memory 204, so the logic control module can be configured in the pass-through mode.

S417: SOC configures PMU Logic control2 to pass-through mode, that is, the signal DDR_RST_N is equal to the SOC output signal PMU_DDR_RST_N. Specifically, the power management unit 201 no longer needs to continue to control the internal memory 203, so the logic control module can be configured in the pass-through mode.

S418: DDR exits self-refresh, FLASH completes fast initialization, and SOC returns to the scene.

S419: SOC returns to Normal mode.

In the embodiment of the present invention, after the processing device enters the standby state, the SoC is completely powered off and the internal memory can still retain the currently stored data. At the same time, the external memory also retains the current configuration parameters. This ensures that The processing device can return to normal working status in a shorter period of time, which also reduces the standby power consumption of the processing device, increases the standby time, and improves user experience.

The above describes the processing device of the embodiment of the present invention in detail, and the following provides relevant methods of the embodiment of the present invention.

Please refer to Figure 15. Figure 15 is a flow chart of a low-power standby control method provided by an embodiment of the present invention. This method is applicable to a processing device in Figure 2 and equipment including the processing device. The method may include the following steps S501 to S503. Wherein, the processing device includes a power management unit, a system on chip SoC and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, and the power management unit provides the SoC with a first power domain. Power is supplied to the internal memory through the second power domain. The detailed description is as follows:

Step S501: Receive the first instruction sent by the SoC through the power management unit.

Specifically, the first instruction is used to instruct the processing device to enter a standby state;

Step S502: Use the power management unit to control the disconnection of the first power domain and keep part or all of the power supply of the second power domain in the power supply state.

Wherein, after the processing device enters the standby state, the SoC is in a completely powered off state and some or all components of the internal memory are in a powered on state;

Step S503: Send a first control signal to the internal memory through the power management unit.

Specifically, the first control signal is used to maintain the internal memory in a first mode, wherein in the first mode, the internal memory saves currently stored data.

In a possible implementation, the method further includes: upon receiving an indication that the processing device needs to resume its working state, using the power management unit to restore the first power domain and supply power to the SOC; Through the power management unit, the second instruction sent by the SOC is received, and the status register is set to the second state; in the second state, the power management unit is used to unblock the SoC to the The signal output by the internal memory, and forward the signal output by the SoC to the internal memory to the internal memory; or, unblock the signal output by the SoC to the external memory, and forward the signal output by the SoC to the external memory. The memory outputs the signal to the external memory.

This application provides a terminal device that has the function of implementing any of the above low-power standby control methods. This function can be implemented by hardware, or it can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

The present application provides a terminal device, which includes a processor, and the processor is configured to support the terminal device to perform corresponding functions in the low-power standby control method provided above. The terminal device may also include a memory coupled to the processor, which stores necessary program instructions and data for the terminal device. The terminal device may also include a communication interface for the terminal device to communicate with other devices or communication networks.

An embodiment of the present invention provides a computer program. The computer program includes instructions. When the computer program is executed by a computer, the computer can execute the process in any of the above-mentioned low-power standby control methods.

The present application provides a semiconductor chip, which is characterized in that the semiconductor chip includes any one of the processing devices mentioned above.

The present application provides an electronic device, which is characterized in that the electronic device includes the above-mentioned semiconductor chip.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

It should be noted that for the sake of simple description, the foregoing method embodiments are expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence. Because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily necessary for this application.

In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the above units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical or other forms.

The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or software functional units.

If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to cause a computer device (which can be a personal computer, a server, a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above methods in various embodiments of the present application. Among them, the aforementioned storage media may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviation: ROM) or random access memory (Random Access Memory, abbreviation: RAM) and other various storage media. The medium for program code.

As mentioned above, the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still make the foregoing technical solutions. The technical solutions described in each embodiment may be modified, or some of the technical features may be equivalently replaced; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in each embodiment of the present application.

Claims

A processing device, characterized in that the processing device includes a power management unit, a system on chip SoC and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, and the power management unit passes through a third One power domain supplies power to the SoC, and supplies power to the internal memory through a second power domain; the power management unit is used to:

Receive a first instruction sent by the SoC, where the first instruction is used to instruct the processing device to enter a standby state;

Control to disconnect the first power domain and keep part or all of the power supply of the second power domain in the power supply state; wherein, after the processing device enters the standby state, the SoC is in a completely powered off state and Some or all components of the internal memory are in a powered-on state;

A first control signal is sent to the internal memory, and the first control signal is used to maintain the internal memory in a first mode, wherein the internal memory saves currently stored data in the first mode.
The device of claim 1, wherein the power management unit includes a status register and a first control module; the power management unit is specifically used to:

After receiving the first indication sent by the SoC, setting the status register to a first state;

In the first state, the signal output by the SoC to the internal memory is shielded through the first control module, and the first control signal is sent to the internal memory to maintain the internal memory in the desired state. Describe the first mode.
The device according to claim 1 or 2, characterized in that the internal memory is used for:

Receive the first control signal sent by the power management unit and maintain the first mode to save currently stored data.
The device according to claim 2 or 3, characterized in that the processing device further includes an external memory, and the power management unit is further coupled with the external memory, and the power management unit provides power to the external memory through a third power domain. The external memory supplies power; the power management unit is also used for:

After receiving the first instruction sent by the SoC, keep part or all of the power supply of the third power domain in the power supply state, wherein after the processing device enters the standby state, part of the external memory Or all devices are powered on;

A second control signal is sent to the external memory, and the second control signal is used to maintain the external memory in a second mode, wherein in the second mode, the external memory retains current configuration parameters.
The device of claim 4, wherein the power management unit further includes a second control module; when the status register is set to the first state, the power management unit is specifically configured to:

Through the second control module, the signal output by the SoC to the external memory is shielded, and the second control signal is sent to the external memory to maintain the external memory in the second mode.
The device according to claim 4 or 5, characterized in that the external memory is used for:

Receive the second control signal sent by the power management unit, and maintain the second mode to retain current configuration parameters.
The device according to any one of claims 4 to 6, characterized in that the power management unit is also used to:

After receiving an indication that the processing device needs to resume working status, restore the first power domain and supply power to the SOC;

Receive the second instruction sent by the SOC and set the status register to the second state;

In the second state, unblock the signal output by the SoC to the internal memory, and forward the signal output by the SoC to the internal memory to the internal memory; or,

Unblock the signal output by the SoC to the external memory, and forward the signal output by the SoC to the external memory to the external memory.
The device of claim 7, wherein the SoC is used for:

After the first power domain is turned on, determine whether the status register in the power management unit is in the first state;

If the status register is in the first state, the second instruction is sent to the power management unit.
A low-power standby control method, characterized in that it is applied to a processing device. The processing device includes a power management unit, a system-on-chip SoC and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit. unit, the power management unit supplies power to the SoC through a first power domain, and supplies power to the internal memory through a second power domain; the method includes:

Receive, through the power management unit, a first instruction sent by the SoC, where the first instruction is used to instruct the processing device to enter a standby state;

Through the power management unit, the first power domain is controlled to be disconnected and part or all of the power supply of the second power domain is kept in the power supply state; wherein, after the processing device enters the standby state, the The SoC is in a completely powered-off state and some or all of the internal memory devices are in a powered-on state;

Through the power management unit, a first control signal is sent to the internal memory. The first control signal is used to maintain the internal memory in a first mode, wherein in the first mode, the internal memory stores The currently stored data.
The method of claim 9, wherein the power management unit includes a status register and a first control module; and sending a first control signal to the internal memory through the power management unit includes:

After receiving the first indication sent by the SoC, setting the status register to a first state;

In the first state, the signal output by the SoC to the internal memory is shielded through the first control module, and the first control signal is sent to the internal memory to maintain the internal memory in the desired state. Describe the first mode.
The method according to claim 9 or 10, characterized in that the method further includes:

Through the internal memory, the first control signal sent by the power management unit is received, and the internal memory is maintained in the first mode, so that in the first mode, the internal memory saves the currently stored The data.
The method according to claim 10 or 11, characterized in that the processing device further includes an external memory, and the power management unit is further coupled with the external memory, and the power management unit provides the third power domain for the The external memory supplies power; the method further includes:

Through the power management unit, after receiving the first instruction sent by the SoC, part or all of the power supply of the third power domain is kept in the power supply state, wherein the processing device enters the standby state. , some or all devices of the external memory are in a powered-on state;

Through the power management unit, a second control signal is sent to the external memory, the second control signal is used to maintain the external memory in a second mode, wherein in the second mode, the external memory retains Current configuration parameters.
The method of claim 12, wherein the power management unit further includes a second control module; when the status register is set to the first state, the power management unit controls The external memory sends a second control signal, including:

Through the second control module, the signal output by the SoC to the external memory is shielded, and the second control signal is sent to the external memory to maintain the external memory in the second mode.
The method according to claim 12 or 13, characterized in that the method further includes:

Through the external memory, receive the second control signal sent by the power management unit, and maintain the external memory in the second mode, so that the external memory retains the current configuration in the second mode. parameter.
The method according to any one of claims 12-14, characterized in that the method further includes:

After receiving an indication that the processing device needs to resume working status, restore the first power domain and power the SOC through the power management unit;

Through the power management unit, receive the second instruction sent by the SOC and set the status register to the second state;

In the second state, the power management unit unblocks the signal output by the SoC to the internal memory, and forwards the signal output by the SoC to the internal memory to the internal memory; or, by The power management unit unblocks the signal output by the SoC to the external memory, and forwards the signal output by the SoC to the external memory to the external memory.
The method of claim 15, further comprising:

After the first power domain is turned on, determine whether the status register in the power management unit is in the first state through the SoC;

If the status register is in the first state, the second indication is sent to the power management unit through the SoC.
A computer storage medium, characterized by including computer instructions, which when the computer instructions are run on an electronic device, cause the electronic device to perform the method according to any one of claims 9 to 16.