WO2024032027A1

WO2024032027A1 - Method for reducing power consumption, and processor, electronic device and storage medium

Info

Publication number: WO2024032027A1
Application number: PCT/CN2023/089977
Authority: WO
Inventors: 鲍道川; 尹磊祖; 李高山
Original assignee: Oppo广东移动通信有限公司
Priority date: 2022-08-11
Filing date: 2023-04-23
Publication date: 2024-02-15
Also published as: CN115390654A

Abstract

A method for reducing power consumption, and a processor (30), an electronic device (100) and a storage medium. The method for reducing power consumption comprises: according to a target instruction, determining a part to be calculated of data to be processed, wherein the data to be processed comprises the part to be calculated and a non-computational part; and calculating the part to be calculated, so as to obtain output data.

Description

Methods, processors, electronic devices and storage media for reducing power consumption

priority information

This application requests the priority and rights of the patent application with patent application number 202210960729.8, which was submitted to the State Intellectual Property Office of China on August 11, 2022, and its full text is incorporated herein by reference.

Technical field

The present application relates to processor technology, and in particular to a method for reducing power consumption, a processor, an electronic device and a storage medium.

Background technique

With the improvement of integrated circuit design level and manufacturing technology, the performance and integration level of processors are getting higher and higher. While ensuring the performance of the chip, reducing the power consumption of the processor has become a research direction to reduce the power consumption of the chip.

Contents of the invention

Embodiments of the present application provide a method, a processor, an electronic device, and a storage medium for reducing power consumption.

The method for reducing power consumption in the embodiment of the present application includes: determining the part to be calculated of the data to be processed according to the target instruction, wherein the data to be processed includes the part to be calculated and the non-computed part; and performing the operation on the part to be calculated. Operation to obtain output data.

The processor in the embodiment of the present application includes a preprocessing module and an operation module. The preprocessing module is used to obtain the parts to be calculated of the data to be processed according to the target instructions, where the data to be processed is divided into the parts to be calculated and the non-calculated parts; the operation module is used to calculate the parts to be calculated. Perform operations on the parts to obtain output data.

The electronic device in the embodiment of the present application includes a housing and the processor described in the above embodiment.

The computer-readable storage medium according to the embodiment of the present application has a computer program stored thereon. When the program is executed by a processor, the steps of the method for reducing power consumption described in the above embodiment are implemented.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

Figure 1 is a schematic flowchart of a method for reducing power consumption in some embodiments of the present application;

Figure 2 is a schematic diagram of a processor in some embodiments of the present application;

Figure 3 is a schematic diagram of an electronic device according to certain embodiments of the present application;

Figure 4 is a schematic flowchart of a method for reducing power consumption in some embodiments of the present application;

Figure 5 is a schematic diagram comparing methods for reducing power consumption and related technologies in certain embodiments of the present application;

Figure 6 is a schematic diagram comparing methods for reducing power consumption and related technologies in certain embodiments of the present application;

Figure 7 is a schematic flowchart of a method for reducing power consumption in some embodiments of the present application;

Figure 8 is a schematic diagram of a processor in some embodiments of the present application;

Figure 9 is a schematic flowchart of a method for reducing power consumption in some embodiments of the present application.

Detailed ways

Embodiments of the present application are described in detail below, embodiments of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and cannot be understood as limiting the present application.

In the description of the embodiments of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present application, "plurality" means two or more, unless otherwise explicitly and specifically limited.

Please refer to Figure 1. The method for reducing power consumption in the embodiment of this application includes:

01: According to the target instruction, determine the part of the data to be processed that needs to be calculated, where the data to be processed includes the part that needs to be calculated and the part that is not calculated.

The target instruction provides the basis for determining the part to be calculated of the data to be processed. Specifically, the target instruction may not only include a part that provides a basis for determining the part to be calculated of the data to be processed, but also may include a part that provides a basis for performing operations on the part to be calculated, and the part to be calculated of the data to be processed can be determined according to the target instruction. That’s it, there are no specific restrictions in this application. For ease of understanding, an example is given below, taking the data to be processed as including a real number part and an imaginary number part. In a certain embodiment, the target instruction may include calculating the real number part, so as to determine the part to be calculated of the data to be processed according to the target instruction: Real number part; in another embodiment, the target instruction may include calculating the addition of the imaginary number part to determine the part to be calculated of the data to be processed as the imaginary number part according to the target instruction, and perform an addition operation on the imaginary number part according to the target instruction to obtain the output data.

The parts to be calculated and the non-calculated parts are different parts of the same data respectively, that is, the parts to be calculated and the non-calculated parts together constitute the same data to be processed. The method of reducing power consumption in this application is to reduce power consumption by distinguishing parts of a certain data to be processed that do not require calculation.

02: Perform operations on the parts to be calculated and obtain output data.

The operations performed on the parts to be calculated may include but are not limited to addition, subtraction, multiplication, division and other operations, which are not specifically limited in this application.

Referring to FIG. 2 , the processor 30 in the embodiment of the present application includes a preprocessing module 31 and an operation module 32 .

The method of reducing power consumption of the present application can be implemented by the processor 30 of the embodiment of the present application, wherein step 01 can be implemented by the preprocessing module 31 and step 02 can be implemented by the computing module 32. That is to say, the preprocessing module 31 can According to the target instruction, the part to be calculated of the data to be processed is obtained, wherein the data to be processed is divided into a part to be calculated and a non-calculated part. The operation module 32 can be used to perform operations on the parts to be calculated to obtain output data.

In the above-mentioned method of reducing power consumption and the processor 30, the data to be processed can be divided into parts to be calculated and non-calculated parts. When calculating the output data of the data to be processed, only the parts to be calculated need to be calculated without calculating the non-calculated parts. , can avoid redundancy in calculation and achieve the effect of reducing power consumption.

In some implementations, referring to FIG. 3 , the processor 30 may be applied to the electronic device 100 . The electronic device 100 may include a smartphone, a tablet, a smart watch, a smart bracelet, and other devices, which are not specifically limited here. The electronic device 100 in the embodiment of the present application is explained by taking a smartphone as an example, which should not be understood as a limitation of the present application. Electronic device 100 also includes housing 50 .

Specifically, in related technologies, power consumption can be reduced by reducing voltage, reducing frequency, power gating and other technical methods. In other related technologies, some processors are configured with corresponding registers to shield redundant calculations. However, configuring corresponding registers will bring many unnecessary operations, and additional registers will also bring unnecessary hardware overhead.

This application does not need to configure registers and avoids additional hardware overhead. This application can obtain the to-be-calculated part of the data to be processed according to the target instruction, thereby avoiding the calculation of the non-calculated part, shielding redundant calculations, and achieving the effect of reducing power consumption.

It is worth noting that step 01 may be to obtain several parts to be calculated of the data to be processed according to the target instruction, and perform operations on each part to be calculated in step 02, which is not specifically limited in this application.

In some implementations, please refer to Figure 4, the target instructions include target calculation instructions, step 02, including:

021. According to the target calculation instruction, perform operations on the parts to be calculated to obtain output data.

In some embodiments, the above steps can be implemented by the operation module 32. That is to say, the operation module 32 can be used to perform operations on the parts to be calculated according to the target calculation instructions to obtain output data.

In this way, output data can be obtained according to the target calculation instructions.

Specifically, the target instructions may include target calculation instructions, and the target instructions may also include other instructions. The target calculation instruction can be understood as a target instruction that can provide a basis for obtaining the part to be calculated of the data to be processed, and Calculation instructions that provide a basis for operations on the parts to be calculated. To facilitate understanding, an example is given below. In a certain embodiment, the data to be processed includes a real number part and an imaginary number part, and the target instruction includes a target calculation instruction that adds the real number part of the data to be processed, then the target calculation instruction that adds the real number part of the data to be processed can be used. , obtain the real number part of the data to be processed; according to the target calculation instruction of adding the real number part of the data to be processed, perform an addition operation on the real number part to obtain the output data.

Further, the data to be processed includes the real part and the imaginary part. Step 01 includes:

According to the target calculation instruction, obtain the real number part or the imaginary number part as the part to be calculated;

Step 021, including:

According to the target calculation instruction, the real number part or the imaginary number part is operated to obtain the output data.

In some embodiments, according to the target calculation instruction, obtaining the real number part or the imaginary number part as the part to be calculated can be implemented by the preprocessing module 31. According to the target calculation instruction, performing operations on the real number part or the imaginary number part, and obtaining the output data can be performed by The operation module 32 implements, that is to say, the preprocessing module 31 can be used to obtain the real part or the imaginary part as the part to be calculated according to the target calculation instruction. The operation module 32 can be used to perform operations on the real number part or the imaginary number part according to the target calculation instruction to obtain output data.

In this way, the real number part or the imaginary number part that needs to be calculated can be obtained according to the target calculation instruction, and the parts that do not need to be calculated are shielded and redundant, thereby reducing power consumption.

Specifically, the target calculation instructions may include but are not limited to calculation instructions such as addition of the real part, multiplication of the real part, subtraction of the real part, addition of the imaginary part, etc., which are not specifically limited in this application. The real number part can be obtained according to the target instruction and the real number part can be operated; or the imaginary number part can be obtained according to the target instruction and the imaginary number part can be operated. There is no specific limitation in this application.

To facilitate understanding, an example is given below. In related technologies, please refer to the upper part of Figure 5. VSUB.SC16VR3 VR2 VR1 represents calculation instructions that do not include real part parameters and imaginary part parameters in related technologies. VR1, VR2 and VR3 respectively represent different vector registers. In this implementation In the method, according to the calculation instruction, the real part and the imaginary part of each element in the vector register VR1 and the vector register VR2 are subtracted correspondingly, and the result is placed in the vector register VR3. That is, in related technologies, the imaginary part needs to be calculated together, resulting in increased power consumption.

Please refer to the lower part of Figure 5. VSUB.SC16.IMAG VR3 VR2 VR1 represents the target calculation instruction of this application. The target calculation instruction includes real part parameters or imaginary part parameters. For example, IMAG refers to the imaginary part parameters, and SUB refers to subtraction. According to the target calculation instruction, you only need to subtract the imaginary part of each element in the vector register VR1 and vector register VR2, and the arithmetic unit corresponding to the real part is automatically turned off, and the output data can be obtained, avoiding the power consumption caused by calculating the real part. , to achieve the effect of reducing power consumption. It can be understood that the expression method of the target calculation instruction is not limited to VSUB.SC16.IMAG VR3 VR2 VR1. There are many other expression methods of the target calculation instruction, and the specific expression method is not specifically limited in this application.

In some embodiments, step 01 includes:

According to the target calculation instruction, obtain at least one quadrant part among the plurality of quadrant parts as the part to be calculated;

Step 021, including:

According to the target calculation instruction, at least one quadrant part among the plurality of quadrant parts is operated to obtain output data.

In some embodiments, according to the target calculation instruction, obtaining at least one quadrant part among the several quadrant parts as the part to be calculated can be implemented by the preprocessing module 31, and according to the target calculation instruction, performing at least one quadrant part among the several quadrant parts. The calculation and obtaining the output data can be implemented by the calculation module 32. That is to say, the pre-processing module 31 can be used to obtain at least one quadrant part among several quadrant parts as the part to be calculated according to the target calculation instruction. The operation module 32 may be used to perform operation on at least one quadrant part among several quadrant parts according to the target calculation instruction to obtain output data.

In this way, the quadrants that need to be calculated can be obtained according to the target calculation instructions, and the parts that do not need to be calculated are shielded and redundant, thereby reducing power consumption.

Specifically, the data to be processed may include two quadrants, three quadrants, four quadrants, etc., which are not specifically limited in this application. The target calculation instructions may include but are not limited to addition in the first quadrant, subtraction in the second quadrant, etc., and are not specifically limited in this application. According to the target instruction, the quadrant that needs to be calculated can be obtained, and the operation can be performed on the quadrant that needs to be calculated.

To facilitate understanding, an example is given below. In related technologies, please refer to the upper part of Figure 6. Taking the data to be processed as including four quadrants as an example, VADD.S8 VR3 VR2 VR1 represents calculation instructions that do not include quadrant parameters in related technologies. VR1, VR2 and VR3 are respectively represents different vector registers. In this embodiment, according to the calculation instruction, the quadrant data of each element in the vector register VR1 and the vector register VR2 are added correspondingly, and the result is placed in the vector register VR3. That is, in the related technology, the data of the other three quadrants need to be calculated together, resulting in a waste of power consumption.

Please refer to the lower part of Figure 6. VADD.S8.Q1 VR3 VR2 VR1 represents the target calculation instruction of this application. The target calculation instruction includes the parameters of the first quadrant. For example, Q1 refers to the parameters of the first quadrant, and ADD means addition. , according to the target calculation instructions, the output data can be obtained by simply adding the data of the first quadrant of each element in VR1 and VR2, avoiding the power consumption caused by calculating other quadrants, and achieving the effect of reducing power consumption. It is understandable that the expression method of target calculation instructions is not limited to VADD.S8.Q1 VR3 VR2 VR1. There are many other expression methods of target calculation instructions, and the specific expression methods are not specifically limited in this application.

In some embodiments, step 021 includes:

When performing operations on the parts to be calculated, close the operation units corresponding to the non-calculated parts.

The above steps can be implemented by the computing module 32. That is to say, the computing module 32 can be used to close the computing unit corresponding to the non-computing part when performing calculations on the part to be calculated.

In this way, power consumption of the computing unit corresponding to the non-computing part can be avoided.

In some implementations, referring to Figure 7, the method of reducing power consumption also includes:

04: When the processor is in target mode and receives a calculation instruction, determine the calculation instruction as a target instruction;

Step 01, including:

011: According to the target mode and calculation instructions, obtain the valid bits of the data to be processed as the parts to be calculated.

In some embodiments, please refer to FIG. 8 , the processor 30 also includes a processing module 33 , step 04 can be implemented by the processing module 33 , and step 011 can be implemented by the preprocessing module 31 , that is to say, the processing module 33 can be used for When the processor is in target mode and a calculation instruction is received, the calculation instruction is determined to be the target instruction. The preprocessing module 31 can be used to obtain the valid bits of the data to be processed as the parts to be calculated according to the target mode and calculation instructions.

In this way, only the effective bits of the data to be processed can be calculated, thereby reducing power consumption.

Specifically, the target mode may include a low-precision mode, a half-precision mode, and other modes. The target mode includes the accuracy requirements for the output data. It is understandable that in some application scenarios, the accuracy of the data to be processed exceeds the accuracy that meets the functional requirements. In related technologies, the data to be processed is usually calculated according to the accuracy of the data to be processed, and then the calculation results are shifted and Processing such as saturation and truncation results in a waste of power consumption. According to the embodiment of the present application, the data to be processed can be preprocessed before calculation according to the accuracy of the target mode, and the valid bits of the data to be processed are obtained as the parts to be calculated, thereby achieving the effect of reducing power consumption. It is worth noting that multiple target modes may be included, and the multiple target modes correspond to different accuracy requirements, so that the corresponding target mode can be determined according to the accuracy requirements. It is worth noting that whether the processor is in target mode can be adjusted according to application scenarios, processor load and other factors, and is not specifically limited in this application.

To facilitate understanding, examples are discussed below. In a certain implementation, the data to be processed is 32-bit data, and the 16-bit calculation accuracy can already meet the functional requirements. When the processor is in the target mode of 16-bit calculation accuracy and receives the calculation instruction, the calculation instruction is determined as The target instruction, according to the target mode and calculation instruction, obtains the 16-bit valid bits of the data to be processed as the part to be calculated. Specifically, combined with a reconfigurable design method, for example, if four 16-bit multipliers are combined into one 32-bit multiplier, then before calculating the 32-bit data to be processed, the 16-bit part to be calculated is obtained and passed through a 16-bit multiplication The processor calculates the 16-bit parts to be calculated, so that one multiplication instruction can reduce power consumption by nearly 75% compared to using four 16-bit multipliers.

It is worth mentioning that when the processor is in target mode but does not receive a calculation instruction, the processor does not start calculation, that is, the processor does not start to obtain the data to be processed. Therefore, it is necessary to wait until the processor is in target mode and receives In the case of a calculation instruction, the step of obtaining the valid bits of the data to be processed as the part to be calculated is then performed.

It should be added that the calculation instructions in this embodiment may include the above target calculation instructions. In the calculation instructions When issuing a target calculation instruction, you can combine the target mode and the target calculation instruction to obtain the part to be calculated of the data to be processed. To facilitate understanding, an example is given below. In some embodiments, the data to be processed includes a 32-bit real number part and a 32-bit imaginary number part. The calculation instruction includes adding the real number part. The target mode includes an accuracy requirement of 16 bits. Then, the data to be processed can be obtained according to the target mode and the calculation instruction. The high 16-bit significant bits of the real number part of the data are used as the parts to be calculated.

In some embodiments, see Figure 9, step 01 includes:

015: Load the part to be calculated.

In some embodiments, the above steps can be implemented by the preprocessing module 31, that is to say, the preprocessing module 31 can be used to load the part to be calculated.

In this way, only the part to be calculated can be loaded and the non-calculated part can be ignored, thereby avoiding the waste of power consumption caused by loading the non-calculated part.

In some embodiments, the method of reducing power consumption also includes:

According to the calculation instructions, perform operations on the data to be processed and obtain the operation results;

According to the target instruction, obtain the part to be stored of the operation result, where the operation result is divided into the part to be stored and the non-storage part;

Store the part to be stored and discard the non-storage part.

In some embodiments, the processor 30 may also include a storage module, and the above steps may be implemented by the storage module. That is to say, the storage module may be used to perform operations on the data to be processed according to the computing instructions to obtain operation results; according to the target instructions , obtain the part to be stored of the operation result, where the operation result is divided into the part to be stored and the non-storage part; store the part to be stored and discard the non-storage part.

In this way, the part to be stored can be obtained and the part to be stored can be avoided, thereby avoiding the power consumption caused by storing the non-storage part, thereby achieving the effect of reducing power consumption.

Specifically, in some application scenarios, for example, the operation result includes the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant, and only the first quadrant needs to be stored. In this case, the first quadrant can be obtained. Quadrant part and store the first quadrant part, discard the second quadrant part, the third quadrant part and the fourth quadrant part, and avoid the power consumption caused by storing the second quadrant part, the third quadrant part and the fourth quadrant part.

The computer-readable storage medium in the embodiment of the present application has a computer program stored thereon. When the program is executed by the processor, the steps of the method for reducing power consumption in any of the above embodiments are implemented.

For example, 01: According to the target instruction, obtain the part to be calculated of the data to be processed, where the data to be processed is divided into the part to be calculated and the non-calculated part;

02: Perform operations on the parts to be calculated and obtain output data.

It will be understood that a computer program includes computer program code. Computer program code may be in the form of source code, Object code form, executable file or some intermediate form, etc. Computer-readable storage media can include: any entity or device that can carry computer program code, recording media, USB flash drives, mobile hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM, Read-Only Memory), random access memory Access memory (RAM, Random Access Memory), and software distribution media, etc. The processor can be a central processing unit, or other general-purpose processor, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (Field-Programmable Gate) Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments, or portions of code that include one or more executable instructions for implementing the specified logical functions or steps of the process. , and the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed out of the order shown or discussed, including in a substantially simultaneous manner or in the reverse order, depending on the functionality involved, which shall It should be understood by those skilled in the technical field to which the embodiments of this application belong.

Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are illustrative and cannot be understood as limitations of the present application. Those of ordinary skill in the art can make modifications to the above-mentioned embodiments within the scope of the present application. The embodiments are subject to changes, modifications, substitutions and variations.

Claims

A method of reducing power consumption, characterized in that the method of reducing power consumption includes:

According to the target instruction, determine the part to be calculated of the data to be processed, wherein the data to be processed includes the part to be calculated and the non-calculated part;

Perform operations on the parts to be calculated to obtain output data.
The method for reducing power consumption according to claim 1, wherein the target instructions include target calculation instructions,

The operation on the part to be calculated to obtain output data includes:

According to the target calculation instruction, the part to be calculated is calculated to obtain the output data.
The method for reducing power consumption according to claim 2, wherein the data to be processed includes a real number part and an imaginary number part,

The step of obtaining the to-be-calculated part of the data to be processed according to the target instruction includes:

According to the target calculation instruction, obtain the real number part or the imaginary number part as the part to be calculated;

The step of performing operations on the part to be calculated according to the target calculation instruction to obtain the output data includes:

According to the target calculation instruction, the real number part or the imaginary number part is operated to obtain the output data.
The method for reducing power consumption according to claim 2, wherein the data to be processed includes several quadrants,

The step of obtaining the to-be-calculated part of the data to be processed according to the target instruction includes:

According to the target calculation instruction, obtain at least one quadrant part among a plurality of quadrant parts as the part to be calculated;

The step of performing operations on the part to be calculated according to the target calculation instruction to obtain the output data includes:

According to the target calculation instruction, at least one quadrant part among a plurality of quadrant parts is calculated to obtain the output data.
The method of reducing power consumption according to claim 2, characterized in that, performing operations on the parts to be calculated according to the target calculation instructions to obtain the output data includes:

When the operation is performed on the part to be calculated, the operation unit corresponding to the non-calculation part is turned off.
The method for reducing power consumption according to claim 1, characterized in that the method for reducing power consumption further includes:

When the processor is in target mode and a calculation instruction is received, determining the calculation instruction as the target instruction;

The step of obtaining the to-be-calculated part of the data to be processed according to the target instruction includes:

According to the target mode and the calculation instruction, the valid bits of the data to be processed are obtained as the parts to be calculated.
The method of reducing power consumption according to claim 1, characterized in that, according to the target instruction, obtaining the to-be-calculated part of the data to be processed includes:

Load the portion to be calculated.
A processor, characterized in that the processor includes:

A preprocessing module, configured to obtain the parts to be calculated of the data to be processed according to the target instructions, where the data to be processed is divided into the parts to be calculated and the non-calculated parts;

An operation module is used to perform operations on the parts to be calculated and obtain output data.
The processor of claim 8, wherein the target instructions comprise target computation instructions,

The computing module is used for:

According to the target calculation instruction, the part to be calculated is calculated to obtain the output data.
The processor according to claim 9, wherein the data to be processed includes a real number part and an imaginary number part,

The preprocessing module is used for:

According to the target calculation instruction, obtain the real number part or the imaginary number part as the part to be calculated;

The computing module is used for:

According to the target calculation instruction, the real number part or the imaginary number part is operated to obtain the output data.
The processor according to claim 9, wherein the data to be processed includes a plurality of quadrants,

The preprocessing module is used for:

According to the target calculation instruction, obtain at least one quadrant part among a plurality of quadrant parts as the part to be calculated;

The computing module is used for:

According to the target calculation instruction, at least one quadrant part among a plurality of quadrant parts is calculated to obtain the output data.
The processor according to claim 9, characterized in that the computing module is used for:

When the operation is performed on the part to be calculated, the operation unit corresponding to the non-calculation part is turned off.
The processor according to claim 8, characterized in that the processor further includes a processing module, the processing module is used for:

When the processor is in target mode and a calculation instruction is received, determining the calculation instruction as the target instruction;

The preprocessing module is used for:

According to the target mode and the calculation instruction, the valid bits of the data to be processed are obtained as the parts to be calculated.
The processor according to claim 8, characterized in that the preprocessing module is used for:

Load the portion to be calculated.
An electronic device, characterized in that the electronic device includes a housing and a processor, and the processor includes:

A preprocessing module, configured to obtain the parts to be calculated of the data to be processed according to the target instructions, where the data to be processed is divided into the parts to be calculated and the non-calculated parts;

An operation module is used to perform operations on the parts to be calculated and obtain output data.
The electronic device according to claim 15, wherein the target instructions include target calculation instructions,

The computing module is used for:

According to the target calculation instruction, the part to be calculated is calculated to obtain the output data.
The electronic device according to claim 16, wherein the data to be processed includes a real number part and an imaginary number part,

The preprocessing module is used for:

According to the target calculation instruction, obtain the real number part or the imaginary number part as the part to be calculated;

The computing module is used for:

According to the target calculation instruction, the real number part or the imaginary number part is operated to obtain the output data.
The electronic device according to claim 16, characterized in that the data to be processed includes a plurality of quadrants,

The preprocessing module is used for:

According to the target calculation instruction, obtain at least one quadrant part among a plurality of quadrant parts as the part to be calculated;

The computing module is used for:

According to the target calculation instruction, at least one quadrant part among a plurality of quadrant parts is calculated to obtain the output data.
The electronic device according to claim 16, characterized in that the computing module is used for:

When the operation is performed on the part to be calculated, the operation unit corresponding to the non-calculation part is turned off.
The electronic device according to claim 15, characterized in that the processor further includes a processing module, the processing module is used for:

When the processor is in target mode and a calculation instruction is received, determining the calculation instruction as the target instruction;

The preprocessing module is used for:

According to the target mode and the calculation instruction, the valid bits of the data to be processed are obtained as the parts to be calculated.
The electronic device according to claim 15, characterized in that the preprocessing module is used for:

Load the portion to be calculated.
A computer-readable storage medium on which a computer program is stored, characterized in that, when the program is executed by a processor, the steps of the method for reducing power consumption described in any one of claims 1-7 are implemented.