WO2024029230A1

WO2024029230A1 - Switching power supply circuit and switching power supply device

Info

Publication number: WO2024029230A1
Application number: PCT/JP2023/023585
Authority: WO
Inventors: 慎吾橋口; 瞬福島; 洋祐福本
Original assignee: ローム株式会社
Priority date: 2022-08-03
Filing date: 2023-06-26
Publication date: 2024-02-08

Abstract

The present invention obtains an output voltage by rectifying and smoothing a voltage generated by an operation that switches between a high-side transistor and a low-side transistor. The switching operation is performed on the basis of voltage information corresponding to the output voltage and coil current information generated through a current sensing operation. The switching frequency can be set to a first frequency or a second frequency (< the first frequency). For the second frequency, for a portion of the period from when the most recent current sensing operation was performed until the next current sensing operation is performed, coil current information is generated by adding pseudo current information to information about the current detected by the most recent current sensing operation.

Description

Switching power supply circuit and switching power supply device

The present disclosure relates to a switching power supply circuit and a switching power supply device.

One type of switching power supply device includes a high-side transistor and a low-side transistor connected in series with each other, and a rectifying and smoothing circuit having a coil and an output capacitor connected to their connection nodes. An input voltage is applied between the high side transistor and the low side transistor. By rectifying and smoothing the rectangular wave voltage generated by alternately turning on and off the high-side transistor and the low-side transistor in a rectifying and smoothing circuit, an output voltage lower than the input voltage can be obtained. At this time, current mode control may be performed with reference to the coil current.

JP 2019-221099 Publication

In applications where the input voltage is sufficiently high compared to the output voltage, the on-time of the high-side transistor will be considerably short while the on-time of the low-side transistor will be sufficiently long in each cycle of the switching operation. Therefore, by performing a current detection operation that detects the current flowing through the low-side transistor during the on-period of the low-side transistor, the coil current necessary for current mode control is detected.

However, when the input voltage temporarily decreases, the on-time of the low-side transistor becomes shorter as the duty increases in pulse width modulation, and the time required for the current detection operation may not be secured. In such a case, by lowering the switching frequency, it is possible to both secure the time necessary for the current detection operation and increase the maximum duty. However, when the switching frequency is lowered, the interval between current detection operations becomes longer, resulting in unstable control and fluctuations in the output voltage.

An object of the present disclosure is to provide a switching power supply circuit and a switching power supply device that contribute to stabilizing the output voltage.

A switching power supply circuit according to the present disclosure is a switching power supply circuit used in a switching power supply device for generating an output voltage through switching of an input voltage. an output stage circuit having a connected high-side transistor and a low-side transistor; a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; and an on-period of the low-side transistor. a current information generating circuit configured to perform a current sensing operation for detecting a current flowing through the low-side transistor in the rectifying and smoothing circuit, wherein a connection node between the high-side transistor and the low-side transistor includes a coil and an output capacitor. The output voltage is generated by rectifying and smoothing the switching voltage generated at the connection node by the switching operation in the rectifier and smoothing circuit, and the switching control circuit generates a voltage corresponding to the output voltage. information and current information of the coil generated through the current sensing operation, the switching control circuit performs the switching operation in the switching operation at a first frequency or lower than the first frequency. When the switching frequency is set to the second frequency, the current information generating circuit is configured to control the frequency from the most recent current sensing operation to the next current sensing operation. During a part of the period, current information of the coil is generated by adding pseudo current information based on the input voltage and the output voltage to the current information detected by the most recent current sensing operation.
Another switching power supply circuit according to the present disclosure is a switching power supply circuit used in a switching power supply device for generating an output voltage through switching of an input voltage. an output stage circuit having a high-side transistor and a low-side transistor connected in series; a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; A current configured to perform a first current sensing operation for detecting a current flowing through the low-side transistor during an on-period, or a second current sensing operation for detecting a current flowing through the high-side transistor during an on-period of the high-side transistor. an information generation circuit, a connection node between the high side transistor and the low side transistor is connected to a rectification and smoothing circuit including a coil and an output capacitor, and a switching voltage generated at the connection node by the switching operation is connected to the rectification and smoothing circuit. The output voltage is generated by rectification and smoothing in the switching control circuit, and the switching control circuit performs the switching operation based on voltage information corresponding to the output voltage and current information of the coil, and in the switching operation, The switching frequency can be set to a first frequency or a second frequency lower than the first frequency, and when the switching frequency is set to the first frequency, the current information generation circuit performs the first current sensing operation. Current information of the coil is generated, and when the switching frequency is set to the second frequency, the first current sensing operation and the second current sensing operation are used together to generate current information of the coil.

According to the present disclosure, it is possible to provide a switching power supply circuit and a switching power supply device that contribute to stabilizing the output voltage.

FIG. 1 is an overall configuration diagram of a switching power supply device according to a first embodiment of the present disclosure. FIG. 2 is an external perspective view of the power supply IC according to the first embodiment of the present disclosure. FIG. 3 is a configuration diagram of a switching power supply device showing the internal configuration of a power supply IC according to the first embodiment of the present disclosure. FIG. 4 is a relationship diagram between lamp voltage and clock signal according to the first embodiment of the present disclosure. FIG. 5 is a timing chart when the switching frequency is stable at the reference frequency according to the first embodiment of the present disclosure. FIG. 6 is a diagram showing a plurality of time relationships according to the first embodiment of the present disclosure. FIG. 7 is a timing chart of the first virtual operation. FIG. 8 is a timing chart in the vicinity of the switching frequency according to Example EX1_1 belonging to the first embodiment of the present disclosure. FIG. 9 is a diagram showing a coil current waveform in a reference switching operation and a coil current waveform in a frequency division switching operation, according to Example EX1_1 belonging to the first embodiment of the present disclosure. FIG. 10 is a timing chart in the vicinity of the switching frequency according to Example EX1_2 belonging to the first embodiment of the present disclosure. FIG. 11 is a configuration diagram of a switching power supply device showing the internal configuration of a power supply IC according to Example EX1_3 belonging to the first embodiment of the present disclosure. FIG. 12 is a configuration diagram of a switching power supply device showing the internal configuration of a power supply IC according to a second embodiment of the present disclosure. FIG. 13 is a timing chart when the switching frequency is stable at the reference frequency according to the second embodiment of the present disclosure. FIG. 14 is a timing chart of the second virtual operation. FIG. 15 is a timing chart in the vicinity of the switching frequency according to Example EX2_1 belonging to the second embodiment of the present disclosure. FIG. 16 is an internal configuration diagram of a current information generation circuit according to Example EX2_1 belonging to the second embodiment of the present disclosure. FIG. 17 is an explanatory diagram of the operation of the current information generation circuit of FIG. 16. FIG. 18 is a timing chart in the vicinity of the switching frequency according to Example EX2_2 belonging to the second embodiment of the present disclosure. FIG. 19 is an internal configuration diagram of a current information generation circuit according to Example EX2_3 belonging to the second embodiment of the present disclosure.

Examples of embodiments of the present disclosure will be specifically described below with reference to the drawings. In each referenced figure, the same parts are given the same reference numerals, and redundant explanations regarding the same parts will be omitted in principle. In this specification, for the purpose of simplifying the description, symbols or codes that refer to information, signals, physical quantities, functional units, circuits, elements, parts, etc. are shown, and information, signals, or codes corresponding to the symbols or codes are written. Names of physical quantities, functional units, circuits, elements, parts, etc. may be omitted or abbreviated. For example, the contrast voltage referred to by “V _C ” (see FIG. 3), which will be described later, may be written as contrast voltage V _C or may be abbreviated as voltage V _C , but they are all refer to the same thing.

First, some terms used in the description of the embodiments of the present disclosure will be explained. The ground refers to a reference conductive portion having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductive part may be formed using a conductor such as metal. The potential of 0V is sometimes referred to as a ground potential. In embodiments of the present disclosure, voltages shown without particular reference represent potentials as seen from ground.

Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal or voltage of interest, a signal or voltage being at a high level strictly means that the level of the signal or voltage is at a high level, and a signal or voltage being at a low level does not strictly mean that the level of the signal or voltage is at a high level. It means that the signal or voltage level is at low level.

In any signal or voltage of interest, switching from a low level to a high level is called an up edge, and the timing of switching from a low level to a high level is called an up edge timing. You can read up edge as rising edge. Similarly, in any signal or voltage of interest, switching from a high level to a low level is called a down edge, and the timing of switching from a high level to a low level is called a down edge timing. You can read down edge as falling edge.

Regarding any transistor configured as a FET (field effect transistor) including a MOSFET, an on state refers to a state in which the drain and source of the transistor are electrically connected, and an off state refers to a state in which the drain and source of the transistor are electrically connected. Refers to the state where there is no conduction between the two (blocked state). The same applies to transistors that are not classified as FETs. The MOSFET is understood to be an enhancement type MOSFET unless otherwise specified. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Furthermore, unless otherwise specified, the back gate of any MOSFET may be considered to be short-circuited to the source. Any switch can be composed of one or more FETs (field effect transistors), and when a switch is on, conduction occurs between both ends of the switch, while when the switch is off, the switch is electrically conductive. There is no conduction between both ends.

Hereinafter, the on state and off state of any transistor or switch may be simply expressed as on or off. For any transistor or switch, switching from an off state to an on state is expressed as turn-on, and switching from an on state to an off state is expressed as turn-off. Further, regarding any transistor or switch, a period in which the transistor or switch is in an on state is referred to as an on period, and a period in which the transistor or switch is in an off state is referred to as an off period. Regarding any signal having a signal level of high level or low level, the period during which the level of the signal is high level is referred to as a high level period, and the period during which the level of the signal is at low level is referred to as a low level period. The same applies to any voltage that takes a high or low voltage level.

Connections between multiple parts forming a circuit, such as arbitrary circuit elements, wiring, nodes, etc., may be understood to refer to electrical connections, unless otherwise specified.

[First embodiment]
A first embodiment of the present disclosure will be described. FIG. 1 is an overall configuration diagram of a switching power supply device 1 according to a first embodiment of the present disclosure. A switching power supply device 1 in FIG. 1 includes a power supply IC 2 that is a switching power supply circuit (a semiconductor device for a switching power supply), and a plurality of discrete components externally connected to the power supply IC 2. includes a capacitor C1 as an output capacitor, a capacitor C2 as a boot capacitor, resistors R1 and R2 as feedback resistors, and a coil L1. The switching power supply device 1 is configured as a step-down switching power supply device (DC/DC converter) that generates a desired output voltage V _OUT from an input voltage V _IN supplied from the outside. An output voltage V _OUT is generated at the output terminal OUT. That is, the output terminal OUT is an application terminal for the output voltage V _OUT (a terminal to which the output voltage V _OUT is applied). The output voltage V _OUT is supplied to a load LD connected to the output terminal OUT.

The input voltage V _IN and the output voltage V _OUT are positive DC voltages, and the output voltage V _OUT is lower than the input voltage V _IN . For example, when the input voltage V _IN is 12V, the output voltage V _OUT can be stabilized at a desired target voltage V _TG (for example, 5V) below 12V by adjusting the resistance values of the resistors R1 and R2.

FIG. 2 shows an external perspective view of the power supply IC 2. The power supply IC 2 includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a casing (package) that houses the semiconductor chip, and a plurality of external terminals exposed to the outside of the power supply IC 2 from the casing. It is an electronic component equipped with The power supply IC 2 is formed by enclosing a semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply IC 2 and the type of casing of the power supply IC 2 shown in FIG. 2 are merely examples, and they can be designed arbitrarily. The output stage circuit MM, main control block 3, and rectifier D1 shown in FIG. 1 are included in the semiconductor integrated circuit.

In FIG. 1, only the input terminal IN, switch terminal SW, feedback terminal FB, output monitoring terminal OS, boot terminal BOOT, and ground terminal GND are shown as some of the plurality of external terminals provided in the power supply IC 2. (Similarly in FIG. 3, which will be described later, etc.), other external terminals (for example, an enable terminal and a power good terminal) may also be provided in the power supply IC 2.

The external configuration of the power supply IC 2 will be explained. An input voltage V _IN is supplied to the input terminal IN from outside the power supply IC2. A coil L1 is interposed in series between the switch terminal SW and the output terminal OUT. That is, one end of the coil L1 is connected to the switch terminal SW, and the other end of the coil L1 is connected to the output terminal OUT. Further, the output terminal OUT is connected to ground via a capacitor C1. That is, one end of the capacitor C1 is connected to the output terminal OUT, and the other end of the capacitor C1 is connected to ground. Further, the output terminal OUT is connected to one end of a resistor R1, and the other end of the resistor R1 is connected to ground via a resistor R2. A connection node between resistors R1 and R2 is connected to feedback terminal FB. Further, the output monitoring terminal OS is connected to the output terminal OUT. Therefore, the output voltage V _OUT is applied to the output monitoring terminal OS. A ground terminal GND is connected to ground. Capacitor C2 is provided between terminals BOOT and SW. That is, one end of the capacitor C2 is connected to the boot terminal BOOT, and the other end of the capacitor C2 is connected to the switch terminal SW. Note that the current flowing through the coil L1 is referred to as a coil current IL.

The internal configuration of the power supply IC 2 will be explained. The power supply IC2 includes an output stage circuit MM, a main control block 3 for controlling the output stage circuit MM, and a rectifier D1.

Output stage circuit MM includes transistors M1 and M2. Here, it is assumed that the transistors M1 and M2 are each N-channel type MOSFETs (Metal Oxide Semiconductor Field effect transistors). The transistors M1 and M2 are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, the ground), and when they are driven to switch, the input voltage V _IN is switched. A rectangular waveform switching voltage V _SW appears at the switch terminal SW. The transistor M1 is a high-side transistor provided on the high side, and the transistor M2 is a low-side transistor provided on the low side. Specifically, the drain of the transistor M1 is connected to the input terminal IN, which is the terminal to which the input voltage V _IN is applied, and the source of the transistor M1 and the drain of the transistor M2 are commonly connected to the switch terminal SW. The source of transistor M2 is connected to ground terminal GND. Note that a current detection resistor (sense resistor) may be inserted between the source of the transistor M2 and the ground.

Transistor M1 functions as an output transistor, and transistor M2 functions as a synchronous rectifier transistor. Coil L1 and capacitor C1 constitute a rectifying and smoothing circuit that rectifies and smoothes rectangular wave switching voltage V _SW appearing at switch terminal SW to generate output voltage V _OUT . Resistors R1 and R2 constitute a voltage divider circuit that divides the output voltage V _OUT , and a feedback voltage V _FB that is a divided voltage of the output voltage V _OUT is generated at a connection node between the resistors R1 and R2. The connection node between the resistors R1 and R2 is connected to the feedback terminal FB, so that the feedback voltage V _FB is input to the feedback terminal FB.

Gate signals G1 and G2 are supplied to the gates of transistors M1 and M2, respectively. Transistors M1 and M2 are turned on and off according to gate signals G1 and G2. When the gate signal G1 is at a high level, the transistor M1 is turned on, and when the gate signal G1 is at a low level, the transistor M1 is turned off. Similarly, when the gate signal G2 is at a high level, the transistor M2 is turned on, and when the gate signal G2 is at a low level, the transistor M2 is turned off. Basically, transistors M1 and M2 are turned on and off alternately, but both transistors M1 and M2 may be turned off. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a Hi-Z state. In the output high state, transistors M1 and M2 are on and off, respectively. In the output low state, transistors M1 and M2 are in an off state and an on state, respectively. In the Hi-Z state, both transistors M1 and M2 are off. Both transistors M1 and M2 are never turned on.

The main control block 3 is connected to each gate of the transistors M1 and M2, a switch terminal SW, a feedback terminal FB, and an output monitoring terminal OS. The main control block 3 controls the on/off states of the transistors M1 and M2 by controlling the levels of the gate signals G1 and G2 based on the feedback voltage V _FB , thereby providing an output to the output terminal OUT according to the feedback voltage V _FB. Generates voltage V _OUT . Further, as shown in FIG. 1, the main control block 3 may be provided with an output voltage V _OUT . The main control block 3 can perform overvoltage protection etc. based on the output voltage V _OUT , and can also generate pseudo current information (details will be described later) by referring to the output voltage V _OUT .

The power supply IC 2 is provided with an internal power supply circuit (not shown) that generates an internal power supply voltage V _REG based on the input voltage V _IN . Internal power supply voltage V _REG has a predetermined positive DC voltage value. In the example of FIG. 1, the rectifying element D1 is a diode. In this case, in the diode serving as the rectifying element D1, the anode is connected to the application terminal of the internal power supply voltage V _REG , and the cathode is connected to the boot terminal BOOT. The rectifying element D1 may be a switching element that is turned on during the on period of the transistor M2. A bootstrap circuit is formed by the rectifying element D1 and the capacitor C2. The voltage applied to the boot terminal BOOT is referred to as a boot voltage V _BOOT . The main control block 3 can be driven based on the internal power supply voltage V _REG or the boot voltage V _BOOT .

When the output stage circuit MM is in the output low state, the capacitor C2 is charged through the rectifier D1 based on the internal power supply voltage V _REG , so that the boot voltage V _BOOT is lower than the switching voltage V _SW by the voltage across the capacitor C2. It also becomes more expensive. Thereafter, even when the output stage circuit MM is brought into the output high state, the boot voltage V _BOOT is maintained higher than the switching voltage V _SW by the voltage across the capacitor C2.

The gate signal G1 is a signal based on the potential of the switch terminal SW. Specifically, the low-level gate signal G1 has the potential of the switch terminal SW, and the high-level gate signal G1 is higher than the potential of the switch terminal SW by the difference between the voltages V _BOOT and V _SW . The main control block 3 can generate a high level gate signal G1 based on the boot voltage V _BOOT . On the other hand, the gate signal G2 is a signal based on the ground potential. Specifically, the low-level gate signal G2 has a ground potential, and the high-level gate signal G2 is higher than the ground potential by a predetermined voltage (eg, internal power supply voltage V _REG ).

FIG. 3 shows the configuration of a switching power supply device 1 having a power supply IC 2A. Power supply IC2A is an example of power supply IC2. All the matters described above regarding the power supply IC 2 also apply to the power supply IC 2A unless there is a contradiction.

The main control block 3 in the power supply IC 2A includes an error amplifier 11, a phase compensation circuit 12, a differential amplifier 13, a phase compensation circuit 14, a clock generation circuit 15, a lamp voltage generation circuit 16, a comparator 17, and a logic circuit. It includes a circuit 18, a driver 19, and a current information generation circuit 30. The power supply IC 2A performs a switching operation using pulse width modulation. The functions and operations of each part will be explained below.

The error amplifier 11 is a current output type transconductance amplifier. The error amplifier 11 includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The output terminal of the error amplifier 11 is connected to the wiring WR1. The inverting input terminal of the error amplifier 11 is connected to the feedback terminal FB and receives the feedback voltage _VFB . A predetermined reference voltage V _REF is supplied to the non-inverting input terminal of the error amplifier 11 . The reference voltage V _REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generation circuit (not shown) in the power supply IC 2A.

The error amplifier 11 outputs a current signal I1 according to the difference between the feedback voltage V _FB and the reference voltage V _REF from its own output terminal, thereby reducing the error according to the difference between the feedback voltage V _FB and the reference voltage V _REF . A voltage V _ERR is generated on the wiring WR1. Charges generated by the current signal I1 are input to and output from the wiring WR1. Specifically, when the feedback voltage V _FB is lower than the reference voltage V _REF , the error amplifier 11 outputs a current based on the current signal I1 from the error amplifier 11 to the wiring WR1 so that the potential of the wiring WR1 increases, and the feedback voltage increases. When V _FB is higher than the reference voltage V _REF , a current based on the current signal I1 is drawn from the wiring WR1 toward the error amplifier 11 so that the potential of the wiring WR1 is lowered. As the absolute value of the difference between the feedback voltage V _FB and the reference voltage V _REF increases, the magnitude of the current due to the current signal I1 also increases.

Note that when the power supply IC 2A is started, a soft start voltage that gradually increases from 0V to a voltage exceeding the reference voltage V _REF may be generated within the power supply IC 2A. In this case, the error amplifier 11 compares the lower voltage between the reference voltage V _REF and the soft start voltage with the feedback voltage V _FB and generates the current signal I1 based on the comparison result. However, in this embodiment, the state after the soft start voltage becomes higher than the reference voltage V _REF will be considered, and the existence of the soft start voltage will be ignored below.

The phase compensation circuit 12 is provided between the wiring WR1 and the ground, receives the current signal I1, and compensates the phase of the error voltage _VERR . The phase compensation circuit 12 includes a series circuit of a resistor 12a and a capacitor 12b. Specifically, one end of the resistor 12a is connected to the wiring WR1, and the other end of the resistor 12a is connected to one end of the capacitor 12b. The other end of capacitor 12b is connected to ground. By appropriately setting the resistance value of the resistor 12a and the capacitance value of the capacitor 12b, it is possible to compensate the phase of the error voltage V _ERR and prevent oscillation of the output feedback loop.

Like the error amplifier 11, the differential amplifier 13 is also a current output type transconductance amplifier. The differential amplifier 13 includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The output terminal of the differential amplifier 13 is connected to the wiring WR2. A non-inverting input terminal of the differential amplifier 13 is connected to the wiring WR1 and receives the error voltage V _ERR . A voltage V _IL is supplied to the inverting input terminal of the differential amplifier 13 . Although details will be described later, the voltage V _IL is coil current information representing the coil current IL.

The differential amplifier 13 outputs a current signal I2 corresponding to the difference between the error voltage V _ERR and the voltage V _IL from its own output terminal, thereby generating a comparison voltage according to the difference between the error voltage V _ERR and the voltage V _IL . Generate V _C in wiring WR2. Charges generated by the current signal I2 are input to and output from the wiring WR2. Specifically, when the error voltage V _ERR is higher than the voltage V _IL , the differential amplifier 13 outputs a current according to the current signal I2 from the differential amplifier 13 to the wiring WR2 so that the potential of the wiring WR2 increases, and the error is reduced. When the voltage V _ERR is lower than the voltage V _IL , a current based on the current signal I2 is drawn from the wiring WR2 toward the differential amplifier 13 so that the potential of the wiring WR2 is lowered. As the absolute value of the difference between error voltage V _ERR and voltage V _IL increases, the magnitude of the current due to current signal I2 also increases.

The phase compensation circuit 14 is provided between the wiring WR2 and the ground, receives the current signal I2, and compensates the phase of the comparison voltage V _C . The phase compensation circuit 14 includes a series circuit of a resistor 14a and a capacitor 14b. Specifically, one end of the resistor 14a is connected to the wiring WR2, and the other end of the resistor 14a is connected to one end of the capacitor 14b. The other end of capacitor 14b is connected to ground. By appropriately setting the resistance value of the resistor 14a and the capacitance value of the capacitor 14b, it is possible to compensate the phase of the comparison voltage V _C and prevent oscillation of the output feedback loop.

The clock generation circuit 15 generates and outputs a clock signal CLK. The clock signal CLK is a rectangular wave signal having a predetermined reference frequency f _REF and alternately takes low and high signal levels. A clock signal CLK is output from the clock generation circuit 15 to the ramp voltage generation circuit 16 and the logic circuit 18.

The ramp voltage generation circuit 16 generates a ramp voltage V _RAMP whose voltage value (in other words, signal level) changes periodically. The lamp voltage V _RAMP has a voltage waveform of, for example, a triangular wave or a sawtooth wave. The ramp voltage V _RAMP depends on the clock signal CLK.

FIG. 4 shows the relationship between the ramp voltage V _RAMP and the clock signal CLK. A time corresponding to the reciprocal of the reference frequency f _REF is referred to as a reference time t _REF . Every time the reference time t _REF elapses, an up edge occurs in the clock signal CLK. Specifically, a down edge occurs in the clock signal CLK when a time (t _REF - Δt) elapses after an up edge occurs in the clock signal CLK, and then, when a predetermined minute time Δt elapses, the clock signal CLK A new up edge is generated.

The ramp voltage generation circuit 16 sets the value of the ramp voltage V _RAMP to a predetermined lower limit voltage value V _{RAMP_MIN} during the low level period of the clock signal CLK, and adjusts the ramp voltage V _RAMP linearly over time during the high level period of the clock signal CLK. increase monotonically. Therefore, the ramp voltage generation circuit 16 starts a monotonous rise of the ramp voltage V _RAMP from the lower limit voltage value V RAMP_MIN at the rising edge of the clock signal CLK, and starts a monotonous rise of the ramp voltage V _RAMP from the lower limit voltage value V _{RAMP_MIN} at the falling edge of the clock signal CLK. Continue until the occurrence of. Then, the ramp voltage generation circuit 16 returns the ramp voltage V _RAMP to the lower limit voltage value V _{RAMP_MIN} in response to the down edge of the clock signal CLK. Hereinafter, the lower limit voltage value V _{RAMP_MIN} may be referred to as an initial level.

The slope of rise of the ramp voltage V _RAMP during the high level period of the clock signal CLK is set to be larger as the input voltage V _IN is higher (however, it may be set to be constant regardless of the input voltage V _IN ). Note that the minute time Δt may be sufficiently smaller than the reference time t _REF . In the following, unless it is particularly necessary, the minute time Δt is considered to be sufficiently smaller than the reference time t _REF and will be ignored (that is, the minute time Δt will be treated as if it were zero).

Referring again to FIG. A non-inverting input terminal of the comparator 17 is connected to the wiring WR2 and receives the comparison voltage V _C . The lamp voltage V _RAMP from the lamp voltage generation circuit 16 is supplied to the inverting input terminal of the comparator 17 . The comparator 17 compares the comparison voltage V _C with the ramp voltage V _RAMP and outputs a signal S _PWM indicating the comparison result. The signal S _PWM becomes high level during the period when “V _C >V _RAMP ” is established, and becomes low level during the period when “V _C <V _RAMP ” is established. During the period when "V _C =V _RAMP " is established, the signal _SPWM becomes high level or low level. "V _C > V _RAMP " represents that the contrast voltage V _C is higher than the lamp voltage V _RAMP , and "V _C < V _RAMP " represents that the contrast voltage V _C is lower than the ramp voltage V _RAMP . The same applies to other expressions including physical quantities such as voltage.

The signal S _PWM from the comparator 17 is input to the logic circuit 18, and the clock signal CLK from the clock generation circuit 15 is input. Logic circuit 18 controls gate signals G1 and G2 by controlling driver 19 based on signals CLK and _SPWM . The driver 19 supplies gate signals G1 and G2 based on the signals CLK and _SPWM to the transistors M1 and M2 under the control of the logic circuit 18, thereby causing the output stage circuit MM to perform a switching operation. In the switching operation, transistors M1 and M2 are alternately turned on and off based on signals CLK and _SPWM . Since the error amplifier 11 generates the current signal I1 so that the feedback voltage V _FB and the reference voltage V _REF are equal, the output voltage V _OUT is equal to the reference voltage V _REF and the resistors R1 and R2 through execution of the switching operation. It is stabilized at a predetermined target voltage V _TG according to the voltage division ratio.

The logic circuit 18 controls and sets the output stage circuit MM to the output high state by supplying the high level gate signal G1 and the low level gate signal G2 from the driver 19 to the gates of the transistors M1 and M2. The logic circuit 18 controls and sets the output stage circuit MM to an output low state by supplying a low level gate signal G1 and a high level gate signal G2 from the driver 19 to the gates of the transistors M1 and M2.

Therefore, the logic circuit 18 uses the driver 19 to generate an up edge in the gate signal G1 and a down edge in the gate signal G2, thereby switching the state of the output stage circuit MM from the output low state to the output high state. However, in this case, in order to suppress the through current, the output stage circuit MM may be switched from the output low state to the output high state via the Hi-Z state. That is, when switching from the output low state to the output high state, a down edge may be generated in the gate signal G2, and then an up edge may be generated in the gate signal G1.

Similarly, the logic circuit 18 uses the driver 19 to generate a down edge in the gate signal G1 and an up edge in the gate signal G2, thereby switching the state of the output stage circuit MM from the output high state to the output low state. . However, in this case, in order to suppress the through current, the output stage circuit MM may be switched from the output high state to the output low state via the Hi-Z state. That is, when switching from the output high state to the output low state, a down edge may be generated in the gate signal G1 and then an up edge may be generated in the gate signal G2.

In this way, the logic circuit 18 uses the driver 19 to control on and off of the transistors M1 and M2, but the description of the driver 19 may be omitted below.

The coil current IL directed from the switch terminal SW to the output terminal OUT has positive polarity. In the following, it is assumed that a positive coil current IL flows during each of the on-periods of the transistor M1 and the on-period of the transistor M2 (assuming operation in a so-called continuous mode).

The current information generation circuit 30 executes a current sensing operation to detect the current flowing through the transistor M2 during the on period of the transistor M2, and generates a voltage V _IL corresponding to coil current information through the current sensing operation. During the ON period of transistor M2, the current flowing through transistor M2 passes through coil L1. Therefore, the current sensing operation can be said to be an operation of detecting the coil current IL by detecting the current flowing through the transistor M2. The current information generation circuit 30 operates so that as the coil current IL increases, a higher voltage V _IL is generated. Since the voltage V _IL is fed back into the differential amplifier 13, an increase in the error voltage V _ERR causes an increase in the coil current IL, and a decrease in the error voltage V _ERR causes a decrease in the coil current IL.

In the configuration of FIG. 3, the current information generation circuit 30 includes a sense resistor 31, an S/H circuit 32, an amplifier circuit 33, a pseudo current generation circuit 34, and an adder 35. The operation of the current information generation circuit 30 may be controlled by the logic circuit 18. The current information generation circuit 30 can detect the current flowing through the transistor M2 (therefore, the coil current IL) by detecting the voltage drop across the sense resistor 31.

The sense resistor 31 is inserted in series with the transistor M2 and ground. Specifically, a first end of the sense resistor 31 is connected to the source of the transistor M2, and a second end of the sense resistor 31 is connected to the ground terminal GND. During the ON period of the transistor M2, the coil current IL flows through the sense resistor 31 and the transistor M2, so a voltage drop proportional to the coil current IL occurs in the sense resistor 31.

The S/H circuit 32 is a sampling/hold circuit for the voltage drop across the sense resistor 31. That is, the S/H circuit 32 is connected to the first and second ends of the sense resistor 31, and in the current sensing operation, the voltage drop across the sense resistor 31 (that is, the voltage generated between both terminals of the sense resistor 31) is transferred to the logic circuit. The data is sampled and held at the sampling timing set by 18. In the current sensing operation, the amplifier circuit 33 amplifies the voltage currently held in the S/H circuit 32 and outputs the amplified voltage. The output voltage of the amplifier circuit 33 is represented by the symbol "V _ISNS ". A current sensor including a sense resistor 31, an S/H circuit 32, and an amplifier circuit 33 detects the value of the coil current IL. The voltage V _ISNS corresponds to detected current information representing a detected value (detected current value) of the coil current IL. The detected value of the coil current IL corresponds to the voltage V _ISNS divided by the product of the value of the sense resistor 31 and the amplification factor of the amplifier circuit 33.

The pseudo current generation circuit 34 generates and outputs a voltage V _IPS representing pseudo current information. The voltage V _IPS is sometimes taken to be zero. The adder 35 adds the output voltage V _IPS of the pseudo current generation circuit 34 to the output voltage V _ISNS of the amplifier circuit 33, and outputs the sum voltage (VI _SNS +V _IPS ) as the voltage V _IL . The voltage V _IL is coil current information representing the coil current IL.

The current information generation circuit 30 sets "V _IPS = 0" during a period in which the current sense operation can be executed stably, and uses the detected current information (V _ISNS ) obtained by the current sense operation as the coil current information (V _IL ). can be generated. During the period in which the current sensing operation cannot be performed, the current information generation circuit 30 generates coil current information (V IL ) by estimating the coil current IL using the detected current information (V _ISNS ) and the pseudo current information (V _IPS ₎ . can be generated. The significance and generation method of the voltage V _IPS will be explained in detail later.

The frequency at which transistors M1 and M2 are alternately turned on and off is called the switching frequency, and is particularly referred to by the symbol "f _SW ". The switching frequency f _SW is both the switching frequency of the transistor M1 (therefore the frequency of the gate signal G1) and the switching frequency of the transistor M2 (therefore the frequency of the gate signal G2). When the input voltage V _IN continues to be sufficiently higher than the output voltage V _OUT , the switching frequency f _SW becomes stable at the reference frequency f _REF .

FIG. 5 shows a timing chart when the switching frequency f _SW is stable at the reference frequency f _REF (that is, a timing chart when the switching frequency f _SW is maintained at the reference frequency f _REF ). In FIG. 5, the waveforms of the signal S _PWM , the lamp voltage V _RAMP , the clock signal CLK, the gate signal G1, the gate signal G2, the coil current IL, the voltage V _ISNS and the voltage V _IL are shown as solid lines, and the comparison voltage V _C The waveform of is shown by the dashed line. In the example of FIG. 5, an up edge occurs in the clock signal CLK at times T11, T12, T13, and T14, which occur sequentially. When an up edge occurs in the clock signal CLK at time T11 when the output stage circuit MM is in the output low state, the logic circuit 18 causes an up edge to occur in the gate signal G1 and a down edge in the gate signal G2. The output stage circuit MM is switched from the output low state to the output high state.

Triggered by the rising edge of the clock signal CLK at time T11, the ramp voltage _VRAMP starts rising from the initial level ( _{VRAMP_MIN} ) as described above. When the ramp voltage V _RAMP is at the initial level, "V _C > V _RAMP " always holds true, and therefore the signal _SPWM is at a high level. When the ramp voltage V _RAMP reaches the comparison voltage V _C during the rising process of the ramp voltage V _RAMP , a down edge occurs in the signal S _PWM . When the lamp voltage V _RAMP reaches the comparison voltage V _C , it refers to a transition from a state in which “V _C >V _RAMP ” holds to a state in which “V _C <V _RAMP ” holds. The low level signal S _PWM functions as a reset signal. Hereinafter, issuing a reset signal means that the comparator 17 outputs a low-level signal S _PWM , or that a down edge occurs in the signal S _PWM .

When the reset signal is issued, the logic circuit 18 causes the gate signal G1 to generate a down edge and the gate signal G2 to generate an up edge to switch the output stage circuit MM from the output high state to the output low state (however, the reset signal (except where invalidated). Thereafter, when a down edge occurs in the clock signal CLK, the ramp voltage _VRAMP is returned to the initial level ( _{VRAMP_MIN} ), and thereby an up edge occurs in the signal _SPWM . Thereafter, another up edge occurs in the clock signal CLK at time T12. Thereafter, similar operations are repeated.

In the output high state of the output stage circuit MM, a current based on the input voltage V _IN flows from the input terminal IN to the output terminal OUT through the transistor M1 and the coil L1, and the coil current IL gradually increases and flows into the coil L1. Energy is being accumulated. In the output low state of the output stage circuit MM, a current based on the stored energy of the coil L1 flows through the transistor M2 and the coil L1, and the coil current IL gradually decreases.

The logic circuit 18 sets the sampling timing within the on period of the transistor M2 (that is, the period during which the output stage circuit MM is in the output low state). The set sampling timing will be referred to below with the symbol "T _SMPL ". One sampling timing T _SMPL is set for each on-period of the transistor M2, and a current sensing operation is performed at each sampling timing T _SMPL .

The S/H circuit 32 samples and holds the voltage drop across the sense resistor 31 at sampling timing _TSMPL . The sampling timing T _SMPL set between times T11 and T12 is particularly referred to by the symbol "T _SMPL1 ", and the sampling timing T _SMPL set between times T12 and T13 is specifically referred to by the symbol "T _SMPL2 ", The sampling timing T _SMPL set between times T13 and T14 is particularly referred to by the symbol "T _SMPL3 ."

The voltages V _ISNS obtained by amplifying the voltages sampled at the sampling timings T _SMPL1 , T _SMPL2 , and T _SMPL3 in the amplifier circuit 33 are referred to by symbols V _ISNS1 , V _ISNS2 , and V _{ISNS3 ,} respectively. The output voltage V _ISNS of the amplifier circuit 33 is maintained at the voltage V _ISNS1 from sampling timing T _SMPL1 to immediately before sampling timing T _SMPL2 . Similarly, the output voltage V _ISNS of the amplifier circuit 33 is maintained at the voltage V _ISNS2 from sampling timing T _SMPL2 to immediately before sampling timing T _SMPL3 . The same applies thereafter. In a state where the switching frequency f _SW is stable at the reference frequency f _REF , pseudo current information is not generated and the voltage V _IPS is maintained at zero. That is, in a state where the switching frequency f _SW is stable at the reference frequency f _REF , "V _IL =V _ISNS " is always satisfied.

Any timing during the on period of the transistor M2 may be set as the sampling timing _TSMPL . For example, the logic circuit 18 may set the sampling timing T _SMPL to a timing when a predetermined period of time has elapsed from the turn-on timing of the transistor M2. Alternatively, for example, the logic circuit 18 may set the sampling timing T _SMPL to a timing that is a predetermined time before the turn-off timing of the transistor M2. Here, it is assumed that the central timing of the on period of the transistor M2 is set to the sampling timing T _SMPL .

A certain amount of time is required for the current sensing operation, and the minimum time that must be secured to perform the current sensing operation is referred to as the minimum sensing time t _{MIN_SNS} . FIG. 6 shows the relationship between the reference time t _REF and the minimum sense time t _{MIN_SNS} . The minimum sense time t _{MIN_SNS} is shorter than the reference time t _REF . The time difference (t _REF - t _{MIN_SNS} ) corresponds to the maximum on-time t _{MAX_ON} when "f _SW = f _REF ". The maximum on-time t _{MAX_ON} represents the maximum length of the on-period of the transistor M1 in one cycle of the switching operation. For example, if the reference frequency f _REF is 2 MHz (megahertz) and the minimum sense time t _{MIN_SNS} is 200 nanoseconds, the maximum on-time t _{MAX_ON} when "f _SW = f _REF " is 300 nanoseconds, The maximum duty when "f _SW = f _REF " is 60%. The duty refers to the ratio of the on time of the transistor M1 that occupies one cycle of the switching operation, and the maximum value that the duty can take is the maximum duty.

Note that the period between two adjacent up edge timings in the clock signal CLK is referred to as a unit period. The length of the unit period matches the reference time t _REF . Each unit period is a composite period of a preceding period and a subsequent period. In each unit period, the latter period is arranged after the former period. The length of the latter period matches the minimum sense time t _{MIN_SNS} . The length of the first stage period matches the maximum on-time t _{MAX_ON} when "f _SW = f _REF ".

The power supply IC2A is basically suitable for applications where the input voltage V _IN is sufficiently higher than the output voltage V _OUT . In this application, in each cycle of the switching operation, the on-time of transistor M1 is considerably shortened while the on-time of transistor M2 is sufficiently long. Therefore, time for detecting the current flowing through the transistor M2 can be easily and stably secured.

However, in the switching power supply device 1, although "V _IN > V _OUT " temporarily, the difference between the voltages V _IN and V _OUT may become small, or "V _IN < V _OUT " may temporarily occur. could be. For example, assume that in in-vehicle applications, the output voltage of a battery (not shown) mounted on a vehicle such as an automobile is used as the input voltage V _IN . In this case, when starting or restarting the engine using the starter, the output voltage of the battery may temporarily drop significantly. In this case, the difference between the voltages V _IN and V _OUT may become small even though “V _IN >V _OUT ” temporarily, or “V _IN <V _OUT ” may temporarily occur.

During a period when the input voltage V _IN is decreasing, it is advantageous to increase the duty as high as possible in order to maintain the output voltage V _OUT . For example, when the target voltage V _TG is 5V and the input voltage V _IN , which is basically 12V, drops to 7V, if the maximum duty is 60%, "7 x 0.6 = 4.2 ”, the output voltage V _OUT can only be raised to about 4.2V, but if the maximum duty is 80%, the output voltage V _OUT will be maintained around 5V because “7 x 0.8 = 5.6”. Is possible.

Since the minimum sense time t _{MIN_SNS} remains unchanged, lowering the switching frequency f _SW is effective in increasing the maximum duty. For example, when the reference frequency f _REF is 2 MHz (megahertz) and the minimum sense time t _{MIN_SNS} is 200 nanoseconds, by lowering the switching frequency f _SW from 2 MHz to 1 MHz, the maximum duty can be reduced to 60% (=( 500ns-200ns)/500ns) to 80% (=(1000ns-200ns)/1000ns). If the switching frequency f _SW is further lowered, the maximum duty will further increase.

The logic circuit 18 can set the switching frequency f _SW to the reference frequency f _REF or (1/n) times the reference frequency f _REF . Here, n is an arbitrary integer of 2 or more. The switching operation when "f _SW = f _REF " is particularly referred to as the reference switching operation. On the other hand, the switching operation when "f _SW =f _REF /n" is particularly referred to as a frequency division switching operation.

The time from the rising edge timing of the clock signal CLK to the issuance of the reset signal increases as the input voltage V _IN decreases, and the increase in the time means the need to increase the duty. Therefore, when "f _SW = f _REF " and after turning on the transistor M1, if the reset signal is not issued before the maximum on time t _{MAX_ON} when "f _SW = f _REF " has elapsed, The logic circuit 18 transitions the switching operation to be performed from the reference switching operation to the frequency division switching operation, thereby increasing the maximum duty.

However, when the frequency division switching operation is performed, the current sensing operation cannot be performed for a relatively long time, as opposed to being able to obtain a high duty.

FIG. 7 shows a timing chart related to the first virtual operation. It is assumed that, unlike the power supply IC 2A according to this embodiment, the voltage V _IPS is fixed to zero in the first virtual operation. In FIG. 7, waveforms 911 to 920 are input voltage V _IN , output voltage V _OUT , comparison voltage V _C , lamp voltage V _RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I _L , and voltage These are the waveforms of V _ISNS and voltage V _IL . The waveform 921 corresponds to an expanded waveform (the waveform 912 expanded in the voltage direction) of the output voltage V _OUT . Each white circle shown on the waveform 918 of the coil current IL represents a sampling timing T _SMPL . Each white circle shown on the waveform 919 of the voltage V _ISNS represents detected current information (V _ISNS ) obtained by the current sensing operation at each sampling timing T _SMPL . In the first virtual operation, since "V _IPS =0" is always "V _IL =V _ISNS ".

In the example of FIG. 7, the reference switching operation is performed until time T21. However, before time T21, the difference between the input voltage V _IN and the output voltage V _OUT is small, and the duty of the output stage circuit MM approximately matches the maximum duty. In other words, in each switching cycle before time T21, the on-time of transistor M2 substantially matches the minimum sense time t _{MIN_SNS} (provided that it is greater than or equal to the minimum sense time t _{MIN_SNS} ). Now, it is assumed that the input voltage V _IN has decreased slightly after time T21. Further, an up edge occurs in the clock signal CLK at time T21. Time T23 represents the time when reference time t _REF has elapsed from time T21, and therefore, the next up edge occurs in clock signal CLK at time T23. Time T22 represents a time before time T23 by the minimum sense time t _{MIN_SNS} .

As the input voltage V _IN decreases, the reset signal is not issued before time T22 in the switching cycle starting from time T21. Therefore, the logic circuit 18 related to the first virtual operation switches the switching operation to be executed from the reference switching operation to the frequency division switching operation, and keeps the output stage circuit MM in the output high state until a reset signal is issued after time T23. keep.

In the example of FIG. 7, at time T24 after time T23, the state of the output stage circuit MM is switched from the output high state to the output low state in response to the issuance of the reset signal, and the current is sensed during the on period of the transistor M2. An action is taken. Time T25 is the time when the next up edge occurs in clock signal CLK after time T23.

In the first virtual operation in FIG. 7, no current sensing operation is performed between times T21 and T24. Therefore, the detected current information (V _ISNS ) obtained in the current sensing operation immediately before time T21 is continuously used as coil current information (V _IL ) until the current sensing operation after time T24 is performed. Then, feedback control is performed in a state where the increase in the coil current IL between times T21 and T24 is not reflected in the coil current information (V _IL ). Therefore, the comparison voltage V _C remains constant until the current sensing operation after time T24 is performed, and as a result, the duty becomes excessively large in the switching operation starting from time T21. Due to an excessive increase in duty, the coil current IL increases more than necessary, causing an overshoot in the output voltage V _OUT . Even after that, undesirable fluctuations occur in the coil current IL for a while, and the output voltage V _OUT becomes unstable.

Examples EX1_1 to EX1_4 will be described below as a plurality of examples related to the switching power supply device 1 of the first embodiment. Any two or more of the embodiments EX1_1 to EX1_4 can also be combined with each other.

<<Example EX1_1>>
Example EX1_1 will be explained. FIG. 8 shows a timing chart according to the embodiment EX1_1. It is assumed that as time passes, times T30 to T36, T41 to T46, T51 to T56, and T61 sequentially occur in this order. In FIG. 8, waveforms 611 to 621 are input voltage V _IN , output voltage V _OUT , comparison voltage V _C , lamp voltage V _RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I _L , and voltage These are the waveforms of V _ISNS , voltage V _IPS and voltage V _IL . Waveform 622 corresponds to an expanded waveform (waveform 612 expanded in the voltage direction) of output voltage V _OUT . A broken line waveform 921 shown in FIG. 8 corresponds to the waveform 921 shown in FIG. 7 (the waveform of the output voltage V _OUT in the first virtual operation). Each white circle shown on the waveform 618 of the coil current IL represents a sampling timing T _SMPL , and the current flowing through the transistor M2 is sampled and detected at each sampling timing T _SMPL . Each white circle shown on the waveform 619 of the voltage V _ISNS represents detected current information (V _ISNS ) obtained by the current sensing operation at each sampling timing T _SMPL .

In the example of FIG. 8, the reference switching operation is performed until time T31, and therefore "f _SW =f _REF ". When "f _SW =f _REF ", the pseudo current generation circuit 34 maintains the voltage V _IPS at zero, so "V _IL =V _ISNS ". The current information generation circuit 30 performs a current sensing operation in each switching cycle before time T31.

In the example of FIG. 8, the switching operation to be executed switches from the reference switching operation to the frequency division switching operation of "n=2" at time T31. During part of the period during which the frequency division switching operation is performed, the pseudo current generation circuit 34 generates and outputs a voltage V _IPS greater than zero. Each open triangle shown on the voltage V _IPS waveform 620 represents a voltage V _IPS greater than zero. Each white triangle shown on the waveform 621 of voltage V _IL represents the sum of voltage I _SNS and voltage V _IPS greater than zero. Each white triangle on the waveform 618 of the coil current IL represents a value (estimated value) of the coil current IL indicated by the voltage V _IL .

Before time T31, the difference between the input voltage V _IN and the output voltage V _OUT is small, and the duty of the output stage circuit MM approximately matches the maximum duty. In other words, in each switching cycle before time T31, the on time of transistor M2 substantially matches the minimum sense time t _{MIN_SNS} (provided that it is greater than or equal to the minimum sense time t _{MIN_SNS} ). Time T30 is the sampling timing T _SMPL of the current sensing operation performed immediately before time T31.

Now, it is assumed that the input voltage V _IN has decreased slightly after time T31. Further, at time T31, an up edge occurs in the clock signal CLK, and the state of the output stage circuit MM is switched from the output low state to the output high state. Time T34 represents the time when reference time t _REF has elapsed from time T31, and therefore, the next up edge occurs in clock signal CLK at time T34. Time T32 represents the time before time T34 by the minimum sense time t _{MIN_SNS} .

As the input voltage V _IN decreases, a reset signal is not issued before time T32 in the switching cycle starting from time T31 (that is, no reset signal is issued during the pre-stage period: see FIG. 6). On the condition that the reset signal is not issued before time T32, the logic circuit 18 switches the switching operation to be executed from the reference switching operation to the frequency division switching operation. When the switching is performed, the logic circuit 18 invalidates the reset signal issued between times T32 and T34, and the logic circuit 18 disables the reset signal issued between times T32 and T34, and the logic circuit 18 disables the reset signal issued between times T32 and T34, regardless of the level relationship between the voltages V _C and V _RAMP between times T32 and T34. The output stage circuit MM is kept in the output high state during the period.

An up edge occurs in the clock signal CLK at time T34, but at this time as well, the logic circuit 18 maintains the output stage circuit MM in the output high state. Time T41 represents the time when reference time t _REF has elapsed from time T34. In the example of FIG. 8, after time T34, the reset signal is issued when the lamp voltage V _RAMP reaches the comparison voltage V _C at time T35. Time T35 is a time before time T41, and the time difference between time T35 and T41 is greater than the minimum sense time t _{MIN_SNS} . Therefore, at time T35, the logic circuit 18 switches the output stage circuit MM from the output high state to the output low state based on the issued reset signal. The logic circuit 18 sets the sampling timing T _SMPL to the time T36, which is the time between the times T35 and T41, and the current information generation circuit 30 performs a current sensing operation at the time T36 according to the setting result.

At time T41, an up edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. Time T44 represents the time when reference time t _REF has elapsed from time T41, and therefore, the next up edge occurs in clock signal CLK at time T44. Time T42 represents a time before time T44 by the minimum sense time t _{MIN_SNS} .

The decreased state of the input voltage V _IN that occurred at time T31 is maintained after time T41. As a result, in the switching cycle starting from time T41, no reset signal is issued before time T42 (that is, no reset signal is issued during the previous period: see FIG. 6). On the condition that the reset signal is not issued before time T42, the logic circuit 18 maintains the switching operation to be performed as the frequency division switching operation. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T42 and T44, and the logic circuit 18 disables the reset signal issued between times T42 and T44, regardless of the level relationship between the voltages V _C and V _RAMP between times T42 and T44. The output stage circuit MM is kept in the output high state between T42 and T44.

An up edge occurs in the clock signal CLK at time T44, but at this time as well, the logic circuit 18 maintains the output stage circuit MM in the output high state. Time T51 represents the time when reference time t _REF has elapsed from time T44. In the example of FIG. 8, after time T44, the reset signal is issued when the lamp voltage V _RAMP reaches the comparison voltage V _C at time T45. Time T45 is a time before time T51, and the time difference between time T45 and T51 is greater than the minimum sense time t _{MIN_SNS} . Therefore, at time T45, the logic circuit 18 switches the output stage circuit MM from the output high state to the output low state based on the issued reset signal. The logic circuit 18 sets time T46, which is the time between time T45 and T51, as the sampling timing T _SMPL , and according to the setting result, the current information generation circuit 30 performs a current sensing operation at time T46.

At time T51, an up edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. Time T54 represents the time when reference time t _REF has elapsed from time T51, and therefore, the next up edge occurs in clock signal CLK at time T54. Time T52 represents a time before time T54 by the minimum sense time t _{MIN_SNS} .

The decreased state of the input voltage V _IN that occurred at time T31 is maintained after time T51. As a result, in the switching cycle starting from time T51, no reset signal is issued before time T52 (that is, no reset signal is issued during the previous period: see FIG. 6). On the condition that the reset signal is not issued before time T52, the logic circuit 18 maintains the switching operation to be performed as the frequency division switching operation. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T52 and T54, and the logic circuit 18 disables the reset signal issued between times T52 and T54, regardless of the level relationship between the voltages V _C and V _RAMP between times T52 and T54. The output stage circuit MM is kept in the output high state between T52 and T54.

An up edge occurs in the clock signal CLK at time T54, but at this time as well, the logic circuit 18 maintains the output stage circuit MM in the output high state. Time T61 represents the time when reference time t _REF has elapsed from time T54. In the example of FIG. 8, after time T54, the reset signal is issued when the lamp voltage V _RAMP reaches the comparison voltage V _C at time T55. Time T55 is a time before time T61, and the time difference between time T55 and T61 is greater than the minimum sense time t _{MIN_SNS} . Therefore, at time T55, the logic circuit 18 switches the output stage circuit MM from the output high state to the output low state based on the issued reset signal. The logic circuit 18 sets time T56, which is the time between time T55 and T61, as the sampling timing T _SMPL , and according to the setting result, the current information generation circuit 30 performs a current sensing operation at time T56.

As long as the input voltage V _IN continues to decrease, the same "n=2" frequency division switching operation continues.

The sensed current information (ie, voltage V _ISNS ) is updated each time a current sensing operation is performed. That is, the detected current information (ie, the voltage _VISNS ) obtained by the current sensing operation at time T30 is continuously output from the amplifier circuit 33 between times T30 and T36. Thereafter, the detected current information (ie, the voltage _VISNS ) obtained by the current sensing operation at time T36 is continuously outputted from the amplifier circuit 33 between times T36 and T46. Further thereafter, the detected current information (ie, the voltage V _ISNS ) obtained by the current sensing operation at time T46 is continuously outputted from the amplifier circuit 33 between times T46 and T56. The same applies thereafter.

The voltage V _IPS representing the pseudo current information is zero before time T33, and therefore “V _IL =V _ISNS ” before time T33. The voltage V _IPS has a positive voltage value V _A1 between times T33 and T36. The voltage V _IPS has a positive voltage value V _A2 between times T43 and T46 and between times T53 and T56. The voltage value V _A1 is greater than the voltage value V _A2 .

Time T33 belongs to the latter period of the unit period starting from time T31 (see FIG. 6). Time T43 belongs to the latter period of the unit period starting from time T41. Time T53 belongs to the latter period of the unit period starting from time T51.

In each unit period, the logic circuit 18 monitors whether or not a reset signal has been issued during the previous stage period, and provides the monitoring result to the pseudo current generation circuit 34. The pseudo current generation circuit 34 determines the value of the voltage V _IPS based on the above monitoring results. The voltage V _IPS is in principle zero. In a specific unit period, if a reset signal is not issued during the previous period, the pseudo current generation circuit 34 generates a current that is greater than zero from the timing during the latter period within the specific unit period until the next current sensing operation is performed. It outputs the voltage V _IPS and returns the voltage V _IPS to zero when a current sensing operation is performed. A specific unit period refers to a unit period in which the transistor M1 is switched from off to on at the start of the unit period. Therefore, a unit period starting from time T31, T41, or T51 corresponds to a specific unit period, but a unit period starting from time T34, T44, or T54 does not correspond to a specific unit period.

In the example of FIG. 8, the reset signal is not issued during the first stage period within the unit period starting from time T31. Therefore, the voltage V _IPS is made to have the voltage value V _A1 from the timing (T33) during the latter period in the unit period starting from time T31 to the timing (T36) when the current sensing operation is performed next time. The voltage V _IPS is returned to zero after time T36, and the zero voltage V _IPS continues until just before time T43.
Similarly, no reset signal is issued during the first stage period within the unit period starting from time T41. Therefore, the voltage V _IPS is made to have the voltage value V _A2 from the timing (T43) during the latter period in the unit period starting from time T41 until the timing (T46) when the current sensing operation is performed next time. The voltage V _IPS is returned to zero after time T46, and the zero voltage V _IPS continues until just before time T53.
Similarly, no reset signal is issued during the first stage period within the unit period starting from time T51. Therefore, the voltage V _IPS is made to have the voltage value V _A2 from the timing (T53) during the latter period in the unit period starting from time T51 to the timing (T56) when the current sensing operation is performed next time. The voltage V _IPS is returned to zero after time T56.

The timing of switching from "V _IPS = 0" to "V _IPS >0" is arbitrary as long as it is during the corresponding subsequent period, and may be, for example, the central timing during the corresponding subsequent period. At each time, the sum of the voltage V _ISNS and the voltage V _IPS becomes the voltage V _IL .

The positive voltage V _IPS corresponds to the increase in the coil current IL that occurs during the period when the current sensing operation is not performed, converted into voltage, and the estimated increase in the coil current IL is the pseudo current. It is superimposed on the detected coil current IL (detected current information). The method of setting the pseudo current will be explained.

The slope ΔIL of the coil current IL in the output high state of the output stage circuit MM is expressed by the following equation (1). L1 in equation (1) represents the inductance (value of inductance) of the coil L1 (the same applies to other equations described later). If the slope ΔIL of the coil current IL is known, the above-mentioned increase in the coil current IL can be found, and therefore the pseudo current to be superimposed can be found.
ΔIL=(V _IN - V _OUT )/L1...(1)

It is assumed that in the switching power supply device 1, the inductance (inductance value) of the coil L1 is set to a predetermined value, and that the inductance (inductance value) of the coil L1 in the power supply IC 2A is known. Further, the power supply IC 2A can recognize the input voltage V _IN by detecting the voltage at the input terminal IN. In addition, the power supply IC 2A can recognize the output voltage V _OUT by detecting the voltage at the output monitoring terminal OS. Alternatively, in the switching power supply device 1, the target of the output voltage V _OUT (target voltage V _TG ) may be fixed to a constant value. In this case, the constant value is recognized in advance by the power supply IC 2A. At this time, the output monitoring terminal OS may be omitted. In any case, the power supply IC 2A (for example, the current information generation circuit 30) can determine the slope ΔIL according to equation (1) based on the input voltage V _IN , the output voltage V _OUT , and the inductance of the coil L1.

The pseudo current to be superimposed is derived by multiplying the slope ΔIL by the necessary time information. Specifically, the pseudo current generation circuit 34 derives and determines the voltage values V _A1 and V _A2 according to the following equations (2) and (3).
V _A1 =ΔIL・t _REF・k _A1
=((V _IN -V _OUT )/L1)・t _REF・k _A1 ...(2)
V _A2 =ΔIL・t _REF・k _A2
= ((V _IN - V _OUT )/L1)・t _REF・k _A2 ...(3)

“ΔIL·t _REF ” represents the amount of increase in the coil current IL that occurs when the output stage circuit MM is maintained in the output high state for the reference time t _REF . The conversion coefficients k _A1 and k _A2 are coefficients for converting the amount of current into the amount of voltage. The conversion coefficients k _A1 and k _A2 are set in the pseudo current generation circuit 34 or the logic circuit 18 . Here, "k _A1 >k _A2 >0" holds true. For example, the conversion coefficient k _A1 may have a value obtained by multiplying the conversion coefficient k _A2 by a predetermined value larger than 1.

The coil current IL does not increase throughout the period between times T30 and T33 in FIG. 8 . For this reason, for example, the conversion coefficient k _A1 may be set according to the time difference between times T30 and T31 and the time difference between times T31 and T33, and thereby a pseudo current close to the ideal may be superimposed. Similarly, for example, the conversion coefficient k _A2 may be set according to the time difference between times T36 and T41 and the time difference between times T41 and T43, thereby superimposing a pseudo current close to the ideal.

Superimposition of the pseudo current (actually superimposition of the positive voltage V _IPS ) corresponds to reflecting the current value of the coil current IL on the contrast voltage V _C , resulting in a decrease in the contrast voltage V _C as shown in FIG. . Therefore, as can be understood from the comparison between FIG. 7 and FIG. 8, excessive increase in duty in the frequency division switching operation is suppressed. As a result, in Example EX1_1, when the switching operation is switched from the reference switching operation to the frequency division switching operation, fluctuations in the output voltage V _OUT can be suppressed to a low level (waveform 622 according to Example EX1_1 and waveform 921 according to the reference operation). ), that is, the output voltage V _OUT can be well stabilized.

The reason for “V _A1 >V _A2 ” will be explained with reference to FIG. 9. Before time T31, the average value I _AVE1 between the peak value I _PK1 and the bottom value I _BTM1 of the coil current IL is sampled under "f _SW = f _REF ", and feedback control is performed based on the average value I _AVE1 . . Thereafter, when it changes to "f _SW = f _REF /2", the ripple in the coil current IL becomes twice as much as when "f _SW = f _REF ". Under "f _SW =f _REF /2", the average value I _AVE2 between the peak value I _PK2 and the bottom value I _BTM2 of the coil current IL is sampled, and feedback control is performed based on the average value I _AVE2 . The right side of FIG. 9 shows the waveform of the coil current IL in a stable state after a sufficient period of time has passed since the change to "f _SW = f _REF /2". If there is no difference in operating conditions other than the switching frequency f _SW between “f _SW = f _REF ” and “f _SW = f _REF /2”, the average value I _AVE1 and the average value I _AVE2 are equal, and therefore “I _PK1 <I _PK2 ” and “I _BTM1 > I _BTM2 ” are established.

Since feedback control was performed based on the average value I _AVE1 of the coil current IL at “f _SW = f _REF ”, feedback control was performed based on the average value I _AVE2 of the coil current IL also at the subsequent “ f _SW = f _REF /2”. It is important to stabilize the output voltage _VOUT . However, immediately after switching from "f _SW = f _REF " to "f _SW = f _REF /2", the coil current IL is not the bottom value I _BTM2 but the bottom value I _BTM1 (in FIG. 8, the coil current IL at time T31 (equivalent to the value of )), the coil current IL becomes higher than ideal. At this time, if a relatively large pseudo current is superimposed (actually, if the voltage V _IPS , which has a relatively large voltage value V _A1 , is superimposed on the voltage I _SNS ), a large drop will occur in the contrast voltage V _C. The coil current IL quickly reaches a stable state.

In this way, the current information generation circuit 30 does not use the current information until a predetermined time (for example, time (t _REF −t _{MIN_SNS} /2)) has elapsed after the transistor M1 is turned on during the period in which the frequency division switching operation is performed. Detected current information ( _VISNS ) by the current sensing operation is generated as coil current information ( _VIL ). The current information generating circuit 30 generates current information detected by the most recent current sensing operation until the next current sensing operation is performed after the predetermined time period has elapsed since the transistor M1 was turned on during the frequency division switching operation. (V _ISNS ) and pseudo current information (V _IPS ) is generated as coil current information (V _IL ).

When switching from “f _SW = f _REF ” to “f _SW = f _REF /n”, the current information generation circuit 30 uses the value (V _A1 ) of the pseudo current information immediately after the switch as the value (V A1 ) of the pseudo current information after that. It is better to set it larger than the value (V _A2 ). More specifically, in the frequency division switching operation based on "f _SW = f _REF /n", the value of the pseudo current information (V _A1 ) in the first period is changed to the value of the pseudo current information (V _A2 ) in the second and subsequent periods. ) is recommended. Thereby, the output voltage V _OUT can be quickly stabilized.

However, "V _A1 = V _A2 " may be used. Although "V _A1 > V _A2 " is suitable for quickly stabilizing the output voltage V _OUT , it is still possible to stabilize the output voltage V _OUT even if "V _A1 = V _A2 ". None.

The logic circuit 18 monitors the time from turning on the transistor M1 until the reset signal is issued each time the transistor M1 is turned on. As can be understood from the above description, the logic circuit 18 performs switching when a reset signal is not issued within a predetermined time period t _D after turning on the transistor M1 while performing a reference switching operation. Switches the operation from reference switching operation to frequency division switching operation. The specified time t _D is the maximum on-time t _{MAX_ON} when "f _SW = f _REF ".

Thereafter, when a reset signal is issued before the specified time t _D has elapsed from the turn-on timing of the transistor M1, the condition for returning to the standard switching operation is satisfied. When the conditions for returning to the standard switching operation are satisfied, the logic circuit 18 returns the switching operation to be performed to the standard switching operation. In the example of FIG. 8, after time T61, the input voltage V _IN increases, so that the switching operation performed can return to the reference switching operation. More specifically, for example, if the input voltage V _IN rises sufficiently at time T61, a reset signal is issued before a predetermined time t _D elapses after transistor M1 is turned on at time T61, and the reset signal is Upon receiving the signal, the logic circuit 18 immediately switches the output stage circuit MM from the output high state to the output low state. Thereafter, if the input voltage V _IN is sufficiently high, a reset signal is always issued during the preceding period in each unit period, so that "f _SW =f _REF " is maintained.

<<Example EX1_2>>
Example EX1_2 will be explained. In the embodiment EX1_1, the frequency division switching operation with "n=2" has been described, but depending on the degree of decrease in the input voltage V _IN , etc., the frequency division switching operation with "n≧3" can also be performed.

For example, the following case CS2 is assumed based on the case shown in FIG. 8 (hereinafter referred to as case CS1). The differences between cases CS1 and CS2 are shown below with reference to FIG. In case CS2, the input voltage V _IN decreases more greatly than in case CS1 at time T31. As a result, in case CS2, the reset signal is not issued in the first period of the unit period 641 starting from time T31, and the reset signal is not issued even in the first period of the unit period 642 starting from time T34. In case CS2, it is assumed that a reset signal is then issued at time T41' which belongs to the first period in the unit period 643 starting from time T41 (whether or not the reset signal is issued is not shown in FIG. 10). The unit periods 641 to 643 are three consecutive unit periods, and time T41' is after time T41 and before time T44.

In case CS2, the logic circuit 18 switches the output stage circuit MM from the output low state to the output high state at time T31, maintains the output stage circuit MM in the output high state until time T41', and then switches the output stage circuit MM to the output high state until time T41'. The output stage circuit MM is returned to the output low state. Thereafter, a current sensing operation is performed at time T43' belonging to the unit period 643, and further at time T44, the output stage circuit MM switches to the output high state in response to the rising edge of the clock signal CLK.

In case CS2, the voltage V _IPS is set to zero until time T33, the value of voltage V _IPS is set to the above voltage value V _A1 between times T33 and T36', and the voltage V IPS is set to zero between times T36' and T43'. The value of _IPS is set to the voltage value V _A3 . Here, the voltage value V _A3 is larger than the voltage value V _A1 . The time T33 is a time belonging to the latter period in the unit period 641, and may be, for example, the center timing (center time) of the latter period in the unit period 641. Similarly, time T36' is a time that belongs to the latter period in the unit period 642, and may be, for example, the center timing (center time) of the latter period in the unit period 642. Here, it is assumed that the difference between times T36' and T43' matches the reference time t _REF .

In case CS2, the switching frequency f _SW switches from the reference frequency f _REF to the frequency (f _REF /3) at time T31, and the coil current IL continues to rise between times T31 and T41'. Therefore, the pseudo current superimposed between times T36' and T43' is made larger than the pseudo current superimposed between times T33 and T36' by the amount of current corresponding to the difference (V _A3 - V _A1 ). The amount of current here is "ΔIL·t _REF ". That is, the difference (V _A3 -V _A1 ) is the amount of current (ΔIL·t _REF ) converted into voltage.

In case CS2, even after time T44, if the reset signal is not issued in each of the preceding periods of the first unit period and the second unit period, and the reset signal is issued in the preceding period of the third unit period, "n =3'' frequency division switching operation continues. Here, the first to third unit periods are three consecutive unit periods, and the third unit period comes after the first unit period passes through the second unit period. The conditions for returning to the standard switching operation are as shown in Example EX1_1.

It can be said that the logic circuit 18 performs the following operations. After turning on the transistor M1, the logic circuit 18 monitors whether a reset signal is issued during the pre-stage period. If a reset signal is issued during the previous stage period in the unit period of interest which is an arbitrary unit period, in response to the issuance of the reset signal, the logic circuit 18 immediately outputs the output stage circuit MM to a high state. Then, the output is switched to a low state, and a current sensing operation is performed during the ON period of the transistor M2 within the unit period of interest. If the reset signal is not issued during the preceding period of the unit period of interest, the logic circuit 18 keeps the output stage circuit MM in the output high state throughout the unit period of interest, regardless of the level relationship between the voltages V _C and V _RAMP . The next unit period is set as a new unit period of interest, and the same operation as described above is performed. Therefore, depending on the degree of decrease in the input voltage V _IN , the on-period of the transistor M1 increases without limit (however, an upper limit may be set).

<<Example EX1_3>>
Example EX1_3 will be explained. FIG. 11 shows the configuration of a switching power supply device 1 having a power supply IC 2B. Power supply IC2B is an example of power supply IC2. A sense resistor 31 is not provided in the current information generation circuit 30 in the power supply IC 2B.

In the power supply IC2B, the on-resistance of the transistor M2 is used instead of the sense resistor 31 to detect the current flowing through the transistor M2 (ie, the coil current IL) during the on-period of the transistor M2. Therefore, the S/H circuit 32 in the power supply IC2B is connected to the drain and source of the transistor M2, and in the current sensing operation, samples and holds the voltage drop occurring between the drain and source of the transistor M2 at the sampling timing T _SMPL . .

Except for the point that the sense resistor 31 is not installed and the above-mentioned matters linked to the fact that the sense resistor 31 is not installed, the power supply IC 2B is the same as the power supply IC 2A in FIG. 3, and the description of Example EX1_1 is the same as the example This also applies to EX1_3. In this application, the "voltage drop across the sense resistor 31" and "value of the sense resistor 31" in Example EX1_1 are replaced with "voltage drop occurring between the drain and source of transistor M2" and "on-on state of transistor M2" in Example EX1_3. It can be read as "resistance value".

<<Example EX1_4>>
Example EX1_4 will be explained.

The main control block 3 includes a switching control circuit that performs switching operations. The switching control circuit can be considered to be formed by including parts referenced by reference numerals 11 to 19 (see FIG. 3 or FIG. 11). The switching control circuit performs a switching operation based on voltage information corresponding to the output voltage V _OUT and coil current information (V _IL ). The feedback voltage V _FB is an example of voltage information corresponding to the output voltage V _OUT . The voltage information may be the output voltage V _OUT itself. The switching control circuit includes a contrast voltage generation circuit that generates a contrast voltage V _C . The comparison voltage generation circuit can be considered to be formed including the respective parts referenced by numerals 11 to 14 (see FIG. 3 or FIG. 11).

Although an example has been given in which the direction of change in the ramp voltage V _RAMP between the up edge timing and the down edge timing of the clock signal CLK is an increasing direction, the changing direction may also be a decreasing direction. In this case, each circuit in the power supply IC 2 (2A, 2B) is configured such that a reset signal is issued when the state in which "V _C < V _RAMP " is established to the state in which "V _C > _V RAMP" is established. is transformed appropriately.

For any signal or voltage, the relationship between high and low levels may be reversed as described above, without detracting from the spirit of the above.

The types of channels of FETs (field effect transistors) shown in each embodiment are merely examples. Without detracting from the above, the channel type of any FET may be varied between P-channel and N-channel.

Any transistor mentioned above may be any type of transistor as long as no inconvenience occurs. For example, any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, as long as no inconvenience occurs. Any transistor has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

The embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values shown in the above-mentioned explanatory text are merely examples, and it goes without saying that they can be changed to various numerical values.

<<First appendix>>
An additional note will be provided regarding the present disclosure, the specific configuration example of which was shown in the above-described first embodiment.

A switching power supply circuit according to one aspect of the present disclosure is a switching power supply circuit (2, 2A) used in a switching power supply device (1) for generating an output voltage (V _OUT ) through switching of an _input voltage (V IN ). , 2B), an output stage circuit (MM) having a high-side transistor (M1) and a low-side transistor (M2) connected in series between an input terminal (IN) receiving the input voltage and a ground terminal (GND). a switching control circuit (11 to 19) configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; and detecting a current flowing through the low-side transistor during an on period of the low-side transistor. a current information generation circuit (30) configured to perform a current sensing operation, wherein a connection node between the high-side transistor and the low-side transistor includes a coil (L1) and an output capacitor (C1). The switching voltage (V _SW ) generated at the connection node due to the switching operation is rectified and smoothed by the rectification and smoothing circuit to generate the output voltage, and the switching control circuit generates the output voltage. The switching operation is performed based on voltage information (V _FB ) corresponding to the current sensing operation and current information (V _IL ) of the coil generated through the current sensing operation, and the switching control circuit controls the switching frequency in the switching operation. can be set to a first frequency (f _REF ) or a second frequency (f _REF /n) lower than the first frequency, and in the current information generation circuit, the switching frequency is set to the second frequency. When, during a part of the period from performing the most recent current sensing operation to performing the next current sensing operation, the input voltage and the current information ( _VISNS ) detected by the most recent current sensing operation are This configuration (hereinafter referred to as configuration P1) generates current information of the coil by adding pseudo current information (V _IP ) based on the output voltage.

As a result, when the switching frequency is set to a relatively low second frequency, the execution interval of the current sensing operation becomes longer, but by generating coil current information through the addition of pseudo current information, the actual coil current This makes it possible to perform feedback control that is generally in accordance with the above. As a result, the output voltage is stabilized.

In the switching power supply circuit according to the configuration P1, the current information generation circuit has a configuration (hereinafter referred to as configuration P2) that generates the pseudo current information based on the input voltage, the output voltage, and the inductance of the coil. ) may also be used.

As a result, it is possible to generate pseudo current information that closely simulates the fluctuations in the coil current during a period in which the current sensing operation is not performed, so it is possible to perform control that closely matches the actual coil current. As a result, the output voltage is stabilized.

In the switching power supply circuit according to the configuration P2, the current information generation circuit is configured to calculate the input voltage, the output voltage, the inductance of the coil, and the time (t _REF ) corresponding to the reciprocal of the first frequency. It may be a configuration (hereinafter referred to as configuration P3) that generates the pseudo current information based on the current information.

Regarding the switching power supply circuit according to any one of the configurations P1 to P3, the current information generation circuit is arranged such that a predetermined period of time elapses after the high-side transistor is turned on during a period in which the switching frequency is set to the second frequency. Until the predetermined time has elapsed, the detected current information from the most recent current sensing operation is generated as current information of the coil, and after the predetermined time has elapsed since the high-side transistor was turned on, the next current sensing operation is performed. A configuration (hereinafter referred to as configuration P4) may be adopted in which the sum of the detected current information from the most recent current sensing operation and the pseudo current information is generated as current information of the coil until an operation is performed.

In the switching power supply circuit according to any one of the configurations P1 to P4, the current information generation circuit is configured to generate a value of the pseudo current information immediately after the switching frequency is switched from the first frequency to the second frequency. (V _A1 ) may be set larger than the subsequent value (V _A2 ) of the pseudo current information (hereinafter referred to as configuration P5).

Thereby, the output voltage can be quickly stabilized after the switching frequency is switched from the first frequency to the second frequency.

In the switching power supply circuit according to any one of the configurations P1 to P5, when the switching frequency is set to the first frequency, the current information generation circuit includes each A configuration (hereinafter referred to as configuration P6) may be adopted in which the current sensing operation is executed during the period, and the detected current information by the current sensing operation is generated as current information of the coil.

In the switching power supply circuit according to the configuration P6, the switching control circuit is configured to generate a contrast voltage (V _C ) based on voltage information corresponding to the output voltage and current information of the coil. circuits (11 to 14), and a lamp voltage generation circuit (16) configured to generate a lamp voltage that monotonically changes from an initial level in a predetermined direction at a period of the reciprocal of the first frequency, In the switching operation, after turning on the high-side transistor, a reset signal (down edge of S _PWM) is generated in response to a change in the level relationship between the comparison voltage and the lamp voltage from a first relationship to a second relationship. is issued, turns off the high side transistor and turns on the low side transistor based on the issuance of the reset signal, and turns on the high side transistor while the switching frequency is set to the first frequency; A configuration (hereinafter referred to as configuration P7) that switches the switching frequency from the first frequency to the second frequency when the reset signal is not issued before a specified time (t _{MAX_ON} ) shorter than the reciprocal of the first frequency has elapsed. ).

As a result, for example, when the input voltage temporarily decreases, it is possible to increase the maximum duty of the output stage circuit, thereby making it easier to maintain the output voltage at a desired value.

In the switching power supply circuit according to the configuration P7, after the switching control circuit switches the switching frequency from the first frequency to the second frequency, the specified time period elapses from the turn-on timing of the high-side transistor. The switching frequency may be configured to return the switching frequency from the second frequency to the first frequency when the reset signal is issued (hereinafter referred to as configuration P8).

With this, for example, when the input voltage increases after decreasing, the switching frequency can be returned to the first frequency.

A switching power supply device according to one aspect of the present disclosure includes a switching power supply circuit according to any one of the configurations P1 to P8, and a rectifier configured to generate the output voltage by rectifying and smoothing the switching voltage. This is a smoothing circuit and a configuration (hereinafter referred to as configuration P9).

[Second embodiment]
A second embodiment of the present disclosure will be described. The overall configuration diagram and external perspective view of the switching power supply device 1 according to the second embodiment are as shown in FIGS. 1 and 2. In the second embodiment, a power IC 2C shown in FIG. 12 is used as the power IC 2.

FIG. 12 shows the configuration of a switching power supply device 1 having a power supply IC 2C. Power supply IC2C is an example of power supply IC2. All the matters described above regarding the power supply IC 2 also apply to the power supply IC 2C unless there is a contradiction.

The main control block 3 in the power supply IC 2C includes an error amplifier 11, a phase compensation circuit 12, a differential amplifier 13, a phase compensation circuit 14, a clock generation circuit 15, a lamp voltage generation circuit 16, a comparator 17, and logic. It includes a circuit 18, a driver 19, and a current information generation circuit 30C. The power supply IC 2C performs a switching operation using pulse width modulation. A power supply IC 2C is obtained by replacing the current information generation circuit 30 of FIG. 3 with a current information generation circuit 30C based on the power supply IC 2A according to the first embodiment. Except for this substitution, the configuration and operation of the power supply IC 2C are similar to those of the power supply IC 2A. Unless otherwise specified and unless there is a contradiction, the description in the first embodiment may be applied to the second embodiment. The relationship between the ramp voltage V _RAMP and the clock signal CLK shown in FIG. 4 also applies to the second embodiment. When interpreting the description of the second embodiment, the description of the second embodiment takes precedence regarding matters that are inconsistent between the first and second embodiments.

The current information generation circuit 30C performs a low-side current sensing operation to detect the current flowing through the transistor M2 during the on-period of the transistor M2, and generates a voltage V _IL corresponding to coil current information through the low-side current sensing operation. During the ON period of transistor M2, the current flowing through transistor M2 passes through coil L1. Therefore, the low-side current sensing operation can be said to be an operation of detecting the coil current IL by detecting the current flowing through the transistor M2.

Further, the current information generation circuit 30C may perform a high-side current sensing operation to detect the current flowing through the transistor M1 during the on period of the transistor M1. At this time, a voltage V _IL corresponding to coil current information may be generated through a high-side current sensing operation. During the ON period of the transistor M1, the current flowing through the transistor M1 passes through the coil L1. Therefore, the high-side current sensing operation can be said to be an operation of detecting the coil current IL by detecting the current flowing through the transistor M1.

The current information generation circuit 30C operates so that as the coil current IL increases, a higher voltage V _IL is generated. Since the voltage V _IL is fed back into the differential amplifier 13, an increase in the error voltage V _ERR causes an increase in the coil current IL, and a decrease in the error voltage V _ERR causes a decrease in the coil current IL.

In the configuration of FIG. 12, the current information generation circuit 30C includes a sense resistor 31, an S/H circuit 32, and an amplifier circuit 33. The operation of the current information generation circuit 30C may be controlled by the logic circuit 18. The current information generation circuit 30C can detect the current flowing through the transistor M2 (therefore, the coil current IL) by detecting the voltage drop across the sense resistor 31. Note that FIG. 12 only shows the portions of the configuration of the current information generation circuit 30C that are involved in the low-side current sensing operation. Parts involved in the high-side current sensing operation are shown in other figures.

The S/H circuit 32 is a sampling/hold circuit for the voltage drop across the sense resistor 31. That is, the S/H circuit 32 is connected to the first and second ends of the sense resistor 31, and in the low-side current sensing operation, the voltage drop across the sense resistor 31 (that is, the voltage generated between both terminals of the sense resistor 31) is controlled by logic. It is sampled and held at the sampling timing set by the circuit 18. In the low-side current sensing operation, the amplifier circuit 33 amplifies the voltage currently held in the S/H circuit 32 and outputs the amplified voltage. The output voltage of the amplifier circuit 33 is outputted as a voltage V _IL from the current information generation circuit 30C. Voltage V _IL represents a detected value (detected current value) of coil current IL. In the low-side current sensing operation, the detected value of the coil current IL corresponds to the voltage V _IL divided by the product of the value of the sense resistor 31 and the amplification factor of the amplifier circuit 33.

FIG. 13 shows a timing chart when the switching frequency f _SW is stabilized at the reference frequency f _REF (that is, a timing chart when the switching frequency f _SW is maintained at the reference frequency f _REF ). When "f _SW =f _REF ", the current information generation circuit 30C detects the coil current IL and generates the coil current information (V _IL ) using only the low-side current sensing operation. In FIG. 13, the waveforms of the signal _SPWM , lamp voltage V _RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current IL, and voltage V _IL are shown as solid lines, and the waveform of the contrast voltage V _C is shown as a broken line. is shown. In the example of FIG. 13, up edges occur in the clock signal CLK at times T11, T12, T13, and T14, which occur sequentially. When an up edge occurs in the clock signal CLK at time T11 when the output stage circuit MM is in the output low state, the logic circuit 18 causes an up edge to occur in the gate signal G1 and a down edge in the gate signal G2. The output stage circuit MM is switched from the output low state to the output high state.

The logic circuit 18 sets the sampling timing within the on period of the transistor M2 (that is, the period during which the output stage circuit MM is in the output low state). The set sampling timing will be referred to below with the symbol "T _SMPL ". One sampling timing T _SMPL is set for each on-period of the transistor M2, and a low-side current sensing operation is performed at each sampling timing T _SMPL .

In the low-side current sensing operation, the S/H circuit 32 samples and holds the voltage drop across the sense resistor 31 at sampling timing T _SMPL . The sampling timing T _SMPL set between times T11 and T12 is specifically referred to by the symbol "T _SMPL1 ", and the sampling timing T _SMPL set between times T12 and T13 is specifically referred to by the symbol "T _SMPL2 ", The sampling timing T _SMPL set between times T13 and T14 is particularly referred to by the symbol "T _SMPL3 ."

The voltages V _IL obtained by amplifying the voltages sampled at the sampling timings T _SMPL1 , T _SMPL2 , and T _SMPL3 in the amplifier circuit 33 are referred to by symbols V _IL1 , V _IL2 , and V _{IL3 ,} respectively. The output voltage V _IL of the amplifier circuit 33 is maintained at the voltage V _IL1 from sampling timing T _SMPL1 to immediately before sampling timing T _SMPL2 . Similarly, the output voltage V _IL of the amplifier circuit 33 is maintained at the voltage V _IL2 from the sampling timing T _SMPL2 to immediately before the sampling timing T _SMPL3 . The same applies thereafter.

Any timing during the on period of the transistor M2 may be set as the sampling timing T _SMPL . For example, the logic circuit 18 may set the sampling timing T _SMPL to a timing when a predetermined period of time has elapsed from the turn-on timing of the transistor M2. Alternatively, for example, the logic circuit 18 may set the sampling timing T _SMPL to a timing that is a predetermined time before the turn-off timing of the transistor M2. Here, it is assumed that the central timing of the on period of the transistor M2 is set to the sampling timing T _SMPL .

A certain amount of time is required for the low-side current sensing operation. The minimum sensing time t _{MIN_SNS} according to the second embodiment is understood to refer to the minimum time that should be secured in order to perform a low-side current sensing operation. The relationship between the reference time t _REF and the minimum sense time t _{MIN_SNS} is as shown in FIG. 6 . The minimum sense time t _{MIN_SNS} is shorter than the reference time t _REF . The time difference (t _REF - t _{MIN_SNS} ) corresponds to the maximum on-time t _{MAX_ON} when "f _SW = f _REF ". The maximum on-time t _{MAX_ON} represents the maximum length of the on-period of the transistor M1 in one cycle of the switching operation. For example, if the reference frequency f _REF is 2 MHz (megahertz) and the minimum sense time t _{MIN_SNS} is 200 nanoseconds, the maximum on-time t _{MAX_ON} when "f _SW = f _REF " is 300 nanoseconds, The maximum duty when "f _SW = f _REF " is 60%. The duty refers to the ratio of the on time of the transistor M1 that occupies one cycle of the switching operation, and the maximum value that the duty can take is the maximum duty.

Similar to the first embodiment, the period between two adjacent up edge timings in the clock signal CLK is referred to as a unit period. The length of the unit period matches the reference time t _REF . Each unit period is a composite period of a preceding period and a subsequent period. In each unit period, the latter period is arranged after the former period. The length of the latter period matches the minimum sense time t _{MIN_SNS} . The length of the first stage period matches the maximum on-time t _{MAX_ON} when "f _SW = f _REF ".

The power supply IC2C is basically suitable for applications where the input voltage V _IN is sufficiently high compared to the output voltage V _OUT . In this application, in each cycle of the switching operation, the on-time of transistor M1 is considerably shortened while the on-time of transistor M2 is sufficiently long. Therefore, time for detecting the current flowing through the transistor M2 can be easily and stably secured.

The time from the rising edge timing of the clock signal CLK to the issuance of the reset signal increases as the input voltage V _IN decreases, and the increase in time means the need to increase the duty. Therefore, when "f _SW = f _REF " and after turning on the transistor M1, if the reset signal is not issued before the maximum on time t _{MAX_ON} when "f _SW = f _REF " has elapsed, The logic circuit 18 causes the switching operation to be executed to transition from the reference switching operation to the frequency division switching operation, thereby increasing the maximum duty.

However, when the frequency division switching operation is performed, the low-side current sensing operation cannot be performed for a relatively long time, as opposed to being able to obtain a high duty. In the power supply IC 2C according to the present embodiment, when a frequency division switching operation is performed, coil current information (V _IL ) is obtained by performing a high-side current sensing operation in an output high state. Before explaining this in detail, the second virtual operation will be explained.

FIG. 14 shows a timing chart related to the second virtual operation. Unlike the power supply IC 2C according to this embodiment, only the low-side current sensing operation is always executed in the second virtual operation. In FIG. 14, waveforms 1911 to 1919 are input voltage V _IN , output voltage V _OUT , comparison voltage V _C , lamp voltage V _RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I _L and voltage This is the waveform of _VIL . Waveform 1920 corresponds to an expanded waveform (waveform 1912 expanded in the voltage direction) of output voltage V _OUT . Each white circle shown on the waveform 1918 of the coil current IL represents the sampling timing T _SMPL . Each white circle shown on the waveform 1919 of voltage V _IL represents coil current information (V _IL ) obtained by low-side current sensing operation at each sampling timing T _SMPL .

In the example of FIG. 14, the reference switching operation is performed until time T21. However, before time T21, the difference between the input voltage V _IN and the output voltage V _OUT is small, and the duty of the output stage circuit MM approximately matches the maximum duty. In other words, in each switching cycle before time T21, the on-time of transistor M2 substantially matches the minimum sense time t _{MIN_SNS} (provided that it is greater than or equal to the minimum sense time t _{MIN_SNS} ). Now, it is assumed that the input voltage V _IN has decreased slightly after time T21. Further, an up edge occurs in the clock signal CLK at time T21. Time T23 represents the time when reference time t _REF has elapsed from time T21, and therefore, the next up edge occurs in clock signal CLK at time T23. Time T22 represents a time before time T23 by the minimum sense time t _{MIN_SNS} .

As the input voltage V _IN decreases, the reset signal is not issued before time T22 in the switching cycle starting from time T21. Therefore, the logic circuit 18 related to the second virtual operation switches the switching operation to be executed from the reference switching operation to the frequency division switching operation, and keeps the output stage circuit MM in the output high state until a reset signal is issued after time T23. keep.

In the example of FIG. 14, at time T24 after time T23, the state of the output stage circuit MM is switched from the output high state to the output low state in response to the issuance of the reset signal, and the low-side current flows during the on period of the transistor M2. A sense operation is performed. Time T25 is the time when the next up edge occurs in clock signal CLK after time T23.

In the second virtual operation in FIG. 14, the low-side current sensing operation is not performed between times T21 and T24. Therefore, the detected current information obtained in the low-side current sensing operation immediately before time T21 is continuously used as coil current information (V _IL ) until the low-side current sensing operation is performed after time T24. Then, feedback control is performed in a state where the increase in coil current IL between times T21 and T24 is not reflected in the coil current information (V _IL ). Therefore, the contrast voltage V _C remains constant until the low-side current sensing operation after time T24 is performed, and as a result, the duty becomes excessively large in the switching operation starting from time T21. Due to an excessive increase in duty, the coil current IL increases more than necessary, causing an overshoot in the output voltage V _OUT . Even after that, undesirable fluctuations occur in the coil current IL for a while, and the output voltage V _OUT becomes unstable.

Examples EX2_1 to EX2_4 will be described below as a plurality of examples related to the switching power supply device 1 of the second embodiment. Any two or more of the embodiments EX2_1 to EX2_4 can also be combined with each other.

<<Example EX2_1>>
Example EX2_1 will be explained. FIG. 15 shows a timing chart according to the embodiment EX2_1. It is assumed that as time passes, times T30 to T35, T41 to T45, T51 to T55, and T61 sequentially occur in this order. In FIG. 15, waveforms 1611 to 1619 are input voltage V _IN , output voltage V _OUT , comparison voltage V _C , lamp voltage V _RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I _L and voltage This is the waveform of _VIL . Waveform 1620 corresponds to an expanded waveform (waveform 1612 expanded in the voltage direction) of output voltage V _OUT . A broken line waveform 1920 shown in FIG. 15 corresponds to the waveform 1920 shown in FIG. 14 (the waveform of the output voltage V _OUT in the second virtual operation). Each white circle shown on the waveform 1618 of the coil current IL represents a sampling timing T _SMPL , and the current flowing through the transistor M2 is sampled and detected at each sampling timing T _SMPL by a low-side current sensing operation. Period HS_D refers to a period during which a high-side current sensing operation is performed.

In the example of FIG. 15, the reference switching operation is performed until time T31, and therefore "f _SW =f _REF ". In each switching period before time T31, the current information generation circuit 30C performs a low-side current sensing operation.

In the example of FIG. 15, the switching operation to be executed switches from the reference switching operation to the frequency division switching operation of "n=2" at time T31.

Before time T31, the difference between the input voltage V _IN and the output voltage V _OUT is small, and the duty of the output stage circuit MM approximately matches the maximum duty. In other words, in each switching cycle before time T31, the on time of transistor M2 substantially matches the minimum sense time t _{MIN_SNS} (provided that it is greater than or equal to the minimum sense time t _{MIN_SNS} ). Time T30 is the sampling timing T _SMPL of the low-side current sensing operation performed immediately before time T31.

Now, it is assumed that the input voltage V _IN has decreased slightly after time T31. Further, at time T31, an up edge occurs in the clock signal CLK, and the state of the output stage circuit MM is switched from the output low state to the output high state. Time T33 represents the time when reference time t _REF has elapsed from time T31, and therefore, the next up edge occurs in clock signal CLK at time T33. Time T32 represents a time before time T33 by the minimum sense time t _{MIN_SNS} .

As the input voltage V _IN decreases, a reset signal is not issued before time T32 in the switching cycle starting from time T31 (that is, no reset signal is issued during the pre-stage period: see FIG. 6). On the condition that the reset signal is not issued before time T32, the logic circuit 18 switches the switching operation to be executed from the reference switching operation to the frequency division switching operation. When the switching is performed, the logic circuit 18 invalidates the reset signal issued between times T32 and T33, and the logic circuit 18 disables the _reset signal issued between times T32 and T33, and _{the logic circuit} 18 disables the reset signal issued between times T32 and T33. The output stage circuit MM is kept in the output high state during the period.

An up edge occurs in the clock signal CLK at time T33, but at this time as well, the logic circuit 18 maintains the output stage circuit MM in the output high state. Time T41 represents the time when reference time t _REF has elapsed from time T33. In the example of FIG. 15, after time T33, the reset signal is issued when the lamp voltage V _RAMP reaches the comparison voltage V _C at time T34. Time T34 is a time before time T41, and the time difference between time T34 and T41 is greater than the minimum sense time t _{MIN_SNS} . Therefore, at time T34, the logic circuit 18 switches the output stage circuit MM from the output high state to the output low state based on the issued reset signal. The logic circuit 18 sets time T35, which is the time between time T34 and T41, as the sampling timing T _SMPL , and according to the setting result, the current information generation circuit 30C performs a low-side current sensing operation at time T35.

At time T41, an up edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. Time T43 represents the time when reference time t _REF has elapsed from time T41, and therefore, the next up edge occurs in clock signal CLK at time T43. Time T42 represents a time before time T43 by the minimum sense time t _{MIN_SNS} .

The decreased state of the input voltage V _IN that occurred at time T31 is maintained after time T41. As a result, in the switching cycle starting from time T41, no reset signal is issued before time T42 (that is, no reset signal is issued during the previous period: see FIG. 6). On the condition that the reset signal is not issued before time T42, the logic circuit 18 maintains the switching operation to be performed as the frequency division switching operation. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T42 and T43, and the logic circuit 18 disables the reset signal issued between times T42 and T43, regardless of the level relationship between the voltages V _C and V _RAMP between times T42 and T43. The output stage circuit MM is kept in the output high state between T42 and T43.

An up edge occurs in the clock signal CLK at time T43, but at this time as well, the logic circuit 18 maintains the output stage circuit MM in the output high state. Time T51 represents the time when reference time t _REF has elapsed from time T43. In the example of FIG. 15, after time T43, the reset signal is issued when the lamp voltage V _RAMP reaches the comparison voltage V _C at time T44. Time T44 is a time before time T51, and the time difference between time T44 and T51 is greater than the minimum sense time t _{MIN_SNS} . Therefore, at time T44, the logic circuit 18 switches the output stage circuit MM from the output high state to the output low state based on the issued reset signal. The logic circuit 18 sets time T45, which is the time between time T44 and T51, as the sampling timing T _SMPL , and according to the setting result, the current information generation circuit 30C performs a low-side current sensing operation at time T45.

At time T51, an up edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. Time T53 represents the time when reference time t _REF has elapsed from time T51, and therefore, the next up edge occurs in clock signal CLK at time T53. Time T52 represents a time before time T53 by the minimum sense time t _{MIN_SNS} .

The decreased state of the input voltage V _IN that occurred at time T31 is maintained after time T51. As a result, in the switching cycle starting from time T51, no reset signal is issued before time T52 (that is, no reset signal is issued during the previous period: see FIG. 6). On the condition that the reset signal is not issued before time T52, the logic circuit 18 maintains the switching operation to be performed as the frequency division switching operation. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T52 and T53, and the logic circuit 18 disables the reset signal issued between times T52 and T53, regardless of the level relationship between the voltages V _C and V _RAMP between times T52 and T53. The output stage circuit MM is kept in the output high state between T52 and T53.

An up edge occurs in the clock signal CLK at time T53, but at this time as well, the logic circuit 18 maintains the output stage circuit MM in the output high state. Time T61 represents the time when reference time t _REF has elapsed from time T53. In the example of FIG. 15, after time T53, the reset signal is issued when the lamp voltage V _RAMP reaches the comparison voltage V _C at time T54. Time T54 is a time before time T61, and the time difference between time T54 and T61 is greater than the minimum sense time t _{MIN_SNS} . Therefore, at time T54, the logic circuit 18 switches the output stage circuit MM from the output high state to the output low state based on the issued reset signal. The logic circuit 18 sets time T55, which is the time between time T54 and T61, as the sampling timing T _SMPL , and according to the setting result, the current information generation circuit 30C performs a low-side current sensing operation at time T55.

In the operation example shown in FIG. 15, a frequency division switching operation with "f _SW =f _REF /2" is performed from time T31. When the frequency division switching operation is performed, the current information generation circuit 30C performs a high-side current sensing operation during a part of the on period of the transistor M1. In the operation example of FIG. 15, the logic circuit 18 converts the period between times T33 and T34, the period between times T43 and T44, and the period between times T53 and T54 into a high-side current sense operation execution period HS_D. A high-side current sensing operation is performed in each period HS_D.

Hereinafter, a current value detected by the low-side current sensing operation will be referred to as a low-side detected current value, and a current value detected by the high-side current sensing operation will be referred to as a high-side detected current value. The low-side detection current value is a detection value of the current flowing through the transistor M2 during the on period of the transistor M2. The high-side detected current value is a detected value of the current flowing through the transistor M1 during the on period of the transistor M1.

In each period HS_D, the current information generation circuit 30C continuously detects (continuously detects) the current flowing through the transistor M1, and generates and outputs a voltage V _IL representing the high-side detected current value. In each period HS_D, the value of voltage V _IL is updated in real time according to the current flowing through transistor M1. From the end time of a certain period HS_D to the next sampling timing T _SMPL , the voltage V _IL has a value that corresponds to the current flowing through the transistor M2 (here, a value that corresponds to the voltage drop across the sense resistor 31). When the low-side current sensing operation is performed at the sampling timing T _SMPL , the value of the voltage V _IL is updated to a value representing the low-side detected current value. Thereafter, the value of voltage V _IL is maintained until the next high-side current sensing operation or low-side current sensing operation is performed.

Therefore, in the operation example of FIG. 15, from time T30 to just before time T33, the voltage V _IL represents the low-side detected current value of the low-side current sense operation with time T30 as the sampling timing T _SMPL (that is, the low-side detected current value at time T30). (maintained at the detected current value). The voltage V _IL between times T33 and T34 represents the high-side detected current value between times T33 and T34 in real time. From time T34 to time T35, voltage V _IL has a value that corresponds to the current flowing through transistor M2 (here, a value that corresponds to the voltage drop across sense resistor 31). However, the value of the voltage V _IL may be maintained unchanged at the value of the voltage V _IL at time T34 from time T34 to time T35. When a low-side current sensing operation is performed with sampling timing T _SMPL at time T35, the voltage V _IL is maintained at the low-side current sensing operation with sampling timing T _SMPL at time T35 from time T35 until the next low-side or high-side current sensing operation is performed. It represents the low-side detected current value of the current sensing operation (that is, it is maintained at the low-side detected current value at time T35).

Therefore, in the operation example of FIG. 15, from time T35 to just before time T43, voltage V _IL represents the low-side detected current value of the low-side current sensing operation with time T35 as the sampling timing T _SMPL . The voltage V _IL between times T43 and T44 represents the high-side detected current value between times T43 and T44 in real time. From time T44 to time T45, voltage V _IL has a value that corresponds to the current flowing through transistor M2 (here, a value that corresponds to the voltage drop across sense resistor 31). However, the value of the voltage V _IL may be maintained unchanged at the value of the voltage V _IL at time T44 from time T44 to time T45. When a low-side current sensing operation with sampling timing T _SMPL at time T45 is performed, from time T45 until the next low-side or high-side current sensing operation is performed, the voltage V _IL is the low-side current sensing operation with sampling timing T _SMPL at time T45. It represents the low-side detected current value of the current sensing operation (that is, it is maintained at the low-side detected current value at time T45).

Therefore, in the operation example of FIG. 15, from time T45 to just before time T53, voltage V _IL represents the low-side detected current value of the low-side current sense operation with time T45 as the sampling timing T _SMPL . If "f _SW =f _REF /2" is maintained after time T53, the same operation is repeated after time T53.

In each unit period, the logic circuit 18 can switch the current information generation circuit 30C to execute the reference switching operation or the frequency division switching operation by monitoring whether a reset signal was issued during the previous period.

FIG. 16 shows a configuration example of the current information generation circuit 30C according to the embodiment EX2_1. In addition to the above-described sense resistor 31, S/H circuit 31, and amplifier circuit 33, the current information generation circuit 30C shown in FIG. 16 includes various parts referenced by 41 to 51. Wirings 52 and 53 and nodes 54 to 46 are also components of current information generation circuit 30C. In FIG. 16, the S/H circuit 32 includes

capacitors

32a and 32b and

switches

32c and 32d, and the amplifier circuit 33 includes a positive input terminal 33a, a negative input terminal 33b, and an output terminal 33c. The amplifier circuit 33 may actually be an amplifier circuit composed of an operational amplifier and a resistor. The amplifier circuit 33 amplifies the voltage at the positive input terminal 33a viewed from the potential at the negative input terminal 33b, and outputs the amplified voltage from the output terminal 33c as a voltage V _IL .

A capacitor 32a is connected between the positive input terminal 33a and ground. Further, the positive input terminal 33a is connected to one end of the switch 32c, and the other end of the switch 32c is connected to a connection node between the sense resistor 31 and the ground terminal GND. A capacitor 32b is connected between the negative input terminal 33b and ground. Further, the negative input terminal 33b is connected to one end of the switch 32d, and the other end of the switch 32d is connected to a connection node between the source of the transistor M2 and the sense resistor 31. The voltage at the ground terminal GND viewed from the source potential of the transistor M2 is referred to as a voltage Va. Further, the resistance value of the sense resistor 31 is represented by the symbol "R _SNS ". “Va=R _SNS ×IL” is established during the on-period of the transistor M2.

One end of the switch 41 is connected to the drain of the transistor M1, and the other end of the switch 41 is connected to the non-inverting input terminal of the operational amplifier 43. One end of the switch 42 is connected to the source of the transistor M1, and the other end of the switch 42 is connected to the wiring 52. The inverting input terminal and output terminal of the operational amplifier 43 are connected to each other. The operational amplifier 43 is driven by receiving the voltage at the wiring 52 as a negative power supply voltage and the boot voltage V _BOOT as a positive power supply voltage, and functions as a voltage buffer. Therefore, the operational amplifier 43 outputs the voltage at its non-inverting input terminal from its output terminal with low impedance. Transistors 45 to 47 are P-channel MOSFETs. The sources of

transistors

45 and 46 are connected to wiring 53 to which boot voltage V _BOOT is applied. The gate and drain of the transistor 45, the gate of the transistor 46, the output terminal of the operational amplifier 43, and one end of the resistor 44 are connected to each other at a node 54. The other end of the resistor 44 is connected to the wiring 52. The voltage drop occurring across the resistor 44 is referred to as voltage Vb. However, the voltage Vb represents the voltage at the node 54 viewed from the potential of the wiring 52.

The drain of transistor 46 is connected to the source of transistor 47. The drain of transistor 47 is connected to one end of resistor 48 at node 55, and the other end of resistor 48 is connected to ground. Internal power supply voltage V _REG is applied to the gate of transistor 47. The voltage drop that occurs across the resistor 48 is referred to as voltage Vc. However, voltage Vc represents the voltage at node 55 viewed from the ground potential. Voltage conversion circuit 49 generates voltage Vd from voltage Vc. In FIG. 16, it is assumed that "Vd<Vc", and therefore, the voltage conversion circuit 49 includes an operational amplifier 49a forming a voltage follower, and

resistors

49b and 49c forming a voltage dividing circuit. In the operational amplifier 49a, the non-inverting input terminal is connected to the node 55, and the output terminal is connected to the inverting input terminal and one end of the resistor 49. The other end of resistor 49b is connected to one end of resistor 49c at node 56, and the other end of resistor 49c is connected to ground. The voltage drop occurring across the resistor 49c is referred to as voltage Vd. However, the voltage Vd represents the voltage at the node 56 viewed from the ground potential.

The current information generation circuit 30C sets the states of the

switches

32c, 32d, 41, 42, 50, and 51 as follows under the control of the logic circuit 18 (see FIG. 17). During the on period of the transistor M2, the current information generation circuit 30C maintains all the

switches

41, 42, 50, and 51 in the off state. The current information generation circuit 30C keeps the

switches

32c and 32d in the on state until the sampling timing T _SMPL during the on period of the transistor M2, and keeps the

switches

32c and 32d in the off state after the sampling timing T _SMPL .
The current information generation circuit 30C keeps the

switches

32c and 32d in the off state during the on period of the transistor M1. The current information generation circuit 30C keeps all the

switches

41, 42, 50, and 51 in the on state only during the execution period HS_D of the high-side current sensing operation during the on period of the transistor M1, and keeps the switch 41 in the on state during other periods. , 42, 50 and 51 are all kept off.

The on-resistance (on-resistance value) of the transistor M1 is expressed as "R _ON H". Then, since the coil current IL flows between the drain and source of the transistor M1 during the period HS_D, "Vb=R _ON H×IL" is satisfied during the period HS_D. A current mirror circuit is formed by

transistors

45 and 46. Here, it is assumed that the drain current ratio of the

transistors

45 and 46 is 1:1, and that the resistance values of the

resistors

44 and 48 are the same. Then, during the period HS_D, a current having the same current value as the current flowing through the resistor 44 flows through the resistor 48, so that "Vc=R _ON H×IL". The transistors 45 to 47 constitute a level shifter that converts a voltage Vb based on the source potential of the transistor M1 to a voltage Vc based on the ground potential.

The voltage conversion circuit 49 is configured based on the ratio of the on-resistance R _ON H and the sense resistor R _SNS so that “Vd=R _SNS ×IL” in the period HS_D. In the configuration example of FIG. 16, it is assumed that "R _ON H>R _SNS ", so "Vd=R _SNS ×IL" is realized using the voltage dividing circuit (49b, 49c). However, if "R _ON H < R _SNS ", the voltage Vd may be generated by amplifying the voltage Vc in the voltage conversion circuit 49. Further, when "R _ON H=R _SNS ", the voltage conversion circuit 49 may be a single voltage follower. In any case, “Vd=R _SNS ×IL” in period HS_D.

With the above configuration and operation, the voltage V _IL shown and explained in FIG. 15 can be obtained. That is, for example, when a low-side current sensing operation is performed with sampling timing T _SMPL at time T30, the amplified difference between the voltages held in

capacitors

32a and 32b at time T30 becomes voltage V _IL (low-side detected current value). voltage). After time T30, switches 32c and 32d are maintained off until the next on-period of transistor M2 begins. Therefore, after time T30, the value of voltage V _IL remains unchanged until the next low-side or high-side current sensing operation is performed. After time T30, the high-side current sensing operation is started at time T33, so switches 41, 42, 50, and 51 are all turned on. Therefore, by applying the voltage Vd between the

input terminals

33b and 33a of the amplifier circuit 33 during the period HS_D between times T33 and T34, a voltage V _IL (a voltage representing the high-side detected current value) corresponding to the voltage Vd is output. Ru. At this time, the voltages Vd and V _IL change in real time in response to changes in the current flowing through the transistor M1.

Thereafter, at time T34, the transistor M1 is turned off and the transistor M2 is turned on, so that the

switches

41, 42, 50, and 51 are all turned off, while the

switches

32c and 32d are turned on. Therefore, the voltage I _L varies in conjunction with changes in the current flowing through the transistor M2. Then, at time T35, the voltage Va at that time is sampled and held, and thereafter, the voltage V _IL is a value corresponding to the voltage Va at time T35 until the next low-side or high-side current sensing operation is performed. will be maintained.

According to this embodiment, the low-side current sensing operation and the high-side current sensing operation are used together in the frequency division switching operation, so that the value of the coil current IL can be accurately reflected in the comparison voltage V _C . When the frequency division switching operation is performed, the increase in the coil current IL during a relatively long output high state is fed back to the differential amplifier 13, resulting in a decrease in the contrast voltage V _C (see FIG. 15). ). As a result, as can be understood from the comparison between FIGS. 14 and 15, excessive increase in duty in the frequency division switching operation is suppressed. Therefore, in Example EX2_1, when the switching operation is switched from the reference switching operation to the frequency division switching operation, it is possible to suppress fluctuations in the output voltage V _OUT to a low level (waveform 1620 according to Example EX2_1 and waveform 1620 according to the second hypothetical operation). (see waveform 1920), that is, the output voltage V _OUT can be well stabilized.

Note that in the output high state, the coil current IL increases with a slope according to the inductance of the coil L1. For this reason, when the frequency division switching operation is performed, it is being considered to superimpose pseudo current information based on the design value of the inductance of the coil L1 on the coil current information in the output high state. However, if the inductance value of the coil L1 actually used deviates from the design value, ideal pseudo-current information cannot be superimposed, and as a result, there is a concern that the stability of the output voltage V _OUT will decrease. In the method of this embodiment, there is no such concern.

The logic circuit 18 monitors the time from turning on the transistor M1 until the reset signal is issued each time the transistor M1 is turned on. As can be understood from the above description, the logic circuit 18 performs switching when a reset signal is not issued within a predetermined time period _tD after turning on the transistor M1 while performing a reference switching operation. Switches the operation from reference switching operation to frequency division switching operation. The specified time t _D is the maximum on-time t _{MAX_ON} when "f _SW = f _REF ".

Thereafter, when a reset signal is issued before the specified time t _D has elapsed from the turn-on timing of the transistor M1, the condition for returning to the standard switching operation is satisfied. When the conditions for returning to the standard switching operation are satisfied, the logic circuit 18 returns the switching operation to be performed to the standard switching operation. In the example of FIG. 15, after time T61, the input voltage V _IN increases, so that the switching operation performed can return to the reference switching operation. More specifically, for example, if the input voltage V _IN rises sufficiently at time T61, a reset signal is issued before a predetermined time t _D elapses after transistor M1 is turned on at time T61, and the reset signal is Upon receiving the signal, the logic circuit 18 immediately switches the output stage circuit MM from the output high state to the output low state. Thereafter, if the input voltage V _IN is sufficiently high, a reset signal is always issued during the preceding period in each unit period, so that "f _SW =f _REF " is maintained.

When the frequency division switching operation is performed, the coil current information (V _IL ) represents the low-side detected current value from the most recent low-side current sensing operation from when the transistor M1 is turned on until the sense result holding time _t P has elapsed. The period from when the transistor M1 is turned on until the transistor M1 is turned off after the sensing result holding time t _P has elapsed is a period HS_D, and during this period HS_D, the coil current information (V _IL ) is Represents the high-side detection current value due to operation. Thereafter, when the current low-side current sensing operation is performed at the next sampling timing T _SMPL , the coil current information (V _IL ) is updated to information representing the low-side detected current value by the current low-side current sensing operation.

In the example of FIG. 15, the sense result holding time t _P matches the reciprocal of the reference frequency f _REF . That is, in FIG. 15, for example, from when the transistor M1 is turned on at time T31 until time T33 when the sense result holding time t _P (=1/f _REF ) has elapsed, the coil current information (V _IL ) is based on the previous low-side current sense. It is maintained at the low side detected current value (corresponding to the voltage Va at time T30) due to the operation. After the sense result holding time t _P has elapsed since the transistor M1 was turned on at time T31, the coil current information (V _IL ) remains on the high side due to the high side current sense operation until the transistor M1 is turned off at time T34. It represents the detected current value (corresponding to the voltage Vd between times T33 and T34). After that, when the current low-side current sensing operation is performed at the next sampling timing T _SMPL (time T35), the coil current information (V _IL ) is changed to information ( (corresponding to voltage Va at time T35).

The sense result holding time t _P may be slightly longer than the reciprocal of the reference frequency f _REF (ie, the reference time t _REF ). However, the sense result holding time t _P is shorter than the time (2·t _REF −t _{MIN_SNS} ).

<<Example EX2_2>>
Example EX2_2 will be explained. In the embodiment EX2_1, the frequency division switching operation with "n=2" has been described, but depending on the degree of decrease in the input voltage V _IN , etc., the frequency division switching operation with "n≧3" can also be performed.

For example, the following case CSb is assumed based on the case shown in FIG. 15 (hereinafter referred to as case CSa). The differences between cases CSa and CSb are shown below with reference to FIG. In case CSb, the input voltage V _IN decreases more greatly than in case CSa at time T31. As a result, in case CSb, the reset signal is not issued in the first period of the unit period 1641 starting from time T31, and the reset signal is not issued even in the first period of the unit period 1642 starting from time T33. In case CSb, it is assumed that a reset signal is then issued at time T41' which belongs to the first period in the unit period 1643 starting from time T41 (whether or not the reset signal is issued is not shown in FIG. 18). Unit periods 1641 to 1643 are three consecutive unit periods. It is assumed that times T41' and T42' are times after time T41 and before time T43. Time T42' is a time after time T41'.

In case CSb, the logic circuit 18 switches the output stage circuit MM from the output low state to the output high state at time T31, maintains the output stage circuit MM in the output high state until time T41', and then switches the output stage circuit MM to the output high state until time T41'. The output stage circuit MM is returned to the output low state. After that, a low-side current sensing operation is performed with sampling timing T _SMPL at time T42' belonging to the unit period 1643, and further, at subsequent time T43, the output stage circuit MM goes into the output high state triggered by the rising edge of the clock signal CLK. Switch.

In case CSb, the above-mentioned sense result holding time t _P is assumed to be the same as the reciprocal of the reference frequency f _REF (ie, the reference time t _REF ). Therefore, from the time the transistor M1 is turned on at time T31 to the time T33, the coil current information (V _IL ) represents the low-side detected current value by the most recent low-side current sensing operation. From time T33 to time T41' when transistor M1 is turned off, coil current information (V _IL ) represents a high-side detected current value by a high-side current sensing operation. After that, when the current low-side current sensing operation is performed at the next sampling timing T _SMPL (that is, at time T42'), the coil current information (V _IL ) is changed to the low-side detected current value by the current low-side current sensing operation. The information is updated to represent the information.

In case CSb, the switching frequency f _SW switches from the reference frequency f _REF to the frequency (f _REF /3) at time T31. In case CSb, even after time T43, if the reset signal is not issued in each of the preceding periods of the first unit period and the second unit period, and the reset signal is issued in the preceding period of the third unit period, "n =3'' frequency division switching operation continues. Here, the first to third unit periods are three consecutive unit periods, and the third unit period comes after the first unit period passes through the second unit period. The conditions for returning to the standard switching operation are as shown in Example EX2_1.

It can be said that the logic circuit 18 performs the following operations. After turning on the transistor M1, the logic circuit 18 monitors whether a reset signal is issued during the pre-stage period. If a reset signal is issued during the previous stage period in the unit period of interest which is an arbitrary unit period, in response to the issuance of the reset signal, the logic circuit 18 immediately outputs the output stage circuit MM to a high state. Then, the output is switched to a low state, and a low-side current sensing operation is performed during the ON period of the transistor M2 within the unit period of interest. If the reset signal is not issued during the preceding period of the unit period of interest, the logic circuit 18 keeps the output stage circuit MM in the output high state throughout the unit period of interest, regardless of the level relationship between the voltages V _C and V _RAMP . The same operation as above is performed by setting the next unit period as a new unit period of interest. Therefore, depending on the degree of decrease in the input voltage V _IN , the on-period of the transistor M1 increases without limit (however, an upper limit may be set).

<<Example EX2_3>>
Example EX2_3 will be explained. The low-side current sensing operation may be performed using the on-resistance of the transistor M2 instead of the sense resistor 31. In this case, the current information generation circuit 30m shown in FIG. 19 can be used as the current information generation circuit 30C in FIG. In Example EX2_3, the current information generation circuit 30m shown in FIG. 19 is used as the current information generation circuit 30C shown in FIG.

The sense resistor 31 is not provided in the current information generation circuit 30m in FIG. In Example EX2_3, the source of transistor M2 is directly connected to the ground terminal GND. Changes to the current information generation circuit 30m in FIG. 19 from the current information generation circuit 30C in FIG. 16 due to the non-installation of the sense resistor 31 are shown below. Regarding matters not particularly described in this embodiment, the current information generation circuit 30m has the same configuration as the current information generation circuit 30C and performs the same operation.

The positive input terminal 33a is connected to one end of the switch 32c, and the other end of the switch 32c is connected to the source of the transistor M2. The negative input terminal 33b is connected to one end of the switch 32d, and the other end of the switch 32d is connected to the drain of the transistor M2. In Example EX2_3, voltage Va refers to the voltage at the source of transistor M2 viewed from the drain potential of transistor M2. The on-resistance of transistor M2 is represented by the symbol "R _ON L". Then, "Va=R _ON L×IL" is established during the on period of the transistor M2.

The voltage conversion circuit 49 in the circuit 30m is configured based on the ratio of the on-resistances R _ON H and R _ON L so that “Vd=R _ON L×IL” in the period HS_D. In the configuration example of FIG. 19, since it is assumed that "R _ON H>R _ON L", "Vd=R _ON L×IL" is realized using the voltage dividing circuit (49b, 49c). However, if "R _ON H < R _ON L", the voltage Vd may be generated by amplifying the voltage Vc in the voltage conversion circuit 49. Further, in the case where "R _ON H=R _ON L", the voltage conversion circuit 49 may be a single voltage follower. In any case, “Vd=R _ON L×IL” in period HS_D.

Basically, the transistors M1 and M2 may be elements having the same structure and the same breakdown voltage. When transistors M1 and M2 are elements having the same structure and the same breakdown voltage, the temperature characteristics of transistor M1 are the same as those of transistor M2 (ignoring errors). The temperature characteristics of the transistor include the temperature characteristics of the on-resistance of the transistor.

The amplifier circuit 33 can have a temperature characteristic for canceling the temperature characteristic of the on-resistance of the transistor M2. That is, when the on-resistance of the transistor M2 increases in response to a decrease in the environmental temperature of the power supply IC2C, the voltage Va during the on-period of the transistor M2 increases, but at this time, the amplification factor of the amplifier circuit 33 is reduced. The amplifier circuit 33 is configured in advance. The same applies when the environmental temperature of the power supply IC 2C rises. This reduces the influence of the environmental temperature of the power supply IC 2C on the coil current information (V _IL ). When the transistors M1 and M2 are elements having the same structure and the same breakdown voltage, the temperature characteristics of the on-resistance of the transistor M1 can also be canceled out by the amplifier circuit 33. That is, a circuit for canceling the temperature characteristics of transistors M1 and M2 can be shared between transistors M1 and M2, leading to a reduction in circuit scale.

Except for the point that the sense resistor 31 is not installed and the above-mentioned matters linked to the fact that the sense resistor 31 is not installed, the power supply IC 2C according to the embodiment EX2_3 is the same as the power supply IC 2C according to the embodiment EX2_1, The description of Example EX2_1 also applies to Example EX2_3. In this application, the "voltage drop across the sense resistor 31" and "value of the sense resistor 31" in Example EX2_1 are replaced with the "voltage drop occurring between the drain and source of transistor M2" and "on-on state of transistor M2" in Example EX2_3. It can be read as "resistance value".

<<Example EX2_4>>
Example EX2_4 will be explained. All the matters described in Example EX1_4 of the first embodiment are also applied to the second embodiment.

<<Second appendix>>
An additional note will be provided regarding the present disclosure, a specific configuration example of which was shown in the second embodiment described above.

A switching power supply circuit according to one aspect of the present disclosure is a switching power supply circuit (2, 2A) used in a switching power supply device (1) for generating an output voltage (V _OUT ) through switching of an _input voltage (V IN ). ), an output stage circuit (MM) having a high-side transistor (M1) and a low-side transistor (M2) connected in series between an input terminal (IN) receiving the input voltage and a ground terminal (GND); a switching control circuit (11 to 19) configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; and a switching control circuit (11 to 19) configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; a current information generation circuit (30C) configured to perform one current sensing operation or a second current sensing operation for detecting a current flowing through the high-side transistor during an on period of the high-side transistor; A connection node between the side transistor and the low-side transistor is connected to a rectification and smoothing circuit including a coil (L1) and an output capacitor (C1), and a switching voltage (V _SW ) generated at the connection node due to the switching operation is applied to the rectification and smoothing circuit. _The output voltage is generated by being rectified and _smoothed at the current information generating circuit is capable of setting the switching frequency to a first frequency (f _REF ) or a second frequency (f _REF /n) lower than the first frequency in the switching operation; is set to the first frequency, current information of the coil is generated by the first current sensing operation, and when the switching frequency is set to the second frequency, the first current sensing operation and the first current sensing operation are performed. This is a configuration (hereinafter referred to as configuration Q1) in which current information of the coil is generated using two current sensing operations.

When the switching frequency is set to a relatively low second frequency, the interval between executions of the first current sensing operation becomes longer. However, by performing the second current sensing operation during the on-period of the high-side transistor, feedback control that reflects the coil current becomes possible even during the period in which the first current sensing operation cannot be performed. As a result, the output voltage is stabilized.

In the switching power supply circuit according to the configuration Q1, the current information generation circuit may perform the second current sensing operation during the on period of the high-side transistor when the switching frequency is set to the second frequency. generate current information of the coil during the on-period of the high-side transistor, and generate current information of the coil during the on-period of the low-side transistor by executing the first current sensing operation during the on-period of the low-side transistor. A configuration (hereinafter referred to as configuration Q2) may also be used.

In the switching power supply circuit according to the configuration Q2, the current information generation circuit is configured to perform a part of the on-period of the high-side transistor in the second current sensing operation when the switching frequency is set to the second frequency. The current information of the coil is updated by continuously detecting the current flowing through the high-side transistor (for example, between T33 and T34 in FIG. 15), and then the high-side transistor is turned off and the low-side transistor is turned off. When turned on, the first current sensing operation is performed to detect the current flowing through the low-side transistor at a sampling timing set within the on-period of the low-side transistor (for example, T35 in FIG. 15). It may be a configuration (hereinafter referred to as configuration Q3) that generates current information of the coil during the on-period.

In the switching power supply circuit according to the configuration Q3, when the switching frequency is set to the second frequency, the coil is turned on until a sense result holding time (t _P ) elapses after the high-side transistor is turned on. The current information represents the current value detected by the previous first current sensing operation (for example, the detected current value at T30 in FIG. 15), and after the sense result holding time has elapsed since the high-side transistor was turned on, the high-side Until the transistor is turned off (for example, between T33 and T34 in FIG. 15), the current information of the coil represents the current detected value by the second current sense operation, and then the current information of the first current sense at the sampling timing. When a current sensing operation is performed, the current information of the coil is updated to information representing the current value detected by the current first current sensing operation (for example, the current value detected at T35 in FIG. 15). (referred to as Q4).

In the switching power supply circuit according to the configuration Q4, the sense result holding time may be a configuration (hereinafter referred to as configuration Q5) in which the sense result holding time is longer than the reciprocal of the first frequency (t _REF ).

In the switching power supply circuit according to any one of the configurations Q1 to Q5, when the switching frequency is set to the first frequency, the current information generation circuit includes each A configuration (hereinafter referred to as configuration Q6) may be used in which the current information of the coil is generated by executing the first current sensing operation during the period.

In the switching power supply circuit according to the configuration Q6, the switching control circuit is configured to generate a contrast voltage (V _C ) based on voltage information corresponding to the output voltage and current information of the coil. circuits (11 to 14), and a lamp voltage generation circuit (16) configured to generate a lamp voltage that monotonically changes from an initial level in a predetermined direction at a period of the reciprocal of the first frequency, In the switching operation, after turning on the high-side transistor, a reset signal (down edge of S _PWM) is generated in response to a change in the level relationship between the comparison voltage and the lamp voltage from a first relationship to a second relationship. is issued, turns off the high side transistor and turns on the low side transistor based on the issuance of the reset signal, and turns on the high side transistor while the switching frequency is set to the first frequency; A configuration (hereinafter referred to as configuration Q7) that switches the switching frequency from the first frequency to the second frequency when the reset signal is not issued before a specified time (t _{MAX_ON} ) shorter than the reciprocal of the first frequency has elapsed. ).

In the switching power supply circuit according to the configuration Q7, the switching control circuit switches the switching frequency from the first frequency to the second frequency until the prescribed time has elapsed from the turn-on timing of the high-side transistor. The switching frequency may be configured to return the switching frequency from the second frequency to the first frequency when the reset signal is issued (hereinafter referred to as configuration Q8).

A switching power supply device according to one aspect of the present disclosure includes a switching power supply circuit according to any one of the configurations Q1 to Q8, and a rectifier configured to generate the output voltage by rectifying and smoothing the switching voltage. This is a smoothing circuit and a configuration (hereinafter referred to as configuration Q9).

1 Switching

power supply device

2, 2A, 2B, 2C Power supply IC
3 Main control block L1 Coil C1 Output capacitor C2 Boot capacitor R1, R2 Resistor D1 Rectifier V _IN input voltage V _OUT output voltage V _FB feedback voltage V _SW switching voltage IN Input terminal GND Ground terminal OUT Output terminal FB Feedback terminal BOOT Boot terminal OS Output monitoring terminal MM Output stage circuit M1 High side transistor M2 Low side transistor 11 Error amplifier 12 Phase compensation circuit 13 Differential amplifier 14 Phase compensation circuit 15 Clock generation circuit 16 Lamp voltage generation circuit 17 Comparator 18 Logic circuit 19

Driver

30, 30C, 30m Current information generation circuit 31 Sense resistor 32 S/H circuit 33 Amplification circuit 34 Pseudo current generation circuit 35 Adder IL Coil current V _ISNS voltage (detection current information)
V _IPS voltage (pseudo current information)
V _IL voltage (coil current information)
V _ERR error voltage V _C comparison voltage

Claims

In a switching power supply circuit used in a switching power supply device for generating an output voltage through switching of an input voltage,
an output stage circuit having a high-side transistor and a low-side transistor connected in series with each other between an input terminal receiving the input voltage and a ground terminal;
a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor;
a current information generation circuit configured to perform a current sensing operation to detect a current flowing through the low-side transistor during an on-period of the low-side transistor;
A connection node between the high-side transistor and the low-side transistor is connected to a rectification and smoothing circuit including a coil and an output capacitor, and a switching voltage generated at the connection node due to the switching operation is rectified and smoothed by the rectification and smoothing circuit. The output voltage is generated by
The switching control circuit performs the switching operation based on voltage information corresponding to the output voltage and current information of the coil generated through the current sensing operation,
The switching control circuit is capable of setting a switching frequency in the switching operation to a first frequency or a second frequency lower than the first frequency,
When the switching frequency is set to the second frequency, the current information generation circuit is configured to detect the current information in the current information generation circuit during a part of the period from performing the most recent current sensing operation to performing the next current sensing operation. A switching power supply circuit that generates current information of the coil by adding pseudo current information based on the input voltage and the output voltage to current information detected by the current sensing operation.
The switching power supply circuit according to claim 1, wherein the current information generation circuit generates the pseudo current information based on the input voltage, the output voltage, and the inductance of the coil.
The current information generation circuit generates the pseudo current information based on the input voltage, the output voltage, the inductance of the coil, and a time corresponding to the reciprocal of the first frequency. switching power supply circuit.
The current information generation circuit is configured to: during a period in which the switching frequency is set to the second frequency,
until a predetermined period of time has elapsed since the high-side transistor was turned on, generating the detected current information from the most recent current sensing operation as current information of the coil;
After the predetermined time has elapsed since the high-side transistor was turned on, the sum of the detected current information and the pseudo current information from the most recent current sensing operation is calculated until the next current sensing operation is performed. 4. The switching power supply circuit according to claim 1, wherein the circuit generates current information of a coil.
When the switching frequency switches from the first frequency to the second frequency, the current information generation circuit sets a value of the pseudo current information immediately after the switching to be larger than a value of the pseudo current information thereafter. A switching power supply circuit according to any one of claims 1 to 4.
When the switching frequency is set to the first frequency, the current information generation circuit executes the current sensing operation in each period having a length equal to the reciprocal of the first frequency, and is configured to perform the current sensing operation according to the current sensing operation. 6. The switching power supply circuit according to claim 1, wherein the detected current information is generated as current information of the coil.
The switching control circuit includes:
a contrast voltage generation circuit configured to generate a contrast voltage based on voltage information corresponding to the output voltage and current information of the coil;
a lamp voltage generation circuit configured to generate a lamp voltage that monotonically changes from an initial level in a predetermined direction at a period of the reciprocal of the first frequency;
In the switching operation, after turning on the high-side transistor, a reset signal is issued in response to a change in the level relationship between the comparison voltage and the lamp voltage from a first relationship to a second relationship; Turn off the high side transistor and turn on the low side transistor based on the issuance of the
In a state where the switching frequency is set to the first frequency, when the reset signal is not issued within a specified time period shorter than the reciprocal of the first frequency after turning on the high-side transistor, the switching frequency is set to the first frequency. The switching power supply circuit according to claim 6, wherein the frequency is switched from the first frequency to the second frequency.
The switching control circuit, after switching the switching frequency from the first frequency to the second frequency, when the reset signal is issued before the specified time elapses from the turn-on timing of the high-side transistor, The switching power supply circuit according to claim 7, wherein the switching frequency is returned from the second frequency to the first frequency.
A switching power supply circuit according to any one of claims 1 to 8,
A switching power supply device comprising: a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing the switching voltage.
In a switching power supply circuit used in a switching power supply device for generating an output voltage through switching of an input voltage,
an output stage circuit having a high-side transistor and a low-side transistor connected in series between an input terminal receiving the input voltage and a ground terminal;
a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor;
A first current sensing operation for detecting a current flowing through the low-side transistor during an on-period of the low-side transistor, or a second current sensing operation for detecting a current flowing through the high-side transistor during an on-period of the high-side transistor. comprising a current information generation circuit configured,
A connection node between the high-side transistor and the low-side transistor is connected to a rectification and smoothing circuit including a coil and an output capacitor, and a switching voltage generated at the connection node due to the switching operation is rectified and smoothed by the rectification and smoothing circuit. The output voltage is generated by
The switching control circuit performs the switching operation based on voltage information corresponding to the output voltage and current information of the coil, and in the switching operation, sets the switching frequency to a first frequency or a second frequency lower than the first frequency. is configurable and
The current information generation circuit generates current information of the coil by the first current sensing operation when the switching frequency is set to the first frequency, and when the switching frequency is set to the second frequency. , a switching power supply circuit that generates current information of the coil by using the first current sensing operation and the second current sensing operation in combination.
The current information generation circuit is configured to perform the second current sensing operation during the on-period of the high-side transistor when the switching frequency is set to the second frequency, thereby increasing the current sensing operation of the coil during the on-period of the high-side transistor. 11. The switching power supply according to claim 10, wherein current information of the coil is generated during the on-period of the low-side transistor by generating current information of the coil during the on-period of the low-side transistor by performing the first current sensing operation during the on-period of the low-side transistor. circuit.
The current information generation circuit is configured such that when the switching frequency is set to the second frequency,
In the second current sensing operation, the current information of the coil is updated by continuously detecting the current flowing through the high-side transistor during a part of the on period of the high-side transistor,
Thereafter, when the high-side transistor is turned off and the low-side transistor is turned on, the first current sensing operation is performed to detect the current flowing through the low-side transistor at a sampling timing set within the on-period of the low-side transistor. 12. The switching power supply circuit according to claim 11, wherein the switching power supply circuit generates current information of the coil during an on period of the low-side transistor.
When the switching frequency is set to the second frequency,
After the high-side transistor is turned on until a sense result holding time elapses, the current information of the coil represents a current value detected by the previous first current sensing operation,
After the sense result holding time has elapsed since the high-side transistor was turned on and until the high-side transistor is turned off, the current information of the coil represents a current detected value by the second current sensing operation,
Thereafter, when the current first current sensing operation is performed at the sampling timing, the current information of the coil is updated to information representing a current value detected by the current first current sensing operation. The switching power supply circuit described.
14. The switching power supply circuit according to claim 13, wherein the sense result holding time is longer than the reciprocal of the first frequency.
The current information generation circuit is configured to perform the first current sensing operation in each period having a length equal to the reciprocal of the first frequency when the switching frequency is set to the first frequency. The circuit for a switching power supply according to any one of claims 10 to 14, which generates current information of.
The switching control circuit includes:
a contrast voltage generation circuit configured to generate a contrast voltage based on voltage information corresponding to the output voltage and current information of the coil;
a lamp voltage generation circuit configured to generate a lamp voltage that monotonically changes from an initial level in a predetermined direction at a period of the reciprocal of the first frequency;
In the switching operation, after turning on the high-side transistor, a reset signal is issued in response to a change in the level relationship between the comparison voltage and the lamp voltage from a first relationship to a second relationship; Turn off the high side transistor and turn on the low side transistor based on the issuance of the
In a state where the switching frequency is set to the first frequency, when the reset signal is not issued within a specified time period shorter than the reciprocal of the first frequency after turning on the high-side transistor, the switching frequency is set to the first frequency. The circuit for a switching power supply according to claim 15, wherein a frequency is switched from the first frequency to the second frequency.
The switching control circuit, after switching the switching frequency from the first frequency to the second frequency, when the reset signal is issued before the specified time elapses from the turn-on timing of the high-side transistor, 17. The switching power supply circuit according to claim 16, wherein the switching frequency is returned from the second frequency to the first frequency.
A switching power supply circuit according to any one of claims 10 to 17,
A switching power supply device comprising: a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing the switching voltage.