WO2024027356A1

WO2024027356A1 - Electronic apparatus, and method for securely accessing software

Info

Publication number: WO2024027356A1
Application number: PCT/CN2023/101009
Authority: WO
Inventors: 谌峰; 薛杉; 李硕
Original assignee: 华为技术有限公司
Priority date: 2022-07-30
Filing date: 2023-06-19
Publication date: 2024-02-08
Also published as: CN117521054A

Abstract

Provided in the present application are an electronic apparatus, and a method for securely accessing software. The electronic apparatus provided in the present application comprises a processor and a controller. The processor is used for running the current software, and sending to the controller a logical address to be accessed by the current software and a target access permission of the software for the logical address; and the controller is used for converting the logical address into a physical address in the processor, and allowing, when the physical address is in a preset physical address space corresponding to the current world of the current software and the target access permission is the same as a preset access permission of the current world for the preset physical address space, the processor to access the logical address, wherein a software running environment of the electronic apparatus has a plurality of worlds, each of the plurality of worlds corresponds to at least two physical address spaces, the at least two physical address spaces respectively correspond to different access permissions, and the current world is one of the plurality of worlds. By means of the electronic apparatus provided in the present application, the security of the run software can be improved.

Description

Electronic devices and methods of secure access to software

This application claims priority to the Chinese patent application filed with the China Patent Office on July 30, 2022, with the application number 202210911423.3 and the application title "Electronic device and method for secure access to software", the entire content of which is incorporated into this application by reference. middle.

Technical field

Embodiments of the present application relate to the field of computer security, and in particular, to an electronic device and a method for securely accessing software.

Background technique

With the rapid development of Internet technology and computer technology, electronic devices such as terminals and servers have more and more functions. In order to support the operation of these electronic devices, more and more important data are stored in these electronic devices. This important data includes, for example, but is not limited to, the kernel page table, the cred structure of the Linux process, the selinux database, biometric data (fingerprint data, facial image data), key data or certificate data, etc. Therefore, the requirements for the safety of the operating environment of electronic devices are getting higher and higher.

In order to ensure the security of the operating environment of the electronic device, in the prior art, the software operating environment of the electronic device is set into multiple worlds (such as a normal world and a secure world), and the physical address space that can be accessed by each world is limited. Access here refers to reading instructions or data stored in the physical address space, or reading data from the physical address space. This may lead to hackers attacking the software running in each world and rewriting the instructions or data stored in the physical address space of the corresponding world through the software running in each world, causing important data to be leaked or rewritten. Therefore, how to improve the software Operational security remains an issue that needs to be addressed.

Contents of the invention

The electronic device and the method for securely accessing software provided by this application can improve the security of the software being run. In order to achieve the above objectives, this application adopts the following technical solutions.

In a first aspect, embodiments of the present application provide an electronic device. The electronic device includes: a processor and a controller; the processor is configured to run current software and send to the controller the information to be accessed by the current software. A logical address and the target access permission of the current software to the logical address; the controller is configured to: receive the logical address and the target access permission from the processor; convert the logical address into The physical address in the memory; when the physical address is within the preset physical address space corresponding to the current world of the current software, and the target access permission is consistent with the preset physical address space of the current world. If the access rights are the same, the processor is allowed to access the logical address; wherein, the software running environment of the electronic device has multiple worlds, and each world in the multiple worlds corresponds to at least two physical address spaces. , and the at least two physical address spaces respectively correspond to different access rights, the current world is one of the plurality of worlds; the access rights include one of the following: reading or rewriting software stored in the physical address space , is limited to reading software stored in the physical address space, is limited to executing software stored in the physical address space.

In this embodiment of the present application, the target access permission is the same as the preset access permission of the current world to the preset physical address space, or it may also mean that the target access permission is within the range of the preset access permission. For example, when the preset access rights include that the current world can either read the software in the preset physical address space or rewrite the software in the preset physical address space, the target access rights are only for reading or rewriting the software in the preset physical address space. If the software in the logical address is only rewritten or can both read and rewrite, it can be understood that the target access rights are the same as the preset access rights of the current world to the preset physical address space.

In traditional technology, only the physical address space that software running in each world can read and rewrite is limited. This results in hackers attacking the software running in a certain world to read or rewrite the instructions or data stored in the physical address space corresponding to that world, causing important instructions or data stored in the physical address space to be leaked or rewritten. This leads to security issues for electronic devices. The embodiments of this application define the physical address space that software running in each world can read and rewrite, the physical address space that software running in each world can only read (cannot rewrite), and the software running in each world. A physical address space that can only be executed (cannot be read and rewritten). Important instructions or data in electronic devices can be stored in memory, in a physical address space that can only be read by software running in each world, or in an electronic device. Important instructions can be stored in memory, within the physical address space that can only be executed by the software running on each world; In addition, based on the world where the processor is currently located, the controller determines whether the physical address is in the preset physical address space corresponding to the current world of the current software based on the world where the software currently running on the processor is located and the access method to the logical address. and determine whether the current world's target access permissions to the physical address space are preset access permissions. Only when both conditions are met can the physical address be provided to the processor, thereby preventing hackers from attacking the software running in each world. , to rewrite the instructions or data stored in the physical address space of the corresponding world, thereby preventing important instruction programs or data from being leaked or rewritten, thereby improving the security of the operation of electronic devices.

In one possible implementation, the physical address provided by the controller to the processor can be an effective address, so that the processor can access instructions or data from the physical address corresponding to the memory based on the effective address; in other possible implementations , the physical address provided by the controller to the processor can be a null address. At this time, the processor can execute other process steps without obtaining instructions or data from the memory.

In a possible implementation, the controller is further configured to: when the physical address is outside the preset physical address space corresponding to the current world of the current software, and the target access permission is consistent with the current world of the current software. When at least one of the two preset access rights is different, a signal indicating an error is sent to the processor.

In a possible implementation, the processor is further configured to: perform a security protection operation based on the signal indicating an error, where the security protection operation includes at least one of the following: resetting the processor, rejecting the Access to a logical address by software currently running on a processor instructs the processor to cease operation, disables at least part of the functionality of the processor, and prevents the processor from accessing the memory.

In a possible implementation, the electronic device further includes the memory, and the memory is further configured to: store the at least two physical address spaces of each world in the plurality of worlds and the at least Mapping relationship between different access rights of two physical address spaces; the controller is also configured to determine the preset physical address space and the preset access corresponding to the current world according to the mapping relationship permissions.

In a possible implementation, the controller converts the logical address into a physical address, specifically for querying at least once a preset first page table and at least once a preset page table based on the logical address. a second page table; according to the first page table, convert the logical address into at least one level of intermediate addresses; according to the first page table and the second page table, when each of the at least one level of intermediate addresses When all first-level intermediate addresses are allowed to be accessed, the last-level intermediate address among the at least one-level intermediate addresses is converted into the physical address; wherein, the at least one-level intermediate address, and the access rights of each world in the plurality of worlds to the at least one level of intermediate address; the second page table records the access rights of each world in the plurality of worlds to the at least one level of intermediate address. access rights.

In traditional technology, the controller converts the logical address into a physical address, which usually requires two-level address translation and detection. That is to say, after the controller obtains the logical address, it first queries the first level in the exception level EL1. The page table translates and detects the logical address, and converts the logical address into an intermediate logical address; then, the controller translates and detects the intermediate logical address by querying the second-level page table set in the exception level EL2, and converts the intermediate logical address into an intermediate logical address. Logical addresses are converted into physical addresses.

In the embodiment of this application, the controller translates and detects the logical address by querying the first page table, and converts the logical address into an intermediate address. The intermediate address is a physical address; by querying the second page table, the intermediate address is Perform permission check, that is, compared with the method of converting a logical address into a physical address shown in the prior art, the conversion step of converting a logical address into an intermediate logical address is omitted, thereby simplifying the conversion step from a logical address to a physical address. In this case, the space originally used to store the intermediate logical address is also omitted to save storage space.

In a possible implementation, the controller is further configured to: when there is at least one level of intermediate address that is not allowed to be accessed, transmit a signal indicating an error to the processor.

In a possible implementation, the electronic device includes multiple exception levels, each exception level corresponds to a section of physical address space in the memory, and software running at a low exception level prohibits access corresponding to a high exception level. physical address space, wherein the mapping relationship is stored in the physical address space corresponding to the highest exception level among the plurality of exception levels.

In a possible implementation, the first page table is stored in a physical address space corresponding to a first exception level among the plurality of exception levels, and the first exception level is lower than the highest exception level. Exception level; the second page table is stored in the physical address space corresponding to the highest exception level.

In the embodiment of the present application, the second-level page table set at the exception level EL2 in the traditional technology for converting the intermediate logical address into an intermediate-level address and detecting the intermediate-level address is replaced with the second-level page table set at the exception level EL3. The second page table is used for intermediate-level address detection. Since the security of abnormal level EL3 is much higher than the security of abnormal level EL2, it can effectively detect electronic devices. safety protection.

In a possible implementation, the electronic device further includes a direct memory access controller; allowing the processor to access the logical address is specifically used to: provide the physical address to the direct memory. Access controller; the direct memory access controller is used to provide instructions or data in the physical address to the processor.

In the second aspect, embodiments of the present application provide a method for securely accessing software. The method includes: based on the logical address to be accessed by the current software, converting the logical address into a physical address in the memory; when the physical address is between When the current software is within the preset physical address space corresponding to the current world, and the target access permission of the current software to the logical address is the same as the preset access permission of the current world to the preset physical address space. , allowing the current software to access the logical address; wherein the software running environment of the electronic device has multiple worlds, each of the multiple worlds corresponds to at least two physical address spaces, and the At least two physical address spaces respectively correspond to different access rights, and the current world is one of the plurality of worlds; the access rights include one of the following: reading or rewriting software stored in the physical address space, reading only Retrieving software stored in the physical address space is limited to executing software stored in the physical address space.

In a possible implementation, the method further includes: when the physical address is outside the preset physical address space corresponding to the current world of the current software, and the target access permission is consistent with the preset physical address space. If at least one of the two access rights are different, security protection operations are performed.

In a possible implementation, the method further includes: determining the preset physical address space and the preset access permission corresponding to the current world according to a prestored mapping relationship; wherein the mapping relationship Used to indicate the at least two physical address spaces of each world in the plurality of worlds and different access rights to the at least two physical address spaces; the mapping relationship is stored in the memory.

In a possible implementation, converting the logical address into a physical address in the memory specifically includes: querying the first page table and the second page table at least once based on the logical address; according to The first page table converts the logical address into at least one level of intermediate addresses; when each level of the at least one level of intermediate addresses is allowed to be accessed, converts the at least one level of intermediate addresses into The last level of intermediate address is converted into the physical address; wherein the at least one level of intermediate address is recorded in the first page table, and the at least one level of intermediate address for each world in the plurality of worlds is recorded in the first page table. The access rights of the at least one-level intermediate address are recorded in the second page table.

In a possible implementation, the method further includes: performing a security protection operation when there is a first-level intermediate address that is not allowed to be accessed.

In a possible implementation, the security protection operation includes at least one of the following: resetting the processor, denying access to logical addresses by software currently running on the processor, instructing the processor to stop running, prohibiting the At least part of the functionality of the processor prevents the processor from accessing the memory.

In a third aspect, embodiments of the present application provide a device, which includes: a conversion module for converting the logical address to be accessed by the current software into a physical address in the memory based on the logical address; and an access permission module for converting the logical address to a physical address in the memory. When the physical address is within the preset physical address space corresponding to the current world of the current software, and the target access permission of the current software to the logical address is consistent with the current world's access to the preset physical address space When the preset access rights are the same, the current software is allowed to access the logical address; wherein, the software running environment of the electronic device has multiple worlds, and each world in the multiple worlds corresponds to at least two physical The address space and the at least two physical address spaces respectively correspond to different access rights, and the current world is one of the plurality of worlds; the access rights include one of the following: reading or rewriting in the physical address space Stored software is limited to reading software stored in the physical address space, and is limited to executing software stored in the physical address space.

In a possible implementation, the device further includes: a first security protection module, configured to operate when the physical address is outside the preset physical address space corresponding to the current world of the current software, and the When at least one of the target access rights and the preset access rights are different, a security protection operation is performed.

In a possible implementation, the device further includes: a determining module, configured to determine the preset physical address space and the preset access permission corresponding to the current world according to a pre-stored mapping relationship; wherein , the mapping relationship is used to indicate the at least two physical address spaces of each world in the plurality of worlds and the different access rights to the at least two physical address spaces; the mapping relationship is stored in the memory middle.

In a possible implementation, the conversion module is specifically configured to: based on the logical address, respectively query at least once a preset first page table and at least once a preset second page table; according to the The first page table converts the logical address into at least one level According to the first page table and the second page table, when each level of intermediate addresses in the at least one level of intermediate addresses is allowed to access, the last one of the at least one level of intermediate addresses is A level intermediate address is converted into the physical address; wherein the at least one level intermediate address is recorded in the first page table, and the access of each world in the plurality of worlds to the at least one level intermediate address Permissions; the second page table records the access permissions of each world in the plurality of worlds to the at least one level of intermediate address.

In a possible implementation, the device further includes: a second security protection module, configured to perform a security protection operation when there is at least one level of intermediate address that is not allowed to be accessed.

In the fourth aspect, embodiments of the present application provide a system-level chip. The device includes a controller and an interface circuit. The interface circuit is used to couple a memory, and an instruction program is stored in the memory. The controller is configured with After calling all or part of the computer program stored in the memory, the method described in the second aspect is executed.

In a fifth aspect, embodiments of the present application provide a computer-readable storage medium. The computer-readable storage medium stores a computer program. When executed by a controller, the computer program is used to implement the method described in the second aspect. .

In a sixth aspect, embodiments of the present application provide a computer program product, which is used to implement the method described in the second aspect when the computer program product is executed by a controller.

It should be understood that the second to sixth aspects of the present application are consistent with the technical solution of the first aspect of the present application, and the beneficial effects achieved by each aspect and corresponding feasible implementations are similar, and will not be described again.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application;

Figure 2 is a schematic diagram of the software architecture of the electronic device provided by the embodiment of the present application;

Figure 3 is a schematic diagram of the mapping relationship between the physical address range in the memory and the access permissions of each world provided by the embodiment of the present application;

Figure 4 is a schematic diagram of the mapping relationship between the access rights of each world, the corresponding bits, and the physical address range in the memory provided by the embodiment of the present application;

Figure 5 is a flow chart of a detection method applied to a controller provided by an embodiment of the present application;

Figures 6A to 6C are schematic diagrams of application scenarios based on the detection method shown in Figure 5 provided by embodiments of the present application;

Figure 7 is a schematic diagram of the conversion process of the controller converting the logical address into the physical address provided by the embodiment of the present application;

Figure 8 is another flow chart of the detection method applied to the controller provided by the embodiment of the present application;

Figure 9 is a flow chart of a method for securely accessing software provided by an embodiment of the present application;

Figure 10 is a schematic structural diagram of a device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

"First", "second" and similar words mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, similar words such as "a" or "one" do not indicate a quantitative limit, but rather indicate the presence of at least one.

In the embodiments of this application, words such as "exemplary" or "for example" are used to express examples, illustrations or illustrations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner. In the description of the embodiments of this application, unless otherwise specified, the meaning of “plurality” refers to two or more.

Please refer to FIG. 1 , which shows a schematic hardware architecture diagram of an electronic device 100 provided by an embodiment of the present application. The electronic device 100 may be located in a terminal. The terminal can be a user equipment (UE), such as a mobile phone, tablet or wearable devices (such as smart watches) and other types of portable terminal devices. FIG. 1 is only an example of the electronic device 100. Alternatively, the electronic device 100 can also be any type of equipment, such as a chip or a chipset, or a circuit board equipped with a chip or a chipset, etc. This embodiment is not limited thereto. . The chip or chipset or the circuit board equipped with the chip or chipset can operate under a suitable software driver. The electronic device 100 includes a processor 101 and a controller 102 . Optionally, the processor 101 and the controller 102 can be integrated into one or more chips, and the one or more chips can be regarded as a chipset. When one or more processors are integrated into the same When inside a chip, the chip is also called a system on a chip (SOC), as shown in Figure 1. The processor 101 may include components such as logical computing units and registers (including but not limited to data registers and instruction registers) for loading programs and executing instruction content. The controller 102 may also exist outside the processor 101. In this implementation The example is not limited to this. The processor 101 includes, for example, but is not limited to, a central processing unit (CPU) or a special-purpose processor. For example, the special-purpose processor includes an artificial intelligence processor, a neural network processor, a digital signal processor, or an image processing processor. The controller 102 may include, but is not limited to, a Memory Management Unit (MMU). As long as the controller 102 can convert the logical address to the physical address and implement the subsequent judgment process, its implementation form is not limited in this embodiment. Electronic device 100 may also include one or more other components, such as memory 103 . The memory 103 may illustratively include volatile memory, such as dynamic random access memory (DRAM) and other components for storing instructions and data. Among them, the memory 103 can be selectively integrated into the above-mentioned SOC or provided outside the above-mentioned SOC. Figure 1 schematically shows the situation where the memory 103 is provided outside the SOC. The memory 103 may store various operating system programs (such as general operating system programs and trusted operating system programs), application programs, instruction codes and data required for operation, etc. The processor 101 and the controller 102 execute various functional applications and data processing of the electronic device 100 by loading programs and instructions and acquiring data. Optionally, the memory 103 may also include a cache, which may be integrated into the system-on-chip.

In the embodiment of the present application, the software running architecture of the electronic device 100 may be the Arm Confidential Compute Architecture (CCA) proposed by ARM Corporation. Under the ArmCCA architecture, the software running environment of the electronic device 100 can include a normal world, a secure world, a realm world and a root world, as shown in Figure 2. normal world, secure world, realm world and root world respectively correspond to different physical address spaces in the memory 103. Among them, the software running in the normal world can only access the physical address space corresponding to the normal world; the software running in the secure world can only access the physical address space corresponding to the secure world in the memory 103; the software running in the realm world can only access the physical address space corresponding to the secure world. The physical address space corresponding to the realm world in the memory 103 can be accessed; software running in the root world can only access the physical address space corresponding to the root world in the memory 103. The normal world has the lowest security, and the root world has the highest security. Software running in the normal world may include, for example, common application (AP, application) software, general operating system software and hypervisor software; software running in the secure world may include, for example, but is not limited to, trusted application (trust application) ) software, trusted operating system software and secure partition management (SPM) software; software running in the realm world may include, for example, realm management monitor (RMM) software and application software, running on root The software in the world may include, for example, monitor software. The software described in the embodiments of the present application may include instructions and data. In addition, switching between normal world, secure world and realm world is monitored and executed by the monitor.

Furthermore, the software running architecture is based on the ArmCCA architecture, and the software running environment can be divided into multiple exception levels (EL, Exception Level). Figure 2 schematically shows the four abnormality levels EL0 to EL3. The above-mentioned ordinary applications (usually third-party applications, such as video applications, shopping applications) and trusted applications can run at the exception level EL0, general operating systems (such as Windows system, Android system, Redhat Linux system or Hongmeng operating system, etc.) and trusted operating systems can run at exception level EL1, hypervisors, secure partition management, and domain management monitors can run at exception level EL2, and monitors can run at exception level EL3. Among them, the abnormality level EL0 is the lowest, and the abnormality level EL3 is the highest.

It should be noted that in the embodiment of this application, the realm world includes hardware that is independent of other worlds, and the hardware of the realm world is completely isolated from the hardware of all other non-root worlds. Realm World can run firmware and virtual machines specific to Realm World. In addition, in the embodiment of this application, the realm word can be initialized by the hypervisor software, and the virtual machine running in the realm word can be generated and controlled by the hypervisor software in the normal world, but the hardware execution is in the realm world. That is to say, after the realm word is initialized, the software running in the realm word, the important codes or data saved, and the status of the realm word cannot be monitored or modified by other software running on the electronic device 100, that is, they cannot be monitored or modified by the normal world. Any software monitoring or modification in. Usually, important data such as the kernel page table, the cred structure of the Linux process, and the selinux database are stored in the physical address space corresponding to the realm word in the memory 103 to ensure that the important data is not monitored or modified by the software running in the normal world. . From this, it can be mentioned High operating safety of the electronic device 100 .

Based on the hardware architecture of the electronic device 100 shown in FIG. 1 and the software architecture of the electronic device 100 shown in FIG. 2, in order to further improve the security of the electronic device 100, the electronic device 100 provided by the embodiment of the present application is provided with a physical address space. The mapping relationship between the access permissions of the above worlds. The following uses specific examples to explain in detail the mapping relationship between the physical address space and the access permissions of the above worlds. As shown in FIG. 3 , FIG. 3 schematically shows the access rights of the above-mentioned worlds corresponding to the physical address space in the memory 103 , that is, the mapping relationship is shown. As shown in Figure 3, the physical address space 0x2000~0x2999 corresponds to secure world read/write only, that is, the software stored in this physical address space is limited to software other than those running in the secure world. The software reads and rewrites, and other worlds cannot access it; the physical address space 0x3000~0x3999 corresponds to normal world read/write only, that is, the software stored in this physical address space is limited to running It is read and rewritten by software in the normal world, and is inaccessible to other worlds; the physical address space 0x4000~0x4999 corresponds to root world read/write only (root world read/write only), that is, the data stored in this physical address space Software is limited to reading and rewriting by software running in the root world, and is inaccessible to other worlds; the physical address space 0x5000~0x5999 corresponds to realm world read/write only, that is, the physical address The software stored in the space can only be read and rewritten by the software running in the realm world, and is inaccessible to other worlds.

The mapping relationship shown above limits the physical address space that software running in each world can both read and rewrite. In the above mapping relationship, a physical address space in the memory 103 that can only be read by the software running in each world and cannot be rewritten can also be defined. As shown in Figure 3, the physical address space 0x7000~0x7999 corresponds to secure world read only, that is, the software stored in this physical address space can only be read by software running in the secure world. , software running in the secure world cannot write to it, and other worlds cannot access this space; the physical address space 0x8000~0x8999 corresponds to normal world read only, that is, within the physical address space The stored software can only be read by software running in the normal world. Software running in the normal world cannot write to it, and other worlds cannot access this space; the physical address space 0x9000~0x9999 corresponds to the root world only. Read (root world read only), that is, the software stored in the physical address space can only be read by software running in the root world. Software running in the root world cannot write to it, and other worlds cannot access it. This space; the physical address space 0x10000~0x10999 corresponds to realm world read only, that is, the software stored in this physical address space can only be read by software running in the realm world, running in the realm Software in the world cannot write to it, and other worlds cannot access the space.

Furthermore, the above mapping relationship also limits the memory 103 to only software running in each world executing software programs, and cannot read or rewrite software programs stored in the physical address space. As shown in Figure 3, the physical address space 0x11000~0x11999 corresponds to the secure world execution only memory, that is, the software programs stored in this physical address space are limited to software running in the secure world. Reading and writing cannot be performed; the physical address space 0x12000~0x12999 corresponds to the normal world execution only memory, that is, the software programs stored in this physical address space are limited to software running in the normal world. Execution; physical address space 0x13000~0x13999 corresponds to root world execution only memory, that is, the software programs stored in this physical address space are limited to software execution running in the root world; physical address space 0x14000 ~0x14999 corresponds to realm world execution only memory, that is, the software programs stored in the physical address space are limited to software running in the realm world.

In this embodiment of the present application, the mapping relationship between the physical address space and the access permissions of the above-mentioned worlds may be stored in the memory 103 . In specific implementation, the memory 103 may store a page table, which is dedicated to recording the mapping relationship between the physical address space and the access rights of each world. The mapping relationship is recorded in the page table in the form of a mapping table. In this possible implementation, in order to prevent hackers from rewriting the mapping relationship recorded in the page table, the above mapping relationship can be stored in the physical address space corresponding to the root word (that is, exception level EL3) shown in Figure 2. The physical address space used to store the above mapping relationship may be, for example, the physical address spaces 0x9000˜0x9999 as mentioned above, or may be other physical address spaces other than this physical address space. Preferably, the physical address space used to store the above mapping relationship can be a physical address space that can only be read by software running in the root word, but cannot be rewritten. In this way, hackers can be prevented from rewriting the above mapping relationship by attacking the software running in the root word, thereby improving the security of the operation of the electronic device 100.

It should be noted that the mapping relationship shown in Figure 3 is only schematic. In actual applications, the access permissions of the above worlds to the physical address space can be divided and established based on the size of the memory capacity. The mapping relationship between the divided physical address space and the access permissions of each world. In addition, in the mapping relationship shown in Figure 3, the mapping relationship of each world is schematically shown. The physical address space corresponding to the access permission is a regional space. In other possible implementation methods, each of the multiple access permissions shown in Figure 3 can correspond to multiple physical address spaces. The corresponding multiple physical address spaces can be continuous or discontinuous address spaces. For example, assume that in addition to the physical address space shown in Figure 3, the memory 103 is also provided with a physical address space 0x15000~0x15999. This physical address space is only readable by the root world. That is to say, in this example, the physical address space read only by the root world includes two discontinuous physical address spaces: physical address space 0x9000~0x9999 and physical address space 0x15000~0x15999.

In traditional technology, based on the software architecture shown in Figure 2, this software architecture only limits the physical address space that can be read and rewritten by software running in each world. This results in hackers attacking the software running in a certain world to read or rewrite the instructions or data stored in the physical address space corresponding to that world, causing important instructions or data stored in the physical address space to be leaked or rewritten. This leads to security issues of the electronic device 100 . On the basis of defining the physical address space that software running in each world can read and rewrite, the embodiment of the present application further limits the physical address space that software running in each world can only read (cannot rewrite). and a physical address space that software running in each world can only execute (cannot read and rewrite). Therefore, important instructions or data in the electronic device 100 can be stored in the memory 103, and software running in each world can only read. In the physical address space, or important instructions in the electronic device 100 can be stored in the memory 103, in the physical address space that can only be executed by software running in each world, thereby reducing the risk of important instructions or data being stolen or tampered with. , improving the safety of the operation of the electronic device 100 .

Furthermore, this embodiment of the present application may use multiple bits to indicate the above various access rights. That is to say, the mapping relationship between the physical address space and the access permissions of the above-mentioned worlds is the mapping relationship between the physical address space and the bits used to indicate each access permission. For example, twelve access rights are shown above, and the twelve access rights can be represented by 4 bits. The correspondence between access rights and bits is shown in Figure 4. In addition, Figure 4 also shows the mapping relationship between bits and physical address space. Among them, the access rights limited to reading and rewriting by software running in the secure world can be represented by bit "1000"; the access rights limited to reading and rewriting by software running in the normal world can be represented by bit "1001" " represents; the permissions limited to reading and rewriting by software running in the root world can be represented by bit "1010"; the permissions limited to reading and rewriting by software running in the realm world can be represented by bit "1011" " represents; the permission that is limited to reading by software running in the secure world can be represented by bit "0010"; the permission that is limited to reading by software running in the normal world can be represented by bit "0100"; only The permissions that are limited to software running in the root world can be represented by bit "0101"; the permissions that are limited to software running in the realm world can be represented by bits "1010"; the permissions that are limited to software running in the secure world can be represented by bits "1010". The permission to execute software in the world can be represented by bit "1100"; the permission limited to the execution of software running in the normal world can be represented by bit "1101"; the permission limited to the execution of software running in the root world Permissions can be represented by bits "1110"; permissions limited to the execution of software running in the realm world can be represented by bits "0110".

The above describes the physical address space in the memory 103 that is exclusively for one world to access. The memory 103 can also be provided with a physical address space for all worlds to read and write. In addition, the memory 103 may also be provided with a physical address space that is prohibited from being accessed by any world. The physical address space that is read and written by all worlds, and the physical address space that is prohibited from being accessed by any world are different from any of the physical address spaces described above. address space. For example, in Figure 3, the physical address space 0x6000~0x6999 corresponds to any read/write access in any world, that is, the software stored in this physical address space can run in any of the above worlds. Can be read and rewritten; the physical address space is 0x16000~0x16999, and access from any world is prohibited. Among them, the permission for all worlds to read and write can be represented by bit "1111"; the permission to prohibit access from any world can be represented by bit "0000".

In the embodiment of the present application, in addition to the physical address space for access by each world, the memory 103 may also include a physical address space for storing information such as area description information (block descriptor) and page table description information (table descriptor). , the physical address space is not shown in the figure. Among them, the block descriptor can be represented by the bit "0001"; the table descriptor can be represented by the bit "0011".

In the embodiment of the present application, the access of the software running in each world to the physical address space is restricted by the controller 102 based on the physical address to be accessed by the software currently running on the processor 101, the current world where the currently running software is located, and the current running software. The target access rights of the software to the physical address and the mapping relationship between the physical address space and the access rights of each world are realized by executing the detection process. Generally, the workflow of the processor 101 usually includes multiple stages such as fetching instructions from the memory 103, decoding the instructions, and executing the instruction content. Among them, the processor 101 needs to obtain instructions from the memory 103 during the instruction fetching stage. The processor 101 needs to read data from the memory 103 and write the completed data back to the memory 103 during the instruction content execution stage. Therefore, the controller 102 limits the access of software running in the current world to the physical address space, which can be applied to the instruction fetch phase and execution of the processor 101 Stage of instruction content. In specific work, before the software currently running on the processor 101 accesses instructions or data in the memory 103, the processor 101 needs to obtain the logical address VA1 in the memory 103 that the currently running software wants to access, and the target of the logical address VA1. Access rights are provided to controller 102. The target access rights may include one of reading instructions or data, writing data, or executing an instruction program. When the processor 101 provides the logical address VA1 to the controller 102, it may also send the target access permission to the controller 102. Alternatively, the processor 101 may also provide the target access permission to the controller 102 in another indication information independent of the logical address VA1, which is not limited in this embodiment. A more detailed description will be given below through the detection process 500 shown in FIG. 5 . Please refer to FIG. 5. FIG. 5 is a detection process 500 applied to the controller 102. The detection process 500 includes the following processes.

Step 501: The controller 102 receives the logical address VA1 from the processor 101 and the target access permission to the logical address VA1. The target access rights here include one of the following: reading instructions or data in the logical address, writing data to the logical address, or executing the software program stored in the logical address.

Step 502: The controller 102 converts the logical address VA1 into the physical address PA1.

Step 503: The controller 102 detects whether the physical address PA1 is within the preset physical address space corresponding to the current world of the current software. When the controller 102 detects that the physical address PA1 is located in the preset physical address space corresponding to the current world of the current software, step 504 is executed; when the controller 102 detects that the physical address PA1 is located in the preset physical address space corresponding to the current world of the current software. When it is outside the physical address space, perform step 506.

Step 504: The controller 102 detects whether the target access permission is the same as the default access permission for the default physical address space in the current world. When the controller 102 detects that the target access rights are the same as the current world's preset access rights to the preset physical address space, step 505 is executed; when the controller 102 detects that the target access rights are the same as the current world's preset access rights to the preset physical address space. If the access rights are different, perform step 506. Access rights here include one of the following: reading or rewriting software stored in the physical address space, being limited to reading software stored in the physical address space, or being limited to executing software stored in the physical address space.

In this embodiment of the present application, the target access permission is the same as the preset access permission of the current world to the preset physical address space, or it may also mean that the target access permission is within the range of the preset access permission. For example, when the preset access permissions include that the current world can either read the software in the preset physical address space or rewrite the software in the preset physical address space, and the target access permission is to read or rewrite For software in the logical address, it can also be understood that the target access rights are the same as the preset access rights of the current world to the preset physical address space.

Step 505: Allow the processor 102 to access the logical address VA1.

In this embodiment of the present application, allowing the processor 102 to access the logical address VA1 may include a variety of possible implementation methods. In a first possible implementation, the controller 102 can directly provide the physical address PA1 obtained by converting the logical address VA1 to the processor 101, so that the processor 101 accesses the physical address PA1 from the memory 103 to obtain the physical address PA1 from the memory 103. The address PA1 reads instructions, reads data, writes data to the physical address PA1, or executes the program stored in the physical address PA1. In a second possible implementation, the electronic device 100 may also include a direct memory access (DMA) controller. The controller 102 may provide the above physical address PA1 to the DMA controller, so that the DMA controller transfers the memory The instructions or data stored at the physical address PA1 in 103 are moved to the storage area that the processor 101 or other processors 101 want to store, or the data to be stored in the processor 101 or the storage area is moved to the physical address PA1. In a third possible implementation, the controller 102 can provide the physical address PA1 to the processor 101, and the processor 101 forwards the physical address PA1 to the DMA controller, so that the DMA controller transfers the instructions stored at the physical address PA1 in the memory 103. Either the data is moved to the storage area where the processor 101 or other processors 101 want to store it, or the data to be stored in the processor 101 or the storage area is moved to the physical address PA1.

Step 506: Send a signal indicating an error to the processor 101. In this implementation, after the processor 501 receives a signal indicating an error, it may perform a security protection operation. The security protection operation may include but is not limited to: at least one of the following: resetting the processor 101, rejecting the current operation of the processor 101 The software accesses the logical address, stops the processor 101 from running, disables at least some functions in the processor 101 and prevents the processor 101 from accessing the memory 103 . Thus, the security of software operation can be improved.

It can be seen from the detection process 500 shown in Figure 5 that the embodiment of the present application limits the physical address space that the software running in each world can read and rewrite. The software running in each world can only read (cannot The physical address space of the electronic device 100 can only be executed (cannot be read and rewritten), and the physical address space of the software running in each world can only be executed (cannot be read and rewritten). Important instructions or data in the electronic device 100 can be stored in the memory 103, and the software running in each world can In the physical address space that the software can only read, or important instructions in the electronic device 100 can be stored in the memory 103, in the physical address space that the software running in each world can only execute; in addition, the controller 102 is based on the processor 101 In the world you are currently in, determine the processing address PA1 at the default physical address corresponding to the current world of the current software. The physical address PA1 can be provided to the processor 101 only when the target access rights are the same as the current world's default access rights to the default physical address space, thereby preventing hackers from attacking the software running in each world. Rewrite the instructions or data stored in the physical address space of the corresponding world, thereby preventing important instruction programs or data from being leaked or rewritten, thereby improving the security of the operation of the electronic device 100 .

It should be noted that in the embodiment of the present application, the controller 102 and the processor 101 can be connected through electronic circuits. After the electronic device 100 is powered on and the world where the processor 101 is currently located changes, the processor 101 can pass The above-mentioned electronic circuit provides an indication signal to the controller 102 indicating the world in which it is currently located. For example, the indication signal can be 2 bits, "00" indicates normal world, "01" indicates secure world, "10" indicates root world, and "11" indicates realm world. For example, assume that the software running on the processor 101 jumps from the secure world to the root world, and the environment of the software running on the processor 101 changes. At this time, the processor 101 can provide the instruction signal "10" to the control Device 102. Thus, the controller 102 can determine the world in which the software running in the processor 101 is currently located based on the indication signal provided by the processor 101 .

Based on the detection process of the controller 102 shown in Figure 5, combined with the mapping relationship between the physical address space and the access rights of each world shown in Figure 3, through the specific application scenarios shown in Figures 6A to 6C, the controller The working process of 102 is described in more detail. Please continue to refer to FIGS. 6A to 6C . FIGS. 6A to 6C are schematic diagrams of application scenarios of the detection process of the controller 102 .

Application scenario one: The controller 102 can obtain an indication signal in advance through an electronic circuit indicating that the software currently running by the processor 101 is located in the realm world. After receiving the logical address VA2 and the access permission indicating writing data into the logical address VA2 from the processor 101, the controller 102 first converts the logical address VA2 into the physical address PA2. Next, it is determined whether physical address PA2 is within the physical address space corresponding to the current world of the current software. As can be seen from Figure 3, the physical address space corresponding to realm world includes physical address space 0x5000~0x5999, physical address space 0x11000~0x11999, and physical address space 0x15000~0x15999. Assume that the physical address PA2 is 0x11500, that is, the physical address PA2 is located in the range of the physical address space 0x11000 to 0x11999 as shown in Figure 3. That is, the physical address PA2 is located in the physical address space corresponding to the current world of the current software. It can be seen from the mapping relationship between the physical address space and the access rights of each world shown in Figure 3 that the physical address space 0x11000~0x11999 corresponds to the realm world read only, that is, the software in the physical address PA2 is limited to running in Software in the realm world reads, software running in the realm world cannot write to the physical address, and software running in other worlds cannot access the physical address PA2. That is to say, the software currently running in the processor 101 needs to write the data in the physical address PA2, and the physical address PA2 is only read by the software in the realm world and is not allowed to be rewritten, that is, the data sent by the processor 101 The access rights to logical address VA2 are different from the access rights of the queried realm word to the physical address space 0x11000~0x11999. Finally, the controller 102 transmits a signal indicating the error to the processor 101 for the processor 101 to perform security protection processing on the electronic device 100 .

Application scenario two: The controller 102 can obtain an indication signal indicating that the software currently running by the processor 101 is in the normal world through electronic circuits in advance. As can be seen from Figure 3, the physical address space corresponding to normal world includes physical address space 0x3000~0x3999, physical address space 0x8000~0x8999, and physical address space 0x13000~0x13999. Assume that the physical address PA3 is 0x11501, that is, the physical address PA3 is located in the range of the physical address space 0x11000 to 0x11999 as shown in Figure 3. It can be seen from the mapping relationship between the physical address space and the access permissions of each world shown in Figure 3 that the physical address space 0x11000~0x11999 corresponds to the realm world read only. That is to say, the software in physical address PA3 can only be read by software running in realm world, and software running in other worlds cannot access physical address PA3. Thus, the physical address PA3 is outside the preset physical address space corresponding to the current world of the current software. Finally, the controller 102 transmits a signal indicating the error to the processor 101 for the processor 101 to perform security protection processing on the electronic device 100 .

Application scenario three: The controller 102 can obtain an indication signal indicating that the software currently running by the processor 101 is located in the realm world through electronic circuits in advance. After receiving the logical address VA4 and the access permission indicating reading data from the logical address VA4 from the processor 101, the controller 102 first converts the logical address VA4 into the physical address PA4. The physical address space corresponding to realm world includes physical address space 0x5000~0x5999, physical address space 0x11000~0x11999, and physical address space 0x15000~0x15999. Assume that the physical address PA4 is 0x11502, that is, the physical address PA4 is located in the range of the physical address space 0x11000 to 0x11999 as shown in Figure 3. That is, the physical address PA2 is located in the physical address space corresponding to the current world of the current software. It can be seen from the mapping relationship between the physical address space and the access permissions of each world shown in Figure 3 that the physical address space 0x11000~0x11999 corresponds to the realm world read only. That is to say, the software in the physical address PA4 can only be read by the software running in the realm world. The software running in the realm world cannot write to the physical address. Software running in other worlds cannot access the physical address PA4. The software currently running in the processor 101 needs to read data from the logical address VA4, and the physical address PA4 is also limited to software reading in the realm world. That is, the access permission to the logical address VA4 sent by the processor 101 is the same as the access permission of the queried realm word to the physical address space 0x11000~0x11999. Finally, the controller 102 provides the physical address PA4 to the processor 101 so that the software currently running on the processor 101 reads data from the physical address PA4.

Based on the detection process of the controller 102 shown in Figure 5, the controller 102 can convert the logical address provided by the processor 101 into a physical address through multi-level translation and detection. In a possible implementation, the controller 102 can convert the logical address provided by the processor 101 into a physical address through two-level conversion. Specifically, the controller 102 can respectively query the first page table at least once, convert the logical address into at least one level of intermediate addresses, and detect whether each level of the at least one level of intermediate addresses is allowed to be accessed; in addition, the controller 102 may query the second page table at least once to detect whether at least one level of intermediate address is allowed to be accessed. When it is detected that each level of intermediate addresses in at least one level of intermediate addresses is allowed to be accessed, the last level of intermediate addresses in at least one level of intermediate addresses is converted into a physical address; wherein, at least one level of intermediate addresses is recorded in the first page table. The intermediate address, and the access rights of each of the multiple worlds to the at least one-level intermediate address; the table on the second page records the access rights of each of the multiple worlds to the at least one-level intermediate address. That is to say, the controller 102 can translate and detect the logical address by querying the first page table, and convert the logical address into the above-mentioned intermediate address. It should be noted that the above-mentioned intermediate addresses are all physical addresses, and the converted Perform permission check on at least one level of intermediate address; perform permission check on at least one level of intermediate address by querying the table on the second page. It should be noted that the various levels of conversion set in the controller 102 may be set in the controller 102 through firmware in advance and cannot be changed after the controller 102 is powered on or during operation. The above-mentioned first page table can be stored in the exception level EL1 shown in Figure 2, and the first page table can also be called (stage1table); the above-mentioned second page table is stored in the physical address corresponding to the exception level EL3 shown in Figure 2 In space, the second page table can also be called (stage3table).

It should be noted that in some other possible implementations, the logical address can be converted into a physical address through three-level conversion. For example, the controller 102 can translate and detect the logical address by querying the first page table, and convert the logical address into a physical address. The address is converted into a first intermediate address, and permission detection is performed on the first intermediate address. The first intermediate address is usually a logical address; then, the controller 102 can convert the first intermediate address into a third intermediate address by querying the second page table. two intermediate addresses, and perform permission detection on the second intermediate address, which is usually a physical address; finally, the controller 102 can perform multi-level permissions on the converted second intermediate address by querying the third page table examine.

In the embodiment of this application, the controller 102 can convert the logical address provided by the processor 101 into a physical address through two-level translation and detection as an example. Through the example shown in Figure 7, the controller 102 can convert the logical address into a physical address. The conversion method is described in more detail. As shown in FIG. 7 , the processor 101 provides the logical address VA1 to the controller 102 , assuming that the software currently running by the processor 101 is at level EL0 as shown in FIG. 2 . The controller 102 queries the first page table multiple times for translation and detection, and queries the second page table multiple times for detection to output the physical address PA1. In Figure 7, horizontally, translation and detection are performed by querying the table on the first page, and vertically, detection is performed by querying the table on the second page. Specifically, the controller 102 executes the first-stage page table query of the first stage based on the logical address VA1.

The first page table query in the first stage: Based on the logical address VA, after querying the first-level page table, the physical address PAlv1 of LV1 stored in the LV0 page table is found, and the physical address is detected at the same time to determine the processor 101 Whether the requested physical address access is allowed. When the access is not allowed, the controller 102 may transmit a message indicating an error to the processor 101; when the access is allowed, the controller 102 performs the second level of the first phase as follows Page table query.

The second page table query in the first stage: Based on the physical address PAlv1 of LV1, the controller 102 queries the LV0 page table entry to find out the detection content recorded in LV0 to detect whether the access to the physical address PAlv1 is allowed. When the access is not allowed, When allowed, the controller 102 can transmit a signal indicating an error to the processor 101; when the access is allowed, the controller 102 continues to query the detection content recorded in LV1 to detect whether the access to the physical address PAlv1 is allowed. When the access is not allowed, When allowed, the controller 102 may transmit a signal indicating an error to the processor 101; when the access is allowed, the controller 102 performs a second-stage first-level page table lookup as follows.

The first page table query in the second stage: the controller 102 finds the physical address PAlv2 of LV2 recorded in the LV1 page table through the physical address PAlv1, and simultaneously detects the physical address to determine whether the physical address access requested by the processor 101 is is allowed, when the access is not allowed, the controller 102 may transmit a signal indicating an error to the processor 101; when the access is allowed, the controller 102 performs the following second-stage second-level page table lookup.

Second page table query in the second stage: Based on the physical address PAlv2 of LV1, the controller 102 queries the detection content in LV0 to detect whether access to the physical address PAlv2 is allowed. When the access is not allowed, the controller 102 can The processor 101 transmits a message indicating an error; when the access is allowed, the controller 102 continues to query the detection content recorded in LV1 to detect whether the access to the physical address PAlv2 is allowed. When the access is not allowed, the controller 102 can The processor 101 transmits a message indicating the error; when the access is allowed, the controller 102 looks up the physical address PAlv3 of LV3 stored in the LV2 page table through the physical address PAlv2, and at the same time Check the physical address.

It should be noted that based on the detection method of the first page table query and the second page table query similar to the above, the controller 102 performs the horizontal third page table query and the second page table query through multiple times of the first page table query and the second page table query. Translation and detection of one-page table, and detection of vertical second-page table. When the translation and detection of the first page table and the detection of the vertical second page table are completed, and the detection at each stage indicates that access is allowed, the controller 102 generates the physical address PA1 corresponding to the logical address VA1, that is, it is completed. Conversion from logical address to physical address.

The above describes the process of the controller 102 converting the logical address VA1 into the physical address PA1 through the two-level translation and detection of the first page table and the second page table through FIG. 7 . Therefore, on the basis of the detection process 500 shown in FIG. 5 , the detection process applied to the controller 102 further refines the above step 501 to obtain the detection process 800 shown in FIG. 8 . The detection process 800 shown in Figure 8 includes the following steps:

Step 801: Based on the logical address VA1 obtained from the processor 101 and the access method to the logical address VA1, the logical address VA1 is converted into at least one level of intermediate address by querying the first page table stored in the exception level EL1 at least once.

Step 802: Based on the first page table, detect whether at least one level of intermediate address is allowed to be accessed; when it is detected that at least one level of intermediate address is allowed to be accessed, step 803 is executed; when it is detected that there is a level one intermediate address that is not allowed to be accessed, Execute step 809.

Step 803: Query the second page table stored in the exception level EL3 to detect whether at least one level of intermediate address is allowed to be accessed; when it is detected that at least one level of intermediate address is allowed to be accessed, step 804 is executed. When the intermediate address is not allowed to be accessed, step 809 is executed.

Step 804: Convert the last level intermediate address among at least one level of intermediate addresses into the physical address PA1, and detect whether the physical address PA1 is allowed to be accessed. When it is detected that the physical address PA1 is allowed to be accessed, step 805 is executed; when it is detected that the physical address PA1 is allowed to be accessed, step 804 is performed. When access to address PA1 is not allowed, step 809 is executed.

Step 805: Query the second page table to detect whether the physical address PA1 is allowed to be accessed. When it is detected that the physical address PA1 is allowed to be accessed, step 806 is executed. When it is detected that the physical address PA1 is not allowed to be accessed, step 809 is executed.

Step 806: Check whether the physical address PA1 is within the preset physical address space corresponding to the current world of the current software. When the controller 102 detects that the physical address PA1 is located in the preset physical address space corresponding to the current world of the current software, step 807 is executed; when the controller 102 detects that the physical address PA1 is located in the preset physical address space corresponding to the current world of the current software. When it is outside the physical address space, perform step 809.

Step 807: When it is detected that the target access rights are the same as the current world's default access rights to the default physical address space, step 808 is executed; when the controller 102 detects that the target access rights are the same as the current world's default access rights to the default physical address space. When the permissions are different, perform step 809.

Step 808: Allow the processor 102 to access the logical address VA1.

Step 809: Send a signal indicating an error to the processor 101.

It should be noted that the above steps 806 to 809 are the same as steps 502 to 506 in the detection process 500 shown in FIG. 5 and will not be described again. In addition, for the specific detection method of the above-mentioned steps 801 to 805, refer to the relevant description of FIG. 7 and will not be described again.

In traditional technology, the controller 102 converts a logical address into a physical address, which usually requires two-level address translation and detection. That is to say, after obtaining the logical address, the controller 102 first queries the third address set in the exception level EL1. The first-level page table translates and detects the logical address, and converts the logical address into an intermediate logical address; then, the controller 102 translates and detects the intermediate logical address by querying the second-level page table set in the exception level EL2. , convert the intermediate logical address into a physical address. As can be seen from the examples shown in Figures 7 and 8 above, in the embodiment of the present application, the controller 102 translates and detects the logical address by querying the first page table, and converts the logical address into an intermediate address. The intermediate address The address is a physical address; by querying the second page table, permissions are checked on the converted intermediate address. That is, compared with the method of converting a logical address to a physical address shown in the prior art, it is omitted to convert the logical address into an intermediate address. The logical address conversion step is to replace the second-level page table set at the exception level EL2 in the traditional technology for physical address detection with the second-level page table set at the exception level EL3 for intermediate-level physical address detection. The page table can thus simplify the steps of converting logical addresses into physical addresses and effectively protect the electronic device 100 .

In this embodiment, the electronic device 100 may further include a communication unit (not shown in the figure). The communication unit includes, but is not limited to, a short-range communication unit or a cellular communication unit. Among them, the short-range communication unit performs information interaction with other devices located outside the mobile terminal for accessing the Internet by running a short-range wireless communication protocol. The short-range wireless communication protocol may include but is not limited to: various protocols supported by radio frequency identification technology, Bluetooth communication technology protocols, or infrared communication protocols, etc. The cellular communication unit operates the cellular wireless The wired communication protocol is connected to the wireless access network to realize information interaction between the mobile communication unit and the servers in the Internet that support various applications. The communication unit can be integrated in the same SOC with the processor 101 and controller 102 described in the embodiment of this application, or can be set up separately. In addition, the electronic device 100 may optionally include a bus or an interface circuit, and the interface circuit may be, for example, an input/output port I/O, or the like. Among them, the bus and interface circuit can be integrated with the above-mentioned processor 101 and controller 102 in the same SOC. Interface circuitry is used to couple the controller 102 with the memory 103 . It should be understood that in actual applications, the electronic device 100 may include more or fewer components than shown in FIG. 1 , which is not limited by the embodiments of this application.

Based on the same inventive concept, embodiments of the present application also provide a method for securely accessing software. The method for securely accessing software is applied to the electronic device 100 as shown in FIG. 1 . Please continue to refer to FIG. 9 , which shows a process 900 of a method for securely accessing software provided by an embodiment of the present application. The process 900 of the method for securely accessing software can be executed by the controller 102 and includes the following steps: Step 901, based on the logical address to be accessed by the current software, convert the logical address into a physical address in the memory; Step 902 , when the physical address is in the preset physical address space corresponding to the current world of the current software, and the target access permission of the current software to the logical address is consistent with the current world's access to the preset physical address. When the preset access permissions of the spaces are the same, the current software is allowed to access the logical address; wherein, the software running environment of the electronic device has multiple worlds, and each world in the multiple worlds corresponds to at least two The physical address space and the at least two physical address spaces correspond to different access rights respectively, and the current world is one of the plurality of worlds; the access rights include one of the following: reading or rewriting the physical address space Software stored in the physical address space is limited to reading software stored in the physical address space, and is limited to executing software stored in the physical address space.

In a possible implementation, the method 900 further includes: when the physical address is outside the preset physical address space corresponding to the current world of the current software, and the target access permission is consistent with the When at least one of the two preset access rights is different, security protection operations are performed.

In a possible implementation, the method 900 further includes: determining the preset physical address space and the preset access permission corresponding to the current world according to a pre-stored mapping relationship; wherein the mapping The relationship is used to indicate the at least two physical address spaces of each world in the plurality of worlds and different access rights to the at least two physical address spaces; the mapping relationship is stored in the memory.

In a possible implementation, converting the logical address into a physical address in the memory includes: querying the first page table at least once and the second page table at least once based on the logical address; The first page table is used to convert the logical address into at least one level of intermediate addresses; when each level of the at least one level of intermediate addresses is allowed to be accessed, the last one of the at least one level of intermediate addresses is The first-level intermediate address is converted into the physical address; wherein the at least one-level intermediate address and the at least one-level intermediate address of each world in the plurality of worlds are recorded in the first page table. Access rights; the second page table records the access rights of the at least one-level intermediate address.

In a possible implementation, the method 900 further includes: performing a security protection operation when there is a first-level intermediate address that is not allowed to be accessed.

It can be understood that, in order to implement the above functions, the controller 102 includes hardware and/or software modules corresponding to each function. In conjunction with the steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software driving the hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions in conjunction with the embodiments for each specific application, but such implementations should not be considered to be beyond the scope of this application.

In this embodiment, the controller 102 can be divided into functional modules according to the above method examples. For example, different functional modules can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. In actual implementation, there may be other division methods.

In the case of dividing each functional module corresponding to each function, Figure 10 shows a possible schematic diagram of the device 1000 involved in the above embodiment. The previously mentioned device can be further expanded. For example, the device corresponding to Figure 10 Device 1000 may be a software device running on controller 102, or device 1000 may be a combination of software and hardware device embedded in controller 102. As shown in Figure 10, the device 1000 may include: a conversion module 1001, configured to based on the logical address to be accessed by the current software, Convert the logical address into a physical address in the memory; allow access module 1002 for when the physical address is within the preset physical address space corresponding to the current world of the current software and the current software has When the target access permission of the logical address is the same as the preset access permission of the current world to the preset physical address space, the current software is allowed to access the logical address; wherein, the software running environment of the electronic device has Multiple worlds, each world in the multiple worlds respectively corresponds to at least two physical address spaces, and the at least two physical address spaces respectively correspond to different access rights, and the current world is the multiple worlds. One; the access rights include one of the following: reading or rewriting software stored in the physical address space, limited to reading software stored in the physical address space, limited to executing software stored in the physical address space.

In a possible implementation, the device 1000 further includes: a first security protection module (not shown in the figure), configured to detect when the physical address is in a preset state corresponding to the current world of the current software. When at least one of outside the physical address space and the target access permission is different from the preset access permission, a security protection operation is performed.

In a possible implementation, the device further includes: a determining module (not shown in the figure), configured to determine the preset physical address space corresponding to the current world and the preset physical address space corresponding to the current world according to a pre-stored mapping relationship. The preset access rights; wherein the mapping relationship is used to indicate the at least two physical address spaces of each world in the plurality of worlds and the different access rights to the at least two physical address spaces; the The mapping relationship is stored in the memory.

In a possible implementation, the conversion module 1001 is specifically configured to: based on the logical address, respectively query at least one preset first page table and at least one preset second page table; According to the first page table, the logical address is converted into at least one level of intermediate addresses; according to the first page table and the second page table, when each level of intermediate addresses in the at least one level of intermediate addresses is allowed During access, the last level intermediate address among the at least one level intermediate addresses is converted into the physical address; wherein the at least one level intermediate address and the at least one level intermediate address in the plurality of worlds are recorded in the first page table. The access rights of each world to the at least one-level intermediate address; the second page table records the access rights of each world in the plurality of worlds to the at least one-level intermediate address.

In a possible implementation, the device 1000 further includes: a second security protection module (not shown in the figure), configured to perform a security protection operation when there is at least one level of intermediate address that is not allowed to be accessed.

The device 1000 provided in this embodiment is used to execute the secure access software method executed by the controller 102, and can achieve the same effect as the above implementation method or device. Specifically, each module corresponding to the above figure 10 may include software, hardware, or a combination of both. For example, each module can be implemented in the form of software and used to drive the controller 102 to work. Alternatively, each module may include a corresponding processor and corresponding driver software, that is, implemented in combination with software or hardware.

Exemplarily, the above controller 102 may also include at least one processor and memory. Among them, at least one processor can call all or part of the computer program stored in the memory to control and manage the actions of the controller 102. For example, it can be used to support the controller 102 in executing the steps performed by each of the above modules. The memory can be used to support the controller 102 to execute and store program codes and data, and the memory includes but is not limited to at least a part of the storage space, cache (Cache) or registers of the memory 103 mentioned above. At least one processor may implement or execute the various exemplary plurality of logic modules described in conjunction with the present disclosure, which may be a combination of one or more microprocessors that implement computing functions. In addition, at least one processor may also include other programmable logic devices, transistor logic devices, or discrete hardware components.

This embodiment also provides a computer-readable storage medium. Computer instructions are stored in the computer-readable storage medium. When the computer instructions are run on a computer, they cause the computer to execute the above related method steps to implement the steps used in the above embodiments. A secure way to access software.

This embodiment also provides a computer program product. When the computer program product is run on a computer, it causes the computer to perform the above related steps to implement the method for securely accessing software in the above embodiment.

Among them, the computer-readable storage medium or computer program product provided by this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects it can achieve can be referred to the corresponding method provided above. The beneficial effects will not be repeated here.

Through the description of the above embodiments, those skilled in the art can understand that for the convenience and simplicity of description, only the division of the above functional modules is used as an example. In practical applications, the above functions can be allocated to different modules according to needs. The functional module is completed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

In addition, each functional unit in each embodiment of the present application can be integrated into one product, or each unit can be physically separated. exist, or two or more units can be integrated into one product. Corresponding to Figure 9, if the above modules are implemented in the form of software functional units and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application are essentially or contribute to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium , including several instructions to cause a device (which can be a microcontroller, a chip, etc.) or a processor to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned readable storage media include: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc. that can store program code. medium.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present application. scope.

Claims

An electronic device, characterized by including a processor and a controller;

The processor is configured to run the current software and send the logical address to be accessed by the current software and the target access permission of the current software to the logical address to the controller;

The controller is used for:

receiving said logical address and said target access rights from said processor;

Convert the logical address into a physical address in memory;

When the physical address is within the preset physical address space corresponding to the current world of the current software, and the target access permission is the same as the preset access permission of the current world to the preset physical address space, allowing the processor to access the logical address;

Wherein, the software running environment of the electronic device has multiple worlds, each world in the multiple worlds respectively corresponds to at least two physical address spaces, and the at least two physical address spaces respectively correspond to different access rights, The current world is one of the plurality of worlds;

The access rights include one of the following: reading or rewriting software stored in the physical address space, being limited to reading software stored in the physical address space, or being limited to executing software stored in the physical address space.
The electronic device according to claim 1, characterized in that the controller is also used for:

When at least one of the following: the physical address is outside the preset physical address space and the target access permission is different from the preset access permission, a signal indicating an error is sent to the processor. .
The electronic device according to claim 2, wherein the processor is further configured to:

Based on the signal indicating an error, a security protection operation is performed, the security protection operation includes at least one of the following: resetting the processor, denying access to the logical address by software currently running on the processor, instructing the processor Stopping operation, disabling at least part of the functionality of the processor, and preventing the processor from accessing the memory.
The electronic device according to any one of claims 1-3, wherein the electronic device further includes the memory;

The memory is further configured to: store a mapping relationship between the at least two physical address spaces of each world in the plurality of worlds and different access rights to the at least two physical address spaces;

The controller is further configured to determine the preset physical address space and the preset access permission corresponding to the current world according to the mapping relationship.
The electronic device according to claim 4, characterized in that the controller converts the logical address into a physical address in the memory, specifically for:

Based on the logical address, query the preset first page table and the preset second page table at least once respectively;

Convert the logical address into at least one level of intermediate address according to the first page table;

According to the first page table and the second page table, when each level of intermediate addresses in the at least one level of intermediate addresses is allowed to access, the last level of intermediate addresses in the at least one level of intermediate addresses is Convert to the physical address;

The first page table records the at least one level intermediate address and the access rights of each world in the plurality of worlds to the at least one level intermediate address; the second page table records Each of the plurality of worlds has access to the at least one level of intermediate address.
The electronic device according to claim 5, wherein the controller is further used for:

When there is at least one level of intermediate address that is not allowed to be accessed, a signal indicating an error is transmitted to the processor.
The electronic device according to claim 5 or 6, characterized in that:

The electronic device includes multiple exception levels, each exception level corresponds to a section of physical address space in the memory, and software running at a low exception level is prohibited from accessing the physical address space corresponding to a high exception level, wherein, the The mapping relationship is stored in the physical address space corresponding to the highest exception level among the plurality of exception levels.
The electronic device according to claim 7, wherein the first page table is stored in a physical address space corresponding to a first abnormality level among the plurality of abnormality levels, and the first abnormality level is lower than the first abnormality level. The exception level of the highest exception level mentioned above;

The second page table is stored in the physical address space corresponding to the highest exception level.
The electronic device according to claim 1, characterized in that the electronic device further includes a direct memory access controller; the allowing the processor to access the logical address is specifically used to: provide the physical address with Give the direct memory access control device;

The direct memory access controller is configured to provide instructions or data in the physical address to the processor.
A method for securely accessing software, which is characterized by including:

Based on the logical address to be accessed by the current software, convert the logical address into a physical address in the memory;

When the physical address is within the preset physical address space corresponding to the current world of the current software, and the target access permission of the current software to the logical address is consistent with the current world's access to the preset physical address space When the preset access rights are the same, the current software is allowed to access the logical address;

Wherein, the software running environment of the electronic device has multiple worlds, each world in the multiple worlds respectively corresponds to at least two physical address spaces, and the at least two physical address spaces respectively correspond to different access rights. , the current world is one of the multiple worlds;

The access rights include one of the following: reading or rewriting software stored in the physical address space, being limited to reading software stored in the physical address space, or being limited to executing software stored in the physical address space.
The method of claim 10, further comprising:

When at least one of the following: the physical address is outside the preset physical address space and the target access permission is different from the preset access permission, a security protection operation is performed.
The method according to claim 10 or 11, characterized in that the method further includes:

Determine the preset physical address space and the preset access permission corresponding to the current world according to the pre-stored mapping relationship;

Wherein, the mapping relationship is used to indicate the at least two physical address spaces of each world in the plurality of worlds and different access rights to the at least two physical address spaces;

The mapping relationship is stored in the memory.
The method according to any one of claims 10-12, characterized in that converting the logical address into a physical address in the memory specifically includes:

Based on the logical address, query the preset first page table and the preset second page table at least once respectively;

Convert the logical address into at least one level of intermediate address according to the first page table;

According to the first page table and the second page table, when each level of intermediate addresses in the at least one level of intermediate addresses is allowed to access, the last level of intermediate addresses in the at least one level of intermediate addresses is Convert to the physical address;

The first page table records the at least one level intermediate address and the access rights of each world in the plurality of worlds to the at least one level intermediate address; the second page table records Each of the plurality of worlds has access to the at least one level of intermediate address.
The method of claim 13, further comprising:

When there is at least one level of intermediate address that is not allowed to be accessed, security protection operations are performed.
The method according to any one of claims 10 to 14, characterized in that the security protection operation includes at least one of the following: resetting the processor, denying access to logical addresses by software currently running on the processor, indicating that all The processor ceases operation, disables at least part of the functionality of the processor, and prevents the processor from accessing the memory.
A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and the computer program is used to implement the method according to any one of claims 10-15 when executed by the controller.
A computer program product, characterized in that when the computer program product is executed by a controller, it is used to implement the method according to any one of claims 10-15.
A system-level chip is characterized by including:

controller and interface circuits;

The interface circuit is used to couple a memory, and an instruction program is stored in the memory;

The controller is configured to execute program instructions in the memory to implement the method of any one of claims 10-15.