WO2024025601A1

WO2024025601A1 - Static clock identification for functional simulation

Info

Publication number: WO2024025601A1
Application number: PCT/US2022/074311
Authority: WO
Inventors: Du Nguyen; George Scott; Ratul BANERJEE
Original assignee: Siemens Industry Software Inc.
Priority date: 2022-07-29
Filing date: 2022-07-29
Publication date: 2024-02-01

Abstract

This application discloses a design verification system (310) to extract timing information associated with a library design cell file and statically analyse the extracted timing information to identify at least one clock signal (500) by identifying one or more candidate clock signals in the extracted timing information and traversing timing checks in the extracted timing information for each of the candidate clock signals to determine at least one of the candidate clock signals corresponds to a clock signal. The design verification system can correlate circuitry described in the library design cell file to a portion of a circuit design describing an electronic system and modify a compiled version of the circuit design (314) based on the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design. The design verification system can simulate the electronic system using the modified version of the compiled circuit design (316).

Description

STATIC CLOCK IDENTIFICATION FOR FUNCTIONAL SIMULATION

TECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, more specifically, to static clock identification for functional simulation.

BACKGROUND

[0002] Designing and fabricating electronic systems typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of electronic system to be manufactured, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system from a design. Initially, a specification for a new electronic system can be transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic system. With this logical design, the electronic system can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as System Verilog or Very high speed integrated circuit Hardware Design Language (VHDL).

[0003] The logic of the electronic system can be analyzed to confirm that it will accurately perform the functions desired for the electronic system, sometimes referred to as “functional verification.” Design verification tools can perform functional verification operations, such as simulating, emulating, and/or prototyping the logical design. For example, when a design verification tool simulates the logical design, the design verification tool can provide transactions or sets of test vectors, for example, generated by a simulated test bench, to the simulated logical design. The design verification tools can determine how the simulated logical design responded to the transactions or test vectors, and verify, from that response, that the logical design describes circuitry to accurately perform functions.

[0004] As the logical designs increase in size and verification runtime becomes longer, functional verification speed-up can be obtained by either making design verification tool faster or by writing logical design more efficiently. One common technique to speed-up simulator operation involves optimizing a compiled version of the logical design to eliminate or suppress unnecessary simulation. Many of the optimizations of the compiled version of the logical design, however, depend on an accurate identification of clock signals in the logical design. Most design verification tools rely on user input as the identification of the clock signals in the logical design. Incorrect prediction of the clock signals, for example, due to errors in the user input, can lead to incorrect grouping or erroneous suppression of circuit elements during simulation, impacting the ability of designers to evaluate the functionality of the logical design. Due to the costs associated with manual error in the user input, some design verification tools can perform dynamic clock detection during simulation. While the dynamic clock detection often can identify the clock signals of the logical design, the ability to modify the compiled code to increase simulation speed can be limited after the simulation of the logical design has already been initiated.

SUMMARY [0005] This application discloses a computing system implementing a design verification system to extract timing information associated with a library design cell file describing circuitry and statically analyze the extracted timing information to identify at least one clock signal for the circuitry by identifying one or more candidate clock signals in the extracted timing information, traversing timing checks in the extracted timing information for each of the candidate clock signals, and determining at least one of the candidate clock signals corresponds to a clock signal of the library design cell file based on the traversal of the timing checks in the extracted timing information. The design verification system can correlate the circuitry described in the library design cell file to a portion of a circuit design describing an electronic system and modify a compiled version of the circuit design based on the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design. The design verification system can include a simulator to simulate the electronic system using the modified version of the compiled circuit design. Embodiments will be described in greater detail below.

DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments.

[0007] Figure 3 illustrates an example design verification system having static clock identification that may be implemented according to various embodiments. [0008] Figure 4 illustrates an example flowchart of electronic system simulation with static clock identification in a circuit design describing the electronic system, which may be implemented according to various embodiments.

[0009] Figure 5 illustrates an example static clock identification system to implement identify clock signals in a circuit design, which may be implemented according to various embodiments.

[0010] Figure 6 illustrates an example flowchart for static clock identification in a circuit design describing an electronic system, which may be implemented according to various embodiments.

DETAILED DESCRIPTION

Illustrative Operating Environment

[0011] Various embodiments may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105. [0012] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 117-123. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and/or removable, a removable optical disk drive 119, and/or a flash memory card. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 117-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 117-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0013] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0014] It should be appreciated that the computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both.

[0015] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and/or instructions for execution.

[0016] Each processor core 201A and 201B is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 20 IB, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input/output interface 209 and a memory controller 210. The input/output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 20 IB. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.

Static Clock Identification for Functional Simulation

[0017] Figure 3 illustrates an example design verification system 310 having static clock identification that may be implemented according to various embodiments. Figure 4 illustrates an example flowchart of electronic system simulation with static clock identification in a circuit design describing the electronic system, which may be implemented according to various embodiments. Referring to Figures 3 and 4, the design verification system 310, for example, implemented with a computer network 101 described above with reference to Figure 1, can perform functional verification on a circuit design 301 describing an electronic device. In some embodiments, the circuit design 301 can describe the electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device. The circuit design 301 can model the electronic device at a register transfer level (RTL), for example, with code in a hardware description language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like.

[0018] The design verification system 310 can receive a test bench 302 to utilize to generate test stimulus during functional verification operations, such as clock signals, activation signals, power signals, control signals, data signals or the like. The test stimulus, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 being functionally verified by the design verification system 310. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design. A methodology library, for example, a Universal Verification Methodology (UVM) library, an Open Verification Methodology (OVM) library, an Advanced Verification Methodology (AVM) library, a Verification Methodology Manual (VMM) library, or the like, can be utilized as a base for creating the test bench 302.

[0019] The design verification system 310, in a block 401 of Figure 4, can receive library cell information, such as a library cell design file 303 and/or cell delay information 304. The library cell design file 303, such as one or more application-specific integrated circuit (ASIC) standard cell designs in a vendor library file, can model integrated circuitry at a register transfer level (RTL) and include timing information, for example, in a specify block coded in System Verilog hardware description language. The specify block can include timing checks for the integrated circuitry, can define pin-to-pin or path delays across the integrated circuitry, and define special timing parameters for the integrated circuitry. The cell delay information 304, for example, in a Standard Delay Format (SDF) file, can be generated from the library cell design file 303, for example, performing parasitic extraction on the library cell design file 303 and determining path delays and timing checks associated with the integrated circuitry based on the parasitic network generated during the parasitic extraction.

[0020] The design verification system 310 can include a static clock identification system 500 to identify clock signals in the circuit design 301 based on at least one of the library cell design file 303 or the cell delay information 304, and to generate clock information 311 corresponding to the identified clock signals. The static clock identification system 500 also can characterize the identified clock signals using at least one of the library cell design file 3030 or the cell delay information 304, and include the characteristics of the identified clock signals in the clock information 311. [0021] The static clock identification system 500, in a block 402 of Figure 4, can extract timing information from at least one of the library cell design file 303 or the cell delay information 304. For example, the static clock identification system 500 can extract timing information from the specify block of the library cell design file 303, which can include signal parameters, path delays, and/or timing checks for the integrated circuitry described in the library cell design file 303. The static clock identification system 500 can extract path delays and/or timing checks for the integrated circuitry described in the library cell design file 303 from the cell delay information 304.

[0022] The static clock identification system 500, in a block 403 of Figure 4, can analyze the extracted timing information to identify one or more clock signals for the integrated circuitry of the library cell design file 303. In some embodiments, the static clock identification system 500 can identify candidate clock signals in the timing information and traverse the timing checks within the extracted timing information to determine whether the candidate clock signals correspond to data signals and/or control signals. When one of the candidate clock signals does not correspond to data signals and/or control signals in the timing checks, the static clock identification system 500 can identify the candidate clock signal as a clock signal for the library cell design file 303. Embodiments of the clock signal identification will be described below in greater detail with reference to Figures 5 and 6.

[0023] The design verification system 310 can include a compiler 312 that, in a block 404 of Figure 4, can compile the circuit design 301 into machine-readable code for execution during functional verification of the circuit design 301. The design verification system 310 can include an optimization engine 314 that, in a block 405 of Figure 4, can correlate the identified clock signal of the library cell design file 303 to signals in the circuit design 301.

In some embodiments, the optimization engine 314 can correlate the integrated circuitry of the library cell design file 303 to a portion of the circuit design 301 and then utilize that correlation to determine at least one signal in the circuit design 301 corresponds to the identified clock signal in the library cell design file 303.

[0024] The optimization engine 314, in a block 406 of Figure 4, can modify the compiled version of the circuit design 301 based, at least in part, on the clock information 311 identified by the static clock identification system 500. In some embodiments, the optimization engine 314 can utilize the clock information 311 to modify the compiled version of the circuit design 301 by grouping the processing of circuitry associated with a common clock tree of the identified clock signal, suppressing simulation of certain events, detect racing conditions, or the like. For example, when the clock information 311 indicates circuitry in the circuit design 301 activates on a rising edge of an identified clock signal, the optimization engine 314 can modify the compiled version of the circuit design 301 to eliminate or suppress simulation of circuitry on the falling edge of the identified clock signal. Since the static clock identification system 500 can identify clock signals in the circuit design 301 prior to simulating the circuit design 301 and without relying on manual input, the design verification system 310 can speed up overall simulation throughput for the circuit design 301 and reduce the presence of human error in the clock identification.

[0025] The design verification system 310 can include a simulator 316 that, in a block 407 of Figure 4, can perform functional verification operations with one or more processors configured to simulate the circuit design 301, for example, by executing the modified complied version of the circuit design 301 from the optimization engine 314. The simulator 316 can utilize the test bench 302 to generate test stimulus during functional verification operations, such as clock signals, activation signals, power signals, control signals, data signals or the like. The test stimulus, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 being functionally verified by the design verification system 310. The simulator 316 can generate simulation results 316 corresponding to the operations of the circuit design 301 in response to the test stimulus during the functional verification operations, which can be compared to expected output of the circuit design 301.

[0026] Figure 5 illustrates an example static clock identification system 500 to implement identify clock signals in a circuit design, which may be implemented according to various embodiments. Figure 6 illustrates an example flowchart for static clock identification in a circuit design describing an electronic system, which may be implemented according to various embodiments. Referring to Figures 5 and 6, the static clock identification system 500 can receive library cell design file 501, such as one or more applicationspecific integrated circuit (ASIC) standard cell designs in a vendor library file, which can model integrated circuitry at a register transfer level (RTL) and include timing information, for example, in a specify block coded in System Verilog hardware description language. The specify block can include timing checks for the integrated circuitry, can define pin-to-pin or path delays across the integrated circuitry, and define special timing parameters for the integrated circuitry. [0027] The static clock identification system 500 can receive cell delay information 502, for example, in a Standard Delay Format (SDF) file. In some embodiments, the cell delay information 502 can be generated from the library cell design file 501, for example, performing parasitic extraction on the library cell design file 501 and determining path delays and timing checks associated with the integrated circuitry based on the parasitic network generated during the parasitic extraction.

[0028] The static clock identification system 500 can include a timing extraction system 510 that, in a block 601 of Figure 6, can extract timing information from the library cell design file 401 or the cell delay information 402. For example, the static clock identification system 500 can extract timing information from the specify block of the library cell design file 401, which can include signal parameters, path delays, and/or timing checks for the integrated circuitry described in the library cell design file 401. The static clock identification system 500 can extract path delays and/or timing checks for the integrated circuitry described in the library cell design file 401 from the cell delay information 402.

[0029] The static clock identification system 500 can include a candidate identification system 520 that, in a block 602 of Figure 6, can identify one or more candidate clock signals in the extracted timing information. In some embodiments, the candidate identification system 520 can locate signals in timing checks in the extracted timing information that correspond to reference events acting as timing triggers for the timing checks and identify those located signals as the candidate clock signals.

[0030] The static clock identification system 500 can include a timing check traversal system 530 that, in a block 603 of Figure 6, can traverse timing checks in the extracted timing information for one of the identified candidate clock signals. In some embodiments, the timing check traversal system 530 can analyze a subset System Verilog timing checks, such as a $hold timing check, a $nochange timing check, a $setuphold timing check, a S roc rem timing check, or the like, to determine whether each of the identified candidate clock signals corresponds to a data signal for a data event or a control signal for a control event in any of the System Verilog timing checks.

[0031] The static clock identification system 500, in a block 604 of Figure 6, can determine whether a candidate signal corresponds to a non-clock signal, such as a data signal or a control signal in the timing checks based on the traversal of the timing checked in the extracted timing information. When the static clock identification system 500 determines the candidate signal corresponds to a non-clock signal, execution can return to the block 603 of Figure 6, where the timing check traversal system 530 can traverse timing checks in the extracted timing information for another one of the identified candidate signals.

[0032] When the static clock identification system 500 determines the candidate signal is not a non-clock signal, execution can proceed to a block 605 in Figure 6, where the static clock identification system 500 can identify the candidate signal as a clock signal. The static clock identification system 500 can include a clock characterization system 540 that, in a block 606 of Figure 6, can characterize the identified clock signal with properties based on the extracted timing information. In some embodiments, the clock characterization system 540 can determine a sensitivity property of the identified clock signal, such as the positive voltage level and the negative voltage level associated with triggering clockswitching in the integrated circuitry of the library cell design file 501. The clock characterization system 540 also can determine a transition property of the identified clock signal, such as which of the edges — rising edge and/or falling edge — of the clock transition triggers switching in the integrated circuitry of the library cell design file 501. The static clock identification system 500 can output the identified clock signals along with any characterization of the identified clock signals as clock information 503.

[0033] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and/or methods described herein may be performed by an apparatus, a device, and/or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0034] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0035] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I/O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine- readable" and may be readable by a processing device.

[0036] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer- readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini- computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and/or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non- removable media, or any combination thereof. [0037] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries.

Conclusion

[0038] While the application describes specific examples of carrying out embodiments, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while some of the specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples may be implemented using any electronic system.

[0039] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0040] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

1. A method comprising: extracting, by a computing system, timing information associated with a library design cell file describing circuitry; statically analyzing, by the computing system, the extracted timing information to identify at least one clock signal for the circuitry; correlating, by the computing system, the circuitry described in the library design cell file to a portion of a circuit design describing an electronic system; modifying, by the computing system, a compiled version of the circuit design based on the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design; and simulating, by a simulator implemented by the computing system, the electronic system using the modified version of the compiled circuit design.

2. The method of claim 1, wherein extracting the timing information associated with the library design cell file further comprises extracting at least one of signal parameters, path delays, or timing checks for the circuitry from a specify block in the library design cell file.

3. The method of claim 1, wherein extracting the timing information associated with the library design cell file describing circuitry further comprises extracting at least one of path delay or timing checks from a Standard Delay Format (SDF) file generated from the library design cell file.

4. The method of claim 1, wherein statically analyzing the extracted timing information to identify at least one clock signal for the circuitry further comprises: identifying one or more candidate clock signals in the extracted timing information; traversing timing checks in the extracted timing information for each of the candidate clock signals; and determining at least one of the candidate clock signals corresponds to a clock signal of the circuitry described in the library design cell file based on the traversal of the timing checks in the extracted timing information.

5. The method of claim 4, wherein traversing the timing checks in the extracted timing information for each of the candidate clock signals further comprises determining at least one of the candidate clock signals does not correspond to a data signal or a control signal in the timing checks, which identifies the candidate clock signal as a clock of the circuitry.

6. The method of claim 1, wherein statically analyzing the extracted timing information to identify at least one clock signal for the circuitry further comprises characterizing the identified clock signal with properties based on the extracted timing information.

7. The method of claim 6, wherein modifying the compiled version of the circuit design is based on the properties of the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design.

8. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: extracting timing information associated with a library design cell file describing circuitry; statically analyzing the extracted timing information to identify at least one clock signal for the circuitry; correlating the circuitry described in the library design cell file to a portion of a circuit design describing an electronic system; and modifying a compiled version of the circuit design based on the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design, wherein a simulator is configured to simulate the electronic system using the modified version of the compiled circuit design.

9. The apparatus of claim 8, extracting the timing information associated with the library design cell file further comprises extracting at least one of signal parameters, path delays, or timing checks for the circuitry from a specify block in the library design cell file.

10. The apparatus of claim 8, wherein extracting the timing information associated with the library design cell file describing circuitry further comprises extracting at least one of path delay or timing checks from a Standard Delay Format (SDF) file generated from the library design cell file.

11. The apparatus of claim 8, wherein statically analyzing the extracted timing information to identify at least one clock signal for the circuitry further comprises: identifying one or more candidate clock signals in the extracted timing information; traversing timing checks in the extracted timing information for each of the candidate clock signals; and determining at least one of the candidate clock signals corresponds to a clock signal of the circuitry described in the library design cell file based on the traversal of the timing checks in the extracted timing information.

12. The apparatus of claim 11, wherein traversing the timing checks in the extracted timing information for each of the candidate clock signals further comprises determining at least one of the candidate clock signals does not correspond to a data signal or a control signal in the timing checks, which identifies the candidate clock signal as a clock of the circuitry.

13. The apparatus of claim 8, wherein statically analyzing the extracted timing information to identify at least one clock signal for the circuitry further comprises characterizing the identified clock signal with properties based on the extracted timing information.

14. The apparatus of claim 13, wherein modifying the compiled version of the circuit design is based on the properties of the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design.

15. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: extract timing information associated with a library design cell file describing circuitry; statically analyze the extracted timing information to identify at least one clock signal for the circuitry; correlate the circuitry described in the library design cell file to a portion of a circuit design describing an electronic system; and modify a compiled version of the circuit design based on the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design, wherein a simulator is configured to simulate the electronic system using the modified version of the compiled circuit design.

16. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to extract the timing information associated with the library design cell file by extracting at least one of signal parameters, path delays, or timing checks for the circuitry from a specify block in the library design cell file.

17. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to extract the timing information associated with the library design cell file describing circuitry by extracting at least one of path delay or timing checks from a Standard Delay Format (SDF) file generated from the library design cell file.

18. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to statically analyze the extracted timing information to identify at least one clock signal for the circuitry by: identifying one or more candidate clock signals in the extracted timing information; traversing timing checks in the extracted timing information for each of the candidate clock signals; and determining at least one of the candidate clock signals corresponds to a clock signal of the circuitry described in the library design cell file based on the traversal of the timing checks in the extracted timing information.

19. The system of claim 18, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to traverse the timing checks in the extracted timing information for each of the candidate clock signals by determining at least one of the candidate clock signals does not correspond to a data signal or a control signal in the timing checks, which identifies the candidate clock signal as a clock of the circuitry.

20. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to statically analyze the extracted timing information to identify at least one clock signal for the circuitry by characterizing the identified clock signal with properties based on the extracted timing information, wherein the modification of the compiled version of the circuit design is based on the properties of the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design.