WO2024016647A1 - 加权轮询仲裁器及其轮询仲裁方法和芯片 - Google Patents

加权轮询仲裁器及其轮询仲裁方法和芯片 Download PDF

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Publication number
WO2024016647A1
WO2024016647A1 PCT/CN2023/076180 CN2023076180W WO2024016647A1 WO 2024016647 A1 WO2024016647 A1 WO 2024016647A1 CN 2023076180 W CN2023076180 W CN 2023076180W WO 2024016647 A1 WO2024016647 A1 WO 2024016647A1
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Prior art keywords
circuit
arbitration
request
gate
request source
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PCT/CN2023/076180
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English (en)
French (fr)
Inventor
田佩佳
蔡凯
刘明
张雨生
闫超
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声龙(新加坡)私人有限公司
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Publication of WO2024016647A1 publication Critical patent/WO2024016647A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration

Definitions

  • This application relates to the field of integrated circuit technology, and in particular to a weighted polling arbiter and its polling arbitration method and chip.
  • This application provides a weighted polling arbiter and its polling arbitration method and chip, which can enable multiple request sources to obtain arbitration in proportion.
  • this application provides a weighted polling arbiter, including: at least two arbitration circuits, a priority control circuit, a weight control circuit and an output circuit; wherein,
  • Each of the arbitration circuits is connected to a request source; each of the arbitration circuits is connected in sequence to form a ring, and is connected to the output circuit and the priority control circuit respectively; the output circuit is connected to a target device ; The priority control circuit is also connected to the request source corresponding to each arbitration circuit; the weight control circuit is connected to the priority control circuit;
  • Each of the arbitration circuits responds to the highest priority control signal sent by the priority control circuit, or the previous arbitration circuit sends an enable control signal based on no request from the connected request source.
  • the issued request is transmitted to the output circuit and sent to the target device through the output circuit, or the enable control signal is sent to the subsequent arbitration circuit based on no request from the connected request source;
  • the weight value of each request source is pre-configured in the weight control circuit, and the priority control circuit adjusts the highest priority control signal based on the pre-configured weight value of the request source.
  • each of the arbitration circuits includes a first OR gate, a NOT gate, a first AND gate and a second AND gate;
  • the first input terminal of the first OR gate is connected to an output terminal of the priority control circuit, and the second input terminal of the first OR gate is connected to the previous arbitration circuit.
  • the first OR gate The output terminals are respectively connected to the first input terminals of the first AND gate and the second AND gate;
  • the second input end of the first AND gate is connected to the corresponding request source, and the output end of the first AND gate is connected to one input end of the output circuit;
  • the second input terminal of the second AND gate is connected to the output terminal of the NOT gate, the input terminal of the NOT gate is connected to the corresponding request source, and the output terminal of the second AND gate is connected to the latter arbitration Circuit connection.
  • each of the arbitration circuits is also connected to the target device respectively;
  • Each of the arbitration circuits transmits requests from a connected request source to the output circuit based on the target device being in a ready state.
  • each of the arbitration circuits further includes a third AND gate; the first input end of the third AND gate is connected to the output end of the first AND gate, and the third AND gate The second input end of the three AND gate is connected to the target device, and the output end of the third AND gate is connected to the corresponding request source.
  • the priority control circuit is also connected to the target device;
  • the priority control circuit issues the highest priority control signal based on the target device being in a ready state.
  • the priority control circuit determines the arbitration circuit with the request that currently has the highest priority
  • the arbitration circuit to which the arbitration circuit is connected in response to the determination of the request having the highest priority If the number of requests issued by the request source is less than or equal to the weight value preconfigured by the request source, the highest priority control signal is adjusted based on the determined priority adjustment order of each arbitration circuit.
  • the priority control circuit keeps the highest priority control signal unchanged based on the fact that there is no request from each of the request sources.
  • the output circuit includes a second OR gate, the input end of the second OR gate is connected to each arbitration circuit, and the output end of the second OR gate is connected to each arbitration circuit.
  • the target device is connected.
  • this application also provides a weighted polling arbitration method, which is applied to the weighted polling arbiter described in the first aspect.
  • the method includes:
  • the latter arbitration circuit In response to the enable control signal sent by the previous arbitration circuit based on the non-request of the connected request source, the latter arbitration circuit is regarded as the arbitration circuit with the highest priority currently;
  • the number of requests issued by the connected request source is less than or equal to the weight value pre-configured for the request source in the weight control circuit.
  • this application also provides a chip including the weighted polling arbiter described in the first aspect.
  • the weighted polling arbiter and its polling arbitration method and chip provided by this application are connected to a request source through each arbitration circuit, and more than two arbitration circuits are connected in sequence to form a ring, and are respectively connected to the priority control circuit and output Circuit connection, the priority control circuit is also connected to the request source corresponding to each arbitration circuit, the weight control circuit is connected to the priority control circuit, and the output circuit is connected to a target device, so that each arbitration circuit can respond to the priority control
  • the highest priority control signal issued by the circuit, or the enable control signal issued by the previous arbitration circuit based on no request from the connected request source transmits the request issued by the connected request source to the output circuit and sends it to the target through the output circuit device, or there is no request for backwards based on the connected request source.
  • An arbitration circuit sends out an enable control signal, in which the weight value of each request source is pre-configured in the weight control circuit.
  • the priority control circuit adjusts the highest priority control signal based on the pre-configured weight value of the request source, which can enable multiple requests.
  • the source obtains arbitration in proportion to the pre-configured weight value.
  • FIG. 1 is a schematic structural diagram of an embodiment of the weighted polling arbiter provided by this application;
  • FIG. 2 is a schematic flow chart of the weighted polling arbitration method provided by this application.
  • FIG. 3 is a schematic structural diagram of another embodiment of the weighted polling arbiter provided by this application.
  • Figure 4 is a schematic flow chart of the priority control circuit provided by this application for adjusting the highest priority control signal
  • FIG. 5 is a schematic structural diagram of another embodiment of the weighted polling arbiter provided by this application.
  • Figure 6 is a schematic structural diagram of the arbitration circuit in Figure 5;
  • FIG. 7 is a schematic diagram of the input and output ports of the priority control circuit in FIG. 5 .
  • FIG. 1 is a schematic structural diagram of an embodiment of the weighted polling arbiter provided by this application.
  • the polling arbiter provided by this application includes: at least two arbitration circuits, a priority control circuit, a weight control circuit and an output circuit.
  • each arbitration circuit is connected to a request source, and each arbitration circuit is connected in sequence to form a ring, and is connected to the output circuit respectively.
  • the priority control circuit is connected to the priority control circuit, the output circuit is connected to a target device, the priority control circuit is also connected to the request source corresponding to each arbitration circuit, and the weight control circuit is connected to the priority control circuit.
  • S00, S01, and S02 are request sources
  • S4 is the polling arbiter
  • S5 is the target device where the requested resource is located.
  • the request sources S00, S01, and S02 are connected to the target device S5 through the polling arbiter S4.
  • the polling arbiter S4 includes: three arbitration circuits S10, S11, S12, a priority control circuit S2, a weight control circuit S6 and an output circuit S3.
  • the arbitration circuit S10 is connected to the request source connection S00 and processes the request from the request source S00.
  • the arbitration circuit S11 is connected to the request source connection S01 and processes the request from the request source S01.
  • the arbitration circuit S12 is connected to the request source connection S02 and processes the request from the request source S01. In response to the request from the request source S02, the arbitration circuits S10, S11, and S12 are sequentially connected to form a ring.
  • the priority control circuit S2 is connected to the arbitration circuits S10, S11, and S12 respectively, and adjusts the priorities of the arbitration circuits S10, S11, and S12.
  • the output circuit S3 is connected to the arbitration circuits S10, S11, and S12 respectively, and aggregates the requests of the arbitration circuits S10, S11, and S12 to the target device S5.
  • the weight control circuit S6 is connected to the priority control circuit S2 and is preconfigured with weight values of the request sources S00, S01, and S02.
  • Each arbitration circuit transmits a request from a connected request source to the output in response to the highest priority control signal issued by the priority control circuit, or an enable control signal issued by the previous arbitration circuit based on no request from the connected request source. circuit and is sent to the target device through the output circuit, or an enable control signal is issued to the subsequent arbitration circuit based on no request from the connected request source.
  • the arbitration circuit S10 responds to the highest priority control signal sent by the priority control circuit S2, or the previous arbitration circuit S12 based on the enable control signal sent without request by the connected request source S02, the connected request source S02
  • the request issued by the request source S00 is transmitted to the output circuit S3 and sent to the target device S5 through the output circuit S3, or an enable control signal is sent to the subsequent arbitration circuit S11 based on the fact that the connected request source S00 has no request.
  • the arbitration circuit S11 responds to the highest priority control signal sent by the priority control circuit S2, or the previous arbitration circuit S10 based on the enable control signal sent by the connected request source S00 without a request, the request sent by the connected request source S01 It is transmitted to the output circuit S3 and sent to the target device S5 through the output circuit S3, or an enable control signal is sent to the next arbitration circuit S12 based on the fact that the connected request source S01 has no request.
  • the arbitration circuit S12 responds to the highest priority control signal sent by the priority control circuit S2, or the previous arbitration circuit S11 based on the enable control signal sent by the connected request source S01 without request, the request sent by the connected request source S02 transmitted to output circuit S3, and It is sent to the target device S5 through the output circuit S3, or an enable control signal is sent to the subsequent arbitration circuit S10 based on the absence of a request from the connected request source S02.
  • the priority control circuit is also connected to the request source corresponding to each arbitration circuit, and adjusts the highest priority control signal based on the weight value preconfigured by the request source.
  • the priority control circuit S2 is also connected to the request source S00 corresponding to the arbitration circuit S10, the request source S01 corresponding to the arbitration circuit S11, and the request source S02 corresponding to the arbitration circuit S12. Based on the request sources S00, S01, and S02 Preconfigured weight values adjust the highest priority control signals.
  • Figure 1 takes three arbitration circuits S10, S11, and S12 as an example for illustration.
  • the number of arbitration circuits in the weighted polling arbiter can be based on the actual situation. To determine the application requirements, the number of arbitration circuits in the weighted polling arbiter can be recorded as N, where N is an integer, and N ⁇ 2.
  • FIG 2 is a schematic flow chart of the weighted polling arbitration method provided by this application.
  • the weighted round robin arbitration method provided in this application is applied to the weighted round robin arbiter shown in Figure 1.
  • the weighted round robin arbitration method at least includes the following steps.
  • the number of requests issued by the connected request source is less than or equal to the weight value pre-configured for the request source in the weight control circuit.
  • the weighted polling arbiter and its arbitration method provided by the embodiment of this application are connected to a request source through each arbitration circuit, and more than two arbitration circuits are connected in sequence to form a ring, and are connected to the priority control circuit and the output circuit respectively.
  • the priority control circuit is also connected to the request source corresponding to each arbitration circuit, the weight control circuit is connected to the priority control circuit, and the output circuit is connected to a target device, so that each arbitration circuit can respond to the priority control circuit.
  • the highest priority control signal, or the enable control signal issued by the previous arbitration circuit based on no request from the connected request source transmits the request issued by the connected request source to the output circuit, and It is sent to the target device through the output circuit, or an enable control signal is sent to the next arbitration circuit based on the connected request source having no request, in which the weight value of each request source is pre-configured in the weight control circuit, and the priority control circuit is based on
  • the pre-configured weight value of the request source adjusts the highest priority control signal, which allows multiple request sources to obtain arbitration according to the proportion of the pre-configured weight value. By reasonably configuring the weight value of the request source, it is possible to ensure that the weighted polling arbiter is used.
  • On-chip system load balancing maintains high data throughput, has high efficiency and stability, and ensures high performance.
  • FIG 3 is a schematic structural diagram of another embodiment of the weighted polling arbiter provided by this application.
  • the difference between the weighted polling arbiter in Figure 3 and the weighted polling arbiter in Figure 1 is that each arbitration circuit of the weighted polling arbiter in Figure 3 is also connected to the target device respectively, and each arbitration circuit is based on the target device.
  • the ready state transmits requests from the connected request source to the output circuit.
  • the three arbitration circuits S10, S11, and S12 of the weighted polling arbiter S4 are also connected to the target device S5 respectively.
  • the arbitration circuit S10 transfers the request issued by the connected request source S00 based on the target device S5 being in the ready state.
  • the arbitration circuit S11 transmits the request issued by the connected request source S01 to the output circuit S3 based on the target device S5 being in the ready state, and the arbitration circuit S12 issues the connected request source S02 based on the target device S5 being in the ready state. The request is transmitted to the output circuit S3.
  • the priority control circuit is further connected to the target device, and the priority control circuit issues the highest priority control signal based on the target device being in a ready state.
  • the priority control circuit S2 is also connected to the target device S5, and the priority control circuit S2 sends the highest priority control signal based on the target device S5 being in a ready state.
  • Figure 4 is a schematic flow chart of the priority control circuit provided by the present application for adjusting the highest priority control signal. As shown in Figure 4, the priority control circuit adjusts the highest priority control signal based on the request from the request source, including at least the following steps.
  • the priority control circuitry leaves the highest priority control signal unchanged based on the absence of requests from each request source.
  • the arbitration circuit in the weighted polling arbiter can be implemented using a logic circuit.
  • Figure 5 is a schematic structural diagram of another embodiment of the weighted polling arbiter provided by this application.
  • Figure 6 is a schematic structural diagram of the arbitration circuit in Figure 5.
  • Figure 7 is a diagram Schematic diagram of the input and output ports of the priority control circuit in 5.
  • the difference between the weighted polling arbiter in Figure 5 and the weighted polling arbiter in Figure 1 is that each arbitration circuit of the weighted polling arbiter in Figure 5 includes an OR gate S100, a NOT gate S110 and two AND gates S120 and S130.
  • each arbitration circuit includes three input terminals i1, i3, and i4 and two output terminals o1 and o3.
  • the input terminal i1 is connected to the request source corresponding to the arbitration circuit and receives the request from the request source.
  • the input terminal i3 is connected to the previous arbitration circuit of the arbitration circuit and receives the enable control signal sent by the previous arbitration circuit.
  • the input terminal i4 is connected to the request source of the arbitration circuit.
  • An output terminal of the priority control circuit S2 is connected to receive the priority control signal sent by the priority control circuit S2.
  • the output terminal o1 is connected to an input terminal of the output circuit S3 and transmits the request to the output circuit S3.
  • the output terminal o3 is connected to the subsequent arbitration circuit of the arbitration circuit and sends an enable control signal to the subsequent arbitration circuit.
  • the first input terminal of the OR gate S100 is the input terminal i4 of the arbitration circuit
  • the second input terminal of the OR gate S100 is the input terminal i3 of the arbitration circuit
  • the output terminals of the OR gate S100 are connected to the AND gates S120 and S120 respectively.
  • the first input terminal of AND gate S130 is connected.
  • the second input terminal of the AND gate S120 is the input terminal i1 of the arbitration circuit
  • the output terminal of the AND gate S120 is the output terminal o1 of the arbitration circuit.
  • the second input terminal of the AND gate S130 is connected to the output terminal of the NOT gate S110.
  • the input terminal of the NOT gate S110 is the input terminal i1 of the arbitration circuit
  • the output terminal of the AND gate S130 is the output terminal o3 of the arbitration circuit.
  • each arbitration circuit may further include an AND gate S140.
  • each arbitration circuit may also include an input terminal i2 and an output terminal o2.
  • the input terminal i2 is connected to the target device S5 and receives the status signal of the target device S5.
  • the output terminal o2 is connected to the request source corresponding to the arbitration circuit and sends the status of the target device S5 to the request source.
  • the first input terminal of the AND gate S140 is the output terminal o1 of the arbitration circuit
  • the second input terminal of the AND gate S140 is the input terminal i2 of the arbitration circuit
  • the output terminal of the AND gate S140 is the output terminal o2 of the arbitration circuit.
  • x can be either 1 or 0; i4 is 1, which means the priority control circuit S2 sends the highest priority control signal, i4 is 0, which means the priority control circuit S2 does not send the highest priority control signal; i3 is 1, which means The previous arbitration circuit sends out the enable control signal. i3 is 0, which means that the previous arbitration circuit has not sent out the enable control signal; i2 is 0, which means the target device S5 is in the ready state; i1 is 1, which means the request source has issued a request, and i1 is 0, which means the request.
  • the source has not sent a request; o3 is 1, which means that the enable control signal is sent to the next arbitration circuit; o3 is 0, which means no enable control signal is sent to the next arbitration circuit; o2 is 0, which means the target device S5 is in the ready state; o1 is 1 Indicates that the request is transmitted to the output circuit S3. If o1 is 0, it indicates that the request is not transmitted to the output circuit S3.
  • the priority control circuit S2 also known as the priority control module, includes four input terminals i1, i2, i3, i5 and three output terminals o1, o2, o3.
  • the input terminal i1 is connected to the request source S00 corresponding to the arbitration circuit S10 and receives the request sent by the request source S00.
  • the input terminal i2 is connected to the request source S01 corresponding to the arbitration circuit S11 and receives the request sent by the request source S01.
  • the input terminal i3 is connected to the request source S01 corresponding to the arbitration circuit S11.
  • the request source S02 corresponding to the arbitration circuit S12 is connected to receive the request from the request source S02.
  • the input terminal i5 is connected to the weight control circuit S6, also known as the weight control module, and the weight control circuit S6 pre-configures the request sources S00, S01 and S02. Weights.
  • the output terminal o1 is connected to the arbitration circuit S12 and sends a priority control signal to the arbitration circuit S12.
  • the output terminal o2 is connected to the arbitration circuit S11 and sends a priority control signal to the arbitration circuit S11.
  • the output terminal o3 is connected to the arbitration circuit S10 and sends a priority control signal to the arbitration circuit S11. S10 sends a priority control signal.
  • the priority control circuit S2 may also be connected to the target device S5. As shown in Figure 7, the priority control circuit S2 may also include an input terminal i4, which is connected to the target device S5 and receives the status signal of the target device S5.
  • the priority control circuit S2 controls the arbitration circuits S10, S11, and S12 through S102, S112, and S122.
  • the priority order is S10>S11>S12.
  • the arbitration circuit S10 has the highest priority. If the request is made at this time, The source S00 has a request sent to the arbitration circuit S10.
  • the request sent by the request source S00 will reach the target device S5 through the arbitration circuit S10 and the output circuit S3. Due to the request
  • the weight of source S00 is 4, so the request source S00 can send up to 4 consecutive requests to the target device S5.
  • the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, and S12 through S102, S112, and S122 to be S11>S12>S10.
  • the request source S01 has a request sent to the arbitration circuit S11 at this time, since the arbitration circuit S11 is the port with the highest priority and has the request, the request from the request source S01 will reach the target device S5 through the arbitration circuit S11 and the output circuit S3. , since the weight of the request source S01 is 2, the request source S01 can send up to 2 consecutive requests to the target device S5. When the request source S01 has sent 2 consecutive requests or the request source S01 has not sent 2 consecutive requests, for example, the request source S01 has only one request, and the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, and S12 through S102, S112, and S122 to be S12>S10>S11.
  • the arbitration circuit S11 will enable the arbitration circuit S12. If the request source S02 has a request to be sent to the arbitration circuit S12 at this time, because the arbitration circuit S12 has the highest priority at this time. For the port with requests, the request sent by the request source S02 will reach the target device S5 through the arbitration circuit S12 and the output circuit S3. Since the weight of the request source S02 is 1, the request source S02 can send at most 1 request to the target device S5. After the request source S02 sends a request, the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, and S12 through S102, S112, and S122 to be S10>S11>S12.
  • the arbitration circuit S11 will enable the arbitration circuit S12. If the request source S02 has no request to be sent to the arbitration circuit S12 at this time, the arbitration circuit S12 will enable the arbitration circuit S10. If the request source S00 has a request sent to the arbitration circuit S10 at this time, since the arbitration circuit S10 is the port with the highest priority and has the request, the request from the request source S00 will reach the target device S5 through the arbitration circuit S10 and the output circuit S3. , since the weight of the request source S00 is 4, the request source S00 can send up to 4 consecutive requests to the target device S5.
  • the priority control circuit S2 will adjust the priority order of the arbitration circuits S10, S11, and S12 through S102, S112, and S122 to be S11>S12>S10.
  • the priority control circuit S2 will keep the priority unchanged, wait for requests from the request sources S00, S01, and S02, and then pass S102, S112 and S122 adjust the priority order of the arbitration circuits S10, S11 and S12.
  • the output circuit in the weighted polling arbiter may also be implemented using a logic circuit.
  • the output circuit S3 may include an OR gate S150, the input end of the OR gate S150 is connected to each arbitration circuit S10, S11, S12, and the output end of the OR gate S150 is connected to the target device S5.
  • the weighted polling arbiter provided by the embodiment of this application implements the arbitration circuit and the output circuit through logic circuits, which can shorten the critical path, increase the operating frequency, make the circuit smaller and consume less power.
  • This application also provides a chip, which may include the weighted polling arbiter of Figure 1, Figure 3 or Figure 5.

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Abstract

本申请提供一种加权轮询仲裁器及其轮询仲裁方法和芯片。其中加权轮询仲裁器包括至少二个仲裁电路，每个仲裁电路与一个请求源连接，每个仲裁电路顺次连接成环状；一个优先级控制电路分别与每个仲裁电路连接；一个输出电路分别与每个仲裁电路和一个目标设备连接；一个权重控制电路与优先级控制电路连接；每个仲裁电路响应于优先级控制电路发出的最高优先级控制信号或前一个仲裁电路发出的使能控制信号，将请求源发出的请求通过输出电路发送至目标设备，或基于请求源无请求向后一个仲裁电路发出使能控制信号；权重控制电路预先配置有每个请求源的权重值，优先级控制电路基于预先配置的权重值调整最高优先级控制信号。本申请可以使多个请求源按比例获得仲裁。

Description

加权轮询仲裁器及其轮询仲裁方法和芯片
相关申请的交叉引用
本申请要求于2022年07月19日提交的申请号为202210844833.0，名称为“加权轮询仲裁器及其轮询仲裁方法和芯片”的中国专利申请的优先权，其通过引用方式全部并入本文。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种加权轮询仲裁器及其轮询仲裁方法和芯片。
背景技术
在计算机结构中，当多个请求源同时请求同一个资源时，如果该资源只能接受一个请求，就需要用到仲裁结构；如果需要让多个请求源均匀的获得资源，就需要用到轮询仲裁，否则会造成某个请求源一直占用该资源导致其他请求源无法获取资源，影响计算性能。
发明内容
本申请提供一种加权轮询仲裁器及其轮询仲裁方法和芯片，可以使多个请求源按比例获得仲裁。
第一方面，本申请提供一种加权轮询仲裁器，包括：至少二个仲裁电路、一个优先级控制电路、一个权重控制电路和一个输出电路；其中，
每一个所述仲裁电路与一个请求源连接；每个所述仲裁电路顺次连接形成环状，并分别与所述输出电路和所述优先级控制电路连接；所述输出电路与一个目标设备连接；所述优先级控制电路还分别与每个所述仲裁电路对应的请求源连接；所述权重控制电路与所述优先级控制电路连接；
每一个所述仲裁电路响应于所述优先级控制电路发出的最高优先级控制信号，或者前一个所述仲裁电路基于所连接的请求源无请求发出的使能控制信号，将所连接的请求源发出的请求传输至所述输出电路，并通过所述输出电路发送至所述目标设备，或者基于所连接的请求源无请求向后一个所述仲裁电路发出所述使能控制信号；
在所述权重控制电路中预先配置有每个所述请求源的权重值，所述优先级控制电路基于所述请求源预先配置的权重值调整所述最高优先级控制信号。
根据本申请提供的加权轮询仲裁器，每一个所述仲裁电路包括第一或门、非门、第一与门和第二与门；
所述第一或门的第一输入端与所述优先级控制电路的一个输出端连接，所述第一或门的第二输入端与前一个所述仲裁电路连接，所述第一或门的输出端分别与第一与门和第二与门的第一输入端连接；
所述第一与门的第二输入端与对应的请求源连接，所述第一与门的输出端与所述输出电路的一个输入端连接；
所述第二与门的第二输入端与所述非门的输出端连接，所述非门的输入端与对应的请求源连接，所述第二与门的输出端与后一个所述仲裁电路连接。
根据本申请提供的加权轮询仲裁器，每个所述仲裁电路还分别与所述目标设备连接；
每一个所述仲裁电路基于所述目标设备处于就绪状态将所连接的请求源发出的请求传输至所述输出电路。
根据本申请提供的加权轮询仲裁器，每一个所述仲裁电路还包括第三与门；所述第三与门的第一输入端与所述第一与门的输出端连接，所述第三与门的第二输入端与所述目标设备连接，所述第三与门的输出端与对应的请求源连接。
根据本申请提供的加权轮询仲裁器，所述优先级控制电路还与所述目标设备连接；
所述优先级控制电路基于所述目标设备处于就绪状态发出所述最高优先级控制信号。
根据本申请提供的加权轮询仲裁器，所述优先级控制电路确定当前具有最高优先级的有请求的一个所述仲裁电路；
基于所确定的具有最高优先级的有请求的所述仲裁电路和预先设定的仲裁电路的优先级顺序，确定每个所述仲裁电路的优先级调整顺序；
响应于所确定的具有最高优先级的有请求的所述仲裁电路所连接的 请求源发出的请求的数量小于或者等于所述请求源预先配置的权重值，基于所确定的每个所述仲裁电路的优先级调整顺序，调整所述最高优先级控制信号。
根据本申请提供的加权轮询仲裁器，所述优先级控制电路基于每个所述请求源均无请求，保持所述最高优先级控制信号不变。
根据本申请提供的加权轮询仲裁器，所述输出电路包括第二或门，所述第二或门的输入端与每个所述仲裁电路连接，所述第二或门的输出端与所述目标设备连接。
第二方面，本申请还提供一种加权轮询仲裁方法，应用于第一方面所述的加权轮询仲裁器，所述方法包括：
响应于所述优先级控制电路发出的最高优先级控制信号，确定一个当前具有最高优先级的所述仲裁电路；
将所连接的请求源发出的请求传输至所述输出电路，并通过所述输出电路发送至所述目标设备，或者基于所连接的请求源无请求向后一个所述仲裁电路发出所述使能控制信号；
响应于前一个所述仲裁电路基于所连接的请求源无请求发出的使能控制信号，将后一个所述仲裁电路作为当前具有最高优先级的所述仲裁电路；
其中，所连接的请求源发出的请求的数量小于或者等于在所述权重控制电路中为所述请求源预先配置的权重值。
第三方面，本申请还提供一种芯片，包括第一方面所述的加权轮询仲裁器。
本申请提供的加权轮询仲裁器及其轮询仲裁方法和芯片，通过每一个仲裁电路与一个请求源连接，二个以上仲裁电路顺次连接形成环状，并分别与优先级控制电路和输出电路连接，优先级控制电路还分别与每个仲裁电路对应的请求源连接，权重控制电路与优先级控制电路连接，输出电路与一个目标设备连接，使得每一个仲裁电路，可以响应于优先级控制电路发出的最高优先级控制信号，或者前一个仲裁电路基于所连接的请求源无请求发出的使能控制信号，将所连接的请求源发出的请求传输至输出电路，并通过输出电路发送至目标设备，或者基于所连接的请求源无请求向后一 个仲裁电路发出使能控制信号，其中在权重控制电路中预先配置有每个请求源的权重值，优先级控制电路基于请求源预先配置的权重值调整最高优先级控制信号，可以使多个请求源按照预先配置的权重值的比例获得仲裁，通过合理配置请求源的权重值，可以保证使用该加权轮询仲裁器的片上系统负载均衡，维持较高的数据吞吐量，具有较高的效率和稳定性，保证较高的性能。
附图说明
为了更清楚地说明本申请或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的加权轮询仲裁器的一实施例的组成结构示意图；
图2是本申请提供的加权轮询仲裁方法的流程示意图；
图3是本申请提供的加权轮询仲裁器的另一实施例的组成结构示意图；
图4是本申请提供的优先级控制电路调整最高优先级控制信号的流程示意图；
图5是本申请提供的加权轮询仲裁器的又一实施例的组成结构示意图；
图6是图5中仲裁电路的组成结构示意图；
图7是图5中优先级控制电路的输入输出端口的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1是本申请提供的加权轮询仲裁器的一实施例的组成结构示意图。本申请提供的轮询仲裁器包括：至少二个仲裁电路、一个优先级控制电路、一个权重控制电路和一个输出电路。其中，每一个仲裁电路与一个请求源连接，每个仲裁电路顺次连接形成环状，并分别与输出电 路和优先级控制电路连接，输出电路与一个目标设备连接，优先级控制电路还分别与每个仲裁电路对应的请求源连接，权重控制电路与优先级控制电路连接。如图1所示，S00，S01，S02为请求源，S4为轮询仲裁器，S5为被请求资源所在的目标设备，请求源S00，S01，S02通过轮询仲裁器S4与目标设备S5连接。轮询仲裁器S4包括：三个仲裁电路S10、S11、S12、一个优先级控制电路S2、一个权重控制电路S6和一个输出电路S3。其中，仲裁电路S10与请求源连接S00连接，处理来自请求源S00的请求，仲裁电路S11与请求源连接S01连接，处理来自请求源S01的请求，仲裁电路S12与请求源连接S02连接，处理来自请求源S02的请求，仲裁电路S10、S11、S12顺次连接形成环状。优先级控制电路S2分别与仲裁电路S10、S11、S12连接，调整仲裁电路S10、S11、S12的优先级。输出电路S3分别与仲裁电路S10、S11、S12连接，汇总仲裁电路S10、S11、S12的请求到目标设备S5。权重控制电路S6与优先级控制电路S2连接，预先配置有请求源S00，S01，S02的权重值。
每一个仲裁电路响应于优先级控制电路发出的最高优先级控制信号，或者前一个仲裁电路基于所连接的请求源无请求发出的使能控制信号，将所连接的请求源发出的请求传输至输出电路，并通过输出电路发送至目标设备，或者基于所连接的请求源无请求向后一个仲裁电路发出使能控制信号。如图1所示，仲裁电路S10响应于优先级控制电路S2发出的最高优先级控制信号，或者前一个仲裁电路S12基于所连接的请求源S02无请求发出的使能控制信号，将所连接的请求源S00发出的请求传输至输出电路S3，并通过输出电路S3发送至目标设备S5，或者基于所连接的请求源S00无请求向后一个仲裁电路S11发出使能控制信号。仲裁电路S11响应于优先级控制电路S2发出的最高优先级控制信号，或者前一个仲裁电路S10基于所连接的请求源S00无请求发出的使能控制信号，将所连接的请求源S01发出的请求传输至输出电路S3，并通过输出电路S3发送至目标设备S5，或者基于所连接的请求源S01无请求向后一个仲裁电路S12发出使能控制信号。仲裁电路S12响应于优先级控制电路S2发出的最高优先级控制信号，或者前一个仲裁电路S11基于所连接的请求源S01无请求发出的使能控制信号，将所连接的请求源S02发出的请求传输至输出电路S3，并 通过输出电路S3发送至目标设备S5，或者基于所连接的请求源S02无请求向后一个仲裁电路S10发出使能控制信号。
优先级控制电路还分别与每个仲裁电路对应的请求源连接，基于请求源预先配置的权重值调整最高优先级控制信号。如图1所示，优先级控制电路S2还分别与仲裁电路S10对应的请求源S00、仲裁电路S11对应的请求源S01以及仲裁电路S12对应的请求源S02连接，基于请求源S00、S01、S02预先配置的权重值调整最高优先级控制信号。
图1是以三个仲裁电路S10、S11、S12为例进行说明，但是本申请实施例对加权轮询仲裁器中仲裁电路的数量不作限定，加权轮询仲裁器中仲裁电路的数量可以根据实际的应用需求确定，可以将加权轮询仲裁器中仲裁电路的数量记为N个，其中N为整数，并且N≥2。
请参阅图2，图2是本申请提供的加权轮询仲裁方法的流程示意图。本申请提供的加权轮询仲裁方法应用于图1所示的加权轮询仲裁器，如图2所示，该加权轮询仲裁方法至少包括下述步骤。
201，响应于优先级控制电路发出的最高优先级控制信号，确定一个当前具有最高优先级的仲裁电路。
202，将所连接的请求源发出的请求传输至输出电路，并通过输出电路发送至目标设备，或者基于所连接的请求源无请求向后一个仲裁电路发出使能控制信号。
203，响应于前一个仲裁电路基于所连接的请求源无请求发出的使能控制信号，将后一个仲裁电路作为当前具有最高优先级的仲裁电路。
其中，所连接的请求源发出的请求的数量小于或者等于在权重控制电路中为请求源预先配置的权重值。
本申请实施例提供的加权轮询仲裁器及其仲裁方法，通过每一个仲裁电路与一个请求源连接，二个以上仲裁电路顺次连接形成环状，并分别与优先级控制电路和输出电路连接，优先级控制电路还分别与每个仲裁电路对应的请求源连接，权重控制电路与优先级控制电路连接，输出电路与一个目标设备连接，使得每一个仲裁电路，可以响应于优先级控制电路发出的最高优先级控制信号，或者前一个仲裁电路基于所连接的请求源无请求发出的使能控制信号，将所连接的请求源发出的请求传输至输出电路，并 通过输出电路发送至目标设备，或者基于所连接的请求源无请求向后一个仲裁电路发出使能控制信号，其中在权重控制电路中预先配置有每个请求源的权重值，优先级控制电路基于请求源预先配置的权重值调整最高优先级控制信号，可以使多个请求源按照预先配置的权重值的比例获得仲裁，通过合理配置请求源的权重值，可以保证使用该加权轮询仲裁器的片上系统负载均衡，维持较高的数据吞吐量，具有较高的效率和稳定性，保证较高的性能。
请参阅图3，图3是本申请提供的加权轮询仲裁器的另一实施例的组成结构示意图。图3中加权轮询仲裁器与图1中加权轮询仲裁器的不同之处在于，图3中加权轮询仲裁器的每个仲裁电路还分别与目标设备连接，每一个仲裁电路基于目标设备处于就绪状态将所连接的请求源发出的请求传输至输出电路。如图3所示，加权轮询仲裁器S4的三个仲裁电路S10、S11、S12还分别与目标设备S5连接，仲裁电路S10基于目标设备S5处于就绪状态将所连接的请求源S00发出的请求传输至输出电路S3，仲裁电路S11基于目标设备S5处于就绪状态将所连接的请求源S01发出的请求传输至输出电路S3，仲裁电路S12基于目标设备S5处于就绪状态将所连接的请求源S02发出的请求传输至输出电路S3。
在示例性实施方式中，优先级控制电路还与目标设备连接，优先级控制电路基于目标设备处于就绪状态发出最高优先级控制信号。如图3所示，优先级控制电路S2还与目标设备S5连接，优先级控制电路S2基于目标设备S5处于就绪状态发出最高优先级控制信号。
请参阅图4，图4是本申请提供的优先级控制电路调整最高优先级控制信号的流程示意图。如图4所示，优先级控制电路基于请求源的请求调整最高优先级控制信号至少包括下述步骤。
401，确定当前具有最高优先级的有请求的一个仲裁电路。
402，基于所确定的具有最高优先级的有请求的仲裁电路和预先设定的仲裁电路的优先级顺序，确定每个仲裁电路的优先级调整顺序。
403，响应于所确定的具有最高优先级的有请求的仲裁电路所连接的请求源发出的请求的数量小于或者等于请求源预先配置的权重值，基于所确定的每个仲裁电路的优先级调整顺序，调整最高优先级控制信号。
在示例性实施方式中，优先级控制电路基于每个请求源均无请求，保持最高优先级控制信号不变。
在上述每个实施例中，加权轮询仲裁器中的仲裁电路可以采用逻辑电路实现。请参阅图5、图6和图7，图5是本申请提供的加权轮询仲裁器的又一实施例的组成结构示意图，图6是图5中仲裁电路的组成结构示意图，图7是图5中优先级控制电路的输入输出端口的示意图。图5中加权轮询仲裁器与图1中加权轮询仲裁器的不同之处在于，图5中加权轮询仲裁器的每一个仲裁电路均包括一个或门S100、一个非门S110和二个与门S120、S130。
如图6所示，每一个仲裁电路均包括三个输入端i1、i3、i4和二个输出端o1、o3。其中，输入端i1与仲裁电路对应的请求源连接，接收请求源发出的请求，输入端i3与仲裁电路的前一个仲裁电路连接，接收前一个仲裁电路发出的使能控制信号，输入端i4与优先级控制电路S2的一个输出端连接，接收优先级控制电路S2发出的优先级控制信号。输出端o1与输出电路S3的一个输入端连接，将请求传输至输出电路S3，输出端o3与仲裁电路的后一个仲裁电路连接，向后一个仲裁电路发出使能控制信号。
如图6所示，或门S100的第一输入端为仲裁电路的输入端i4，或门S100的第二输入端为仲裁电路的输入端i3，或门S100的输出端分别与与门S120和与门S130的第一输入端连接。与门S120的第二输入端为仲裁电路的输入端i1，与门S120的输出端为仲裁电路的输出端o1。与门S130的第二输入端与非门S110的输出端连接，非门S110的输入端为仲裁电路的输入端i1，与门S130的输出端为仲裁电路的输出端o3。
在示例性实施方式中，如图5所示，每一个仲裁电路还可以包括与门S140。如图6所示，每一个仲裁电路还可以包括输入端i2和输出端o2。其中，输入端i2与目标设备S5连接，接收目标设备S5的状态信号，输出端o2与仲裁电路对应的请求源连接，向请求源发送目标设备S5的状态。与门S140的第一输入端为仲裁电路的输出端o1，与门S140的第二输入端为仲裁电路的输入端i2，与门S140的输出端为仲裁电路的输出端o2。
图6中仲裁电路的每个输入端i1、i2、i3、i4与输出端o1、o2、o3的 真值表如表1所示。
表1
其中，x既可以为1，又可以为0；i4为1表示优先级控制电路S2发出最高优先级控制信号，i4为0表示优先级控制电路S2未发出最高优先级控制信号；i3为1表示前一个仲裁电路发出使能控制信号，i3为0表示前一个仲裁电路未发出使能控制信号；i2为0表示目标设备S5处于就绪状态；i1为1表示请求源发出请求，i1为0表示请求源未发出请求；o3为1表示向后一个仲裁电路发出使能控制信号，o3为0表示未向后一个仲裁电路发出使能控制信号；o2为0表示目标设备S5处于就绪状态；o1为1表示向输出电路S3传输请求，o1为0表示未向输出电路S3传输请求。
如图7所示，优先级控制电路S2，或者称为优先级控制模块，包括四个输入端i1、i2、i3、i5和三个输出端o1、o2、o3。其中，输入端i1与仲裁电路S10对应的请求源S00连接，接收请求源S00发出的请求，输入端i2与仲裁电路S11对应的请求源S01连接，接收请求源S01发出的请求，输入端i3与仲裁电路S12对应的请求源S02连接，接收请求源S02发出的请求，输入端i5与权重控制电路S6，或者称为权重控制模块连接，接收权重控制电路S6预先配置请求源S00、S01、S02的权重值。输出端o1与仲裁电路S12连接，向仲裁电路S12发送优先级控制信号，输出端o2与仲裁电路S11连接，向仲裁电路S11发送优先级控制信号，输出端o3与仲裁电路S10连接，向仲裁电路S10发送优先级控制信号。
在示例性实施方式中，如图5所示，优先级控制电路S2还可以与目标设备S5连接。如图7所示，优先级控制电路S2还可以包括输入端i4，输入端i4与目标设备S5连接，接收目标设备S5的状态信号。
图7中优先级控制电路S2的每个输入端i1、i2、i3、i4、i5与输出端 o1、o2、o3的真值表如表2所示。
表2
其中，x既可以为1，又可以为0；i5为1表示权重控制电路S6有效，i5为0表示权重控制电路S6无效；i4为1表示目标设备S5处于就绪状态，i4为0表示目标设备S5未处于就绪状态；i3为1表示请求源S02发出请求，i3为0表示请求源S02未发出请求；i2为1表示请求源S01发出请求，i2为0表示请求源S01未发出请求；i1为1表示请求源S00发出请求，i1为0表示请求源S00未发出请求；o3为1表示向仲裁电路S10发送最高优先级控制信号，o3为0表示未向仲裁电路S10发送最高优先级控制信号；o2为1表示向仲裁电路S11发送最高优先级控制信号，o2为0表示未向仲裁电路S11发送最高优先级控制信号；o1为1表示向仲裁电路S12发送最高优先级控制信号，o1为0表示未向仲裁电路S12发送最高优先级控制信号；o3n、o2n和o1n表示当前时钟周期，o3n+1、o2n+1和o1n+1表示下一时钟周期；在优先级控制电路S2的输出端o1、o2、o3中，同时有且仅有1个输出端输出1，使该仲裁电路具有最高优先级，例如，优先级控制电路S2在初始状态下输出为o3＝0，o2＝0，o1＝1，仲裁电路S10具有最高优先级。
如图5所示，优先级控制电路S2通过S102、S112、S122控制仲裁电路S10、S11、S12的优先级顺序为S10>S11>S12，此时仲裁电路S10具有最高优先级，若此时请求源S00有请求发往仲裁电路S10，请求源S00发出的请求将通过仲裁电路S10和输出电路S3到达目标设备S5，由于请求 源S00的权重为4，因此请求源S00可以最多连续发送4个请求到目标设备S5，当请求源S00发送完连续4个请求或者请求源S00没有连续4个请求后，例如请求源S00只有连续3个请求，优先级控制电路S2将通过S102、S112、S122调整仲裁电路S10、S11、S12的优先级顺序为S11>S12>S10。
若此时请求源S01有请求发往仲裁电路S11，由于此时仲裁电路S11为具有最高优先级的有请求的端口，请求源S01发出的请求将通过仲裁电路S11和输出电路S3到达目标设备S5，由于请求源S01的权重为2，因此请求源S01可以最多连续发送2个请求到目标设备S5，当请求源S01发送完连续2个请求或者请求源S01没有连续2个请求后，例如请求源S01只有1个请求，优先级控制电路S2将通过S102、S112、S122调整仲裁电路S10、S11、S12的优先级顺序为S12>S10>S11。
若此时请求源S01无请求发往仲裁电路S11，仲裁电路S11将使仲裁电路S12使能，若此时请求源S02有请求发往仲裁电路S12，由于此时仲裁电路S12是具有最高优先级的有请求的端口，请求源S02发出的请求将通过仲裁电路S12和输出电路S3到达目标设备S5，由于请求源S02的权重为1，因此请求源S02可以最多发送1个请求到目标设备S5，当请求源S02发送完1个请求后，优先级控制电路S2将通过S102、S112、S122调整仲裁电路S10、S11、S12的优先级顺序为S10>S11>S12。
若此时请求源S01无请求发往仲裁电路S11，仲裁电路S11将使仲裁电路S12使能，若此时请求源S02无请求发往仲裁电路S12，仲裁电路S12将使仲裁电路S10使能，若此时请求源S00有请求发往仲裁电路S10，由于此时仲裁电路S10是具有最高优先级的有请求的端口，请求源S00发出的请求将通过仲裁电路S10和输出电路S3到达目标设备S5，由于请求源S00的权重为4，因此请求源S00可以最多连续发送4个请求到目标设备S5，当请求源S00发送完连续4个请求或者请求源S00没有连续4个请求后，例如请求源S00只有1个请求，优先级控制电路S2将通过S102、S112、S122调整仲裁电路S10、S11、S12的优先级顺序为S11>S12>S10。
若三个请求源S00、S01、S02均没有请求，此时优先级控制电路S2将保持优先级不变，等待请求源S00，S01，S02发来请求，再通过S102、 S112、S122调整仲裁电路S10、S11、S12的优先级顺序。
在示例性实施方式中，加权轮询仲裁器中的输出电路也可以采用逻辑电路实现。如图5所示，输出电路S3可以包括或门S150，或门S150的输入端与每个仲裁电路S10、S11、S12连接，或门S150的输出端与目标设备S5连接。
本申请实施例提供的加权轮询仲裁器，通过逻辑电路来实现仲裁电路和输出电路，可以缩短关键路径，提高的工作频率，使电路规模更小，功耗更低。
本申请还提供了一种芯片，该芯片可以包括图1、图3或图5加权轮询仲裁器。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种加权轮询仲裁器，包括：至少二个仲裁电路、一个优先级控制电路、一个权重控制电路和一个输出电路，
    其中，每一个所述仲裁电路与一个请求源连接；每个所述仲裁电路顺次连接形成环状，并分别与所述输出电路和所述优先级控制电路连接；所述输出电路与一个目标设备连接；所述优先级控制电路还分别与每个所述仲裁电路对应的请求源连接；所述权重控制电路与所述优先级控制电路连接；
    每一个所述仲裁电路响应于所述优先级控制电路发出的最高优先级控制信号，或者前一个所述仲裁电路基于所连接的请求源无请求发出的使能控制信号，将所连接的请求源发出的请求传输至所述输出电路，并通过所述输出电路发送至所述目标设备，或者基于所连接的请求源无请求向后一个所述仲裁电路发出所述使能控制信号；
    在所述权重控制电路中预先配置有每个所述请求源的权重值，所述优先级控制电路基于所述请求源预先配置的权重值调整所述最高优先级控制信号。
  2. 根据权利要求1所述的加权轮询仲裁器，其中，每一个所述仲裁电路包括第一或门、非门、第一与门和第二与门；
    所述第一或门的第一输入端与所述优先级控制电路的一个输出端连接，所述第一或门的第二输入端与前一个所述仲裁电路连接，所述第一或门的输出端分别与第一与门和第二与门的第一输入端连接；
    所述第一与门的第二输入端与对应的请求源连接，所述第一与门的输出端与所述输出电路的一个输入端连接；
    所述第二与门的第二输入端与所述非门的输出端连接，所述非门的输入端与对应的请求源连接，所述第二与门的输出端与后一个所述仲裁电路连接。
  3. 根据权利要求2所述的加权轮询仲裁器，其中，每个所述仲裁电路还分别与所述目标设备连接；
    每一个所述仲裁电路基于所述目标设备处于就绪状态将所连接的请求源发出的请求传输至所述输出电路。
  4. 根据权利要求3所述的加权轮询仲裁器，其中，每一个所述仲裁电路还包括第三与门；所述第三与门的第一输入端与所述第一与门的输出端连接，所述第三与门的第二输入端与所述目标设备连接，所述第三与门的输出端与对应的请求源连接。
  5. 根据权利要求3所述的加权轮询仲裁器，其中，所述优先级控制电路还与所述目标设备连接；
    所述优先级控制电路基于所述目标设备处于就绪状态发出所述最高优先级控制信号。
  6. 根据权利要求1至5中任一项所述的加权轮询仲裁器，其中，所述优先级控制电路确定当前具有最高优先级的有请求的一个所述仲裁电路；
    基于所确定的具有最高优先级的有请求的所述仲裁电路和预先设定的仲裁电路的优先级顺序，确定每个所述仲裁电路的优先级调整顺序；
    响应于所确定的具有最高优先级的有请求的所述仲裁电路所连接的请求源发出的请求的数量小于或者等于所述请求源预先配置的权重值，基于所确定的每个所述仲裁电路的优先级调整顺序，调整所述最高优先级控制信号。
  7. 根据权利要求6所述的加权轮询仲裁器，其中，所述优先级控制电路基于每个所述请求源均无请求，保持所述最高优先级控制信号不变。
  8. 根据权利要求1至5中任一项所述的加权轮询仲裁器，其中，所述输出电路包括第二或门，所述第二或门的输入端与每个所述仲裁电路连接，所述第二或门的输出端与所述目标设备连接。
  9. 一种加权轮询仲裁方法，应用于权利要求1至8中任一项所述的加权轮询仲裁器，所述方法包括：
    响应于所述优先级控制电路发出的最高优先级控制信号，确定一个当前具有最高优先级的所述仲裁电路；
    将所连接的请求源发出的请求传输至所述输出电路，并通过所述输出电路发送至所述目标设备，或者基于所连接的请求源无请求向后一个所述仲裁电路发出所述使能控制信号；
    响应于前一个所述仲裁电路基于所连接的请求源无请求发出的使能控制信号，将后一个所述仲裁电路作为当前具有最高优先级的所述仲裁电路；
    其中，所连接的请求源发出的请求的数量小于或者等于在所述权重控制电路中为所述请求源预先配置的权重值。
  10. 一种芯片，包括权利要求1至8中任一项所述的加权轮询仲裁器。
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