WO2024016557A1 - Shift register circuit and electronic device - Google Patents

Abstract

A shift register circuit and an electronic device, related to the technical field of integrated circuits. The shift register circuit comprises a number m of cascaded flip-flops, clock input terminals of at least some of the flip-flops among the 2nd stage to the m-th stage of flip-flops being provided with a clock control circuit, the clock control circuit receiving an initial clock signal, coupling a data input terminal of an n-th stage of flip-flops and a data output terminal of an (n+1)-th stage of flip-flops, and being used to control the (n+1)-th stage of flip-flops to perform data sampling when an instruction signal received at the data input terminal of the n-th stage of the flip-flops is an effective level, and to control the (n+1)-th stage of flip-flops to stop data sampling after the effective level of the instruction signal is outputted by the (n+1)-th stage of flip-flops. A shift register circuit capable of reducing power consumption is provided.

Description

Shift register circuits and electronic equipment

Cross-references to related applications

This application claims priority to the Chinese patent application with application number 202210870368.8 and titled "Shift Register Circuit and Control Method, Electronic Equipment" submitted on July 22, 2022. The entire content of this Chinese patent application is incorporated by reference in its entirety. Enter this article.

Technical field

The present disclosure relates to the field of integrated circuit technology, and specifically to a shift register circuit and electronic equipment.

Background technique

DDR5 SDRAM (Double Data Rate Fourth Synchronous Dynamic Random Access Memory, Double Data Rate Fourth Synchronous Dynamic Random Access Memory) is a synchronous DRAM memory. After issuing read and write commands, it needs to reach the DRAM pin within a predetermined delay time. foot.

DDR5 SDRAM uses a shift register circuit to implement delay. The shift register (Shift Register) is a device based on multiple flip-flops that works under several identical time pulses.

Normally, when the shift register is transmitting a signal, all flip-flops will continue to work. However, for each flip-flop, it only works effectively during the time when the signal is actually transmitted, and the other times are idling. , which will inevitably bring unnecessary power consumption.

Contents of the invention

According to a first aspect of the present disclosure, a shift register circuit is provided, including: m cascaded flip-flops, the data input terminal of each stage of the flip-flop is coupled to the data output terminal of the previous stage of the flip-flop. , the data input terminal of the flip-flop in the first level receives the command signal, and the clock input terminal of the flip-flop in the first level receives the initial clock signal; at least some of the triggers in the flip-flops in the second to mth levels The clock input end of the device is provided with a clock control circuit, the clock control circuit receives the initial clock signal and is coupled to the data input end of the n-th stage flip-flop and the data output end of the n+1-th stage flip-flop. , used to control the flip-flop at level n+1 to perform data sampling when the instruction signal received at the data input end of the flip-flop at level n is a valid level; when the valid level of the command signal is After the flip-flop at the n+1th level is output, the flip-flop at the n+1th level is controlled to stop data sampling; where m is a positive integer greater than or equal to 2, and n is a positive integer less than m.

In an exemplary implementation of the present disclosure, the clock control circuit includes: a judgment circuit, the input terminals of the judgment circuit are respectively coupled to the data input terminal of the n-th stage flip-flop and the n+1-th stage flip-flop. The data output end of the flip-flop is used to output a judgment result based on the level of the flip-flop data input end of the nth level and the level of the flip-flop data output end of the n+1th level; a clock signal shielding circuit is coupled to the judgment result A circuit configured to start or stop outputting the initial clock signal to the clock input terminal of the flip-flop at the n+1th stage according to the judgment result.

In an exemplary implementation of the present disclosure, the effective level of the instruction signal is a logic low level; the judgment circuit includes: a first switch tube, a second switch tube, a first NOR gate, a first inverter phase inverter and a second inverter; wherein, the gate of the first switch tube is coupled to the data input terminal of the n-th stage flip-flop, and the source stage of the first switch tube is coupled to the power supply voltage terminal, so The drain of the first switch tube is coupled to the drain of the second switch tube; the first input terminal of the first NOR gate is coupled to the output terminal of the first inverter, and the first inverter The input terminal of the phase converter is coupled to the data input terminal of the n-th stage flip-flop, and the second input terminal of the first NOR gate is coupled to the data output terminal of the n+1-th stage flip-flop; The gate of the two switching tubes is connected to the output terminal of the first NOR gate, the source of the second switching tube is grounded; the input terminal of the second inverter is connected to the drain of the first switching tube, The output terminal of the second inverter is used to output the judgment result.

In an exemplary implementation of the present disclosure, the effective level of the instruction signal is a logic high level; the judgment circuit includes: a first switch tube, a second switch tube, a first NOR gate, a first inverter inverter, a second inverter and a third inverter; wherein, the input terminal of the third inverter is coupled to the data input terminal of the n-th stage flip-flop, and the output of the third inverter The terminal is connected to the gate of the first switch, the source of the first switch is coupled to the power supply voltage terminal, and the drain of the first switch is coupled to the drain of the second switch; The first input terminal of the first NOR gate is coupled to the data input terminal of the n-th stage flip-flop, and the second input terminal of the first NOR gate is coupled to the output terminal of the first inverter, so The input terminal of the first inverter is coupled to the data output terminal of the n+1th stage flip-flop; the gate of the second switch tube is connected to the output terminal of the first NOR gate, and the second The source of the switch tube is grounded; the input terminal of the second inverter is connected to the drain of the first switch tube, and the output terminal of the second inverter is used to output the judgment result.

In an exemplary embodiment of the present disclosure, the judgment circuit further includes: a reset circuit; wherein the reset circuit is connected to the input end of the second inverter and the output end of the second inverter, Used to reset the input terminal of the second inverter according to the reset signal.

In an exemplary embodiment of the present disclosure, the reset circuit includes: a second NOR gate; wherein the first input terminal of the second NOR gate is connected to the output terminal of the second inverter, so The second input terminal of the second NOR gate is connected to the reset signal, and the output terminal of the second NOR gate is connected to the input terminal of the second inverter.

In an exemplary implementation of the present disclosure, the first switching transistor is a P-type MOS transistor, and the second switching transistor is an N-type MOS transistor.

In an exemplary implementation of the present disclosure, the clock signal shielding circuit includes: a third NOR gate; wherein the first input end of the third NOR gate receives the judgment result, and the third NOR gate The second input terminal of the NOT gate receives the initial clock signal, and the output terminal of the third NOR gate is used to output the initial clock signal.

In an exemplary embodiment of the present disclosure, the clock signal shielding circuit further includes: a first selection circuit; wherein the first selection circuit is configured to output the third NOR gate according to the first selection signal. The signal is selected for output.

In an exemplary embodiment of the present disclosure, the first selection circuit includes a first data selector; wherein the first input terminal of the first data selector is coupled to the output terminal of the third NOR gate. , the second input terminal of the first data selector is connected to a low level signal or a high level signal, and the selection terminal of the first data selector receives the first selection signal.

In an exemplary implementation of the present disclosure, at least part of the two adjacent flip-flops are connected through a second selection circuit; wherein the second selection circuit is used to select and output the instruction according to the second selection signal. signal, or select to output the signal output by the data output terminal of the flip-flop at the nth stage to the data input terminal of the flip-flop at the n+1th stage.

In an exemplary implementation of the present disclosure, the second selection circuit includes a second data selector, wherein a first input end of the second data selector is connected to the instruction signal, and the second data The second input terminal of the selector is connected to the data output terminal of the flip-flop of the nth stage, and the output terminal of the second data selector is connected to the data input terminal of the flip-flop of the n+1th stage. The second data The selection end of the selector receives the second selection signal.

In an exemplary implementation of the present disclosure, a delayer is further provided between the clock control circuit and the data output end of the n+1th stage flip-flop, and the delayer is used to The output signal of the data output terminal of the flip-flop is delayed.

In an exemplary implementation of the present disclosure, the delay time of the delayer is greater than or equal to the duration of the effective level of the instruction signal.

In an exemplary implementation of the present disclosure, the delay time of the delayer is greater than or equal to 1 clock cycle of the initial clock signal.

According to a second aspect of the present disclosure, an electronic device is provided, including the above-mentioned shift register circuit.

Description of drawings

Figure 1 schematically shows a structural diagram of a D flip-flop according to an exemplary embodiment of the present disclosure;

FIG. 2 schematically shows a structural diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

Figure 3 schematically shows a schematic structural diagram of a clock control circuit according to an exemplary embodiment of the present disclosure;

Figure 4 schematically shows a block diagram of a clock control circuit according to an exemplary embodiment of the present disclosure;

Figure 5 schematically shows a circuit diagram of a clock control circuit according to an exemplary embodiment of the present disclosure;

6 schematically illustrates a circuit diagram of another clock control circuit according to an exemplary embodiment of the present disclosure;

Figure 7 schematically shows a structural diagram of a second data selector according to an exemplary embodiment of the present disclosure;

Figure 8 schematically shows a timing diagram of a signal transmission process according to an exemplary embodiment of the present disclosure;

FIG. 9 schematically shows a timing diagram of another signal transmission process according to an exemplary embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art. The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.

The flowcharts shown in the figures are illustrative only and do not necessarily include all steps. For example, some steps can be decomposed, and some steps can be merged or partially merged, so the actual order of execution may change according to the actual situation. In addition, all the following terms "first", "second" and "third" are only for the purpose of distinction and should not be used to limit the present disclosure.

With the development of memory technology, DDR4 SDRAM (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory, the fourth generation of double data rate synchronous dynamic random access memory) and DDR5 SDRAM have emerged. Both DDR4 SDRAM and DDR5 SDRAM have relatively high performance. Low power supply voltage, high transmission rate, and the memory unit group (Bank Group) on it has the characteristics of independently starting operations such as reading and writing. In addition, compared to memories such as DDR3/DDR2, DDR4 and DDR5 are fast and power-saving, and can also enhance signal integrity and improve the reliability of data transmission and storage.

Both DDR4 and DDR5 are synchronous DRAM memories. In other words, if the read command is issued at x tCK time, then the DRAM internal data needs to arrive at the DRAM DQ/DQS pin at (x+RL)tCK time. If a write command is issued at y tCK time, then the sent data needs to be sent to the DRAM DQ/DQS pin at (y+WL)tCK time. It can be seen that after the read or write commands are issued, a certain delay is required to execute these commands.

In order to achieve the above delay, it can usually be achieved through a shift register circuit. Among them, the shift register (Shift Register) is a flip-flop-based device that works under several identical time pulses. Data can be input into the shift register in a parallel or serial manner, and then each time pulse is sequentially shifted one bit to the left or right and output at the output terminal. Shift registers have a wide range of application scenarios. For example, shift registers can be used to form counters, sequential pulse generators, serial accumulators, data converters for converting between serial data and parallel data, etc.

In a shift register, a flip-flop is a memory cell circuit with triggering characteristics, where triggering is a state refresh under the action of the edge of a clock pulse. Taking the D flip-flop as an example, as shown in Figure 1, the D flip-flop can capture the D terminal data on the rising edge of the clock CK and output it at the Q terminal until the next rising edge of the clock arrives, that is, the D flip-flop is on The rising edge of clock CK is triggered. During this period, data changes at the D terminal will not directly affect the output at the Q terminal. In addition, the D flip-flop will also implement the reset function according to the reset signal RST, which will not be described in detail here.

For a shift register circuit composed of multiple flip-flops, for example, the existing DFF (D type flip-flop) array composed of multiple D flip-flops, in the process of realizing delay, during the transmission During the entire process of a command signal CMD_IN, all DFFs are triggered in response to the clock signal. That is to say, when the current DFF transmits the effective level of the signal, other DFFs are also triggered. For other DFFs, this state It is an idling state, which will inevitably bring unnecessary power consumption.

Based on this, exemplary embodiments of the present disclosure provide a shift register circuit, which can be used not only in memories such as DRAM, but also in other electronic devices that require delay. The embodiment is not particularly limited in this regard.

Referring to FIG. 2 , a schematic structural diagram of a shift register circuit provided by an exemplary embodiment of the present disclosure is shown. As shown in Figure 2, the shift register circuit 200 includes: m cascaded flip-flops 210. The data input terminal of each stage flip-flop 210 is coupled to the data output terminal of the previous stage flip-flop 210. The coupling here is The connection may be a direct connection between two adjacent flip-flops 210 , or an indirect connection between two adjacent flip-flops 210 through other devices, which is not particularly limited in the exemplary embodiment of the present disclosure.

In the above-mentioned m cascaded flip-flops 210, the data input terminal (i.e., D terminal) of the first-stage flip-flop receives the command signal CMD_IN, and the clock input terminal (i.e., CK terminal) of the first-stage flip-flop receives the initial clock signal CLK. . In other words, the first-level flip-flop will continue to work when triggered by the initial clock signal CLK.

Relative to the first-level flip-flops, in the exemplary embodiment of the present disclosure, the clock input terminals (ie, CK terminals) of at least some of the second-level to m-th flip-flops may be provided with a clock control circuit 220, which is controlled by the clock. The circuit 220 can control the corresponding trigger 210 to be triggered to work only when the effective level of the command signal CMD_IN is transmitted, and can be turned off and not work at other times, thereby achieving the purpose of saving power consumption.

In practical applications, the above-mentioned clock control circuit 220 can be provided in all flip-flops 210 from the second-level flip-flop to the m-th level flip-flop, or the above-mentioned clock control circuit 220 can be provided only in some flip-flops 210. The exemplary embodiments of the present disclosure are not particularly limited in this regard.

In practical applications, m can be any positive integer greater than or equal to 2. The specific value of m can be determined according to the actual required delay size. In the shift register circuit shown in Figure 2, m is 6 . The exemplary embodiments of the present disclosure do not place special limitations on the specific value of m.

In an exemplary embodiment of the present disclosure, the clock control circuit 220 provided at the clock input terminals of at least some of the flip-flops of the second to mth stages can receive the initial clock signal CLK and be coupled to the nth stage flip-flops. Data input terminal and data output terminal of the n+1th level flip-flop. For example, as shown in Figure 2, the clock control circuit 220 provided at the clock input end of the second-level flip-flop, in addition to receiving the initial clock signal CLK, is also coupled to the data input end of the first-level flip-flop and the second-level flip-flop. The data output end; the clock control circuit 220 provided at the clock input end of the third-level flip-flop, in addition to receiving the initial clock signal CLK, is also coupled to the data input end of the second-level flip-flop and the data output of the third-level flip-flop. terminal, and by analogy, the clock control circuit 220 provided at the clock input terminal of the sixth-level flip-flop, in addition to receiving the initial clock signal CLK, is also coupled to the data input terminal of the fifth-level flip-flop and the data of the sixth-level flip-flop. output terminal. It should be noted that the coupling here may be a direct connection or an indirect connection.

Referring to FIG. 3 , a schematic structural diagram of a clock control circuit provided by an exemplary embodiment of the present disclosure is shown. As shown in Figure 3, the clock control circuit 220 includes a first data access terminal I1, a second data access terminal I2, a clock input terminal CKI and a clock output terminal CKO; wherein the first data access terminal I1 is connected to the nth The data input terminal (i.e., D terminal) of the level flip-flop, the second data access terminal I2 is connected to the data output terminal (i.e., Q terminal) of the n+1-th level flip-flop, and the clock input terminal CKI is used to receive the initial clock signal CLK. The clock output terminal CKO is connected to the clock input terminal (that is, the CK terminal) of the n+1-th stage flip-flop. The clock control circuit 220 is used to control the initial clock signal CLK received by the clock input terminal CKI to output or not output to the clock output terminal CKO according to the data input by the first data access terminal I1 and the second data access terminal I2, thereby achieving Control the clock signal input to the clock input end of the n+1-th level flip-flop, thereby achieving the purpose of controlling the switch of the n+1-th level flip-flop, that is, controlling the n+1-th level flip-flop to perform data sampling or stop data sampling. .

Specifically, in the exemplary embodiment of the present disclosure, the above-mentioned clock control circuit 220 is used to control the n+1th level trigger when the instruction signal received by the data input terminal (ie, D terminal) of the nth stage flip-flop is at a valid level. The device performs data sampling; in addition, after the effective level of the command signal is output by the n+1-th level flip-flop, that is, after being output by the Q terminal, the n+1-th level flip-flop is controlled to stop data sampling. It is equivalent to controlling the n+1th level flip-flop to open when it receives the command signal. After the n+1th level flip-flop outputs the command signal, it controls the n+1th level flip-flop to close, so that the n+1th level flip-flop is controlled to open. The n+1th level flip-flop is realized to work when transmitting the command signal and is closed at other times to achieve the purpose of saving power consumption.

In practical applications, the above n is a positive integer less than m.

Referring to FIG. 4 , a block diagram of a clock control circuit provided by an exemplary embodiment of the present disclosure is shown. As shown in Figure 4, the clock control circuit 220 includes a judgment circuit 221 and a clock signal shielding circuit 222; wherein,

The input terminals of the judgment circuit 221 are respectively coupled to the data input terminal (i.e., D terminal) of the n-th level flip-flop and the data output terminal (i.e., Q-terminal) of the n+1-th level flip-flop. The level of the input terminal and the level of the n+1th stage flip-flop data output terminal output the judgment result; that is to say, the judgment circuit 221 includes the first data access terminal I1 and the second data access terminal I2, and according to the first data connection The signals input from the input terminal I1 and the second data access terminal I2 output a judgment result.

The clock signal shielding circuit 222 is coupled to the judgment circuit 221 and is used to start or stop outputting the initial clock signal to the clock input terminal (ie, the CK terminal) of the n+1th stage flip-flop according to the judgment result. That is to say, when the initial clock signal is output to the clock input terminal of the n+1th level flip-flop according to the judgment result, the n+1th level flip-flop starts sampling; when the n+1th level flip-flop stops triggering to the n+1th level according to the judgment result. When the clock input terminal of the device outputs the initial clock signal, the n+1-th level flip-flop stops sampling. In this way, the n+1-th level flip-flop can work when transmitting signals and be turned off at other times, thereby saving power consumption.

In practical applications, the judgment circuit 221 is different depending on the effective level of the command signal.

Specifically, as shown in Figure 5, when the effective level of the command signal is a logic low level, that is, when the command signal CMD_IN is active at a low level, the above-mentioned judgment circuit 221 may include: a first switch 2211, a second switch tube 2212, the first NOR gate 2213, the first inverter 2214 and the second inverter 2215; wherein, the gate of the first switch tube 2211 is coupled to the data input end of the n-th stage flip-flop (i.e. the first data Input terminal I1), the source of the first switching tube 2211 is coupled to the power supply voltage terminal VDD, the drain of the first switching tube 2211 is coupled to the drain of the second switching tube 2212; the first input of the first NOR gate 2213 The first NOR gate 2213 The second input terminal of is coupled to the data output terminal of the n+1-th stage flip-flop (ie, the second data access terminal I2). The gate of the second switching tube 2212 is connected to the output terminal of the first NOR gate 2213, and the source of the second switching tube 2212 is grounded; the input terminal of the second inverter 2215 is connected to the drain of the first switching tube 2211, and the second switching tube 2212 is grounded. The output terminal of the inverter 2215 is used to output the judgment result.

In practical applications, both the first switch transistor 2211 and the second switch transistor 2212 may be MOS transistors or thin film transistors. Further, MOS tubes are divided into P-type MOS tubes and N-type MOS tubes, and the thin film transistors can be P-type thin film transistors or N-type thin film transistors. Due to the high mobility of polysilicon thin film transistors, they are particularly suitable for use in shift registers.

In an exemplary embodiment of the present disclosure, taking the first switching transistor 2211 as a P-type MOS transistor and the second switching transistor 2212 as an N-type MOS transistor as an example, the working principle of the above-mentioned judgment circuit 221 is described in detail as follows:

First of all, for P-type MOS transistors, they only conduct when the signal input to the gate is low level; for N-type MOS transistors, they only conduct when the signal input to the gate is high level.

Based on this, for the judgment circuit 221 shown in FIG. 5 , when the data input terminal of the n-th stage flip-flop coupled to the gate of the first switch tube 2211 is a logic low level 0, that is, the first data access terminal I1 When receiving the logic low level 0, the first switch tube 2211 is turned on; since the source stage of the first switch tube 2211 is coupled to the power supply voltage terminal VDD, therefore, after the first switch tube 2211 is turned on, the first switch tube 2211 The drain outputs a logic high level 1 to the input terminal of the second inverter 2215 .

At this time, since the first input terminal of the first NOR gate 2213 is coupled to the data input terminal of the n-th level flip-flop, that is to say, the logic low level 0 received by the first data access terminal I1 will also Input to the first input terminal of the first NOR gate 2213; and since the first input terminal of the first NOR gate 2213 is provided with the first inverter 2214, the voltage entering the first input terminal of the first NOR gate 2213 level will become a logic high level 1. For the first NOR gate 2213, no matter whether the level connected to its second input terminal is a logic high level or a logic low level, the first NOR gate 2213 The outputs are all logic low 0. That is to say, no matter whether the second data access terminal I2 receives a logic high level 1 or a logic low level 0, the output of the first NOR gate 2213 is a logic low level 0. Since the first NOR gate 2213 outputs a logic low level 0, and the second switch transistor 2212, which is an N-type MOS transistor, is conductive at a high level, therefore, the second switch transistor 2212 is not conductive. That is to say, when the data input terminal of the n-th stage flip-flop is a logic low level 0, that is, when the first data access terminal I1 receives a logic low level 0, the drain of the first switch tube 2211 will A logic high level 1 is output to the input terminal of the second inverter 2215.

After receiving the logic high level 1 output by the drain of the first switch tube 2211, the input terminal of the second inverter 2215 inverts the logic high level 1 to obtain a logic low level 0, that is, Say, the judgment result output by the output terminal of the second inverter 2215 is logic low level 0.

In an exemplary embodiment of the present disclosure, based on the above-mentioned judgment circuit 221, as shown in FIG. 5, the clock signal shielding circuit 222 included in the clock control circuit 220 may include a third NOR gate 2221; wherein, the third OR The first input terminal of the NOT gate 2221 receives the above judgment result, the second input terminal of the third NOR gate 2221 receives the initial clock signal CLK, and the output terminal of the third NOR gate 2221 is used to selectively output the initial clock signal CLK. .

When the judgment result is logic low level 0, the judgment result input to the first input terminal of the third NOR gate 2221 will not generate a signal for the initial clock signal CLK connected to the second input terminal of the third NOR gate 2221 Shielding effect. At this time, the third NOR gate 2221 outputs the initial clock signal CLK. That is to say, when the data input terminal of the n-th stage flip-flop is a logic low level 0, that is, the first data access terminal I1 receives a logic low level. 0, no matter whether the second data access terminal I2 receives a logic high level 1 or a logic low level 0, the initial clock signal CLK is output to the clock input terminal of the n+1th stage flip-flop, so that the nth The +1-level flip-flop is in the working state, that is, the status (Status) of the signal received by the clock input terminal of the n+1-th level flip-flop is in the Toggle state, as shown in the truth table in Table 1.

Table 1

I1	I2		Status
0	0	Toggle
0	1	Toggle
1	0	Block
1	1	Reserved

As shown in Table 1, when the first data access terminal I1 receives a logic high level 1 and the second data access terminal I2 receives a logic low level 0, that is to say, at the nth level When the data input terminal of the flip-flop is a logic high level 1 and the data output terminal of the n+1th stage flip-flop is a logic low level 0, for the judgment circuit 221 and the clock signal shielding circuit 222 shown in Figure 5 In other words, the gate of the first switch transistor 2211 is connected to a logic high level 1. Since the P-type MOS is conductive at a low level, the first switch transistor 2211 is not conductive at this time.

At this time, since the logic high level 1 received by the first data access terminal I1 passes through the first inverter 2214 and then is input to the first input terminal of the first NOR gate 2213, the second input terminal of the first NOR gate 2213 What the input terminal receives is the logic low level 0 received by the second data access terminal I2. That is to say, the two data input to the first NOR gate 2213 are both logic low level 0. Through the first NOR gate 2213, the logic low level 0 is received. After gate 2213, the output is a logic high level 1. At this time, the second switch tube 2212, which is an N-type MOS tube, is turned on. Since the source of the second switch tube 2212 is grounded, the input to the second inverting Device 2215 is a logic low level 0. After the logic low level 0 is inverted, the judgment result is a logic high level 1.

After the logic high level 1 of the above determination result enters the third NOR gate 2221 of the clock signal shielding circuit 222, it will have a shielding effect on the initial clock signal CLK connected to the second input terminal of the third NOR gate 2221. At this time, the third NOR gate 2221 will not output the initial clock signal CLK, and the clock input terminal of the n+1th stage flip-flop cannot receive the initial clock signal CLK, that is, the clock input terminal of the n+1th stage flip-flop receives The signal is no longer toggled, the n+1th level trigger is not triggered, stops working, and is in a closed state. That is to say, the data input terminal of the n-th level flip-flop is a logic high level 1, that is, the first data access terminal I1 receives a logic high level 1, and the data output terminal of the n+1-th level flip-flop outputs a logic low level. Level 0, that is, when the second data access terminal I2 receives the logic low level 0, it stops outputting the initial clock signal CLK to the clock input terminal of the n+1-th level flip-flop, so that the n+1-th level flip-flop does not Being triggered, it is in a closed state, that is, the status Status of the clock input terminal of the n+1-th level flip-flop is a shielded (Block) state, as shown in the truth table in Table 1.

In addition, when the first data access terminal I1 receives a logic high level 1, and the second data access terminal I2 also receives a logic high level 1, that is to say, the data of the nth level flip-flop When the input terminal is a logic high level 1 and the data output terminal of the n+1th stage flip-flop is also a logic high level 1, for the judgment circuit 221 and the clock signal shielding circuit 222 shown in Figure 5, since The input to the gate of the first switch 2211 is a logic high level 1, and the first switch 2211, which is a P-type MOS transistor, is not conductive; because the input to the gate of the second switch 2212 is a logic low level 0 , the second switch transistor 2212, which is an N-type MOS transistor, is also not turned on.

In this case, a reset circuit 2216 can be provided in the judgment circuit 221, as shown in Figure 5. The reset circuit 2216 is connected to the input terminal of the second inverter 2215 and the output terminal of the second inverter 2215. The reset circuit 2216 is used to reset the input terminal of the second inverter 2215 according to the reset signal RST. In addition, the reset circuit 2216 can also be configured as a device with a latch function as needed, so that it can latch the previously output judgment result.

In other words, the reset circuit 2216 can determine the output when the first data access terminal I1 receives a logic high level 1 and the second data access terminal I2 receives a logic low level 0. The result is latched. When neither the first switch tube 2211 nor the second switch tube 2212 is conductive, the judgment result output by the judgment circuit 221 is still a logic high level 1. Finally, after passing through the clock signal shielding circuit 222, The previous state will be maintained and the initial clock signal CLK will not be output, that is, the status of the n+1th level flip-flop is the Reserved state, as shown in the truth table in Table 1.

According to the truth table 1, it can be seen that when the first data access terminal I1 receives a logic low level 0, no matter whether the second data access terminal I2 receives a logic high level 1 or a logic Low level 0, the signals at the clock input end of the n+1-th level flip-flop are all in the Toggle state, that is, the n+1-th level flip-flop is in the working state, that is, as long as the data input end of the n-th level flip-flop receives The effective level of the command signal, the n+1th level flip-flop is in working state; the first data access terminal I1 receives a logic high level 1, and the second data access terminal I2 receives a logic low level When the level is 0, the signal at the clock signal input end of the n+1th level flip-flop is no longer toggled and is in the Block state, that is, the n+1th level flip-flop is not triggered and enters the closed state. That is to say, in the instruction When the effective level of the signal is output by the n+1-th level flip-flop, the n+1-th level flip-flop is not triggered and is in a closed state; then, it is received at the first data access terminal I1 and the second data access terminal I2 When all the signals are logic high level 1, the signal at the clock signal input end of the n+1th level flip-flop will maintain the state of the previous stage and be in the Reserved state, that is, the n+1th level flip-flop remains closed. The status remains unchanged.

In this way, it can be ensured that the n+1-th level flip-flop is only in the working state when the effective level of the command signal reaches the n-th level flip-flop and comes out of the n+1-th level flip-flop, that is, it only transmits the command signal. When the level is valid, the n+1th level flip-flop is in the working state, and is in the off state at other times, thereby achieving the purpose of reducing power consumption and saving energy.

As shown in Figure 6, when the effective level of the command signal is a logic high level, that is, when the command signal CMD_IN is active at a high level, the above-mentioned judgment circuit 221 may include: a first switch tube 2211, a second switch tube 2212, The first NOR gate 2213, the first inverter 2214, the second inverter 2215 and the third inverter 2217; wherein, the input terminal of the third inverter 2217 is coupled to the data input terminal of the n-th stage flip-flop. (i.e., the first data access terminal I1), the output terminal of the third inverter 2217 is connected to the gate of the first switch tube 2211, the source stage of the first switch tube 2211 is coupled to the power supply voltage terminal VDD, and the first switch tube 2211 The drain of is coupled to the drain of the second switch 2212; the first input terminal of the first NOR gate 2213 is coupled to the data input terminal of the n-th stage flip-flop (i.e., the first data access terminal I1). The second input terminal of the NOT gate 2213 is coupled to the output terminal of the first inverter 2214, and the input terminal of the first inverter 2214 is coupled to the data output terminal (i.e., the second data access terminal) of the n+1th stage flip-flop. I2). The gate of the second switching tube 2212 is connected to the output terminal of the first NOR gate 2213, and the source of the second switching tube 2212 is grounded; the input terminal of the second inverter 2215 is connected to the drain of the first switching tube 2211, and the second switching tube 2212 is grounded. The output terminal of the inverter 2215 is used to output the judgment result.

Compared with the judgment circuit in Figure 5 when the effective level of the command signal is a logic low level, the judgment circuit in Figure 6 when the effective level of the command signal is a logic high level only detects I1 and I2 After inversion, the subsequent circuit structure and working principle are the same and will not be described again here. When the effective level of the command signal is a logic high level, the obtained truth table is shown in Table 2:

Table 2

I1	I2	Status
1	1	Toggle
1	0	Toggle
0	1	Block
0	0	Reserved

In an exemplary embodiment of the present disclosure, the reset circuit 2216 may include a second NOR gate, the first input terminal of the second NOR gate is connected to the output terminal of the second inverter 2215, and the second input terminal of the second NOR gate terminal is connected to the reset signal RST, and the output terminal of the second NOR gate is connected to the input terminal of the second inverter 2215. When the reset signal RST is high level 1, the level of the clock input terminal of the n+1th stage flip-flop can be preset to high level or low level.

In practical applications, the clock signal shielding circuit 222 may also include a first selection circuit 2222, which is used to select and output the signal output by the third NOR gate 2221 according to the first selection signal SEL1. Specifically, the first selection circuit 2222 may include a first data selector, the first input terminal of the first data selector is coupled to the output terminal of the third NOR gate 2221, and the second input terminal of the first data selector is coupled to The low-level signal VSS or the high-level signal VDD is input, and the selection terminal of the first data selector receives the first selection signal SEL1.

As shown in Figure 5, when the second input end of the first data selector is connected to the low-level signal VSS, the first data selector can be determined based on the reset signal RST and the first selection signal SEL1. The signal output by the clock output terminal CKO. Specifically, as shown in the truth table 3, when the reset signal RST and the first selection signal SEL1 are both low level 0, the signal output by the clock output terminal CKO of the first data selector is determined by the truth table 1 or the true value. Table 2 determines that when the reset signal RST is low level 0 and the first selection signal SEL1 is high level 1, the signal output by the clock output terminal CKO of the first data selector is a Low level signal; When the reset signal RST is high level 1 and the first selection signal SEL1 is low level 0, the signal output by the clock output terminal CKO of the first data selector is a High high level signal; when the reset signal RST is high level Level 1, when the first selection signal SEL1 is high level 1, the signal output by the clock output terminal CKO of the first data selector is a Low level signal.

table 3

RST	SEL1		CKO
0	0	Table 1 or Table 2
0	1	Low
1	0	High
1	1	Low

In an exemplary embodiment of the present disclosure, at least part of two adjacent flip-flops 210 may also be connected through a second selection circuit 230, as shown in FIG. 2 . The second selection circuit 230 is used to select and output the command signal CMD_IN according to the second selection signal SEL2, or to select and output the signal output by the data output terminal of the n-th stage flip-flop to the data input terminal of the n+1-th stage flip-flop.

In practical applications, the above-mentioned second selection circuit 230 may include a second data selector, the first input terminal of the second data selector is used to access the command signal CMD_IN, and the second input terminal of the second data selector The data output end of the second data selector is used to connect the data output end of the n-th level flip-flop. The output end of the second data selector is used to connect the data input end of the n+1-th level flip-flop. The selection end of the second data selector receives the second selection signal. SEL2.

Referring to FIG. 7 , a schematic structural diagram of a second data selector in an exemplary embodiment of the present disclosure is shown. For the second data selector shown in Figure 7, when the second selection signal SEL2 is low level 0, the second data selector selects and outputs the signal output by the data output terminal of the n-th stage flip-flop, that is to say , the command signal CMD_IN is transmitted through the flip-flop, which is equivalent to delaying the command signal CMD_IN through the flip-flop; when the second selection signal SEL2 is high level 1, the second data selector will directly output the command signal CMD_IN, That is to say, the command signal CMD_IN is not delayed from passing through the flip-flop.

For the shift register circuit with six flip-flops 210 (DFF0-DFF5) shown in Figure 2, if a second data selector as shown in Figure 7 is set between two adjacent flip-flops 210, Moreover, the clock input terminals of the five flip-flops 210 of DFF1 to DFF5 are all provided with a clock control circuit 220. Therefore, the transmission method of the command signal CMD_IN is also different according to the second selection signal SEL2.

In the case of SEL2<N:0>=<000000>, since SEL2<*>=0, the output Q of the data output terminal of the n-th level flip-flop is passed on from the n+1-th level flip-flop, from its corresponding It can be seen from the timing diagram shown in Figure 8 that the first-level flip-flop DFF0 is always in working state, and the second-level to sixth-level flip-flops only work when transmitting valid signals. From the first-level flip-flop to the sixth level, The trigger command signal CMD_IN is delayed.

In the case of SEL2<N:0>=<110000>, since SEL2<*>=0, the output Q of the data output terminal of the n-th flip-flop is passed on from the n+1-th flip-flop, SEL2<*> =1, the initial command signal CMD_IN is selected to be passed, and the output Q of the data output terminal of the n-th level flip-flop is not passed on. Combined with the corresponding timing diagram in Figure 9, it can be seen that the input signal D of the first-level flip-flop to the third-level flip-flop (DFF0-DFF2) is the command signal CMD_IN, and the fourth-level flip-flop to the sixth-level flip-flop (DFF0-DFF2) The input signal of DFF3-DFF5) is the output signal Q of the previous stage flip-flop. Starting from the output of the third-stage flip-flop DFF2, the command signal CMD_IN is delayed at each stage. Similarly, the first-level flip-flop DFF0 is always in working state, and the second-level to sixth-level flip-flops only work when valid signals are transmitted.

In an exemplary embodiment of the present disclosure, as shown in FIG. 2 , a delayer 240 is further provided between the clock control circuit 220 and the data output end of the n+1th stage flip-flop. The delayer 240 is used to control the n+1th level flip-flop. The output signal of the data output terminal of the 1-level flip-flop is delayed, thereby preventing the effective level of the command signal CMD_IN from being transmitted correctly due to premature closure of the n+1-th level flip-flop.

In practical applications, the delay time of the delayer 240 can be determined according to the actual situation. For example, the delay time of the delayer 240 can be greater than or equal to the duration of the effective level of the command signal CMD_IN, or the delayer 240 The delay time is greater than or equal to 1 clock cycle of the initial clock signal CLK. In addition, the delay time of the delay device 240 can also be set to be less than or equal to 3 clock cycles of the initial clock signal CLK to achieve the purpose of saving power consumption.

The shift register circuit provided by the exemplary embodiment of the present disclosure can control the flip-flop to work only during the time when transmitting valid signals by setting a corresponding clock control circuit for the flip-flop, and to be in a closed state at other times, thereby achieving savings. power consumption purposes.

Further, exemplary embodiments of the present disclosure also provide an electronic device, which may include the above-mentioned shift register circuit. The specific structure and working principle of the shift register circuit have been described in detail in the foregoing embodiments, and therefore will not be described again here.

It should be noted that the above-mentioned electronic device can be any device that requires the use of a shift register, such as DDR4 SDRAM, DDR5 SDRAM, various memories, etc.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When computer program instructions are loaded and executed on a computer, processes or functions described in accordance with embodiments of the present disclosure are produced in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or include one or more data storage devices such as servers and data centers that can be integrated with the medium. The available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, solid state disk (SSD)), etc. In the embodiment of the present disclosure, the computer may include the aforementioned device.

Although the present disclosure has been described herein in connection with various embodiments, in practicing the claimed disclosure, those skilled in the art will understand and understand by reviewing the drawings, the disclosure, and the appended claims. Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may perform several of the functions recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not mean that a combination of these measures cannot be combined to advantageous effects.

Although the present disclosure has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made without departing from the spirit and scope of the disclosure. Accordingly, the specification and drawings are intended to be merely illustrative of the disclosure as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations, or equivalents within the scope of the disclosure. Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims (16)

1. A shift register circuit including:

   m cascaded flip-flops, the data input end of the flip-flop at each level is coupled to the data output end of the flip-flop at the previous level, the data input end of the flip-flop at the first level receives the command signal, and the data input end of the flip-flop at the first level receives the command signal. The clock input terminal of the flip-flop receives an initial clock signal;

   The clock input terminals of at least some of the flip-flops in the second to mth stages are provided with a clock control circuit. The clock control circuit receives the initial clock signal and is coupled to the nth stage flip-flops. The data input terminal and the data output terminal of the flip-flop of the n+1th stage are used to control the n+1th stage when the instruction signal received by the data input terminal of the flip-flop of the nth stage is a valid level. The flip-flop performs data sampling; after the effective level of the instruction signal is output by the flip-flop of the n+1th level, the flip-flop of the n+1th level is controlled to stop data sampling; wherein,

   m is a positive integer greater than or equal to 2, and n is a positive integer less than m.
2. The shift register circuit of claim 1, wherein the clock control circuit includes:

   Determination circuit, the input end of the determination circuit is respectively coupled to the data input end of the flip-flop at the nth level and the data output end of the flip-flop at the n+1th level, used to determine the data of the flip-flop at the nth level. The level of the input terminal and the level of the flip-flop data output terminal of the n+1th level output the judgment result;

   A clock signal shielding circuit, coupled to the judgment circuit, is used to start or stop outputting the initial clock signal to the clock input end of the n+1-th flip-flop according to the judgment result.
3. The shift register circuit according to claim 2, wherein the effective level of the instruction signal is a logic low level;

   The judgment circuit includes: a first switching tube, a second switching tube, a first NOR gate, a first inverter and a second inverter; wherein,

   The gate of the first switch is coupled to the data input terminal of the n-th flip-flop, the source of the first switch is coupled to the power supply voltage terminal, and the drain of the first switch is coupled to the The drain of the second switch tube;

   The first input terminal of the first NOR gate is coupled to the output terminal of the first inverter, and the input terminal of the first inverter is coupled to the data input terminal of the n-th stage flip-flop, so The second input terminal of the first NOR gate is coupled to the data output terminal of the n+1th stage flip-flop;

   The gate of the second switch tube is connected to the output end of the first NOR gate, and the source of the second switch tube is connected to ground;

   The input terminal of the second inverter is connected to the drain of the first switch tube, and the output terminal of the second inverter is used to output the judgment result.
4. The shift register circuit according to claim 2, wherein the effective level of the instruction signal is a logic high level;

   The judgment circuit includes: a first switching tube, a second switching tube, a first NOR gate, a first inverter, a second inverter and a third inverter; wherein,

   The input terminal of the third inverter is coupled to the data input terminal of the n-th stage flip-flop, and the output terminal of the third inverter is coupled to the gate of the first switch tube. The source stage of the tube is coupled to the power supply voltage terminal, and the drain of the first switch tube is coupled to the drain of the second switch tube;

   The first input terminal of the first NOR gate is coupled to the data input terminal of the n-th stage flip-flop, and the second input terminal of the first NOR gate is coupled to the output terminal of the first inverter. , the input terminal of the first inverter is coupled to the data output terminal of the n+1th stage flip-flop;

   The gate of the second switch tube is connected to the output end of the first NOR gate, and the source of the second switch tube is connected to ground;

   The input terminal of the second inverter is connected to the drain of the first switch tube, and the output terminal of the second inverter is used to output the judgment result.
5. The shift register circuit according to claim 3 or 4, wherein the judgment circuit further includes: a reset circuit; wherein,

   The reset circuit is connected to the input terminal of the second inverter and the output terminal of the second inverter, and is used to reset the input terminal of the second inverter according to a reset signal.
6. The shift register circuit according to claim 5, wherein the reset circuit includes: a second NOR gate; wherein,

   The first input terminal of the second NOR gate is connected to the output terminal of the second inverter, the second input terminal of the second NOR gate is connected to the reset signal, and the output terminal of the second NOR gate terminal is connected to the input terminal of the second inverter.
7. The shift register circuit according to claim 3 or 4, wherein the first switch tube is a P-type MOS tube, and the second switch tube is an N-type MOS tube.
8. The shift register circuit according to any one of claims 2-4, wherein the clock signal shielding circuit includes: a third NOR gate; wherein,

   The first input terminal of the third NOR gate receives the judgment result, the second input terminal of the third NOR gate receives the initial clock signal, and the output terminal of the third NOR gate is used to output the initial clock signal.
9. The shift register circuit according to claim 8, wherein the clock signal shielding circuit further includes: a first selection circuit; wherein,

   The first selection circuit is configured to select and output the signal output by the third NOR gate according to the first selection signal.
10. The shift register circuit of claim 9, wherein the first selection circuit includes a first data selector; wherein,

    The first input terminal of the first data selector is coupled to the output terminal of the third NOR gate, and the second input terminal of the first data selector is coupled to a low level signal or a high level signal, so The selection end of the first data selector receives the first selection signal.
11. The shift register circuit according to claim 1, wherein at least part of the flip-flops of two adjacent stages are connected through a second selection circuit; wherein,

    The second selection circuit is used to select and output the command signal according to the second selection signal, or to select and output the signal output by the data output terminal of the n-th stage flip-flop to the data input of the n+1-th stage flip-flop. end.
12. The shift register circuit of claim 11, wherein the second selection circuit includes a second data selector, wherein,

    The first input end of the second data selector is connected to the instruction signal, and the second input end of the second data selector is connected to the data output end of the nth stage flip-flop. The second data selector The output end of the trigger is connected to the data input end of the flip-flop of the n+1th stage, and the selection end of the second data selector receives the second selection signal.
13. The shift register circuit according to claim 2, wherein a delayer is further provided between the clock control circuit and the data output end of the n+1th stage flip-flop, and the delayer is used to The output signal of the data output terminal of the flip-flop at level n+1 is delayed.
14. The shift register circuit according to claim 13, wherein the delay time of the delayer is greater than or equal to the duration of the effective level of the command signal.
15. The shift register circuit according to claim 13 or 14, wherein the delay time of the delayer is greater than or equal to 1 clock cycle of the initial clock signal.
16. An electronic device including the shift register circuit according to any one of claims 1-15.

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