WO2024016540A1

WO2024016540A1 - Chip system

Info

Publication number: WO2024016540A1
Application number: PCT/CN2022/133276
Authority: WO
Inventors: 田应超; 刘天建; 曹瑞霞; 王逸群; 谢冬
Original assignee: 湖北三维半导体集成创新中心有限责任公司; 湖北江城实验室
Priority date: 2022-07-21
Filing date: 2022-11-21
Publication date: 2024-01-25
Also published as: CN114937659B; CN114937659A

Abstract

The present disclosure provides a chip system. The chip system comprises: a first substrate; a plurality of first functional chips arranged in an array on the first substrate; and a plurality of second functional chips located on the surfaces of the first functional chips; wherein the first functional chips and the second functional chips have different types of functions; the projection of each second functional chip on the first substrate at least partially overlaps the projections of at least two first functional chips on the first substrate, respectively; the second functional chip and the at least two first functional chips are bonded in the overlapping areas; a multi-path connection channel is provided between the first functional chips and the second functional chip which are bonded; and the multi-path connection channel is configured to provide signal communication between the second functional chip and the at least two first functional chips.

Description

chip system

Cross-references to related applications

This application is based on a Chinese patent application with application number 202210858221.7, the filing date is July 21, 2022, and the application name is "Chip System", and claims the priority of the Chinese patent application. The full content of the Chinese patent application is here This application is incorporated by reference.

Technical field

The present disclosure relates to the field of semiconductor technology, and is related to but not limited to a chip system.

Background technique

With the advent of the big data era, the rapid development of 5G and AIoT has placed higher and higher requirements on chip performance, mainly reflected in large capacity, high bandwidth, high computing speed, low latency, etc.; however, the development of Moore's Law has slowed down. , the device characteristic size has approached the physical limit, and material and process research and development have also encountered bottlenecks. Three-dimensional integration technology changes the two-dimensional chip interconnection structure into three-dimensional interconnection, which greatly increases the packaging density and thus improves chip performance.

However, existing three-dimensional integration technologies tend to build a small number of chips with different functions into small chip systems. When facing the demand for ultra-high computing power and ultra-high bandwidth in supercomputers, servers, switches, etc., it is still necessary to interconnect the small chip systems that have been built and piece them together into a very large chip system. This will result in a larger chip system. large, and the interconnection speed is also lower.

Contents of the invention

In view of this, embodiments of the present disclosure provide a chip system, including:

first substrate;

A plurality of first functional chips arranged in an array on the first substrate; and

a plurality of second functional chips located on the surface of the first functional chip;

Wherein, the first functional chip and the second functional chip have different types of functions; the projection of each second functional chip on the first substrate is respectively different from that of at least two first functional chips. The projections on the first substrate at least partially overlap; the second functional chip and at least two of the first functional chips are bonded and connected in the overlapping area;

There are multiple connection channels between the first functional chip and the second functional chip that are bonded together; the multiple connection channels are configured to connect the second functional chip with at least two of the first functional chips. There is signal communication between chips.

In some embodiments, any four adjacent first functional chips are connected to the same second functional chip.

In some embodiments, the first functional chip includes a functional module;

The second functional chip includes at least one core module and a plurality of interconnection modules; the interconnection module is located in an area of the second functional chip that overlaps the first functional chip, and the core module is located in the first functional chip. The area in the dual-function chip other than the interconnection module.

In some embodiments, the functional module includes a processor; the core module includes a memory, and the interconnect module includes a memory controller.

In some embodiments, the functional module includes a programmable logic unit; the core module includes a switch unit, and the interconnection module includes a connection unit.

In some embodiments, there is a gap between adjacent first functional chips;

The second functional chip is connected to the first substrate through a first interconnection structure in the area where the gap is located.

In some embodiments, the chip system further includes:

A plurality of third functional chips located on the second functional chip and arranged in an array;

Wherein, the third functional chip and the second functional chip have different types of functions; the projection of each second functional chip on the first substrate is respectively different from that of at least two third functional chips. The projections on the first substrate at least partially overlap; the second functional chip and at least two third functional chips are bonded and connected in the overlapping area;

There are multiple connection channels between the bonded third functional chip and the second functional chip; the multiple connection channels are configured to connect the second functional chip with at least two of the third functional chips. There is signal communication between chips.

In some embodiments, the projection of the third functional chip on the first substrate overlaps with the projection of the first functional chip on the first substrate;

There is a second interconnection structure between the third functional chip and the first functional chip.

In some embodiments, the chip system further includes:

Wherein, the third functional chip and the second functional chip have different types of functions; the projection of each third functional chip on the first substrate is respectively different from that of at least two second functional chips. The projections on the first substrate at least partially overlap; the third functional chip and at least two second functional chips are bonded and connected in the overlapping area;

There are multiple connection channels between the bonded third functional chip and the second functional chip; the multiple connection channels are configured to connect the third functional chip with at least two of the second functional chips. There is signal communication between chips.

In some embodiments, the chip system further includes:

Multiple input and output chips;

Any one of the input and output chips is connected to at least one of the first functional chip or the second functional chip.

In some embodiments, the input/output chip is located at the edge of the first substrate; among the plurality of first functional chips arranged in the array, the first functional chip close to the edge of the first substrate is different from the input/output chip. The chips are connected through the first substrate.

In some embodiments, the input/output chip is located in the gap between any two adjacent first functional chips, and the input/output chip is located within the coverage of the second functional chip;

The input-output chip is bonded and connected to the second functional chip, and the input-output chip is also bonded and connected to the first substrate.

In some embodiments, the input-output chip is located adjacent to the second functional chip on the first functional chip;

The projection of the input/output chip on the first substrate overlaps with two adjacent first functional chips respectively, and the input/output chip and the first functional chip are bonded and connected in the overlapping area. .

In some embodiments, the chip system further includes:

a second substrate covering the second functional chip and the input/output chip;

The second substrate is bonded and connected to the input/output chip, and there is an input/output channel between the input/output chip and the second substrate;

The second substrate has a rewiring layer; the rewiring layer has a signal channel connecting the input and output chip and the surface of the second substrate.

In some embodiments, the chip system further includes:

A heat dissipation structure covering the first functional chip and the second functional chip;

Wherein, the heat dissipation structure is in contact with the surface of the first functional chip in an area covering the surface of the first functional chip; the heat dissipation structure covers an area of the surface of the second functional chip and the surface of the second functional chip. Contact; the heat dissipation structure is in contact with the first substrate in a region covering the exposed first substrate between the first functional chips.

In some embodiments, the heat dissipation structure includes a plurality of protruding structures;

The protruding structure located in the area covering the first functional chip extends toward the surface of the first functional chip and contacts the first functional chip;

The protruding structure located in the area covering the exposed first substrate between the first functional chips extends toward the first substrate and contacts the first substrate.

Description of drawings

Figure 1 is a schematic diagram of a chip system provided by an embodiment of the present disclosure;

Figure 2 is a top view of a chip system provided by an embodiment of the present disclosure;

Figure 3 is a top view of another chip system provided by an embodiment of the present disclosure;

Figure 4 is a schematic diagram of a first interconnection structure in a chip system provided by an embodiment of the present disclosure;

Figure 5 is a schematic diagram of a third functional chip in a chip system provided by an embodiment of the present disclosure;

Figure 6 is a schematic diagram of a third functional chip in another chip system provided by an embodiment of the present disclosure;

Figure 7 is a top view of an input and output chip in a chip system provided by an embodiment of the present disclosure;

Figure 8 is a cross-sectional view of an input and output chip in a chip system provided by an embodiment of the present disclosure;

Figure 9 is a top view of an input and output chip in another chip system provided by an embodiment of the present disclosure;

Figure 10 is a cross-sectional view of an input and output chip in another chip system provided by an embodiment of the present disclosure;

Figure 11 is a top view of an input and output chip in yet another chip system provided by an embodiment of the present disclosure;

Figure 12 is a cross-sectional view of an input and output chip in yet another chip system provided by an embodiment of the present disclosure;

Figure 13 is a schematic diagram of a second substrate in a chip system provided by an embodiment of the present disclosure;

Figure 14 is a top view of a heat dissipation structure in a chip system provided by an embodiment of the present disclosure;

Figure 15 is a cross-sectional view of a heat dissipation structure in a chip system provided by an embodiment of the present disclosure;

Figure 16 is a cross-sectional view of the heat dissipation structure in another direction in a chip system provided by an embodiment of the present disclosure;

Figure 17 is a schematic diagram of another chip system provided by an embodiment of the present disclosure.

Detailed ways

To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are given in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features well-known in the art are not described; that is, all features of the actual embodiments may not be described here, and well-known functions and structures may not be described in detail.

Generally, terms can be understood, at least in part, from context of use. For example, depending at least in part on context, the term "one or more" as used herein may be used in the singular to describe any feature, structure or characteristic, or may be used in the plural to describe a combination of features, structures or characteristics. . Similarly, terms such as "a" or "the" may equally be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on context.

Unless otherwise defined, the terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be provided in the following description to explain the technical solutions of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, in addition to these detailed descriptions, the present disclosure may also have other implementations.

As shown in Figure 1, an embodiment of the present disclosure provides a chip system 10, including:

first substrate 100;

A plurality of first functional chips 101 arranged in an array on the first substrate 100; and

A plurality of second functional chips 102 located on the surface of the first functional chip 101;

Wherein, the first functional chip 101 and the second functional chip 102 have different types of functions; the projection of each second functional chip 102 on the first substrate 100 is different from at least two of the second functional chips 102 . The projection of a functional chip 101 on the first substrate 100 at least partially overlaps; the second functional chip 102 and at least two first functional chips 101 are bonded and connected in the overlapping area;

There is a multi-way connection channel 110 between the bonded first functional chip 101 and the second functional chip 102; the multi-way connection channel 110 is configured to connect the second functional chip 102 with at least two There is signal communication between the first functional chips 101 .

It should be understood that in order to clearly illustrate each layer structure in the figure, the dimensional proportional relationship of each layer structure may be inconsistent with the actual structure. In some embodiments, a multi-chip two-dimensional network system can be constructed through wafer reorganization before packaging. In this case, the multi-chip interconnection structure is distributed in the organic rewiring layer located at the bottom of the restructured wafer. Density and velocity are lower.

In the embodiment of the present disclosure, the first substrate 100 includes but is not limited to an organic substrate, a ceramic substrate, a silicon substrate, a heat dissipation substrate, and the like. The first substrate 100 can be used to carry multiple chips in the chip system 10, enhance the heat dissipation capability of the chip system 10, and electrically lead out the multiple chips.

A plurality of first functional chips 101 arranged in an array are located on the first substrate 100. There may be a gap between each two first functional chips 101, and the plurality of first functional chips 101 may not be directly interconnected. The first functional chip 101 may be a die, and the multiple first functional chips 101 may also be multiple uncut die located on the same wafer. In some embodiments, the first functional chip 101 may It is a known good die (KGD) to improve the reliability of the chip system 10 . The type of the first function chip 101 includes but is not limited to the programmable logic function block (Configurable Logic Block, CLB) in the field programmable gate array (Field Programmable Gate Array, FPGA), the graphics processor (Graphics Processing Unit, GPU) Streaming Multiprocessor (SM), etc.

The plurality of second functional chips 102 are located on the surface of the plurality of first functional chips 101 away from the first substrate 100 . Each second functional chip 102 has an overlapping area with at least two first functional chips 101 in a direction perpendicular to the surface of the first substrate 100 . Each second functional chip 102 is bonded and connected with at least two first functional chips 101 below it in the overlapping area, and there are multiple connection channels 110 between the bonded-connected first functional chips 101 and the second functional chips 102 . Bidirectional signal communication can be achieved between the second functional chip 102 and the first functional chip 101 through the multi-channel connection channel 110 . The type of the second function chip 102 includes but is not limited to the Connect Block (CB) and Switch Block (SB) in the FPGA, the video memory chip (Memory) and the video memory controller (Memory Controller) in the GPU. wait. For example, the second functional chip 102 can be bonded to at least two first functional chips 101 in the overlapping area through a hybrid bonding process, and a multi-way connection channel 110 can be formed. The hybrid bonding process can make the multiple connection channels 110 have good transmission stability and signal integrity, and the pitch of the multiple connection channels 110 is small, and the number of multiple connection channels 110 per unit area is large. The distance between chips is short, thereby increasing the integration level of the chip system 10 while increasing the speed and bandwidth of signal transmission.

In addition, in addition to the function of the device itself, the second functional chip 102 can also play the role of an interposer. Therefore, two adjacent first functional chips 101 can communicate through the second functional chip 102. The chip system 10 can be based on a plurality of second function chips 102 to form a mesh interconnection structure. Since the types of multiple chips in the chip system 10 can be the same or different, the chip system 10 has good functional scalability, and the failure of any one chip will not affect the entire chip system 10, and the fault tolerance rate is high. It can be understood that the first functional chip 101 can also be connected to the second functional chip 102 through other means, such as leads, micro-bumps, etc. In some embodiments, the first functional chip 101 can also be connected to the first substrate 100 through hybrid bonding, wires, micro-bumps, etc., and form multiple connection channels between the first functional chip 101 and the first substrate 100 110.

The first functional chip 101 and the second functional chip 102 may have different types of functions. For example, one of the first functional chip 101 and the second functional chip 102 may be used for logical operation processing, while the other may be used for logical operation processing. Used in routing and switching, sensing and identifying external signals and/or data storage, etc. In some embodiments, the second functional chip 102 may have active devices for signal amplification, conversion, calculation, etc. In some embodiments, the combination of the first functional chip 101 and the second functional chip 102 may also include a logic chip and a memory chip, a logic chip and an image chip, a logic chip, a memory chip and an image chip, etc. The memory chips here include but Not limited to static random access memory (Static Random Access Memory, SRAM) and dynamic random access memory (Dynamic Random Access Memory, DRAM), etc.

In some embodiments, as shown in FIG. 2 , which is a top view of the chip system 10 , any four adjacent first functional chips 101 are connected to the same second functional chip 102 .

In the embodiment of the present disclosure, in a direction perpendicular to the surface of the first substrate 100, there is an overlapping area between the second functional chip 102 and the four two-by-two adjacent first functional chips 101 below it, and the second functional chip 102 is bonded and connected with the four first functional chips 101 in the overlapping area, and forms a multi-way connection channel. In this way, as shown by the arrows in Figure 2, each first functional chip 101 can input and output signals with another adjacent first functional chip 101 through the second functional chip 102; and multiple third functional chips that are spaced apart from each other. One functional chip 101 can communicate through multiple second functional chips 102, that is, the entire chip system 10 has a mesh interconnection structure. Therefore, the chip system 10 has good functional scalability, and the failure of any one chip will not affect the entire chip system 10, and the fault tolerance rate is high.

In some embodiments, as shown in Figure 3, the first functional chip 101 includes a functional module 1011;

The second functional chip 102 includes at least one core module 1021 and a plurality of interconnection modules 1022; the interconnection modules 1022 are located in an area of the second functional chip 102 that overlaps with the first functional chip 101. The core module 1021 is located in an area of the second functional chip 102 other than the interconnection module 1022 .

In this embodiment of the present disclosure, the first functional chip 101 has functional modules 1011 that implement specific functions. The functional modules 1011 in multiple first functional chips 101 may be the same or different. For example, the functional module 1011 can be used as a controller to control other chips in the chip system 10 to perform their respective tasks; the functional module 1011 can also be used for logical operations, such as floating point calculations, integer calculations, etc.

The second functional chip 102 includes at least one core module 1021 and a plurality of interconnection modules 1022. The core module 1021 may be located in the central area of the second functional chip 102; the interconnection module 1022 may be located around the core module 1021, such as the area in the second functional chip 102 that overlaps the first functional chip 101. The core module 1021 and the interconnection module 1022 can implement their respective functions according to instructions issued by the first functional chip 101, such as data storage, signal sensing, routing and switching, etc. It can be understood that the multi-channel connection channel may be located in the area where the interconnection module 1022 is located, that is, the second functional chip 102 implements communication with other chips through the interconnection module 1022.

In some embodiments, the functional module 1011 includes a processor; the core module 1021 includes a memory, and the interconnection module 1022 includes a storage controller.

In the embodiment of the present disclosure, the functional module 1011 in the first functional chip 101 can be a processor, such as an SM, a digital signal processor (Digital Signal Processor, DSP), a microcontroller unit (Microcontroller Unit, MCU), a microprocessor Unit (Micro Processor Unit, MPU), etc. The core module 1021 in the second functional chip 102 can be a memory, such as DRAM, SRAM, magnetic random access memory (Magnetoresistive Random Access Memory, MRAM), etc.; and the interconnection module 1022 in the second functional chip 102 can be a memory controller. , used to operate the memory according to instructions issued by the processor. In this way, the chip system 10 can have a higher integration level and achieve better functional scalability.

In some embodiments, the functional module 1011 includes a programmable logic unit; the core module 1021 includes a switch unit, and the interconnection module 1022 includes a connection unit.

In the embodiment of the present disclosure, the functional module 1011 in the first functional chip 101 can be a programmable logic unit, which has the advantages of flexible configuration and simple programming method; the core module 1021 in the second functional chip 102 can be a switch unit, It is used to realize switching of wiring directions and switching between different wiring types; and the interconnection module 1022 in the second functional chip 102 can be a connection unit, used to provide rich wiring resources and increase the flexibility of wiring. In this way, the chip system 10 has greater design flexibility and better versatility.

In some embodiments, as shown in Figure 4, there is a gap between adjacent first functional chips 101;

The second functional chip 102 is connected to the first substrate 100 through the first interconnection structure 111 in the area where the gap is located.

In the embodiment of the present disclosure, there is a gap between adjacent first functional chips 101, and the second functional chip 102 can be connected to the first substrate 100 through the first interconnection structure 111 located in the gap. The first interconnection structure 111 may be a conductive material such as metal or doped semiconductor, and the length of the first interconnection structure 111 may be greater than or equal to the thickness of the first functional chip 101 . For example, the first interconnection structure 111 may be a through mold via (TMV), a through dielectric via (Through Dielectric Via, TDV), a lead, etc. The first interconnection structure 111 may be perpendicular to the surface of the first substrate 100, or may be a non-vertical structure such as curved or inclined. It can be understood that the shorter the length of the first interconnection structure 111, the faster the signal transmission speed.

In some embodiments, the gaps between adjacent first functional chips 101 are also filled with insulating material to isolate the plurality of first interconnect structures 111 in the gaps. The insulating material here can be dielectric organic polymers, such as epoxy resin, etc.

In some embodiments, as shown in Figure 5, the chip system 10 further includes:

A plurality of third functional chips 103 located on the second functional chip 102 and arranged in an array;

Wherein, the third functional chip 103 and the second functional chip 102 have different types of functions; the projection of each second functional chip 102 on the first substrate 100 is different from at least two of the third functional chips 102 . The projection of the three-function chip 103 on the first substrate 100 at least partially overlaps; the second functional chip 102 and at least two third functional chips 103 are bonded and connected in the overlapping area;

There is a multi-way connection channel 110 between the bonded third functional chip 103 and the second functional chip 102; the multi-way connection channel 110 is configured to connect the second functional chip 102 with at least two There is signal communication between the third functional chips 103 .

In the embodiment of the present disclosure, there may also be a plurality of third functional chips 103 arranged in an array on the surface of the second functional chip 102 away from the first substrate 100 . There is an overlapping area between the second functional chip 102 and at least two third functional chips 103 above it, and the second functional chip 102 and the two third functional chips 103 are bonded and connected in the overlapping area to form a multi-way connection. Channel 110. Bidirectional signal communication can be achieved between the third functional chip 103 and the second functional chip 102 through the multi-channel connection channel 110 .

The third functional chip 103 may be a bare chip. In some embodiments, the third functional chip 103 may be a known good chip to improve the reliability of the chip system 10 . The types of the third functional chip 103 include but are not limited to CLB in FPGA, SM in GPU, etc. For example, the second functional chip 102 can be bonded to at least two third functional chips 103 in the overlapping area through a hybrid bonding process, and a multi-way connection channel 110 can be formed. The multiple connection channels 110 formed by hybrid bonding can improve the integration level of the chip system 10 and increase the speed and bandwidth of signal transmission.

In addition, two adjacent third functional chips 103 can communicate through the second functional chip 102, and the third functional chip 103 can also communicate with the first functional chip 101 through the second functional chip 102. In this way, the chip system 10 has good functional scalability, and the failure of any one chip will not affect the entire chip system 10, and the fault tolerance rate is high. It can be understood that the third functional chip 103 can also be connected to the second functional chip 102 through other means, such as leads, micro-bumps, etc. The third functional chip 103 and the second functional chip 102 may have different types of functions. For example, one of the third functional chip 103 and the second functional chip 102 may be used for logical operation processing, while the other may be used for logical operation processing. Used in routing and switching, sensing and identifying external signals and/or data storage, etc.

In some embodiments, as shown in Figure 5, the projection of the third functional chip 103 on the first substrate 100 overlaps with the projection of the first functional chip 101 on the first substrate 100;

There is a second interconnection structure 112 between the third functional chip 103 and the first functional chip 101 .

In the embodiment of the present disclosure, in the direction perpendicular to the surface of the first substrate 100, the projections of the third functional chip 103 and the first functional chip 101 overlap. In this way, the area occupied by the chip system 10 in the horizontal direction can be saved. The second interconnection structure 112 may be located in a portion of the projection area of the third functional chip 103 and the first functional chip 101 except for the second functional chip 102 . The second interconnection structure 112 may be made of conductive material such as metal or doped semiconductor, and the length of the second interconnection structure 112 may be greater than or equal to the thickness of the second functional chip 102 . For example, the second interconnection structure 112 may be a TMV, a TDV, a lead, or the like. The second interconnection structure 112 may be perpendicular to the surface of the first substrate 100, or may be a non-vertical structure such as curved or inclined. It can be understood that the shorter the length of the second interconnection structure 112, the faster the signal transmission speed. In some embodiments, insulating material is also filled between the third functional chip 103 and the first functional chip 101 to isolate the plurality of second interconnect structures 112 . The insulating material here can be dielectric organic polymers, such as epoxy resin, etc.

In some embodiments, the stacking and connection method of the first functional chip 101 , the second functional chip 102 and the third functional chip 103 can also be repeated in the vertical direction, so that the chip system 10 has more chip layers, further improving the Integration and scalability of the chip system 10.

In some embodiments, as shown in Figure 6, the chip system 10 further includes:

Wherein, the third functional chip 103 and the second functional chip 102 have different types of functions; the projection of each third functional chip 103 on the first substrate 100 is different from that of at least two of the third

functional chips

103 and 102 respectively. The projections of the two functional chips 102 on the first substrate 100 at least partially overlap; the third functional chip 103 and at least two second functional chips 102 are bonded and connected in the overlapping area;

There is a multi-channel connection channel 110 between the bonded third functional chip 103 and the second functional chip 102; the multi-channel connection channel 110 is configured to connect the third functional chip 103 with at least two There is signal communication between the second functional chips 102 .

In the embodiment of the present disclosure, there may also be a plurality of third functional chips 103 arranged in an array on the surface of the second functional chip 102 away from the first substrate 100 . There is an overlapping area between the third functional chip 103 and at least two second functional chips 102 below it, and the third functional chip 103 and the two second functional chips 102 are bonded and connected in the overlapping area to form a multi-way connection. Channel 110. Bidirectional signal communication can be achieved between the third functional chip 103 and the second functional chip 102 through the multi-channel connection channel 110 . It can be understood that since the third functional chip 103 is stacked on at least two second functional chips 102, and the second functional chip 102 is stacked on at least two first functional chips 101, the number of chips is gradually increased from bottom to top. The chip system 10 with reduced layers has better structural stability, stronger functional scalability and higher fault tolerance rate.

The third functional chip 103 may be a bare chip. In some embodiments, the third functional chip 103 may be a known good chip to improve the reliability of the chip system 10 . The types of the third functional chip 103 include but are not limited to CLB in FPGA, SM in GPU, etc. For example, the third functional chip 103 can be bonded to at least two second functional chips 102 in the overlapping area through a hybrid bonding process, and a multi-way connection channel 110 can be formed. The multiple connection channels 110 formed by hybrid bonding can improve the integration level of the chip system 10 and increase the speed and bandwidth of signal transmission.

In some embodiments, as shown in Figures 7 to 13, the chip system 10 further includes:

Multiple input and output chips 104;

Any one of the input and output chips 104 is connected to at least one of the first functional chip 101 or the second functional chip 102 .

In the embodiment of the present disclosure, the chip system 10 may also have multiple input and output chips 104. The input and output chips 104 are used to electrically connect the multiple chips in the chip system 10 to other external systems, where any input and output The chip 104 is connected to at least one first functional chip 101 or a second functional chip 102 . The input/output chip 104 can be an input/output function block in an FPGA, an input/output interface in a GPU, and other peripheral circuits. The input/output chip 104 can connect multiple chips in the chip system 10 and the first substrate 100 through hybrid bonding, wires, micro-bumps, etc., to realize communication interaction between the chip system 10 and external systems.

In some embodiments, as shown in Figures 7 and 8, the input/output chip 104 is located at the edge of the first substrate 100; among the plurality of first functional chips 101 arranged in the array, it is close to the first substrate 100 The first functional chip 101 on the edge and the input/output chip 104 are connected through the first substrate 100 .

In the embodiment of the present disclosure, as shown in FIG. 7 , a plurality of input and output chips 104 are located at the edge of the first substrate 100 , and the plurality of input and output chips 104 can be arranged around a plurality of first functional chips 101 arranged in an array. For example, as shown in FIG. 8 , which is a schematic diagram of the AA cross-section in FIG. 7 , the input/output chip 104 can be connected to the first functional chip 101 near the edge of the first substrate 100 through wiring in the first substrate 100 . It can be understood that arranging the input/output chip 104 at the edge of the first substrate 100 is beneficial to simplifying the layout structure of the chip system 10 and the manufacturing process is relatively simple.

In some embodiments, as shown in FIGS. 9 and 10 , the input-output chip 104 is located in the gap between any two adjacent first functional chips 101 , and the input-output chip 104 is located in the gap between any two adjacent first functional chips 101 . Within the coverage of the second functional chip 102;

The input/output chip 104 is bonded and connected to the second functional chip 102 , and the input/output chip 104 is also bonded and connected to the first substrate 100 .

In the embodiment of the present disclosure, as shown in FIG. 9 , there is also an input/output chip 104 in the gap between any two adjacent first functional chips 101. In the direction perpendicular to the surface of the first substrate 100, the input/output chip 104 is provided. The chip 104 can also be within the coverage of the second functional chip 102, so that the input and output chips 104 do not occupy additional area in the chip system 10 to improve integration. As shown in FIG. 10 , which is a schematic diagram of the AA cross-section in FIG. 9 , the upper surface of the input/output chip 104 can be bonded to the second functional chip 102 , and the lower surface of the input/output chip 104 can be bonded to the first substrate 100 . It can be understood that the connection method between the input and output chip 104, the second functional chip 102 and the first substrate 100 includes but is not limited to hybrid bonding, wires, micro-bumps, etc. In some embodiments, according to the layout requirements of the chip system 10, the input and output chips 104 may also exceed the coverage of the second functional chip 102.

In some embodiments, as shown in Figures 11 and 12, the input-output chip 104 is located adjacent to the second functional chip 102 on the first functional chip 101;

The projection of the input/output chip 104 on the first substrate 100 overlaps with the two adjacent first functional chips 101 respectively, and the input/output chip 104 and the first functional chip 101 are in the overlapping position. Intra-area bonding connections.

In the embodiment of the present disclosure, as shown in Figure 11, the input/output chip 104 and the second functional chip 102 are located in the same layer, and the input/output chip 104 is located adjacent to any second functional chip 102. For example, The input-output chip 104 may be located between two adjacent second function chips 102 . The input-output chip 104 can also span the two first functional chips 101 located below it, that is, the projection of the input-output chip 104 on the first substrate 100 overlaps with the two adjacent first functional chips 101 respectively, and the input-output chip 104 overlaps with the two adjacent first functional chips 101 respectively. The chip 104 and the first functional chip 101 are bonded and connected in an overlapping area. In this way, on the one hand, the input/output chip 104 does not occupy additional area in the chip system 10; on the other hand, the input/output chip 104 can also play the role of an intermediary layer to increase the space between two adjacent first functional chips 101. The signal transmission bandwidth ensures that the signal transmission between two adjacent first functional chips 101 is not affected when the second functional chip 102 fails, thereby improving the fault tolerance rate of the chip system 10 . It can be understood that the connection method between the input and output chip 104 and the first functional chip 101 includes but is not limited to hybrid bonding, wires, micro-bumps, etc.

In some embodiments, as shown in FIG. 12 , which is a schematic diagram of the AA cross-section in FIG. 11 , the input and output chips 104 can also be connected through the third interconnection structure 113 located in the gap between the two adjacent first functional chips 101 below it. to the first substrate 100 . The third interconnection structure 113 may be made of conductive material such as metal or doped semiconductor, and the length of the third interconnection structure 113 may be greater than or equal to the thickness of the first functional chip 101 . For example, the third interconnection structure 113 may be a TMV, a TDV, a lead, or the like. The third interconnection structure 113 may be perpendicular to the surface of the first substrate 100, or may be a non-vertical structure such as curved or inclined. It can be understood that the shorter the length of the third interconnection structure 113, the faster the signal transmission speed.

In some embodiments, at least part of the first functional chip 101 may also have an input/output function and a switching function, and the first functional chip 101 may pass through the first substrate 100 through a through silicon via (TSV), Interconnect structures such as TMV lead multiple chips in the chip system 10 from the back of the first substrate 100 to communicate with external systems. It can be understood that the back side of the first substrate 100 here refers to the surface of the first substrate 100 away from the first functional chip 101 .

In some embodiments, as shown in Figure 13, the chip system 10 further includes:

The second substrate 200 covers the second functional chip 102 and the input/output chip 104;

The second substrate 200 is bonded and connected to the input/output chip 104, and there is an input/output channel 114 between the input/output chip 104 and the second substrate 200;

The second substrate 200 has a redistribution layer (RDL) 201; the redistribution layer 201 has a signal channel 210 connecting the input/output chip 104 and the surface of the second substrate 200.

In the embodiment of the present disclosure, as shown in FIG. 13 , the second substrate 200 covers the second functional chip 102 and the input/output chip 104 , and the second substrate 200 can be bonded and connected to the input/output chip 104 and formed with Input and output channel 114. It can be understood that, for convenience of illustration, the second substrate 200 is located below the second functional chip 102 and the input/output chip 104 in FIG. 13 . In this way, multiple chips in the chip system 10 can be electrically connected to other external systems via the input/output chip 104 and the second substrate 200 , and the second substrate 200 can also increase the structural stability of the chip system 10 . It can be understood that the input and output channels 114 include, but are not limited to, hybrid bonding, wires, micro-bumps, etc.

The second substrate 200 may have a rewiring layer 201 . The rewiring layer 201 may increase the layout flexibility of pins, bumps and other structures in the chip system 10 to simplify circuit design. The redistribution layer 201 has a signal channel 210 that connects the input/output chip 104 and the surface on the side of the second substrate 200 away from the first substrate 100. The signal channel 210 here may be a metal line formed by a deposition process. For example, the signal channel 210 may connect the input and output channel 114 to a ball grid array (Ball Grid Array, BGA) on the other side surface of the second substrate 200 .

In some embodiments, as shown in Figures 14 to 16, the chip system 10 further includes:

The heat dissipation structure 300 covers the first functional chip 101 and the second functional chip 102;

Wherein, the heat dissipation structure 300 is in contact with the surface of the first functional chip 101 in an area covering the surface of the first functional chip 101; the heat dissipation structure 300 is in contact with the surface of the second functional chip 102 in an area covering the surface of the second functional chip 102. The second functional chips 102 are in surface contact; the heat dissipation structure 300 covers the exposed area of the first substrate 100 between the first functional chips 101 and is in contact with the first substrate 100 .

In the embodiment of the present disclosure, FIG. 14 is a top view of the chip system 10 with the heat dissipation structure 300, and FIG. 15 and FIG. 16 are schematic diagrams of the AA cross-section and the BB cross-section in FIG. 14, respectively.

The heat dissipation structure 300 covers the first functional chip 101 and the second functional chip 102 . The heat dissipation structure 300 can be made of copper, aluminum nitride, diamond composite materials, or other materials with higher thermal conductivity and lower thermal expansion coefficient. The heat dissipation structure 300 is in contact with the surfaces of the first functional chip 101 and the second functional chip 102 respectively, and the heat dissipation structure 300 can also be in contact with the first substrate 100 through the gaps between the plurality of first functional chips 101 to improve the chip system 10 heat dissipation efficiency. In some embodiments, the heat dissipation structure 300 may be a heat sink.

In some embodiments, as shown in Figures 15 and 16, the heat dissipation structure 300 includes a plurality of protruding structures 310;

The protruding structure 310 located in the area covering the first functional chip 101 extends toward the surface of the first functional chip 101 and contacts the first functional chip 101;

The protruding structure 310 located in the area covering the exposed first substrate 100 between the first functional chips 101 extends toward the first substrate 100 and contacts the first substrate 100 .

In the embodiment of the present disclosure, the heat dissipation structure 300 includes a plurality of protruding structures 310, and the protruding structures 310 include but are not limited to comb-shaped or lattice-shaped. As shown in Figure 15, the protruding structure 310 located in the area covering the first functional chip 101 and not covering the second functional chip 102 can extend downward and contact the surface of the first functional chip 101; as shown in Figure 16, located in the area that does not cover the second functional chip 102 The protruding structures 310 above the gaps between the plurality of first functional chips 101 may extend downward and contact the surface of the first substrate 100 . In this way, the heat dissipation structure 300 can be in contact with various chips and substrates in the chip system 10 to improve heat dissipation efficiency.

As shown in Figure 17, an embodiment of the present disclosure also provides a chip system 40, including:

first substrate 400;

A plurality of first functional chips 401 arranged in an array on the first substrate 400; and

A plurality of second functional chips 402 located on the surface of the first functional chip 401;

A plurality of input and output chips 404 located at the edge of the first substrate 400;

Wherein, the projection of each second functional chip 402 on the first substrate 400 at least partially overlaps with the projection of at least two first functional chips 401 on the first substrate 400; The two-function chip 402 and at least two first functional chips 401 are bonded and connected in an overlapping area; there are multiple connection channels between the bonded-connected first functional chip 401 and the second functional chip 402 ;

The second functional chip 402 also includes a core module 4021 and an interconnection module 4022; wherein the interconnection module 4022 is located in the area of the second functional chip 402 that overlaps with the projection of the first functional chip 401; the core module 4021 is located in the second functional chip 402. The central area of chip 402 excluding interconnect module 4022;

Among the plurality of first functional chips 401 arranged in the array, the first functional chip 401 close to the edge of the first substrate 400 is connected to the input/output chip 404 through the first substrate 400 .

In the embodiment of the present disclosure, the chip system 40 may be a network on chip (NOC) or other architecture suitable for parallel computing. Among them, the second functional chip 402 can be bonded to at least two first functional chips 401 in the overlapping area through a hybrid bonding process, and multiple connection channels can be formed. The multiple connection channels formed by the hybrid bonding process have good transmission stability and signal integrity, and the spacing between the multiple connection channels is small. The number of multiple connection channels per unit area is large, and the distance between the chips is Shorter, thereby increasing the integration level of the chip system 40 while increasing the speed and bandwidth of signal transmission. In addition, the second functional chip 402 can also function as an intermediary layer, allowing the chip system 40 to form a mesh-like interconnection structure and have good fault tolerance and function expandability.

In some embodiments, the chip system 40 may be an FPGA, in which the first functional chip 401 may be a CLB in the FPGA; the core module 4021 in the second functional chip 402 may be an SB in the FPGA, and the second functional chip 402 may be an SB in the FPGA. The interconnection module 4022 may be a CB in the FPGA; and the input and output chip 404 may be an IOB in the FPGA.

In the embodiment of the present disclosure, the chip system 40 is an FPGA. The FPGA includes multiple CLBs. The CLBs are composed of a look-up table (LUT) and a register (Register). The look-up table is used to implement combinational logic functions. The registers inside the FPGA can be configured as flip-flops with synchronous/asynchronous reset and set, clock enable, or as latches. A CLB can consist of a lookup table and a register, or any other number of combinations. The CLB may be the first functional chip 401 located at the bottom of the chip system 40 . In FPGA, SB and CB are respectively located in the core module 4021 and interconnection module 4022 in the second functional chip 402. One SB in each second functional chip can be connected to the four lower ones through four CBs. One functional chip 401, namely CLB. In this way, through SB and CB, communication between multiple CLBs can be achieved, and the optimal signal transmission path can be selected to reduce communication delays. In addition, the failure of a single CLB will not affect the entire FPGA system, increasing the fault tolerance rate of the FPGA. The IOB in the FPGA can be set on the input and output chip 404, so that the FPGA communicates with the external system through the IOB.

In some embodiments, the chip system 40 may be a GPU, where the first functional chip 401 may be an SM in the GPU; the core module 4021 in the second functional chip 402 may be a video memory chip in the GPU, and the second functional chip 402 The interconnection module 4022 in can be the video memory controller in the GPU; and the input and output chip 404 can be the I/O and other peripheral circuits in the GPU.

In the embodiment of the present disclosure, the chip system 40 is a GPU, and the GPU includes multiple SMs. The SM can be a processor with a single-instruction multi-thread architecture and is mainly used to perform computing operations. The SM can be the first processor located at the bottom of the chip system 40 Function chip 401. The video memory chip and video memory controller in the GPU are respectively located in the core module 4021 and the interconnection module 4022 in the second function chip 402. Each video memory chip in the second function chip 402 can pass four video memory controllers. They are respectively connected to the four first function chips 401 below, namely SM. In some embodiments, the SM also includes a first-level cache and a register, and a second-level cache is also connected between the SM and the video memory controller. The registers can be connected to the video memory controller via the first-level cache and the second-level cache in turn. The first-level cache here can be set in the first functional chip 401, and the second-level cache can be set in the second functional chip 402; or it can be additionally set between the first functional chip 401 and the second functional chip 402. A layer of chips to serve as a secondary cache. In addition, I/O and other peripheral circuits in the GPU can be provided on the input and output chip 404, so that the GPU communicates with external systems through I/O. It should be noted that the features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide a chip system. In the chip system provided by the embodiment of the present disclosure, the second functional chip is located on the first functional chip arranged in an array, and the projection of the second functional chip on the first substrate is respectively the same as that of at least two first functional chips on the first substrate. The projections on the substrate at least partially overlap, and the second functional chip and at least two first functional chips are bonded and connected in the overlapping area and have multiple connection channels. In this way, on the one hand, the first functional chip and the second functional chip arranged in a staggered stack reduce the size of the chip system; on the other hand, multiple first functional chips can be interconnected through the second functional chip, which improves the efficiency of the chip system. The chip system is scalable, and the failure of a single chip will not affect the entire chip system, and the fault tolerance rate is high.

Claims

A chip system including:

first substrate;

A plurality of first functional chips arranged in an array on the first substrate; and

a plurality of second functional chips located on the surface of the first functional chip;

Wherein, the first functional chip and the second functional chip have different types of functions; the projection of each second functional chip on the first substrate is respectively different from that of at least two first functional chips. The projections on the first substrate at least partially overlap; the second functional chip and at least two of the first functional chips are bonded and connected in the overlapping area;

There are multiple connection channels between the first functional chip and the second functional chip that are bonded together; the multiple connection channels are configured to connect the second functional chip with at least two of the first functional chips. There is signal communication between the chips; multiple first functional chips spaced apart from each other can communicate with each other through multiple second functional chips.
The chip system according to claim 1, wherein any four adjacent first functional chips are connected to the same second functional chip.
The chip system according to claim 1, wherein the first functional chip includes a functional module;

The second functional chip includes at least one core module and a plurality of interconnection modules; the interconnection module is located in an area of the second functional chip that overlaps the first functional chip, and the core module is located in the first functional chip. The area in the dual-function chip other than the interconnection module.
The chip system of claim 3, wherein the functional module includes a processor; the core module includes a memory, and the interconnection module includes a memory controller.
The chip system according to claim 3, wherein the functional module includes a programmable logic unit; the core module includes a switch unit, and the interconnection module includes a connection unit.
The chip system according to claim 1, wherein there is a gap between adjacent first functional chips;

The second functional chip is connected to the first substrate through a first interconnection structure in the area where the gap is located.
The chip system according to claim 1, further comprising:

A plurality of third functional chips located on the second functional chip and arranged in an array;

Wherein, the third functional chip and the second functional chip have different types of functions; the projection of each second functional chip on the first substrate is respectively different from that of at least two third functional chips. The projections on the first substrate at least partially overlap; the second functional chip and at least two third functional chips are bonded and connected in the overlapping area;

There are multiple connection channels between the bonded third functional chip and the second functional chip; the multiple connection channels are configured to connect the second functional chip with at least two of the third functional chips. There is signal communication between chips.
The chip system according to claim 7, wherein the projection of the third functional chip on the first substrate overlaps with the projection of the first functional chip on the first substrate;

There is a second interconnection structure between the third functional chip and the first functional chip.
The chip system according to claim 1, further comprising:

A plurality of third functional chips located on the second functional chip and arranged in an array;

Wherein, the third functional chip and the second functional chip have different types of functions; the projection of each third functional chip on the first substrate is respectively different from that of at least two second functional chips. The projections on the first substrate at least partially overlap; the third functional chip and at least two second functional chips are bonded and connected in the overlapping area;

There are multiple connection channels between the bonded third functional chip and the second functional chip; the multiple connection channels are configured to connect the third functional chip with at least two of the second functional chips. There is signal communication between chips.
The chip system according to claim 1, further comprising:

Multiple input and output chips;

Any one of the input and output chips is connected to at least one of the first functional chip or the second functional chip.
The chip system according to claim 10, wherein the input/output chip is located at the edge of the first substrate; the first function chip close to the edge of the first substrate among the plurality of first functional chips arranged in the array The chip is connected to the input/output chip through the first substrate.
The chip system according to claim 10, wherein the input/output chip is located in a gap between any two adjacent first functional chips, and the input/output chip is located between the second functional chip and the second functional chip. within coverage;

The input-output chip is bonded and connected to the second functional chip, and the input-output chip is also bonded and connected to the first substrate.
The chip system according to claim 10, wherein the input and output chip is located adjacent to the second functional chip on the first functional chip;

The projection of the input/output chip on the first substrate overlaps with two adjacent first functional chips respectively, and the input/output chip and the first functional chip are bonded and connected in the overlapping area. .
The chip system according to claim 13, further comprising:

a second substrate covering the second functional chip and the input/output chip;

The second substrate is bonded and connected to the input/output chip, and there is an input/output channel between the input/output chip and the second substrate;

The second substrate has a rewiring layer; the rewiring layer has a signal channel connecting the input and output chip and the surface of the second substrate.
The chip system according to claim 1, further comprising:

A heat dissipation structure covering the first functional chip and the second functional chip;

Wherein, the heat dissipation structure is in contact with the surface of the first functional chip in the area covering the surface of the first functional chip; the heat dissipation structure covers the area of the surface of the second functional chip and the surface of the second functional chip. Contact; the heat dissipation structure contacts the first substrate in a region covering the exposed first substrate between the first functional chips.
The chip system of claim 15, wherein the heat dissipation structure includes a plurality of protruding structures;

The protruding structure located in the area covering the first functional chip extends toward the surface of the first functional chip and contacts the first functional chip;

The protruding structure located in the area covering the exposed first substrate between the first functional chips extends toward the first substrate and contacts the first substrate.