WO2024009733A1

WO2024009733A1 - Semiconductor device and communication system

Info

Publication number: WO2024009733A1
Application number: PCT/JP2023/022447
Authority: WO
Inventors: 圭長尾
Original assignee: ローム株式会社
Priority date: 2022-07-04
Filing date: 2023-06-16
Publication date: 2024-01-11

Abstract

A semiconductor device (1) comprises a first reception unit (11) configured to receive reception data (RX) as serial data from a transmission device (40) via a first bus (BS1), and a first transmission unit (12) configured to connect to a device (10) via a second bus (BS2). The first reception unit and the first transmission unit are configured to perform thru-output of data (DDT) corresponding to the protocol of the device included in the reception data to the second bus when bridge selection data (BR) included in the reception data indicates that thru-ouput, in which bit data is output as-is between the first bus and the second bus, is in an on state.

Description

Semiconductor devices and communication systems

The present disclosure relates to a semiconductor device and a communication system.

Semiconductor devices equipped with serial communication functions are used in various applications.

Note that an example of circuit technology related to serial communication is disclosed in Patent Document 1.

JP2017-224946A

Here, in an application, a communication system may be constructed using a semiconductor device that performs serial communication using a protocol different from that of the application itself, as well as its own semiconductor device.

An object of the present disclosure is to provide a semiconductor device that can effectively construct a communication system together with a device using a protocol different from the semiconductor device itself.

A semiconductor device (1) according to one aspect of the present disclosure includes:
A semiconductor device connectable to an external transmitting device via a first bus, and connectable to an external device via a second bus,
a first receiving unit configured to be able to receive received data, which is serial data, from the transmitting device via the first bus;
a first transmitter configured to be connectable to the device via the second bus;
Equipped with
The first receiving section and the first transmitting section indicate that the bridge selection data included in the received data is ON of a through output in which the bit data is output as is between the first bus and the second bus. In this case, data corresponding to the protocol of the device included in the received data is configured to be through-outputted to the second bus.

According to the exemplary semiconductor device of the present disclosure, it is possible to effectively construct a communication system together with a device using a protocol different from the semiconductor device itself.

FIG. 1 is a diagram showing the configuration of a communication system according to a first comparative example. FIG. 2 is a diagram showing the configuration of a communication system according to a second comparative example. FIG. 3 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. FIG. 4 is a block diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 5 is a diagram showing the data structure of received data RX when writing or reading is performed using the semiconductor device 1 as a target device. FIG. 6 is a diagram illustrating another configuration example of the communication system according to the embodiment of the present disclosure. FIG. 7 is a diagram showing the data structure of received data RX when writing or reading is performed using the device 10 as a target device. FIG. 8 is a timing chart showing communication control when writing to the device 10. FIG. 9 is a timing chart showing communication control when reading from the device 10. FIG. 10 is a timing chart showing communication control when writing to the device 10 in a modified example. FIG. 11 is a timing chart showing communication control when reading from the device 10 in a modified example. FIG. 12 is a diagram illustrating a modification of the communication system according to the embodiment of the present disclosure.

Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

<1. Communication system>
FIG. 1 is a diagram showing the configuration of a communication system 501 according to a first comparative example for comparison with the embodiment of the present disclosure. The communication system 501 includes an MCU (Micro Controller Unit) 20, a CAN (Controller Area Network) transceiver 30, a CAN transceiver 40, a semiconductor device 1, and n devices 10 (n is an integer of 1 or more). Be prepared. The communication system 501 is installed in a vehicle as an example, and the same applies to other communication systems described below.

Communication is performed between the MCU 20 and the CAN transceiver 30 using a UART (Universal Asynchronous Receiver/Transmitter). UART is a protocol for exchanging serial data between two devices. In UART, bidirectional communication is performed between a transmitting side and a receiving side using two lines.

Communication is performed between the CAN

transceivers

30 and 40 via the CAN bus 35. CAN is a serial communication protocol standardized by international standards such as ISO11898.

The CAN transceiver 30 has a TXD (transmission data input) terminal 30A and an RXD (reception data output) terminal 30B. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus 35, and outputs data input from the CAN bus 35 to the RXD terminal 30B.

The CAN transceiver 40 has an RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus 35, and outputs data input from the CAN bus 35 to the RXD terminal 40A.

The semiconductor device 1 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light emitting diode) driver IC. The n devices 10 are ICs in which circuits with predetermined functions are integrated, and are configured as, for example, a matrix switch IC.

The semiconductor device 1 has an RX (reception data input) terminal 1A and a TX (transmission data output) terminal 1B. The device 10 has an RX terminal 10A and a TX terminal 10B. The RX terminal 1A and n RX terminals 10A are commonly connected to the RXD terminal 40A. The TX terminal 1B and n TX terminals 10B are commonly connected to the TXD terminal 40B.

In the first comparative example shown in FIG. 1, since the semiconductor device 1 and the n devices 10 support the same protocol, the semiconductor device 1 and the n devices 10 can be commonly connected to the same CAN transceiver 40. . Reception data RX output from the RXD terminal 40A is input to the RX terminal 1A and n RX terminals 10A. The device address of one of the semiconductor device 1 and n devices 10 is specified in the received data RX. Further, transmission data TX output from the TX terminal 1B and n TX terminals 10B is input to the TXD terminal 40B.

However, if the semiconductor device 1 and the n devices 10 have different protocols, the configuration of the first comparative example shown in FIG. 1 is difficult to handle. Therefore, in such a case, a second comparative example configuration as shown in FIG. 2 can be adopted.

A communication system 502 according to the second comparative example shown in FIG. 2 uses

CAN transceivers

401 and 402 instead of the CAN transceiver 40, as a difference from the first comparative example. A CAN transceiver 401 is connected to the semiconductor device 1, and a CAN transceiver 402 is connected to the n devices 10. CAN

transceivers

401 and 402 perform CAN communication with CAN transceiver 30.

In this way, by grouping devices with different protocols (a group of semiconductor devices 1 and a group of n devices 10), communication control can be performed using devices with different protocols. However, as the number of CAN transceivers such as

CAN transceivers

401 and 402 increases and the amount of wiring increases, there is a problem of increased costs.

Therefore, in order to solve such problems, embodiments of the present disclosure as described below are implemented. FIG. 3 is a diagram illustrating a configuration of a communication system 50 according to an exemplary embodiment of the present disclosure.

In the configuration shown in FIG. 3, communication is performed between the CAN transceiver 40, the semiconductor device 1, and the n devices 10 using the UART. The semiconductor device 1 has an RXD (reception data output) terminal 1C and a TXD (transmission data input) terminal 1D in addition to an RX terminal 1A and a TX terminal 1B. RX terminal 1A is connected to RXD terminal 40A of CAN transceiver 40. TX terminal 1B is connected to TXD terminal 40B of CAN transceiver 40. That is, the RX terminal 1A and TX terminal 1B are connected to the RXD terminal 40A and TXD terminal 40B via the bus BS1. Communication of reception data RX and transmission data TX is possible via bus BS1. Reception data RX and transmission data TX are serial data.

The RXD terminal 1C is connected to the RX terminals 10A of the n devices 10. TXD terminal 1D is connected to TX terminals 10B of n devices 10. That is, the RXD terminal 1C and TXD terminal 1D are connected to the RX terminal 10A and TX terminal 10B by a bus (local bus) BS2. Communication of reception data BRX and transmission data BTX is possible via bus BS2. Reception data BRX and transmission data BTX are serial data.

In the configuration according to the embodiment of the present disclosure shown in FIG. 3, the protocols supported by the semiconductor device 1 and the n devices 10 are different. When the CAN transceiver 40 writes or reads to the semiconductor device 1, the received data RX output from the RXD terminal 40A to the RX terminal 1A is composed only of data corresponding to the protocol of the semiconductor device 1. Note that Write is a process of writing data to a target device, and Read is a process of reading data from a target device. In the case of Read, the semiconductor device 1 outputs the transmission data TX from the TX terminal 1B to the TXD terminal 40B after receiving the reception data RX.

On the other hand, when the CAN transceiver 40 writes or reads to the device 10, the received data RX output from the RXD terminal 40A to the RX terminal 1A includes data corresponding to the protocol of the device 10. At this time, the semiconductor device 1 turns on the bridge function and outputs data included in the received data RX that corresponds to the protocol of the device 10 from the RXD terminal 1C as the received data BRX. Through output means to output bit data as is. The device address of the device 10 is specified in the received data BRX.

In the case of Read, the device 10, which is the target device (the device specified by the device address), outputs the transmission data BTX from the TX terminal 10B to the TXD terminal 1D. Since the bridge function is on, the semiconductor device 1 outputs the transmission data BTX through the TX terminal 1B as the transmission data TX.

As described above, according to the embodiment of the present disclosure, even if the protocols of the semiconductor device 1 and the device 10 are different, the CAN transceiver 40 can write and read to the semiconductor device 1 and the device 10. Compared to the second comparative example (FIG. 2), costs can be reduced by reducing the number of CAN transceivers 40 and reducing the amount of wiring.

<2. Configuration of semiconductor device>
FIG. 4 is a block diagram of the semiconductor device 1 according to the embodiment of the present disclosure. The semiconductor device 1 includes a first receiving section 11, a first transmitting section 12, a second receiving section 13, a second transmitting section 14, and a control section 15 as functional blocks. Note that FIG. 4 illustrates only functional blocks related to communication functions in the communication system 50, and may include other functional blocks. For example, if the semiconductor device 1 is an LED driver, it has a block function related to LED driving.

The first receiving unit 11 receives received data RX via the RX terminal 1A. The first transmitter 12 outputs the received data BRX via the RXD terminal 1C. The second receiving unit 13 receives the transmission data BTX via the TXD terminal 1D. The second transmitter 14 outputs transmission data TX via the TX terminal 1B.

The control section 15 controls the first receiving section 11, the first transmitting section 12, the second receiving section 13, and the second transmitting section 14. The control unit 15 has a register 151.

<3. Received data structure>
FIG. 5 is a diagram showing the data structure of received data RX when writing or reading is performed using the semiconductor device 1 as a target device. The received data RX shown in FIG. 5 is composed only of data corresponding to the protocol of the semiconductor device 1.

In UART, communication is performed in data units called frames. As shown in FIG. 5, the frame FR is composed of bit data from a start bit S to a stop bit P. The start bit S is at low level and the stop bit P is at high level. Between the start bit S and stop bit P, bit data of a predetermined number of bits is arranged. In the example of FIG. 5, 8-bit bit data is arranged. That is, the frame FR is composed of 10 bits of bit data.

As shown in FIG. 5, the received data RX includes a synchronization frame SYNC, a Read/Write etc. frame RWD, a data number frame ND, a register address frame AD, a data frame DT, and a CRC (Cyclic Redundancy Check) frame CR in order from the beginning. have

The synchronization frame SYNC is bit data for setting the baud rate in the semiconductor device 1.

The Read/Write etc. frame RWD includes a device address DA, a bridge bit BR, a broadcast/parity bit B/PA, and a Read/Write bit RW. The device address DA is bit data (5-bit data in the example of FIG. 5) indicating the address of the target device (semiconductor device 1). The bridge bit BR is bit data indicating whether the bridge function of the semiconductor device 1 is on or off. Broadcast/parity bit B/PA is bit data indicating on/off of broadcast of semiconductor device 1 or the parity of data address DA. The Read/Write bit RW is bit data indicating Read or Write.

Here, the bridge bit BR=0 indicates the off of the bridge function, that is, the normal mode (in the received data RX shown in FIG. 5, the bridge function is off). In this case, broadcast/parity bit B/PA indicates whether broadcast is on or off. Broadcast/parity bit B/PA=0 indicates broadcast off, and broadcast/parity bit B/PA=1 indicates broadcast on.

Note that when broadcasting the semiconductor devices 1, as shown in FIG. 6, a plurality of semiconductor devices 1 are connected to the CAN transceiver 40. A device 10 is connected to each semiconductor device 1. When broadcast is on, all of the plurality of semiconductor devices 1 become target devices.

Bridge bit BR=1 indicates that the bridge function is on (in the received data RX shown in FIG. 7, which will be described later, the bridge function is on). In this case, broadcast/parity bit B/PA becomes the parity of device data DA. This makes it possible to detect errors in the device data DA. Note that in the configuration shown in FIG. 6, if the protocols are different for each group of devices 10 connected to each of the plurality of semiconductor devices 1, when the broadcast of the semiconductor device 1 is turned on, the same received data RX is different as received data BRX. The data will be transmitted to the devices 10 according to the protocol, and the protocol will become incompatible with some devices 10. Therefore, when the bridge function is turned on, broadcasting is not performed.

The data number frame ND is bit data indicating the number of frames of the data frame DT. Register address frame AD is bit data indicating an address in register 151. The data frame DT is bit data indicating the data body to be transmitted by the received data RX. The CRC frame CR is bit data indicating an error detection code added to the data frame DT. Note that when the Read/Write bit RW indicates Read, the data frame DT and CRC frame CR are not included in the received data RX.

FIG. 7 is a diagram showing the data structure of received data RX when writing or reading is performed with the device 10 as the target device. The synchronization frame SYN and Read/Write etc. frame RWD in the received data RX shown in FIG. 7 are as described above.

In the received data RX shown in FIG. 7, the data number frame ND indicates the number of frames for the end condition of through output, unlike the case shown in FIG. Control using the data number frame ND will be described later.

In the received data RX shown in FIG. 7, device data DDT follows the data number frame ND. The device data DDT is data that corresponds to the protocol of the device 10, and is to be output as received data BRX. Device data DDT includes device address BDA. The device address BDA indicates the address of the device 10 that is the target device. The position where the device address BDA is placed in the device data DDT is a position according to the protocol of the device 10.

<4. Through output control>
Here, through output control by the semiconductor device 1, that is, control when the bridge function is on, will be described.

FIG. 8 is a timing chart showing communication control when writing to the device 10. From the top of FIG. 8, reception data RX, reception data output selection signal (RX output select), transmission data output selection signal (TX output select), reception data BRX, transmission data BTX, and transmission data TX are shown (FIG. 9 ~The same applies to Figure 11). The received data RX has the configuration shown in FIG. 7.

The received data RX is received by the first receiving unit 11 (FIG. 4). By receiving the first start bit S1 (low level) of the reception data RX, the control unit 15 recognizes the start of reception of the reception data RX. Thereafter, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and recognizes that it is a write from the Read/Write bit RW.

Thereafter, when the data number frame ND is received, the control unit 15 changes the received data output selection signal in the register 151 from a low level to a high level at the stop bit P1 of the data number frame ND (timing t1). As a result, through output of the received data RX is started, and the first receiving section 11 and the first transmitting section 12 output the received data RX as is as the received data BRX. That is, through output of device data DDT (FIG. 7) is performed.

When the received data output selection signal becomes high level, the control unit 15 starts counting the number of frames of received data RX (that is, the number of frames of device data DDT). When the counted number of frames reaches the number of frames indicated by the received data number frame ND, the control unit 15 switches the received data output selection signal to low level and stops the through output (timing t2). Thereafter, the received data BRX is fixed at a high level.

FIG. 9 is a timing chart showing communication control when reading from the device 10. In this case, the received data RX has the configuration shown in FIG. 7.

After receiving the first start bit S1 (low level) of the received data RX, the control unit 15 recognizes that the bridge function is on based on the bridge bit BR included in the received data RX, and also sets the Read/Write bit. It recognizes that it is Read by RW.

Thereafter, when the data number frame ND is received, the control unit 15 changes both the reception data output selection signal and the transmission data output selection signal in the register 151 from a low level to a high level at the stop bit P1 of the data number frame ND. timing t1). As a result, through-output of reception data RX and transmission data BTX is started. The first receiving section 11 and the first transmitting section 12 output the received data RX as is as the received data BRX, that is, through-output of the device data DDT (FIG. 7) is performed. After the output of the received data BRX is completed, the second receiving section 13 and the second transmitting section 14 output the transmission data BTX sent from the device 10 as transmission data TX.

When the received data output selection signal and the transmitted data output selection signal become high level, the control unit 15 starts counting the total number of frames of the received received data RX and the received transmitted data BTX. When the counted number of frames reaches the number of frames indicated by the received data number frame ND, the control unit 15 switches both the received data output selection signal and the transmitted data output selection signal to low level, and stops the through output (timing t2). Thereafter, the received data BRX is fixed at a high level, and the transmitted data TX is fixed at Hi-z (high impedance).

As described above, in this embodiment, the number of frames received by the semiconductor device 1 can be used as the condition for terminating the through output. In particular, in this embodiment, even if transmission of received data RX from the MCU 20 is interrupted due to interrupt processing in the MCU 20, the frame number count does not proceed during the interruption, so through output may be interrupted by mistake. You can avoid putting it away. That is, interruption of the through output can be avoided regardless of the interrupt time, and therefore it is less likely to be restricted by the specifications of the MCU 20.

<5. Modified example of through output control>
The condition for terminating the through output is not limited to the number of frames described above, but may be the number of bits or the time during which the data received by the semiconductor device 1 is continuously at a high level, as in a modification described below.

FIG. 10 is a timing chart showing communication control when writing to the device 10 in a modified example. Here, after the received data output selection signal becomes high level and through output is started, reception of the received data RX is completed and the received data RX is fixed at high level. The control unit 15 monitors whether the number of bits in which the received data RX is continuously at a high level reaches a predetermined number of bits, and switches the received data output selection signal to a low level at the timing (timing t2) when the received data RX reaches a predetermined number of bits. to stop through output. Thereafter, the received data BRX is fixed at a high level. Note that the predetermined number of bits may be selected from a plurality of candidates (eg, 12 bits/24 bits/48 bits/96 bits).

Note that instead of monitoring the number of bits as described above, the control unit 15 may monitor whether the time during which the received data RX is continuously at a high level reaches a predetermined time. In this case, the predetermined time may be selected from a plurality of candidates (eg, 10 μs/20 μs/30 μs/50 μs).

FIG. 11 is a timing chart showing communication control when reading from the device 10 in a modified example. Here, after the reception data output selection signal and the transmission data output selection signal become high level and through output is started, reception of transmission data BTX is completed and transmission data BTX is fixed at high level. The control unit 15 monitors whether the number of bits in which the transmission data BTX is continuously at a high level reaches a predetermined number of bits, and at the timing (timing t2) when the transmission data BTX reaches a predetermined number, the reception data output selection signal and the transmission data output selection signal are set. Switch the signal to low level to stop through output. Thereafter, the received data BRX is fixed at high level, and the transmitted data TX is fixed at Hi-z. Note that the predetermined number of bits may be selected from a plurality of candidates.

Note that instead of monitoring the number of bits as described above, the control unit 15 may monitor whether the time during which the transmission data BTX is continuously at a high level reaches a predetermined time. In this case, the predetermined time may be selected from a plurality of candidates.

According to such a modification, there is no need to include the data number frame ND in the received data RX, and it is possible to set the termination condition for through output. Note that when selecting the predetermined number of bits or the predetermined time from a plurality of candidates, select a candidate corresponding to a time longer than the interrupt time in the MCU 20 in order to avoid interruption of through output.

<6. Others＞
Note that the various technical features disclosed in this specification can be modified in addition to the above-described embodiments without departing from the gist of the technical creation. That is, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is not limited to the above embodiments, and the claims Ranges and equivalents should be understood to include all changes falling within the range.

For example, if a command to the RX terminal 10A is absolutely necessary when outputting transmission data from the TX terminal 10B of the device 10, that is, if the transmission data output of the device 10 can be completely controlled by inputting to the RX terminal 10A, A bridge for the TX terminal 10B of the device 10 is not required. In this case, as shown in FIG. 12, the TX terminal 10B of the device 10 may be connected to the bus BS1 connected to the TX terminal 1B of the semiconductor device 1.

<7. Additional notes>
As described above, the semiconductor device (1) according to one embodiment of the present disclosure includes
A semiconductor device connectable to an external transmitter (40) via a first bus (BS1) and connectable to an external device (10) via a second bus (BS2),
a first receiving unit (11) configured to be able to receive received data (RX) that is serial data from the transmitting device via the first bus;
a first transmitter (12) configured to be connectable to the device via the second bus;
Equipped with
The first receiving unit and the first transmitting unit are configured such that bridge selection data (BR) included in the received data turns on a through output that outputs bit data as it is between the first bus and the second bus. In the case shown, the data (DDT) corresponding to the protocol of the device included in the received data is configured to be through-outputted to the second bus (first configuration).

Further, in the first configuration, when the read/write selection data (RW) included in the received data (RX) indicates write, the first receiving section (11) and the first transmitting section (12 ) may be configured to stop through output to the second bus when the number of received frames of the received data reaches a predetermined number of frames (second configuration).

Furthermore, in the second configuration, the data (ND) indicating the predetermined number of frames may be included in the received data (RX) (third configuration).

Further, in the first configuration, when the read/write selection data (RW) included in the received data (RX) indicates write, the first receiving section (11) and the first transmitting section (12 ) is configured to stop the through output to the second bus when the number of bits or time at which the received data continuously reaches a predetermined logic level reaches a predetermined number of bits or a predetermined time. (fourth configuration).

Furthermore, in the fourth configuration, the predetermined number of bits or the predetermined time may be selectable from a plurality of candidates (fifth configuration).

Further, in any one of the first to fifth configurations, a second receiving section (13) configured to be connectable to the device (10) via the second bus (BS2);
a second transmitter (14) configured to be connectable to the transmitter (40) via the first bus (BS1);
Equipped with
When the bridge selection data (BR) indicates through output is on and the read/write selection data (RW) included in the reception data (RX) indicates read, the second reception section The transmission data (BTX), which is the received serial data, may be configured to be output from the second transmission unit to the first bus (sixth configuration).

Further, in the sixth configuration, when the read/write selection data (RW) included in the received data (RX) indicates read, the first receiving section (11) and the first transmitting section (12 ), the second receiving unit (13), and the second transmitting unit (14), the sum of the number of received frames of the received data and the number of received frames of the transmitted data (BTX) is a predetermined number of frames. It may be configured to stop through output to the first bus (BS1) and the second bus (BS2) when the second bus (BS2) reaches the above (seventh configuration).

Further, in the sixth configuration, when the read/write selection data (RW) included in the received data (RX) indicates read, the first receiving section (11) and the first transmitting section (12 ), the second receiving section (13), and the second transmitting section (14) are arranged so that the transmission data (BTX) continuously reaches a predetermined logic level by a predetermined number of bits or by a predetermined time. It may be configured to stop through output to the first bus (BS1) and the second bus (BS2) when the second bus (BS1) reaches the target (eighth configuration).

Further, in any one of the first to eighth configurations, the received data (RX) includes a device address (DA) of the semiconductor device (1) and a broadcast/parity bit (B/PA). ,
When the bridge selection data (BR) indicates through output is off, the broadcast/parity bit indicates whether broadcast is on or off for the semiconductor device,
When the bridge selection data indicates that through output is on, the broadcast/parity bit may indicate the parity of the device address (ninth configuration).

Further, a communication system (50) according to an aspect of the present disclosure includes a semiconductor device (1) having any one of the first to ninth configurations, the transmitting device (40), the device (10), (10th configuration).

The present disclosure can be used, for example, in an in-vehicle communication system.

1 Semiconductor device

1A RX terminal

1B TX terminal

1C RXD terminal

1D TXD terminal 10 Device

10A RX terminal

10B TX terminal 11 First receiving section 12 First transmitting section 13 Second receiving section 14 Second transmitting section 15

Control section

30, 40 CAN Transceiver

30A TXD terminal

30B RXD terminal 35 CAN bus 40 CAN transceiver 40A RXD terminal 40B TXD terminal 50 Communication system 151

Register

401, 402

CAN transceiver

501, 502 Communication system BS1, BS2 bus

Claims

A semiconductor device connectable to an external transmitting device via a first bus, and connectable to an external device via a second bus,
a first receiving unit configured to be able to receive received data, which is serial data, from the transmitting device via the first bus;
a first transmitter configured to be connectable to the device via the second bus;
Equipped with
The first receiving section and the first transmitting section indicate that the bridge selection data included in the received data is ON of a through output in which the bit data is output as is between the first bus and the second bus. In this case, the semiconductor device is configured to output data included in the received data that corresponds to a protocol of the device to the second bus.
When the read/write selection data included in the received data indicates write, the first receiving section and the first transmitting section perform a process when the number of received frames of the received data reaches a predetermined number of frames. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to stop through output to the second bus.
The semiconductor device according to claim 2, wherein data indicating the predetermined number of frames is included in the received data.
When the read/write selection data included in the received data indicates write, the first receiving section and the first transmitting section determine the number of bits or the time period during which the received data continuously reaches a predetermined logic level. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to stop through output to the second bus when a predetermined number of bits or a predetermined time is reached.
The semiconductor device according to claim 4, wherein the predetermined number of bits or the predetermined time can be selected from a plurality of candidates.
a second receiving section configured to be connectable to the device via the second bus;
a second transmitter configured to be connectable to the transmitter via the first bus;
Equipped with
When the bridge selection data indicates that through output is on, and the read/write selection data included in the received data indicates read, the second reception section transmits the transmission data that is serial data received from the device. 6. The semiconductor device according to claim 1, wherein the semiconductor device is configured to perform through output from the second transmitter to the first bus.
When the read/write selection data included in the received data indicates read, the first receiving section, the first transmitting section, the second receiving section, and the second transmitting section receive the received data. 2. The transmitter is configured to stop through-output to the first bus and the second bus when the sum of the number of frames received and the number of frames of the transmitted data received reaches a predetermined number of frames. 6. The semiconductor device according to 6.
When the read/write selection data included in the received data indicates read, the first receiving section, the first transmitting section, the second receiving section, and the second transmitting section are configured so that the transmitted data is continuous. 7. The through output to the first bus and the second bus is stopped when the number of bits reaches a predetermined number of bits or a predetermined time reaches a predetermined logic level. The semiconductor device described in .
The received data includes a device address of the semiconductor device and a broadcast/parity bit,
When the bridge selection data indicates through output is off, the broadcast/parity bit indicates on/off of broadcast for the semiconductor device,
9. The semiconductor device according to claim 1, wherein when the bridge selection data indicates that through output is on, the broadcast/parity bit indicates parity of the device address.
A communication system comprising the semiconductor device according to any one of claims 1 to 9, the transmitter, and the device.