WO2024008306A1

WO2024008306A1 - Dual polarity power amplifier with nonlinear supply modulation

Info

Publication number: WO2024008306A1
Application number: PCT/EP2022/069074
Authority: WO
Inventors: Henrik Sjöland; Christian Elgaard
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2022-07-08
Filing date: 2022-07-08
Publication date: 2024-01-11

Abstract

A method and a power amplifier with non-linear supply modulation are disclosed. According to one aspect, a method in a power amplifier includes receiving a first input signal and a first modulated supply voltage to produce a first output signal having a first amplitude based on the first modulated supply voltage. The method includes receiving a second input signal and a second modulated supply voltage to produce a second output signal having a second amplitude and a second polarity based on the second modulated supply voltage, there being a relative phase shift between the first and second input signals. The method also includes producing a combined signal that has an amplitude based on one of a sum and a difference of the first and second modulated supply voltages depending on whether a target output signal amplitude is greater than a first threshold.

Description

DUAL POLARITY POWER AMPLIFIER WITH NONLINEAR SUPPLY MODULATION

TECHNICAL FIELD

The present disclosure relates to wireless communications, and in particular, to dual polarity power amplifiers with non-linear supply modulation.

BACKGROUND

The Third Generation Partnership Project (3GPP) has developed and is developing standards for Fourth Generation (4G) (also referred to as Long Term Evolution (LTE)) and Fifth Generation (5G) (also referred to as New Radio (NR)) wireless communication systems. Such systems provide, among other features, broadband communication between network nodes, such as base stations, and mobile wireless devices (WD), as well as communication between network nodes and between WDs.

The Institute of Electrical and Electronics Engineers (I.E.E.E.) has developed standards for wireless local area networks (WLANs) including standards for Wireless Fidelity (Wi-Fi) networks. Such networks include wireless devices that communicate with each other and with a wired or wireless network via one or more access points (APs).

Base stations and wireless devices (whether for 4G, 5G, 6G, WLAN, or other wireless networks) have transmitters for radio frequency (RF) communication. These transmitters have power amplifiers which consume power to amplify an RF signal before it is transmitted over the air. Power efficiency in the power amplifiers is desired to reduce power consumption by the transmitters. High efficiency is difficult to obtain when the trend towards higher data-rates drives the wireless systems to use higher operating frequencies, higher channel bandwidths, and higher order modulations that require less distortion and that have high peak to average power ratios. New solutions that can help obtain high efficiency in present and future wireless system, such as 6G, are therefore desired. Achieving efficiency at high order modulation requires high efficiency not only at peak output power, but also in back-off conditions, since the transmitter will spend a large part of the time in back-off, and more seldomly near the peak. One technique to obtain high efficiency in back-off conditions is to modulate the supply voltage of the power amplifier according to the required output amplitude, so that the supply voltage is not higher than needed for the power amplifier to linearly amplify the signal. This technique is known as envelope tracking. Even higher efficiency can be obtained by operating the power amplifier in deep compression and let the amplitude of the output signal be controlled by the supply voltage rather than by the input signal amplitude. This technique is known as operating the power amplifier in a switched mode. The input signal can then be configured to have a constant envelope carrying only phase information.

The amplitude and phase are thus used to represent the modulated signal, rather than I and Q signal components. This calls for performance of a Cartesian to polar coordinate transformation. This polar architecture, with an input signal of constant envelope carrying the phase component, and with the power amplifier supply voltage being made proportional to the amplitude component, is known as envelope elimination and restoration (EER). For signal modulations with a trajectory passing close to the origin of the constellation diagram, the polar signals have rapid transitions, resulting in wide bandwidth signals that are very difficult to process correctly. There are different polar architectures used, ranging from the pure polar EER, to the more Cartesian-like envelope tracking, with different bandwidthefficiency tradeoffs.

There are also techniques for reducing the bandwidth expansion in polar transmitters by introducing deliberate errors to avoid the signal trajectory getting too close to the origin. This technique is known as hole-punching. According to another technique, the signal trajectory is allowed to pass directly through the origin by using an amplifier capable of using an amplitude signal with two polarities. In this technique, there would be no abrupt transitions in amplitude and phase when the signal trajectory passes through the origin. How to design such a power amplifier has not been fully developed.

A technique to generate amplitude modulated signals from power amplifiers operating at constant amplitude is out-phasing. In out-phasing, two or more power amplifiers generate signals that are out of phase with each other to generate low output signals when the generated signals are combined or that are in phase with each other to generate high output signals. By modulating the phase difference between the amplifier branches, the output signal amplitude after the combiner can be controlled, and the phase modulation is then imposed as a common phase modulation to all amplifier branches. This is a polar architecture and may be implemented with additional non-linear mapping between signal amplitude and phase difference. Hence, this architecture suffers from bandwidth expansion. One example of a known power amplifier suitable for switched mode operation in an out-phasing architecture is shown in FIG. 1. An example of normalized amplitude versus out-phasing angle is shown in FIG. 2. An example of back-off level versus out-phasing angle is shown in FIG. 3. An example of sensitivity versus out-phasing angle is shown in FIG. 4.

The ability for the trajectory to pass directly through the origin without any abrupt phase transition with a two-branch out-phasing amplifier has been identified. By having one such amplifier for the I signal and one for the Q signal, a Cartesian architecture based on out-phasing can be created. No abrupt phase transitions are then needed, and the bandwidth expansion will be limited, as long as sufficient margin is left from the peak power of the system. This is because the amplitude to phase difference mapping becomes very non-linear at the extreme points, with the sensitivity approaching zero at maximum amplitude. See FIG. 4. The amplifiers should have low output impedance, like class-D amplifiers, and a combiner is needed at the output to add the output of the I and the Q amplifiers.

While the two-branch out-phasing amplifier has the ability to pass through the origin without any abrupt signal transitions, it has some other shortcomings. A problem arises when the two branches operate at full output voltage and when only a small (or zero) output signal is needed or desired. The switching losses of the amplifiers will thus be as large at low output amplitudes as at large output amplitudes, which is bad for back-off efficiency. Another issue is that the large signals present from the amplifiers will make the signal quality at low output levels sensitive to combiner accuracy. For instance, even a small amplitude imbalance in the I combiner will create a significant Q component, and vice versa. Another concern is that the load impedance will have a large reactive part, especially at lower output amplitudes, the corresponding load current degrading back-off efficiency. It is also difficult to obtain the full output power of the I or Q amplifier, as the phase difference characteristic is heavily non-linear close to peak power as shown in FIG. 2 and FIG. 4. For instance, 90% of the signal level (0.85dB back off) is reached with a 50 degree out-phasing angle. The gain (sensitivity) at that point is 0.36% of peak amplitude per degree. At zero signal level, the gain is maximum, almost 2.5 times higher, at 0.87% of peak amplitude per degree. The last 10% or so of signal level (from 90% to 100% of peak amplitude) may thus need to be sacrificed to keep bandwidth expansion limited.

SUMMARY

Some embodiments advantageously provide methods and dual polarity power amplifiers with non-linear supply modulation.

In some embodiments, two power amplifiers are connected to a load trough a combiner. The amplifiers operate in a switched mode and their output amplitudes are controlled by the supply voltages. The supply voltages are individually controlled to obtain a desired output voltage having a magnitude and sign that depends on the magnitude and polarity of the input signal. The polarity of the individual amplifiers can also be individually reversed depending on magnitude and polarity of the input signal, e.g., by cross-connecting differential signals. For large output voltage amplitudes, the amplifiers generate in-phase signals at the load, whereas for low output voltage amplitudes, the amplifiers operate in an out-phasing mode to generate out-of-phase signals at the load.

Some embodiments may include one or more of the following features and advantages:

• The use of smooth supply voltage functions having continuous derivatives, even when passing zero amplitude, limits bandwidth expansion;

• Low supply voltage when out-phasing yields high backoff efficiency;

• Minimized reactive load currents result in high backoff efficiency;

• Zero supply voltage having a zero derivative at sign reversal limit distortion due to sign reversal time errors;

• Amplifiers operating in phase at amplitudes above a sign reversal point can reach the full output power available and higher efficiency;

• Out-phasing at low amplitude allows smooth supply voltage curves around zero crossings; and/or

• Some embodiments can be used in polar or Cartesian transmitter.

According to one aspect, a power amplifier includes first amplifier circuitry configured to receive a first input signal and comprising a first modulated supply voltage to produce a first output signal in response to the first input signal, the first output signal having a first amplitude based at least in part on the first modulated supply voltage. The power amplifier includes second amplifier circuitry configured to receive a second input signal and comprising a second modulated supply voltage to produce a second output signal in response to the second input signal, the second output signal having a second amplitude based at least in part on the second modulated supply voltage. The power amplifier also includes the first and second amplifier circuitry being configured to provide a combined signal that is a combination of the first and second output signals, the combined signal having an amplitude determined based at least in part on a sum of the first and second modulated supply voltages when a target output signal amplitude is greater than a first threshold; and having an amplitude determined based at least in part on a difference between the first and second modulated supply voltages when a target output signal amplitude is less than the first threshold.

According to this aspect, in some embodiments, the first polarity is reversed and the second polarity is not reversed to produce the combined signal amplitude based at least in part on the sum of the first and second modulated supply voltages. In some embodiments, a first polarity of the first output signal is reversed and a second polarity of the second output signal is also reversed to produce the combined signal amplitude based at least in part on the difference of the first and second modulated supply voltages. In some embodiments, the first and second modulated supply voltages are based at least in part on at least one of first and second order piecewise polynomials as a function of target output amplitude. In some embodiments, a coefficient of a second order term of a first polynomial representing the first modulated supply voltage is equal to a coefficient of a second order term of a second polynomial representing the second modulated supply voltage. In some embodiments, the sum of the first and second modulated supply voltages is linear in at least a first target output amplitude range, and a magnitude of the difference between the first and second modulated supply voltages is linear in at least a second target output amplitude range. In some embodiments, a slope of one of the first and second output signals is zero and a slope of the other of the first and second output signals is non-zero when the target output signal amplitude is greater than a first threshold; the first and second output signals have slopes of a same sign when the target output signal amplitude is below the first threshold and above a second threshold; and the first and second output signals have slopes of an opposite sign when the target output signal amplitude is less than the second threshold. In some embodiments, the polarity of at least one of the first and second output signal switches between -1 and +1 when at least one of the respective first and second modulated supply voltages falls below a second threshold. In some embodiments, the relative phase shift is caused to switch between 180 degrees and zero degrees when a slope of one of the first and second modulated supply voltages is zero. In some embodiments, the relative phase shift is caused to switch between 180 degrees and zero degrees by cross connecting differential signals.

According to another aspect, a method of power amplification includes: receiving by first amplifier circuitry a first input signal and a first modulated supply voltage to produce a first output signal in response to the first input signal, the first output signal having a first amplitude based at least in part on the first modulated supply voltage; receiving by second amplifier circuitry a second input signal and a second modulated supply voltage to produce a second output signal in response to the second input signal, the second output signal having a second amplitude based at least in part on the second modulated supply voltage; and combining the first and second output signals to produce a combined signal, the combined signal having an amplitude determined based at least in part on a sum of the first and second modulated supply voltages when a target output signal amplitude is greater than a first threshold; and having an amplitude determined based at least in part on a difference between the first and second modulated supply voltages when a target output signal amplitude is less than the first threshold.

In some embodiments, the first polarity is reversed and the second polarity is not reversed to produce the combined signal amplitude based at least in part on the sum of the first and second modulated supply voltages. In some embodiments, a first polarity of the first output signal is reversed and a second polarity of the second output signal is also reversed to produce the combined signal amplitude based at least in part on the difference of the first and second modulated supply voltages. In some embodiments, the first and second modulated supply voltages are based at least in part on at least one of first and second order piecewise polynomials as a function of target output signal amplitude. In some embodiments, a coefficient of a second order term of a first polynomial representing the first modulated supply voltage is equal to a coefficient of a second order term of a second polynomial representing the second modulated supply voltage. In some embodiments, the sum of the first and second modulated supply voltages is linear in at least a first target output amplitude range and a magnitude of the difference between the first and second modulated supply voltages is linear in at least a second target output amplitude range. In some embodiments, a slope of one of the first and second output signals is zero and a slope of the other of the first and second output signals is nonzero when the target output signal amplitude is greater than a first threshold; the first and second output signals have slopes of a same sign when the target output signal amplitude is below the first threshold and above a second threshold; and the first and second output signals have slopes of an opposite sign when the target output signal amplitude is less than the second threshold. In some embodiments, the polarity of at least one of the first and second output signal is switches between -1 and +1 when at least one of the respective first and second modulated supply voltages falls below a second threshold. In some embodiments, the relative phase shift is caused to switch between 180 degrees and zero degrees when a slope of one of the first and second modulated supply voltages is zero. In some embodiments, the relative phase shift is caused to switch between 180 degrees and zero degrees by cross connecting differential signals. BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present embodiments, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIG 1 is a an example of a known amplifier suitable for switched-mode operation;

FIG. 2 is an example of normalized amplitude versus out-phasing angle for an out-phasing amplifier arrangement;

FIG. 3 is an example of back-off level versus out-phasing angle for an out- phasing amplifier arrangement;

FIG. 4 is an example of sensitivity versus out-phasing angle for an out-phasing amplifier arrangement;

FIG. 5 is a schematic diagram of an example network architecture illustrating a communication system according to principles disclosed herein;

FIG. 6 is a block diagram of a network node in communication with a wireless device over a wireless connection according to some embodiments of the present disclosure;

FIG. 7 is a circuit diagram of an example of a dual polarity (DP) power amplifier constructed in accordance with principles disclosed herein;

FIG. 8 is a flowchart of an example process in a dual polarity power amplifier with non-linear supply modulation according to principles disclosed herein;

FIG. 9 is a graph of two modulated supply voltages Vddl and Vdd2 versus amplitude of the input signal;

FIG. 10 shows output power versus backoff level for the DP power amplifier of FIG. 7;

FIG. 11 is a graph of amplitude-to-amplitude modulation (AMAM) for negative and positive amplitudes versus back-off value for the DP power amplifier of FIG. 7;

FIG. 12 is a graph of amplitude-to-phase modulation (AMPM) for negative and positive amplitudes versus back-off value for the DP power amplifier of FIG. 7;

FIG. 13 is a graph of drain efficiency for the DP power amplifier of FIG. 7; FIG. 14 is an example of results of a time domain simulation of the DP power amplifier of FIG. 7;

FIG. 15 is a circuit diagram of a Cartesian DP power amplifier; and

FIG. 16 is a graph of results of a time domain simulation of the Cartesian DP power amplifier of FIG. 15.

DETAILED DESCRIPTION

Before describing in detail example embodiments, it is noted that the embodiments reside primarily in combinations of apparatus components and processing steps related to dual polarity power amplifiers with non-linear supply modulation. Accordingly, components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

As used herein, relational terms, such as “first” and “second,” “top” and “bottom,” and the like, may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In embodiments described herein, the joining term, “in communication with” and the like, may be used to indicate electrical or data communication, which may be accomplished by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling or optical signaling, for example. One having ordinary skill in the art will appreciate that multiple components may interoperate and modifications and variations are possible of achieving the electrical and data communication.

In some embodiments described herein, the term “coupled,” “connected,” and the like, may be used herein to indicate a connection, although not necessarily directly, and may include wired and/or wireless connections.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The term “network node” used herein can be any kind of network node comprised in a radio network which may further comprise any of base station (BS), radio base station, base transceiver station (BTS), base station controller (BSC), radio network controller (RNC), g Node B (gNB), evolved Node B (eNB or eNodeB), Node B, multi-standard radio (MSR) radio node such as MSR BS, multi-cell/multicast coordination entity (MCE), relay node, donor node controlling relay, radio access point (AP), transmission points, transmission nodes, Remote Radio Unit (RRU) Remote Radio Head (RRH), a core network node (e.g., mobile management entity (MME), self-organizing network (SON) node, a coordinating node, positioning node, MDT node, etc.), an external node (e.g., 3rd party node, a node external to the current network), nodes in distributed antenna system (DAS), a spectrum access system (SAS) node, an element management system (EMS), etc. The network node may also comprise test equipment. The term “radio node” used herein may be used to also denote a wireless device (WD) such as a wireless device (WD) or a radio network node.

In some embodiments, the non-limiting terms wireless device (WD) or a user equipment (UE) are used interchangeably. The WD herein can be any type of wireless device capable of communicating with a network node or another WD over radio signals, such as wireless device (WD). The WD may also be a radio communication device, target device, device to device (D2D) WD, machine type WD or WD capable of machine to machine communication (M2M), low-cost and/or low-complexity WD, a sensor equipped with WD, Tablet, mobile terminals, smart phone, laptop embedded equipped (LEE), laptop mounted equipment (LME), USB dongles, Customer Premises Equipment (CPE), an Internet of Things (loT) device, or a Narrowband loT (NB-IOT) device etc.

Also, in some embodiments the generic term “radio network node” is used. It can be any kind of a radio network node which may comprise any of base station, radio base station, base transceiver station, base station controller, network controller, RNC, evolved Node B (eNB), Node B, gNB, Multi-cell/multicast Coordination Entity (MCE), relay node, access point, radio access point, Remote Radio Unit (RRU) Remote Radio Head (RRH).

Note that although terminology from one particular wireless system, such as, for example, 3GPP LTE and/or New Radio (NR), may be used in this disclosure, this should not be seen as limiting the scope of the disclosure to only the aforementioned system. Other wireless systems, including without limitation Wide Band Code Division Multiple Access (WCDMA), Worldwide Interoperability for Microwave Access (WiMax), Ultra Mobile Broadband (UMB) and Global System for Mobile Communications (GSM), may also benefit from exploiting the ideas covered within this disclosure.

Note further, that functions described herein as being performed by a wireless device or a network node may be distributed over a plurality of wireless devices and/or network nodes. In other words, it is contemplated that the functions of the network node and wireless device described herein are not limited to performance by a single physical device and, in fact, can be distributed among several physical devices.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Some embodiments are directed to dual polarity power amplifiers with nonlinear supply modulation. In some embodiments, the supply voltages are square law functions of target amplitude. At zero amplitude the two supply voltages are equal, so that no output signal is produced, due to symmetry and assuming closely matched amplifiers and a well-matched combiner. The square law functions have the same second order coefficient, one function being zero with a zero derivative at a negative value of the target amplitude, and the other function being zero with a zero derivative at a positive value of the target amplitude. Ideally, this configuration creates a linear output amplitude characteristic in the out-phasing region, as the difference of the derivatives with respect to amplitude of the two supply voltages is constant. When square law functions are used for the supply voltages, sharp supply voltage corners are avoided as the input signal passes through zero amplitude, i.e., between positive and negative amplitudes.

As the supply voltage of an amplifier reaches zero, the signal polarity of the amplifier is reversed. For instance, for a differential signal, the signal halves can be cross-connected with switches to reverse the signal polarity. The signal polarity can be reversed at the input of the amplifier, at internal nodes of the amplifier, or at the amplifier output. The switches for sign reversal may be located where the signal level is low, to reduce their impact on power efficiency i.e. at the amplifier input. At amplitudes above the level where the supply voltage reaches zero for one of the amplifiers, the two amplifiers may operate in phase, to be able to provide all available output power to the load. The supply voltage of the sign-reversed amplifier continues on the same parabola (second order function), smoothly touching zero supply voltage at the point of sign reversal. Both the supply voltage and its derivative are then equal to zero, making the scheme less sensitive to timing errors or glitches in the sign reversal. When out-phasing, the difference of the derivatives should be constant to create a linear characteristic, whereas when operating in phase, the sum of derivatives should instead be constant To keep the sum of derivatives of the two supply voltage curves constant, the second order coefficient of the other supply voltage function is reversed in sign. The curves fit together with a continuous voltage and continuous first order derivative. In some embodiments, when the output voltage amplitude reaches a level corresponding to a supply voltage maxima of the amplifier having a negative second order coefficient, further increases in output voltage amplitude may be achieved by keeping that supply voltage fixed at the maxima, while linearly increasing the supply voltage of the other amplifier with a continuation of the parabola that is continuous in both magnitude and derivative. The maximum output is reached when both amplifiers have the same supply voltage.

The supply voltages are piecewise linear and second order functions, which are simple to calculate and provide smooth curves with a continuous derivative over the full signal range. The full signal range can be used, with both amplifiers able to operate in phase with full voltage without any signal degradation due to bandwidth expansion near peak amplitude as compared to known out-phasing amplifiers. The signal polarity switching takes place at zero supply voltage and zero derivative. The efficiency is high since the supply voltage is low in back-off and reactive load currents may be minimized when the amplifiers are supply modulated rather than out-phased.

The dual polarity amplifier can be used in a polar transmitter where the trajectory is able to pass directly through the origin. This provides additional degrees of freedom that can be used for bandwidth reduction. Or, in a Cartesian transmitter with one amplifier pair used for the I signal and one for the Q signal, some embodiments may also include a combiner for the I and Q signals at the output.

When used in a Cartesian transmitter, the problem of time synchronization between amplitude and phase related to polar transmitters may be avoided. The phase and amplitude information is a combination of the I and Q signals, which can be fed through two identical paths.

The amplifiers may operate in switched mode, and their supply voltages are individually controlled, depending on the magnitude and sign of the desired output amplitude. The magnitude and sign of the desired output amplitude also control the polarity of the input signals. The signal polarity of the individual amplifiers can be reversed, e.g., by cross-connecting differential signals, so that for large output amplitudes, the amplifiers generate in-phase signals at the load, whereas for low output amplitudes the amplifiers may operate in an out-phasing mode. The supply voltages versus target amplitude functions may be piecewise linear or parabolic, which may be continuous functions and have a continuous derivative. At a point of sign reversal, both the supply voltage and its derivative are equal to zero for low sensitivity to timing errors. The amplifier arrangement can be used in a polar transmitter with direct origin passages, or in a Cartesian transmitter with one arrangement for I and one for Q, with a combiner for I and Q at the transmitter output. When used in a Cartesian transmitter, the problem of time synchronization problem between amplitude and phase related to polar transmitters is avoided. The phase and amplitude information is a combination of the I and Q signals, which can be fed through two identical paths.

Returning to the drawing figures, in which like elements are referred to by like reference numerals, there is shown in FIG. 5 a schematic diagram of a communication system 10, according to an embodiment, such as a 3 GPP -type cellular network or WLAN network that may support standards such as LTE and/or NR (5G) and/or WiFi,, which comprises an access network 12, such as a radio access network, and a core network 14. The access network 12 comprises a plurality of network nodes 16a, 16b, 16c (referred to collectively as network nodes 16), such as NBs, eNBs, gNBs or other types of wireless access points, each defining a corresponding coverage area 18a, 18b, 18c (referred to collectively as coverage areas 18). Each network node 16a, 16b, 16c is connectable to the core network 14 over a wired or wireless connection 20. A first wireless device (WD) 22a located in coverage area 18a is configured to wirelessly connect to, or be paged by, the corresponding network node 16a. A second WD 22b in coverage area 18b is wirelessly connectable to the corresponding network node 16b. While a plurality of WDs 22a, 22b (collectively referred to as wireless devices 22) are illustrated in this example, the disclosed embodiments are equally applicable to a situation where a sole WD is in the coverage area or where a sole WD is connecting to the corresponding network node 16. Note that although only two WDs 22 and three network nodes 16 are shown for convenience, the communication system may include many more WDs 22 and network nodes 16.

Also, it is contemplated that a WD 22 can be in simultaneous communication and/or configured to separately communicate with more than one network node 16 and more than one type of network node 16. For example, a WD 22 can have dual connectivity with a network node 16 that supports LTE and the same or a different network node 16 that supports NR. As an example, WD 22 can be in communication with an eNB for LTE/E-UTRAN and a gNB for NR/NG-RAN.

Example implementations, in accordance with an embodiment, of the WD 22 and network node 16 discussed in the preceding paragraphs will now be described with reference to FIG. 6.

The communication system 10 includes a network node 16 provided in a communication system 10 and including hardware 28 enabling it to communicate with the WD 22. The hardware 28 may include a radio interface 30 for setting up and maintaining at least a wireless connection 32 with a WD 22 located in a coverage area 18 served by the network node 16. The radio interface 30 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and/or one or more RF transceivers. The radio interface 30 includes an array of antennas 34 to radiate and receive signal(s) carried by electromagnetic waves. The radio interface 30 also includes a dual polarity (DP) power amplifier 24 which is configured to amplify RF signals to be radiated by the antennas 34. Note that although only one DP power amplifier 24 is shown in FIG. 6, a network node may typically have more than one DP power amplifier 24.

In the embodiment shown, the hardware 28 of the network node 16 further includes processing circuitry 36. The processing circuitry 36 may include a processor 38 and a memory 40. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 36 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs (Field Programmable Gate Array) and/or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 38 may be configured to access (e.g., write to and/or read from) the memory 40, which may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM (Random Access Memory) and/or ROM (Read-Only Memory) and/or optical memory and/or EPROM (Erasable Programmable Read-Only Memory).

Thus, the network node 16 further has software 42 stored internally in, for example, memory 40, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the network node 16 via an external connection. The software 42 may be executable by the processing circuitry 36. The processing circuitry 36 may be configured to control any of the methods and/or processes described herein and/or to cause such methods, and/or processes to be performed, e.g., by network node 16. Processor 38 corresponds to one or more processors 38 for performing network node 16 functions described herein. The memory 40 is configured to store data, programmatic software code and/or other information described herein. In some embodiments, the software 42 may include instructions that, when executed by the processor 38 and/or processing circuitry 36, causes the processor 38 and/or processing circuitry 36 to perform the processes described herein with respect to network node 16.

The communication system 10 further includes the WD 22 already referred to. The WD 22 may have hardware 44 that may include a radio interface 46 configured to set up and maintain a wireless connection 32 with a network node 16 serving a coverage area 18 in which the WD 22 is currently located. The radio interface 46 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and/or one or more RF transceivers. The radio interface 46 includes an array of antennas 48 to radiate and receive signal(s) carried by electromagnetic waves. The radio interface 46 also includes a dual polarity (DP) power amplifier 26 which is configured to amplify RF signals to be radiated by the antennas 48. Note that although only one DP power amplifier 26 is shown in FIG. 6, a WD may typically have more than one DP power amplifier 26.

The hardware 44 of the WD 22 further includes processing circuitry 50. The processing circuitry 50 may include a processor 52 and memory 54. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 50 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs (Field Programmable Gate Array) and/or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 52 may be configured to access (e.g., write to and/or read from) memory 54, which may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM (Random Access Memory) and/or ROM (Read-Only Memory) and/or optical memory and/or EPROM (Erasable Programmable Read-Only Memory).

Thus, the WD 22 may further comprise software 56, which is stored in, for example, memory 54 at the WD 22, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the WD 22. The software 56 may be executable by the processing circuitry 50. The software 56 may include a client application 58. The client application 58 may be operable to provide a service to a human or non-human user via the WD 22.

The processing circuitry 50 may be configured to control any of the methods and/or processes described herein and/or to cause such methods, and/or processes to be performed, e.g., by WD 22. The processor 52 corresponds to one or more processors 52 for performing WD 22 functions described herein. The WD 22 includes memory 54 that is configured to store data, programmatic software code and/or other information described herein. In some embodiments, the software 56 and/or the client application 58 may include instructions that, when executed by the processor 52 and/or processing circuitry 50, causes the processor 52 and/or processing circuitry 50 to perform the processes described herein with respect to WD 22.

In some embodiments, the inner workings of the network node 16 and WD 22 may be as shown in FIG. 6 and independently, the surrounding network topology may be that of FIG. 5.

The wireless connection 32 between the WD 22 and the network node 16 is in accordance with the teachings of the embodiments described throughout this disclosure. More precisely, the teachings of some of these embodiments may improve the data rate, latency, and/or power consumption and thereby provide benefits such as reduced user waiting time, relaxed restriction on file size, better responsiveness, extended battery lifetime, etc. In some embodiments, a measurement procedure may be provided for the purpose of monitoring data rate, latency and other factors on which the one or more embodiments improve.

FIG. 7 is a circuit diagram of one example of dual polarity power amplifiers 24, 26. Note that although the topology in FIG. 7 is shown to be the same for the DP power amplifier 24 in the network node 16 and the DP power amplifier 26 in the WD 22, the DP power amplifier 24 and the DP power amplifier 26 may be designed to meet different power requirements for power amplifiers at the network node and power amplifiers in the WD 22. The example DP power amplifier 24, 26 includes two power amplifier circuits 60 and 62. Amplifier circuit 60 receives a first input signal 64 and amplifier circuit 62 receives a second input signal 66. Both the first and second input signals 64, 66 are cosine waves having equal amplitude and a common phase modulation 0_m, and differ in phase by 0i - 02, where 0i and 02 are either zero or 180 degrees. Amplifier circuit 60 is supplied by a first modulated supply voltage 68 and amplifier circuit 62 is supplied by a second modulated supply voltage 70. First amplifier circuit 60 outputs a first output signal 72 and second amplifier circuit 62 outputs a second output signal 74. A combiner 76 combines the first output signal 72 and the second output signal 74 to produce a combined signal delivered to the load 78. Although the combiner 76 is shown in FIG. 7 as a transformer, other types of combiners such as summing circuitry may be used to combine the first and second output signals 72, 74.

FIG. 8 is a flowchart of an example process in a dual polarity power amplifier 24, 26 with non-linear supply modulation, receiving by first amplifier circuitry 60 a first input signal 64 and a first modulated supply voltage 68 to produce a first output signal 72 in response to the first input signal 64, the first output signal 72 having a first amplitude based at least in part on the first modulated supply voltage 68 (Block S10). The process also includes receiving by second amplifier circuitry 62 a second input signal 66 and a second modulated supply voltage 70 to produce a second output signal 74 in response to the second input signal 66, the second output signal 74 having a second amplitude based at least in part on the second modulated supply voltage 70 (Block S12). The process also includes combining the first and second output signals 72, 74 to produce a combined signal, the combined signal having an amplitude determined based at least in part on a sum of the first and second modulated supply voltages 68, 70 when a target output signal amplitude is greater than a first threshold; and having an amplitude determined based at least in part on a difference between the first and second modulated supply voltages 68, 70 when a target output signal amplitude is less than the first threshold (Block S14).

In some embodiments, a first polarity of the first output signal is reversed and a second polarity of the second output signal is not reversed to produce the combined signal amplitude based at least in part on the sum of the first and second modulated supply voltages. In some embodiments, a first polarity of the first output signal is reversed and a second polarity of the second output signal is also reversed to produce the combined signal amplitude based at least in part on the difference of the first and second modulated supply voltages. In some embodiments, the first and second modulated supply voltages are based at least in part on at least one of first and second order piecewise polynomials as a function of target output signal amplitude. In some embodiments, a coefficient of a second order term of a first polynomial representing the first modulated supply voltage is equal to a coefficient of a second order term of a second polynomial representing the second modulated supply voltage. In some embodiments, the sum of the first and second modulated supply voltages is linear in at least a first target output amplitude range and a magnitude of the difference between the first and second modulated supply voltages is linear in at least a second target output amplitude range. In some embodiments, a slope of one of the first and second output signals is zero and a slope of the other of the first and second output signals is non-zero when the target output signal amplitude is greater than a first threshold; the first and second output signals have slopes of a same sign when the target output signal amplitude is below the first threshold and above a second threshold; and the first and second output signals have slopes of an opposite sign when the target output signal amplitude is less than the second threshold. In some embodiments, the polarity of at least one of the first and second output signal is switched between -1 and +1 when at least one of the respective first and second modulated supply voltages falls below a second threshold. In some embodiments, the relative phase shift is caused to switch between 180 degrees and zero degrees when a slope of one of the first and second modulated supply voltages is zero. In some embodiments, the relative phase shift is caused to switch between 180 degrees and zero degrees by cross connecting differential signals.

FIG. 9 is a graph of two modulated supply voltages Vddl and Vdd2 and a resultant combined supply voltage output. In regions 1 and 5, the combined supply voltage output amplitude is above a first threshold. In these regions, one supply voltage has zero slope and the other supply voltage has non-zero slope. In regions 2 and 4, where the combined supply voltage output is less than the first threshold and greater than a second threshold, the slope of the two supply voltages are the same. Below the second threshold, in region 3, the slopes of the two supply voltages are opposite in sign.

To demonstrate the operation of the DP power amplifier 24, 26, a test bench using the GF 22nm FDSOI PDK was set up and simulated in a Cadence circuit simulator. The supply voltages Vddl (68) and Vdd2 (70) were modulated using the functions of FIG. 9 and the parameters shown in Table 1. An input signal of constant amplitude of 0.8V was used to drive the two DP amplifiers 60-62. The phase shift 0i and 02 are defined in Table 2. These phase shifts are used to control the polarity of the input signals, so that the amplifiers operate in an out-phasing mode at low amplitudes, and operate in phase at higher amplitudes. Table 1

Table 2

Comments on phase switching As shown in Table 2, the input signal to PAI (amplifier circuit 60) should be phase shifted by 180 degrees when the trajectory goes from region 2 to region 3, or from region 3 to region 2, and PA2 (second amplifier circuit 62) should be phase shifted by 180 degrees when the trajectory goes from region 3 to region 4 or from region 4 to region 3. Since the amplifier circuit 60 or 62 that has its input signal phase shifted ideally should produce zero output signal, since the supply voltage is equal to zero at the time of the phase reversal, the phase shift may be expected to be carried out smoothly without effect on signal fidelity. Moreover, as the supply voltage (such as modulated supply voltage 68 or 70) decreases toward zero slowly and symmetrically from both sides, there will be time to perform the phase shifting, relative to the modulation bandwidth. As an example, if the switching is restricted to occur when the output signal from the amplifier circuit having its input signal polarity switched is below -40 dB of the peak value, as much as 7% of the symbol time is an available time window to perform the switching of the input signal.

Simulation results

The results of the simulations are shown in FIGS. 10-12 below. The amplifier arrangement described herein may also be implemented in a Cartesian transmitter.

FIG. 10 illustrates output power for the circuit in FIG. 7. The upper plot is for positive amplitude and the lower plot is for negative amplitude. The output power is very linear and Pmax is 10 dBm. Above -12 dB backoff, for input vector =0.25 (or -0.25), the DP power amplifier 24, 26 goes from out-phasing mode to in- phase mode..

FIG. 11 illustrates amplitude-to-amplitude modulation (AMAM) plotted for positive and negative amplitudes versus back-off value in dB. An extra simulation point can be seen at -12 dB back-off where the DP power amplifier 24, 26 goes from out-phasing mode to in-phase mode.

FIG. 12 illustrates output phase for the circuit in FIG. 7. The upper plot is for positive amplitude and lower plot is for negative amplitude. Maximum amplitude- to-phase modulation (AM-PM) is about 2 degrees. Above -12 dB backoff, and with the input vector = 0.25 (or -0.25), the DP power amplifier 24, 26 goes from out- phasing mode to in-phase mode.

FIG. 13 illustrates drain efficiency for the circuit in FIG. 7. The upper plot is for positive amplitude and the lower plot is for negative amplitude. Drain efficiency is above 60% above -20dB backoff. Above -12 dB backoff, and with the input vector =0.25 (or -0.25), the DP power amplifier 24, 26 goes from out-phasing mode to in-phase mode.

FIG. 14 illustrates an example time domain simulation when linearly sweeping the input amplitude from maximum negative amplitude to maximum positive amplitude, and back, and controlling the supply voltages Vddl 68 and Vdd2 70 for the circuit in FIG. 7. When the input vector goes from a negative value to a positive value, which occurs at zero output voltage, the phase alters by 180 degrees.

FIG. 15 is a diagram of an amplifier portion of a Cartesian transmitter based on a combination of two DP power amplifiers 80-1 and 80-Q, each DP power amplifier 80-1, 80-Q may be designed as disclosed above with respect to FIG. 7. One of the DP power amplifiers 80-1 is configured to transmit I signals and the other DP power amplifier 80-Q is configured to transmit Q signals. The I-amplifier 80-1 has a first amplifier circuit 60-1, that operates as explained above with reference to first amplifier circuit 60. The I-amplifier 80-1 also has a second amplifier circuit 62- I, that operates as explained above with reference to second amplifier circuit 62. Similarly, the Q-amplifier 80-Q has a first amplifier circuit 60-Q, that operates as explained above with reference to first amplifier circuit 60. The Q-amplifier 80-Q also has a second amplifier circuit 62-Q, that operates as explained above with reference to second amplifier circuit 62.

FIG. 16 illustrates a graph of example results of a time domain simulation for a complete 100 MHz orthogonal frequency division multiplexed (OFDM) modulated IQ signal. The upper plot shows an ideal envelope and output signal at 2.5 GHz. The plot in the middle shows the I vector and its corresponding supply voltages. The lower plot shows the Q vector and its corresponding supply voltages.

Abbreviations that may be used in the preceding description include: Abbreviation Explanation

ADC Analog to Digital Converter

CMOS Complementary Metal Oxide Semiconductor

DAC Digital to Analog Converter

DC Direct Current

Det Detector

DPD Digital Predistortion

FFT Fast Fourier Transform

I In Phase

IM Intermodulation IMD Intermodulation distortion

Mult Complex Multiplier

N Number of PA outputs to combine

PA Power Amplifier

PGA Programmable Gain Amplifier

Q Quadrature Phase

RF Radio Frequency

TDD Time Division Duplex

T-line Transmission Line

TX Transmitter

VGA Variable Gain Amplifier

It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings without departing from the scope of the following claims.

Claims

CLAIMS What is claimed is:

1. A power amplifier (24, 26), comprising: first amplifier circuitry (60) configured to receive a first input signal (64) and comprising a first modulated supply voltage (68) to produce a first output signal (72) in response to the first input signal (64), the first output signal (72) having a first amplitude based at least in part on the first modulated supply voltage (68); second amplifier circuitry (62) configured to receive a second input signal (66) and comprising a second modulated supply voltage (70) to produce a second output signal (74) in response to the second input signal (66), the second output signal (74) having a second amplitude based at least in part on the second modulated supply voltage (70); and a combiner to combine the first and second output signals to produce a combined signal having an amplitude determined based at least in part on a sum of the first and second modulated supply voltages (68, 70) when a target output signal amplitude is greater than a first threshold; and having an amplitude determined based at least in part on a difference between the first and second modulated supply voltages (68, 70) when a target output signal amplitude is less than the first threshold.

2. The power amplifier (24, 26) of Claim 1, wherein a first polarity of the first output signal is reversed and a second polarity of the second output signal is not reversed to produce the combined signal amplitude based at least in part on the sum of the first and second modulated supply voltages (68, 70).

3. The power amplifier (24, 26) of any of Claims 1 and 2, wherein a first polarity of the first output signal is reversed and a second polarity of the second output signal is also reversed to produce the combined signal amplitude based at least in part on the difference of the first and second modulated supply voltages (68, 70).

4. The power amplifier (24, 26) of any of Claims 1-3, wherein the first and second modulated supply voltages (68, 70) are based at least in part on at least one of first and second order piecewise polynomials as a function of target output amplitude.

5. The power amplifier (24, 26) of Claim 4, wherein a coefficient of a second order term of a first polynomial representing the first modulated supply voltage (68) is equal to a coefficient of a second order term of a second polynomial representing the second modulated supply voltage (70).

6. The power amplifier (24, 26) of any of Claims 1-5, wherein the sum of the first and second modulated supply voltages (68, 70) is linear in at least a first target output amplitude range, and a magnitude of the difference between the first and second modulated supply voltages (68, 70) is linear in at least a second target output amplitude range.

7. The power amplifier (24, 26) of any of Claims 1-6, wherein: a slope of one of the first and second output signals is zero and a slope of the other of the first and second output signals is non-zero when the target output signal amplitude is greater than a first threshold; the first and second output signals (72, 74) have slopes of a same sign when the target output signal amplitude is below the first threshold and above a second threshold; and the first and second output signals (72, 74) have slopes of an opposite sign when the target output signal amplitude is less than the second threshold.

8. The power amplifier (24, 26) of any of Claims 1-6, wherein the polarity of at least one of the first and second output signal (74) switches between -1 and +1 when at least one of the respective first and second modulated supply voltages (68, 70) falls below a second threshold.

9. The power amplifier (24, 26) of any of Claims 1-8, wherein the relative phase shift is caused to switch between 180 degrees and zero degrees when a slope of one of the first and second modulated supply voltages (68, 70) is zero.

10. The power amplifier (24, 26) of any of Claims 1-9, wherein the relative phase shift is caused to switch between 180 degrees and zero degrees by cross connecting differential signals.

11. A method of power amplification, the method comprising: receiving (S10) by first amplifier circuitry (60) a first input signal (64) and a first modulated supply voltage (68) to produce a first output signal (72) in response to the first input signal (64), the first output signal (72) having a first amplitude based at least in part on the first modulated supply voltage (68); receiving (SI 2) by second amplifier circuitry (62) a second input signal (66) and a second modulated supply voltage (70) to produce a second output signal (74) in response to the second input signal (66), the second output signal (74) having a second amplitude based at least in part on the second modulated supply voltage (70); and combining (S14) the first and second output signals to produce a combined signal, the combined signal having an amplitude determined based at least in part on a sum of the first and second modulated supply voltages (68, 70) when a target output signal amplitude is greater than a first threshold; and having an amplitude determined based at least in part on a difference between the first and second modulated supply voltages (68, 70) when a target output signal amplitude is less than the first threshold.

12. The method of Claim 11, wherein a first polarity of the first output signal is reversed and a second polarity of the second output signal is not reversed to produce the combined signal amplitude based at least in part on the sum of the first and second modulated supply voltages (68, 70).

13. The method of any of Claims 11 and 12, wherein a first polarity of the first output signal is reversed and a second polarity of the second output signal is also reversed to produce the combined signal amplitude based at least in part on the difference of the first and second modulated supply voltages (68, 70).

14. The method of any of Claims 11-13, wherein the first and second modulated supply voltages (68, 70) are based at least in part on at least one of first and second order piecewise polynomials as a function of target output signal amplitude.

15. The method of Claim 14, wherein a coefficient of a second order term of a first polynomial representing the first modulated supply voltage (68) is equal to a coefficient of a second order term of a second polynomial representing the second modulated supply voltage (70).

16. The method of any of Claims 11-15, wherein the sum of the first and second modulated supply voltages (68, 70) is linear in at least a first target output amplitude range, and a magnitude of the difference between the first and second modulated supply voltages (68, 70) is linear in at least a second target output amplitude range.

17. The method of any of Claims 11-16, wherein: a slope of one of the first and second output signals is zero and a slope of the other of the first and second output signals is non-zero when the target output signal amplitude is greater than a first threshold; the first and second output signals (72, 74) have slopes of a same sign when the target output signal amplitude is below the first threshold and above a second threshold; and the first and second output signals (72, 74) have slopes of an opposite sign when the target output signal amplitude is less than the second threshold.

18. The method of any of Claims 11-17, wherein the polarity of at least one of the first and second output signal (74) is switches between -1 and +1 when at least one of the respective first and second modulated supply voltages (68, 70) falls below a second threshold.

19. The method of any of Claims 11-18, wherein the relative phase shift is caused to switch between 180 degrees and zero degrees when a slope of one of the first and second modulated supply voltages (68, 70) is zero.

20. The method of any of Claims 11-19, wherein the relative phase shift is caused to switch between 180 degrees and zero degrees by cross connecting differential signals.