WO2024006183A1 - Adaptation d'alimentation électrique de commutation à transistor divisé sur la base d'une condition - Google Patents

Adaptation d'alimentation électrique de commutation à transistor divisé sur la base d'une condition Download PDF

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Publication number
WO2024006183A1
WO2024006183A1 PCT/US2023/026189 US2023026189W WO2024006183A1 WO 2024006183 A1 WO2024006183 A1 WO 2024006183A1 US 2023026189 W US2023026189 W US 2023026189W WO 2024006183 A1 WO2024006183 A1 WO 2024006183A1
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Prior art keywords
power supply
signal
control signal
logic circuit
gate
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PCT/US2023/026189
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English (en)
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A. Robert NEIDORFF
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Texas Instruments Incorporated
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Publication of WO2024006183A1 publication Critical patent/WO2024006183A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0029—Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H03K17/122—Modifications for increasing the maximum permissible switched current in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H03K17/164—Soft switching using parallel switching arrangements

Definitions

  • This description relates to switching power supplies, and more particularly, to techniques for adapting split-transistor switching power supplies based on a condition such as temperature and/or process strength.
  • a switching power supply is commonly used to transfer power from an AC or DC input power source to a DC load by switching one or more power transistors (such as metal oxide semiconductor field effect transistors, MOSFETs) coupled via a switching node to an energy storage element (such as an inductor, a transformer via an inductance of the transformer, and/or a capacitor), which in turn is capable of coupling to a load.
  • a switching power supply may further include a controller that provides drive signals to a corresponding gate of a given power transistor.
  • the power transistor(s) are switched on or off which causes rapid changes in current, generally referred to as switching current.
  • the switching current can cause ringing to manifest at the output of the power supply. Accordingly, a number of non-trivial issues remain with switching power supplies.
  • a switching power supply includes a switching element and a logic circuit.
  • the switching element includes two or more parallel-coupled transistors.
  • the logic circuit has a first logic circuit input, a second logic circuit input, and a logic circuit output.
  • the logic circuit is configured to: (a) receive at the first logic circuit input a pulse width modulation (PWM) signal, (b) receive at the second logic circuit input a logic control signal that is based on one or more conditions, and (c) provide from the logic circuit output to a gate of one of the two or more parallel- coupled transistors a gate control signal that is based on both the PWM signal and the logic control signal.
  • PWM pulse width modulation
  • one or more conditions on which the logic control signal is based include one or both of process strength associated with the switching element and ambient temperature associated with the power supply. Other conditions may be used (e.g., ringing amplitude, input voltage, load current, and/or switching speed).
  • a switching power supply that includes a switching element and a logic circuit.
  • the switching element includes a plurality of parallel-coupled transistors.
  • the logic circuit is configured to: (a) initially provide one or more gate drive signals to one or more of the parallel-coupled transistors, respectively, but not to all of the parallel-coupled transistors, and (b) after a delay period provide a respective gate drive signal to each of the parallel-coupled transistors, the initially-provided one or more gate signals being based on one or more conditions.
  • the one or more conditions may include one or more of drain -to- source on- resistance (RdsOn) associated with the switching element, ambient temperature associated with the power supply, ringing amplitude, input voltage, load current, and/or switching speed.
  • Ron drain -to- source on- resistance
  • Another example is method for controlling a switching power supply that includes a switching element having two or more parallel-coupled transistors.
  • the method includes receiving a pulse width modulation (PWM) control signal, and generating a logic control signal that is based on one or both of process strength associated with the switching element and ambient temperature associated with the power supply. Responsive to the logic control signal indicating that the process strength and/or ambient temperature is beyond a given threshold, the method includes initially providing one or more gate drive signals to a first set of the two or more parallel-coupled transistors, respectively, the first set including one or more but not all of the two or more parallel- coupled transistors, and after a delay period providing a respective gate drive signal to each of the two or more parallel-coupled transistors.
  • PWM pulse width modulation
  • the method includes initially providing one or more gate drive signals to a second set of the two or more parallel- coupled transistors, respectively, the second set having one or more fewer transistors than the first set or one or more different transistors than the first set, and after a delay period providing a respective gate drive signal to each of the two or more parallel-coupled transistors.
  • the logic control signal may be based on conditions other than process strength and/or temperature (or in addition to process strength and/or temperature), such as ringing amplitude, input voltage, load current, and/or switching speed.
  • FIG. 1A illustrates a split-transistor switching power supply, in an example.
  • FIG. IB illustrates example waveforms of the split-transistor switching power supply of FIG. 1A.
  • FIG. 1C illustrates a split-transistor switching power supply, in another example.
  • FIG. ID illustrates example waveforms of the split-transistor switching power supply of
  • FIG. 2A is a diagrammatic representation of FIG. 2A.
  • FIG. IE comparatively illustrates example switching power supply output waveforms with ringing undamped and damped, in an example.
  • FIGS. 2A-B each illustrates a split-transistor switching power supply, in another example.
  • FIG. 3 is a schematic diagram of a split-transistor switching power supply, in an example.
  • FIG. 4 is a schematic diagram of a split-transistor switching power supply, in another example.
  • FIG. 5 is a schematic diagram of a split-transistor switching power supply, in another example.
  • FIG. 6 is a schematic diagram of a split-transistor switching power supply, in another example.
  • FIG. 7 illustrates an example process for measuring process strength of a transistor, in an example.
  • Such power supplies generally include at least one switching element coupled between a voltage supply node (voltage supply terminal or voltage reference terminal) and a switching node.
  • the switching power supply includes a switching element and a logic circuit.
  • the switching element includes a plurality of parallel-coupled transistors.
  • the logic circuit is configured to initially provide one or more gate drive signals to one or more of the parallel-coupled transistors, respectively, but not to all of the parallel-coupled transistors.
  • the initially-switched switching transistor is adaptively-sized based on temperature and/or process strength (and/or on or more other conditions associated with the power supply, such as ringing amplitude, input voltage, load current, and/or switching speed) so as to damp ringing, and a relatively larger switching transistor (e.g., all transistors in parallel) is subsequently switched for low conduction loss.
  • the initially-switched switching transistor can be selected, for instance, from two or more possible choices. So, the splittransistor ratio (transistorrmai size : transistorinitial size) of the split-transistor power supply can be adaptively and automatically selected from two or more choices based on the one or more conditions. The conditions are local to the power supply and the given application.
  • a switching power supply turns on and off power switches (e.g., MOSFETs, or power FETs) to redirect current from one power conductor (e.g., switching node) to another (e.g., inductor).
  • power switches e.g., MOSFETs, or power FETs
  • the switching current causes ringing to manifest on the switching node and output of the power supply, which in turn can cause electromagnetic interference (EMI) and over-voltage stress.
  • EMI electromagnetic interference
  • the initial output slewing of the power supply is accomplished by just one of the FETs, and full-conduction is subsequently accomplished by both the FETs connected in parallel.
  • the result is that the ringing during the initial output slewing can be dampened or otherwise reduced by the relatively larger on-resistance of the single FET that is initially switched.
  • Such a split-FET configuration works well, but can be limited because the first-switched FET must be large enough to handle all of the current, not only under ideal conditions but also under less than ideal conditions, such as worst-case temperature and worst-case process variation.
  • a switching power supply includes a switching element and a logic circuit.
  • the switching element includes two or more parallel-coupled transistors coupled between a voltage supply node (voltage supply terminal or voltage reference terminal) and a switching node.
  • the logic circuit is configured to initially provide one or more gate drive signals to one or more of the parallel-coupled transistors, respectively, but not to all of the parallel-coupled transistors. After a delay period, the logic circuit is further configured to provide a respective gate drive signal to each of the parallel-coupled transistors.
  • the initially-provided one or more gate signals is/are based on one or both of process strength associated with the switching element (e.g., low RdsOn equals strong process, and high RdsOn equals weak process) and ambient temperature associated with the power supply.
  • the split-transistor ratio (transistorrmai size : transistorinitial size) of the split-transistor power supply can be adaptively and automatically selected from two or more choices based on temperature and/or process strength.
  • the number of splittransistor ratios available for selection can range from two or more.
  • the switching element has a total of three parallel-coupled field effect transistors (FETs), including two IX-sized transistors and one 6X-sized transistor.
  • the FET size X may refer, for instance, to gate width or some other dimension that correlates to a device strength of interest.
  • both of the two smaller (IX) transistors initially receive respective gate drive signals, and then after the delay period all three of the transistors receive respective gate drive signals. So, the split-transistor ratio would be 4: 1.
  • the split-transistor ratio would be 8:1.
  • Other examples may have additional split-transistor ratios that can be selected by the logic circuit based on one or both of process strength and ambient temperature, depending on the number of transistors included in the switching element.
  • the split-transistor ratio can be selected based on one or both of process strength and ambient temperature.
  • the ambient temperature and process strength can be measured in real-time, or measured in advance and stored in a memory, or predicted based on theoretical and/or empirical analysis and stored in a memory, according to some examples.
  • the ambient temperature is measured in real-time by a temperature sensor, and the output signal of the temperature sensor is compared to a temperature reference signal by a comparator circuit.
  • the temperature reference signal can be fixed (e.g., 60°C), and in other example cases the temperature reference signal can be a variable (e.g., 60°C or 90°C) that is selected based on one or more other signals.
  • the temperature reference signal can be selected based on process strength (e.g., RdsOn), such that the split-transistor ratio is determined by a Boolean of temperature and process strength.
  • the temperature reference signal can be stored in a memory and accessed for purposes of assessing a stored or real-time measured ambient temperature.
  • the temperature comparator circuit can be adjusted or trimmed (e.g., with calibration data derived from testing and stored in memory) to improve its accuracy across a range of temperature or other such environmental factors.
  • the process strength can be measured in real-time by a process strength sensor, and the output signal of the process strength sensor is compared to a process strength reference signal by a comparator circuit.
  • the process strength reference signal can be fixed (e.g., 5 ohms, for RdsOn), and in other example cases the process strength reference signal can be a variable (e.g., 2.5 ohms or 5 ohms, for RdsOn) that is selected based on one or more other signals.
  • the process strength reference signal can be selected based on the ambient temperature (e.g., measured or predicted), such that the split-transistor ratio is determined by a Boolean of process strength and temperature.
  • the process strength reference signal can be stored in a memory and accessed for purposes of assessing a stored or real-time measured process strength.
  • the process strength comparator circuit can be adjusted or trimmed (e.g., with calibration data derived from testing and stored in memory) to improve its accuracy across a range of temperature or other such environmental factors.
  • the techniques can be used, for example, in any application that uses a switching power supply and is susceptible to ringing as well as temperature and/or process strength variations (e.g., automotive applications, radar systems, vision systems such as those used in robotics and autonomous driving, gaming and infotainment systems, communication systems, to name a few examples).
  • the split-transistor switching element helps to reduce ringing, and adapting the splittransistor ratio based on temperature and/or process strength further helps reduce ringing across temperature and process strength variation. More generally, the split-transistor ratio can be adapted based on any number of conditions local to the power supply.
  • any one or more of switching element process strength e.g., RdsOn
  • ambient temperature e.g., ambient temperature
  • ringing amplitude at the supply output e.g., power supply input voltage (e.g., +V)
  • load current level e.g., load current level
  • switching speed can be taken into consideration as part of the decision tree to select an appropriate splittransistor ratio.
  • the techniques may also help reduce power dissipation (e.g., caused by high RdsOn).
  • the techniques can be implemented with no or minimal impact to cost and footprint, and do not require switching speeds to be slowed (no need to drive transistors slower).
  • FIG. 1A illustrates a split-transistor switching power supply configured in an example.
  • the power supply includes a high-side/low-side buck converter configuration operatively coupled to a controller 100, although any number of switching power supply topologies can be used as described above.
  • inductor LI and capacitor Cl form a tank circuit connected to the switching node SN and provide energy storage during switching operations.
  • the high-side switching element is implemented as a split-transistor having a fixed ratio (transistorrinai_size : transistorinitial size) and which includes parallel-coupled FETs Sla and Sib.
  • a delay circuit 101 allows Sib to be gated slightly after Sla is gated.
  • the low-side switching element is implemented with a single FET S2.
  • the high-side switching element is connected between the switching node SN and a supply node (which is +V in this example), and the low-side switching element is connected between the switching node and power reference node (which is ground in this example)
  • Controller 100 can be any standard or proprietary controller, such as a pulse width modulation (PWM) controller that generates control signals based on feedback representative of output voltage Vout.
  • PWM pulse width modulation
  • the low-side switching element may be implemented with a split-transistor configuration instead of the high-side switching element.
  • both the low-side and high-side switching elements can be implemented with a splittransistor.
  • the controller 100 generates high-side and low-side PWM control signals based on feedback representative of output voltage Vout. The feedback allows Vout to be adjusted as needed by changing the ON-time of the switching elements.
  • Delay circuit 101 may be any standard or proprietary delay circuit, such as a rising edge delay circuit.
  • the amount of delay provided by delay circuit 101 can vary from one example to the next but in some examples is in the range of 3 nanoseconds (ns) to 30 ns. In one such example, the delay period is 10 ns (+/-1 ns). In some examples, the delay period provided by delay circuit 101 can be tuned or otherwise adjusted to a desired delay amount or range.
  • FETs Sla and Sib are the same size (e.g., IX), although they are not required to be the same size.
  • ringing at the switching node SN is proportional to the quality factor at the switch node, which is approximately represented by Q where Q is the quality factor,
  • R is an effective resistance that exists at switching node SN (including the on-resistance of the active switching element and any parasitic resistance)
  • L is an effective inductance that exists in series with the switched transistor (parasitic inductance)
  • C is an effective capacitance that exists at switching node SN (parasitic capacitance).
  • the voltage ringing in some implementations, is at a frequency sufficient to cause EMI that can exceed specified limits of a given application. These limits can be specified, in various examples, by regulatory or governing bodies, industry standards, or other applicable specifications.
  • FIG. IB illustrates example waveforms of the split-transistor switching power supply of FIG. 1A.
  • controller 100 generates a pulse- width modulation (PWM) control signal G1 a, which is applied (directly or via a driver) to the gate of S 1 a of the high-side switching element and to the input of delay circuit 101.
  • the delay circuit 101 in turn generates PWM control signal Gib, which is applied (directly or via a driver) to the gate of Sib of the high-side switching element.
  • Controller 100 also generates a PWM control signal G2, which is applied (directly or via a driver) to the gate of S2 of the low-side switching element.
  • Controller 100 is configured such that the high-side switching element (Sla and Sib) is not active at the same time as the low-side switching element (S2), and vice-versa.
  • delay circuit 101 is a rising edge delay circuit in which the output of delay circuit 101 follows the input of delay circuit 101 high after the delay period (e.g., 10 ns), and remains high until the input of delay circuit 101 falls. So, in this example case, responsive to the high-side control signal transitioning high, control signal Gia initially transitions high to turn on FET Sla, and after the delay period control Gib transitions high to turn on FET Sib. Responsive to the high-side control signal transitioning low, both Gia and Gib transition low.
  • Low-side switching can then take place in turn, and so on.
  • the resulting voltage VSN at the switching node SN rises and falls accordingly, to provide an efficiently regulated output voltage Vout.
  • the low-side switching element can be implemented with a split FET as well, or instead of the high-side switching element.
  • FIG. 1C illustrates a split-transistor switching power supply configured in another example.
  • the power supply of this example is similar to the configuration shown in FIG. 1A, except there is only one switching element instead of high-side and low-side switching elements.
  • the power supply may have any number of other switching power supply topologies (e.g., buck, boost, buck-boost, flyback, half-bridge, and full-bridge), and the techniques described herein may be similarly applied.
  • the sole switching element is implemented as a split-transistor having a fixed ratio (transistorfmat .size : transistorinitial size) which includes parallel-coupled field effect transistors (FETs) Sla and Sib.
  • FETs parallel-coupled field effect transistors
  • a delay circuit 101 allows Sib to be gated slightly after Sla is gated.
  • the switching element in this example is connected between the switching node SN and a supply node (which is +V in this example).
  • FIG. ID illustrates example waveforms of the split-transistor switching power supply of FIG. 1C.
  • controller 100 generates a pulse-width modulation (PWM) control signal Gia, which is applied (directly or via a driver) to the gate of Sla of the switching element and to the input of delay circuit 101.
  • the delay circuit 101 in turn generates PWM control signal Gib, which is applied (directly or via a driver) to the gate of Sib of the switching element.
  • PWM pulse-width modulation
  • Gib PWM control signal
  • delay circuit 101 is a rising edge delay circuit in which the output of delay circuit 101 follows the input of delay circuit 101 high after the delay period (e.g., 10 ns), and remains high until the input of delay circuit 101 falls.
  • control signal Gia initially transitions high to turn on FET Sla, and after the delay period control Gib transitions high to turn on FET Sib. Responsive to the control signal transitioning low, both Gia and Gib transition low. The resulting voltage VSN at the switching node SN rises and falls accordingly, to provide an efficiently regulated output voltage Vout.
  • FIG. IE comparatively illustrates example switching power supply output waveforms with ringing undamped and damped, in an example.
  • the waveform labeled no split-transistor was generated with a standard switching power supply having a single transistor switching element (e.g., single size 212X transistor). Note the magnitude of the initial voltage ringing.
  • the waveform labeled split-transistor with no delay was generated with a switching power supply having a switching element implemented with a split-transistor but no delay in between switching the individual transistors of that split transistor (e.g., size 62X transistor parallel-connected with size 150X transistor, effectively providing a 212X transistor when both are switched with 0 ns delay).
  • a switching power supply having a switching element implemented with a split-transistor but no delay in between switching the individual transistors of that split transistor (e.g., size 62X transistor parallel-connected with size 150X transistor, effectively providing a 212X transistor when both are switched with 0 ns delay).
  • the waveform labeled split-transistor with delay was generated with a switching power supply having a switching element implemented with a split-transistor and a 5 ns delay in between switching the individual transistors of that split transistor (e g., switch size 62X transistor, delay 5 ns, and then switch size 150X transistor).
  • a switching power supply having a switching element implemented with a split-transistor and a 5 ns delay in between switching the individual transistors of that split transistor (e g., switch size 62X transistor, delay 5 ns, and then switch size 150X transistor).
  • switch size 62X transistor e.g., delay 5 ns, and then switch size 150X transistor.
  • FIGS. 2A and 2B each illustrates such an example.
  • the power supply includes a high-side/low-side switching configuration operatively coupled to a controller via a logic circuit 203.
  • the high- side switching element is implemented as a split-transistor that includes three parallel-connected FETs Sla, Sib, and Sic.
  • the low-side switching element in this example is implemented with a single FET S2, and can be controlled as normally done.
  • the power supply may have any number of switching power supply topologies (e.g., buck, boost, buck-boost, flyback, half-bridge, and full-bridge).
  • each of FETs Sla, Sib, Sic, and S2 receives a gate control signal from logic circuit 203, which is configured to delay delivery of one or more of those gate signals relative to one or more other of those gate signals, so as to provide two or more initial FET sizes (e.g., each initial size including one or more but not all of parallel- connected FETs Sla, Sib, and Sic) and then a final FET size (e.g., all of parallel-connected FETs Sla, Sib, and Sic) after the delay period.
  • a gate control signal from logic circuit 203, which is configured to delay delivery of one or more of those gate signals relative to one or more other of those gate signals, so as to provide two or more initial FET sizes (e.g., each initial size including one or more but not all of parallel- connected FETs Sla, Sib, and Sic) and then a final FET size (e.g., all of parallel-connected FETs Sla, Sib, and Sic) after the delay period
  • comparators 201 and 202 are configured to assess the local conditions of process strength (on-resistance, RdsOn, in this example) and ambient temperature (temp), and inform logic circuit 203 as to the result of that assessment, thus allowing logic circuit 203 to select an appropriately sized initial FET.
  • process strength on-resistance, RdsOn, in this example
  • ambient temperature temp
  • logic circuit 203 is configured to assess the local conditions of process strength (on-resistance, RdsOn, in this example) and ambient temperature (temp), and inform logic circuit 203 as to the result of that assessment, thus allowing logic circuit 203 to select an appropriately sized initial FET.
  • Such a configuration thus allows the split-transistor to have an adjustable ratio (transistorimaLsize : transistorinitial size), in that it provides two or more ratios that can be selected based on the assessment of temperature and process strength.
  • the power supply can be any type of switching power supply, including those that have only one switching element (e.g., FIG. 1C) rather than high-side and low-side switching elements (e.g., FIG. 1 A), and that above description is equally applicable here.
  • the power supply is configured as a buck switching regulator.
  • the application may vary, but one such example switching regulator may be, for instance, within a passenger vehicle and operatively coupled between an automotive battery and one or more loads to convert the battery voltage (e.g., 12 volts or 48 volts) to a lower voltage (e.g., 3.3 volts or 5 volts).
  • control input to logic circuit 203 has a dashed line through it, indicating that control input may include more than one control signal, such as high-side and low-side control signals, as is the case with the examples of FIGS. 2A and 2B.
  • control signal(s) can be provided by any suitable controller, such as a standard PWM switching power supply controller that generates control signals based on feedback representative of an output voltage sensed at a switching node or output node.
  • FETs Sla, Sib, and Sic may all be the same size or differently sized.
  • Sla and Sib may be the same size (e g., IX) and Sic may be larger (e.g., 2X).
  • FET Sla is the smallest (e.g., 12X)
  • FET Sib is mid-sized (e.g., 24X)
  • FET Sic is the largest (e.g., 64X).
  • each of FETs Sla, Sib, and Sic has a larger on- resistance (RdsOn) as compared to the on-resistance of a single larger FET formed by the parallel combination of FETs Sla, Sib, and Sic.
  • a second ratio of 100:24 (which reduces to 25:6) can be achieved by initially gating only FET Sib and then gating S 1 a and S 1 c after the delay period, such that the initial output slewing of the power supply is accomplished by FET Sib only, and full-conduction is subsequently accomplished by all FETs Sla, Sib, and Sic.
  • a third ratio of 100:36 (which reduces to 25:9) can be achieved by initially gating only FETs Sla and Sib and then gating Sic after the delay period, such that the initial output slewing of the power supply is accomplished by FET Sla and Sib only, and fullconduction is subsequently accomplished by all FETs Sla, Sib, and Sic.
  • a fourth ratio of 100:64 (which reduces to 25:16) can be achieved by initially gating only FET Sic and then gating Sla and Sib after the delay period, such that the initial output slewing of the power supply is accomplished by FET Sic only, and full-conduction is subsequently accomplished by all FETs Sla, Sib, and Sic. Additional ratios may be achieved by initially gating only Si c and Sl a, or Si c and Sib, and then gating all three after the delay period. In any such cases, the result may be that the ringing (at switching node SN) during the initial output slewing can be reduced by a relatively larger on-resistance RdsOn of the initially-gated FET(s).
  • the logic circuit 203 includes a first logic circuit input, a second logic circuit input, a first logic circuit output, a second logic circuit output, a third logic circuit output, and a fourth logic circuit output.
  • the first logic circuit input of logic circuit 203 is configured to receive one or more control signals (e.g., PWM control signal from controller 101), and the second logic circuit input of logic circuit 203 is configured to receive a logic control signal from comparator 202.
  • each of the first, second, third and fourth logic circuit outputs is configured to provide a corresponding gate control signal to a gate of a corresponding one of FETs Sla, Sib, Sic and S2, respectively.
  • the gate control signal applied to FET S2 can be based on the PWM signal.
  • the gate control signals applied to FETs Sla, Sib, Sic can be based on both the PWM signal and the logic control signal.
  • the logic control signal provided by comparator 202 is based on both process strength associated with the switching element and ambient temperature associated with the power supply.
  • comparator 202 is configured to receive at its temperature signal input (non-inverting input in this example case) a signal representative of the ambient temperature (Temp), and to receive at its temperature reference signal input (inverting input in this example case) a temperature reference signal (TRef). So, if the magnitude of the Temp signal is larger than the TRef signal, the comparator 202 output is high; otherwise, the comparator 202 output is low.
  • the TRef signal is provided by comparator 201.
  • comparator 201 is configured to receive at its process strength signal input (noninverting input in this example case) a signal representative of the process strength (which in this example is RdsOn), and to receive at its process strength reference signal input (inverting input in this example case) a process strength reference signal (RRef). So, if the magnitude of the RdsOn signal is larger than the RRef signal, the comparator 201 output is high; otherwise, the comparator 201 output is low. In this manner, the TRef signal can be selected based on the process strength as indicated by RdsOn. Comparator 202 may be further configured with hysteresis, to prevent chatter.
  • the split-FET ratio can be adapted based on temperature and process strength, and ringing at the switching node SN can be reduced.
  • FIG. 2B shows another example similar to that of FIG. 2A, except that there is no comparator 201 and the logic control signal provided by comparator 202 is based on one of process strength associated with the switching element or ambient temperature associated with the power supply.
  • comparator 202 is configured to receive at its non-inverting input a signal representative of either the ambient temperature (Temp) or process strength (RdsOn, in this example case), and to receive at its inverting input a reference signal (Ref) provided from a non-volatile memory (NVM) 205.
  • comparator 202 if the magnitude of the Temp or RdsOn signal is larger than the Ref signal, the comparator 202 output is high; otherwise, the comparator 202 output is low.
  • comparator 202 may be further configured with hysteresis, to prevent chatter.
  • logic circuit 203 is responsive to the comparator 202 output signal, and accordingly adapts the split-FET ratio based on temperature or process strength, and reduces ringing at the switching node SN.
  • the non-volatile memory 205 from which data representing the Ref signal is provided can be, for example, a programmable/erasable read-only memory (ROM) or a look-up table that is populated with data representative of the desired temperature or process strength reference signal value for a given application.
  • data representative of one or both of the Temp signal and the RdsOn signal may also be stored in the memory, along with the reference signal data. For instance, RdsOn can be measured (in advance) for a given wafer lot or die using automatic test equipment (such as the example described with reference to FIG. 7) and stored into memory 205.
  • a process strength indicator such as RdsOn for a given IX transistor on a given wafer or die tends to be the same (within a reasonable tolerance, such as +/- 5% or +/-2% or +/-!%) across all the IX transistors of that wafer or die, and is proportional to larger transistors (e.g., 2X, 3X, etc.).
  • Such process strength indicators also tend not to change once set in the fabrication facility, in that they tend to maintain the same profile over temperature that is subsequently exhibited in the field (any use application) as compared to that profile exhibited in the fabrication or test facility.
  • the ambient temperature profile of a given application may be relatively consistent or otherwise predictable.
  • Temp and RdsOn signal data may be measured live or stored in advance, according to some examples.
  • the reference values can be tuned or set based on desired performance forgiven application. For instance, assume it is desired for a given application to achieve a balance between a sufficiently high RdsOn for a sufficiently low level of ringing, and a sufficiently large FET to carry full load current.
  • the level of acceptable ringing can be set, for example, so that EMI meets a given specification and also so that voltage excursion does not exceed a given breakdown specification or otherwise cause damage.
  • the initially-gated switching device e.g., one or more parallel-connected FETs but not all
  • one way to select the RdsOn reference value is to set it to achieve the desired amount of ringing.
  • ringing occurs due to stray inductance (L), stray capacitance (C), and FET resistance (R) giving an RLC resonant network.
  • the damping factor of an RLC network is directly proportional to R, so raising R proportionately raises the damping factor.
  • a circuit with a damping factor of 1 has no overshoot (referred to as critically damped). This can be used as one bound on the RdsOn reference value.
  • RdsOn can be selected so that the initially-gated FET can carry full load current.
  • the on-resistance of a power FET is related to the total current that the FET can carry with a specific gate voltage. This can be used as the other bound on the RdsOn reference value.
  • the RdsOn reference value (RRef) can be set between these two bounds with a desired safety margin, according to some such examples.
  • maximum drive current Id can also be used as a process strength indicator, according to some examples.
  • FIG. 3 is a schematic diagram of a split-transistor switching power supply that has some similar features to the supplies shown in FIGS. 1A, 1C, 2A, and 2C, but further includes details of logic circuit 203 and the comparator-based assessment circuitry, according to some examples.
  • the above relevant description is equally applicable here, with respect to common features.
  • any number of other switching power supply topologies can be used (e.g., buck, boost, buck-boost, flyback, halfbridge, and full-bridge).
  • any split-transistor switching element of a given switching power supply topology whether that switching element is a high-side switching element, a low-side switching element, a sole switching element, or some other switching element.
  • the non-inverting input of comparator 202 is coupled to a temperature sensor 301, which can be any number of temperature sensing circuits cable of providing a signal Temp that is representative of the ambient temperature.
  • a temperature sensor 301 can be any number of temperature sensing circuits cable of providing a signal Temp that is representative of the ambient temperature.
  • the ambient temperature can be normalized into a desired unit, such as Celsius, Fahrenheit, or other temperature scale.
  • the TRef signal is adjustable by operation of switch S3 and is dependent on the process strength indicator RdsOn.
  • RdsOn can be measured live or provided from a memory and is compared to the RRef signal. If RdsOn is greater than RRef, then comparator 201 outputs a high signal which in turn switches S3 to the 90°C position, thereby setting the TRef signal to 90°C. In contrast, if RdsOn is less than RRef, then comparator 201 outputs a low signal which in turn switches S3 to the 60°C position, thereby setting the TRef signal to 60°C.
  • switch S3 can be implemented with a look-up table that is indexed by possible output signal values from comparator 201, and that outputs TRef value that corresponds to the received output signal value.
  • Logic circuit 203 can be implemented with a number of logic schemes.
  • the example shown in FIG. 3 includes a delay circuit 304, an AND-gate 302, and an OR-gate 303.
  • the delay circuit 304 is configured to receive the high-side control signal and output a delayed version of that control signal.
  • the control signal can be, for example, a PWM control signal generated by controller 100.
  • the delay circuit 304 may be, for example, similar to the delay circuit 101 described above with reference to FIGS. 1A and 1C, and that relevant description is equally applicable here.
  • the AND-gate 302 is configured to receive as inputs the control signal (high-side PWM control signal in this example case) and the logic control signal from comparator 202.
  • the output of AND-gate 302 will only be high if both the PWM control signal and the logic control signal are high; otherwise, the output of AND-gate 302 is low.
  • the OR-gate 303 is configured to receive as inputs the output signal of AND-gate 302 and the delayed version of the PWM control signal. The output of OR-gate 303 is high if either or both of the delayed PWM control signal and the output of AND-gate 302 are high; otherwise, if both inputs to OR-gate 303 are low, the output of OR-gate 303 is low.
  • the AND-gate 302 outputs a low signal which in turn causes the OR-gate 303 to initially output a low signal.
  • FETs Sib and Sic remain off for the delay period. After the delay period, FETs Sib and Sic are also gated, so that all three FETs Sla- c are active.
  • logic circuit 203 may be included in an integrated circuit chip.
  • the high-side control signal passes directly through that integrated circuit chip to the gate of FET Sla.
  • the high-side control signal may be directly applied to the gate of FET Sla, without passing through the integrated circuit chip.
  • Such deviations are considered equivalents in this description.
  • a portion of logic circuit 203 is included in an integrated circuit chip that includes a first input to receive the PWM control signal input (high-side, in this example), a second input to receive the logic control signal, a first output to provide the output of OR-gate 303, and a second output to provide the delayed version of the PWM control signal.
  • the gate drive signal provided to FET Sla may or may not pass through the integrated circuit chip. In either case, that gate drive signal can be considered to be an output of the logic circuit 203.
  • the same principle may apply to a low-side PWM control signal, or any other control signal.
  • the delay circuit 304 may be provided outside of the integrated circuit, but may still be considered to be part of the logic circuit 203.
  • FIG. 4 is a schematic diagram of a split-transistor switching power supply that has some similar features to the supplies shown in FIGS. 1A, 1C, 2A, 2C, and 3, with some notable distinctions.
  • the split-FET switching element includes four parallel-connected FETs (Sla, Sib, Sic, and Sid) instead of three (Sla, Sib, and Sic), thus increasing the split-FET ratios available for selection responsive to temperature and/or process strength indications.
  • the circuitry configured to assess the temperature and/or process strength indications as well as the logic circuit 203 are configured to facilitate that increased selection process. The above relevant description is equally applicable here, with respect to common features. Further recall that any number of other switching power supply topologies can be used.
  • the comparator or assessment circuitry is implemented with analog temperature test circuit 401, analog RdsOn test circuit 402, analog-to-digital (A/D) converters 403 and 404, and a look-up table (LUT) 405.
  • the A/D converter 403 receives an analog signal representative of the ambient temperature from measurement circuit 401, and generates a 3- bit digital equivalent of that analog signal.
  • the A/D converter 404 receives an analog signal representative of the process strength (in this case, RdsOn) from measurement circuit 402, and generates a 3 -bit digital equivalent of that analog signal.
  • the LUT 405 receives as input 3 -bit outputs from each of the A/D converters 403 and 404, and outputs a corresponding set of logic control signals that includes four signals in this example. Such an arrangement allows for greater resolution in the split-transistor ratio selection process for the switching element. Also, in this example configuration, the delay period is configurable or otherwise adjustable based on a 2-bit select code output by LUT 405.
  • the analog temperature test circuit 401 can be any suitable circuit for indicating ambient temperature (e.g., similar to sensor 301).
  • the analog RdsOn test circuit 402 can include, for instance, any one of the IX FETs included on the die on which the switching elements are formed and that is dedicated for RdsOn (or drive current) assessment.
  • the transistor can have a known drive signal applied to its gate, a known current source (Ids) applied to its drain, and its source can be connected to ground. With the gate drive signal applied and the current source on, the voltage across the source and drain (Vds) of the transistor can be measured. With Vds and Ids known, RdsOn can be computed (Vds/Ids).
  • Ids current source
  • the resulting analog signals representative of the ambient temperature and the process strength are then converted to digital signals, which are 3-bits each in this example (other examples may have fewer bits or more bits).
  • the A/D converters 403 and 404 can be implemented with standard or proprietary technology.
  • the LUT 405 receives the two 3 -bit signals and generates an output that corresponds to that 6-bit input.
  • the 3-bits from the A/D converter 403 are 000, then temperature can be ignored and the split-FET ratio can be selected based solely on process strength; likewise, if the 3-bits from the A/D converter 404 are 000, then RdsOn can be ignored and the split-FET ratio can be selected based solely on temperature. In still other examples, both temperature and RdsOn can be simultaneously taken into consideration to determine the split-FET ratio.
  • the LUT 405 outputs a set of logic control signals (four logic control signals, in this example case) to logic circuit 203.
  • logic circuit 203 can vary from one example to the next, but in this example includes AND-gates 406, 408, OR-gates 407, 409, and delay circuit 410.
  • the AND-gate 406 is configured to receive as inputs the high-side PWM control signal (in this example case) and one of the four logic control signals from LUT 405. The output of AND- gate 406 will only be high if both the PWM control signal and the logic control signal are high; otherwise, the output of AND-gate 406 is low.
  • the OR-gate 407 is configured to receive as inputs the output signal of AND-gate 406 and the delayed version of the PWM control signal.
  • OR-gate 407 is connected to the gate of FET Sib and is high if either or both of the delayed PWM control signal and the output of AND-gate 406 are high; otherwise, if both inputs to OR- gate 407 are low, the output of OR-gate 407 is low.
  • the AND-gate 408 is configured to receive as inputs the high-side PWM control signal and another one of the four logic control signals from LUT 405.
  • the OR-gate 409 is configured to receive as inputs the output signal of AND-gate 408 and the delayed version of the PWM control signal.
  • OR-gate 409 is connected to the gate of FET Sic and is high if either or both of the delayed PWM control signal and the output of AND-gate 408 are high; otherwise, if both inputs to OR-gate 409 are low, the output of OR-gate 409 is low.
  • Delay circuit 410 is configured to receive the other two of the four logic control signals from LUT 405, at its delay select input (Dselect).
  • the delay circuit 410 can be implemented, for instance, as individual edge delay circuits, each configured to provide a fixed delay and that are enabled (or disabled) based on the 2-bit select code received from LUT 405.
  • delay circuit 410 can be implemented as an edge delay circuit that has a variable delay based on the 2-bit select code received from LUT 405.
  • the 2-bit logic control signal applied to the Dselect input of delay circuit 410 is 00, then a fixed or default delay period can be used. As further shown in FIG. 4, the PWM control signal passes through logic circuit 203 to the gate of Sla (with no delay or intervening logic).
  • FETs Sic (if not already gated) along with FETs Sib and Sid are also gated so that all four FETs Sla-d are active.
  • AND-gate 408 outputs a high signal which in turn causes the OR-gate 409 to output a high signal, then at least FETs Sla and Sic are initially gated.
  • FETs Sib (if not already gated) and Sid are also gated so that all four FETs Sla-d are active.
  • the AND-gate 408 outputs a low signal which in turn causes OR-gate 409 to initially output a low signal, then FET S la is initially gated without Sic being gated.
  • FETs Sib (if not already gated) along with FETs Sic and Sid are also gated so that all four FETs Sla-d are active.
  • the two least significant bits of the 3-bit input from A/D converter 404 are used to indicate the process strength condition, and the most significant bit is used as the other bit of the 2-bit delay indicator.
  • there are four possible process strength conditions PSI, PS2, PS3, and PS4
  • four possible temperature conditions Tl, T2, T3, and T4
  • four possible delay conditions DI, D2, D3, and D4. Any of these conditions can be considered in a singular fashion in which the other conditions are ignored or set to a default value, or can be considered in a Boolean fashion in which one or more of the other conditions are also simultaneously considered. Numerous permutations are possible to provide a set of two or more options for the split-FET ratio of a given switching element, according to this description.
  • Table 1 Example LUT for generating gate control signals and delay control signals
  • FIG. 4 and Table 1 has four parallel-connected transistors making up the split-FET switching element, with one FET (SI a) that is directly-gated by the PWM control signal, one FET (Sid) that is directly-gated by the delayed PWM control signal, and two FETs (Sib and Sic) that can each be selectively-gated (or not) to provide up to four different split- FET ratios in conjunction with Sla and Sid
  • other examples may have fewer parallel-connected FETs or more parallel-connected FETs.
  • another example is similar to that shown in FIG. 4, but without FET SI a.
  • Another example is similar to that shown in FIG.
  • logic circuit 203 is shown here with two gate control signal outputs (from OR-gates 407 and 409, respectively) that can vary depending on temperature and/or process strength, but other examples may have fewer such gate control signals (e.g., FIG. 3) or more of such gate control signals. In the latter case, for instance, logic circuit 203 may include one or more additional AND-gate/OR-gate pairs similar to those shown in FIG.
  • the number of logic control signals generated by the assessment circuitry can be increased to support those additional pairs (gate driver channels) of logic circuit 203.
  • the A/D converters 403 and 404 may have 4-bit outputs instead of 3 -bit outputs, thereby increasing the number of logic control signal entries populated into LUT 405.
  • the output of comparator 202 may be one of a plurality of comparator outputs, with each additional comparator to detect a specific range of temperature and/or process strength.
  • FIGS. 2A-4 adapt the split-transistor ratio based on temperature and/or process strength.
  • other conditions may be used to inform the adaptation of the split-transistor ratio in addition to, or alternatively to, temperature and/or process strength.
  • Other example conditions that are local to the power supply and can be sensed or otherwise known for a given application include ringing amplitude, input voltage, load current, and/or switching speed. Such conditions are not necessarily mutually exclusive and each one may be a valid indicator of a similar impact on power supply performance. In this manner, the various conditions may overlap in their ability to indicate a performance issue.
  • a given goal for a given application may be to reduce absolute voltage peak to avoid damage. Damage could occur, for instance, if the voltage peak exceeds the absolute maximum rating of a component in the power supply, such as the breakdown voltage of a switching element. So, in a similar manner to sensing temperature, the power supply input voltage can be sensed and that sensed value can be used as an input to a look-up table or compared to a reference value, and the resulting output signal(s) can be used, directly or indirectly, to generate gate control signal(s).
  • the voltage excursion from ringing may tend to be higher if the power supply is operating at a higher load current.
  • high load current may benefit from an initially larger FETs.
  • the load current (Hoad) can be sensed and that sensed value can be used as an input to a look-up table or compared to a reference value, and the resulting output signal(s) can be used, directly or indirectly, to generate gate control signal(s).
  • the switching speed of a given switching element may be assessed and used to inform the split-transistor ratio adaptation.
  • many things may cause variation in switching speed of power systems, including differences in stray capacitance and differences in silicon (or other semiconductor process) manufacturing parameters such as gate oxide thickness. If the power supply switches faster, then the rate of current change with respect to time (dl/dt) will be different.
  • the initial FET size can be tuned for a desired amount of ringing.
  • temperature may or may not be included, because switching speed may include some temperature effects (overlap of conditions).
  • measuring switching speed is accomplished as shown in the example depicted in FIG. 5, which is similar to that shown in FIG. 2A, except that this example further includes a comparator 501 and timer 502 which are used to determine switching speed, and the result of that determination is provided to comparator 202 to inform the split-FET ratio selection (process strength and/or other conditions may also be sensed and used in the split-FET ratio selection).
  • process strength and/or other conditions may also be sensed and used in the split-FET ratio selection.
  • a timer 502 is started after the PWM controller initially commands a FET to turn on.
  • Comparator 501 detects when the voltage on the switching node SN reaches some threshold, such as Vin, and commands timer 502 to stop.
  • the elapsed time is directly related to switching speed (dV/dt).
  • Speed can be determined from a switching cycle of the actual power system (live, as shown here), but can also be measured on a scale replica of the switching system or other speed measurement circuit, built only for the purpose of indicating speed.
  • a ring oscillator can be used as a low-cost method to indicate speed.
  • Vpk voltage excursion
  • FIG. 6 which is similar to that shown in FIG. 2A, except that this example further includes a peak sensor implemented with comparators 603 and 604, an up/down counter 601, and a look-up table or decoder logic 602 to translate the output of counter 601 to control signals for logic 203 (or for direct application to gates).
  • this approach adapts to the right FET size after a few PWM switching cycles.
  • comparator 604 senses that the peak is higher than VMax, it causes counter 601 to count down. The output of counter 601 causes a different size FET to be used for the next switching cycle initial surge.
  • comparator 603 senses that the peak is lower than VMin, the counter 601 counts up. In this fashion, the system finds the initial split-FET size to give a desired amount of ringing. It may take a few switching cycles for the system to find a correct initial FET size.
  • the system could start with counter 601 in the lowest setting (e.g., least ringing, lowest efficiency) and gradually increase initial FET size for higher efficiency until the desired amount of overshoot is achieved. Following this initial stabilization, the system would be able to track any changes by stepping up or down the counter 601 setting once per PWM switching cycle responsive to too much or too little overshoot.
  • lowest setting e.g., least ringing, lowest efficiency
  • FIG. 7 illustrates an example process for measuring process strength of a transistor, in an example.
  • automatic test equipment (ATE) 700 is configured to deliver stimulus to a given transistor that is representative of the devices making up the split-FET switching element, and to compute RdsOn for that transistor.
  • the transistor being tested may be, for example, on a wafer or a die that includes the power supply having the split-FET switching element.
  • the transistor is biased in the linear region by applying a fixed voltage signal to the gate of the transistor so as to provide a fixed gate-to-source voltage, Vgs (e.g., 1 volt) and by applying a fixed current source to provide a fixed drain-source current, Ids (e.g., 10 mA).
  • Vgs gate-to-source voltage
  • Ids e.g. 10 mA
  • Vds drain-to-source voltage
  • ATE 700 is implemented external to the wafer or die. In some other examples, ATE 700 may be implemented on the wafer or die, so as to allow for in-field testing.
  • the transistor to be tested can effectively be made available via contact pads or input/output VO) pins or pads to which stimulus (e.g., Vgs, Ids) can be applied, and from which output (e.g., Vds) can be detected.
  • An ATE or on-die processor can be provisioned to facilitate any computations (e.g., Vds/Ids).
  • the computed process strength indicator (RdsOn, in this example case) can then be stored in NVM or represented as a live input signal as variously described above.
  • Example 1 is a switching power supply that includes a switching element and a logic circuit.
  • the switching element has two or more parallel-coupled transistors.
  • the logic circuit has a first logic circuit input, a second logic circuit input, and a logic circuit output.
  • the logic circuit is configured to: (a) receive at the first logic circuit input a pulse width modulation (PWM) signal, (b) receive at the second logic circuit input a logic control signal that is based on one or more conditions associated with the power supply, and (c) provide from the logic circuit output to a gate of one of the two or more parallel-coupled transistors a gate control signal that is based on both the PWM signal and the logic control signal.
  • PWM pulse width modulation
  • Example 2 includes the switching power supply of Example 1, in which the logic circuit output is a first logic circuit output and the gate control signal is a first gate control signal, and the logic circuit includes a second logic circuit output, the logic circuit configured to provide from the second logic circuit output to a gate of a second of the two or more parallel-coupled transistors a second gate control signal that is based only on a delayed version of the PWM signal.
  • Example 3 includes the switching power supply of Example 2, and further includes a delay circuit configured to receive the PWM signal and output the delayed version of the PWM signal.
  • Example 5 includes the switching power supply of any one of Examples 1 through 4, in which the logic circuit output is a first logic circuit output, the gate control signal is a first gate control signal and the logic control signal is a first logic control signal, and the logic circuit includes a second logic circuit output, the logic circuit configured to provide from the second logic circuit output to a gate of a second of the two or more parallel-coupled transistors a second gate control signal that is based on the PWM signal and a second logic control signal, the second logic control signal being based on the one or more conditions.
  • Example 7 includes the switching power supply of any one of Examples 1 through 4, and further includes a comparator circuit configured to generate the logic control signal based on the one or more conditions.
  • Example 8 includes the switching power supply of Example 7, in which the one or more conditions include process strength associated with the switching element and ambient temperature associated with the power supply, and the comparator circuit is configured to generate the logic control signal based on both the ambient temperature and the process strength.
  • Example 9 includes the switching power supply of Example 8, in which the comparator circuit includes: a first comparator having a temperature signal input, a temperature reference signal input, and a first comparator output, the first comparator configured to (a) receive at the temperature signal input a signal representative of the ambient temperature, (b) receive at the temperature reference signal input a temperature reference signal, and (c) provide from the first comparator output the logic control signal; and a second comparator having a process strength signal input, a process strength reference signal input, and a second comparator output, the second comparator configured to (a) receive at the process strength signal input a signal representative of the process strength, (b) receive at the process strength reference signal input a process strength reference signal, and (c) provide from the second comparator output the temperature reference signal or a control signal by which the temperature reference signal is selected or otherwise based.
  • the comparator circuit includes: a first comparator having a temperature signal input, a temperature reference signal input, and a first comparator output, the first comparator configured to (a) receive at the
  • Example 10 includes the switching power supply of any one of Examples 7 through 9, in which the comparator circuit includes: a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator configured to (a) receive at the first comparator input a signal representative of the one or more conditions, (b) receive at the second comparator input a reference signal, and (c) provide from the comparator output the logic control signal or another signal by which the logic control signal is selected or otherwise based.
  • the comparator circuit includes: a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator configured to (a) receive at the first comparator input a signal representative of the one or more conditions, (b) receive at the second comparator input a reference signal, and (c) provide from the comparator output the logic control signal or another signal by which the logic control signal is selected or otherwise based.
  • Example 11 includes the switching power supply of Example 10, in which the reference signal is provided from a non-volatile memory.
  • the second comparator input is coupled to a memory circuit.
  • Example 12 includes the switching power supply of any one of Examples 7 through 11, in which the one or more conditions include process strength associated with the switching element and ambient temperature associated with the power supply, and the comparator circuit includes: one or more analog-to-digital (A/D) converters including an A/D converter configured to receive as input an analog signal representative of the ambient temperature and/or an A/D converter configured to receive as input an analog signal representative of the process strength; and a lookup table configured to (a) receive as input one or more digital outputs from the one or more A/D converters, and (b) output one or more logic control signals, the one or more logic control signals including the logic control signal that is based on one or both of the process strength and the ambient temperature.
  • A/D analog-to-digital
  • Example 13 includes the switching power supply of any one of Examples 1 through 12, in which the one or more conditions include process strength associated with the switching element and ambient temperature associated with the power supply, and the switching power supply includes: a temperature sensor circuit configured to provide a signal representative of the ambient temperature; and/or a process strength sensor circuit configured to provide a signal representative of the process strength.
  • Example 14 includes the switching power supply of any one of Examples 1 through 13, in which the logic circuit includes: a delay circuit configured to receive the PWM signal and output a delayed version of the PWM signal; an AND-gate configured to receive as inputs the PWM signal and the logic control signal, and output an AND-gate output signal; and an OR-gate configured to receive as inputs the AND-gate output signal and the delayed version of the PWM signal, and output the gate control signal.
  • the logic circuit includes: a delay circuit configured to receive the PWM signal and output a delayed version of the PWM signal; an AND-gate configured to receive as inputs the PWM signal and the logic control signal, and output an AND-gate output signal; and an OR-gate configured to receive as inputs the AND-gate output signal and the delayed version of the PWM signal, and output the gate control signal.
  • Example 15 includes the switching power supply of any one of Examples 1 through 16, in which the logic circuit is included in an integrated circuit chip that includes at least the first logic circuit input, the second logic circuit input, and the logic circuit output.
  • Example 16 includes the switching power supply of Example 15, in which the one or more conditions include process strength associated with the switching element and ambient temperature associated with the power supply, and the integrated circuit chip includes a comparator circuit configured to generate the logic control signal based on one or both of the ambient temperature and the process strength.
  • Example 17 includes the switching power supply of any one of Examples 1 through 16, in which the switching element is one of: a high-side switching element coupled to a voltage supply terminal; or a low-side switching element coupled to a voltage reference terminal.
  • the switching element is one of: a high-side switching element coupled to a voltage supply terminal; or a low-side switching element coupled to a voltage reference terminal.
  • Example 18 includes the switching power supply of any one of Examples 1 through 17, in which the one or more conditions includes process strength associated with the switching element, and the process strength is represented by an on-resistance of the switching element.
  • Example 19 includes the switching power supply of any one of Examples 1 through 18, in which the one or more conditions includes one or more of: process strength associated with the switching element, ambient temperature associated with the power supply, ringing amplitude associated with the power supply, input voltage associated with the power supply, load current associated with the power supply, and/or switching speed associated with the power supply.
  • Example 20 includes the switching power supply of any one of Examples 1 through 19, in which the one or more conditions includes one or both of process strength associated with the switching element and ambient temperature associated with the power supply.
  • Example 21 is a buck switching regulator including the switching power supply of any one of Examples 1 through 20.
  • Other switching power supply topologies can be used as well, such as buck, boost, buck-boost, flyback, half-bridge, or full-bridge.
  • Example 22 is a switching power supply, including a switching element and a logic circuit.
  • the switching element has a plurality of parallel-coupled transistors.
  • the logic circuit is configured to (a) initially provide one or more gate drive signals to one or more of the parallel- coupled transistors, respectively, but not to all of the parallel-coupled transistors, and (b) after a delay period provide a respective gate drive signal to each of the parallel-coupled transistors, the initially-provided one or more gate signals being based on one or both of drain-to-source on- resistance (RdsOn) associated with the switching element and ambient temperature associated with the power supply.
  • Ron drain-to-source on- resistance
  • Example 23 includes the switching power supply of Example 22, in which responsive to the ambient temperature being higher than a temperature threshold and/or the RdsOn being higher than an on-resistance threshold, two or more but not all of the parallel-coupled transistors initially receive respective gate drive signals.
  • Example 24 includes the switching power supply of Example 22 or 23, in which responsive to the ambient temperature being lower than a temperature threshold and/or the RdsOn being lower than an on-resistance threshold, only one of the parallel -coupled transistors initially receives a gate drive signal.
  • Example 25 is a method for controlling a switching power supply that includes a switching element having two or more parallel-coupled transistors, the method including: receiving a pulse width modulation (PWM) control signal; generating a logic control signal that is based on one or both of process strength associated with the switching element and ambient temperature associated with the power supply; responsive to the logic control signal indicating that the process strength and/or ambient temperature is beyond a given threshold, initially providing one or more gate drive signals to a first set of the two or more parallel-coupled transistors, respectively, the first set including one or more but not all of the two or more parallel-coupled transistors, and after a delay period providing a respective gate drive signal to each of the two or more parallel-coupled transistors; and responsive to the logic control signal indicating that the process strength and/or ambient temperature is not beyond a given threshold, initially providing one or more gate drive signals to a second set of the two or more parallel-coupled transistors, respectively, the second set having one or more fewer transistors than the first set or one or
  • Example 26 includes the method of Example 25, in which the logic control signal that is based on both of the process strength and the ambient temperature.
  • Example 27 includes the method of Example 26, in which the logic control signal is determined based on a comparison of the ambient temperature to a threshold that is based on the process strength.
  • Example 28 includes the method of Example 26, in which the logic control signal is determined based on a comparison of the process strength to a threshold that is based on the ambient temperature.
  • the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
  • a device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions.
  • the configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
  • terminal As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
  • a circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device.
  • a structure described as including one or more semiconductor elements such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end user and/or a third party.
  • semiconductor elements such as transistors
  • passive elements such as resistors, capacitors, and/or inductors
  • sources such as voltage and/or current sources
  • references herein to a field effect transistor (FET) being “ON” means that the conduction channel of the FET is present and drain current may flow through the FET.
  • References herein to a FET being “OFF” means that the conduction channel is not present and drain current does not flow through the FET. A FET that is OFF, however, may have current flowing through the transistor’s body-diode.
  • Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement.
  • Components shown as resistors are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown.
  • a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes.
  • a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
  • ground in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description.
  • “about,” “approximately” or “substantially” preceding a parameter means being within +/- 10 percent of that parameter.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne des techniques de commande d'un convertisseur de commutation. Dans un exemple, le convertisseur comprend un élément de commutation et un circuit logique. L'élément de commutation comprend une pluralité de transistors couplés en parallèle (S1a-b). Le circuit logique (203) est configuré pour fournir initialement un ou plusieurs signaux d'attaque de grille à un ou plusieurs des transistors couplés en parallèle (S1a-b), respectivement, mais pas à tous les transistors (S1a-b). Après une période de retard, le circuit logique (203) est en outre configuré pour fournir un signal d'attaque de grille respectif à tout ou un nombre autrement plus grand des transistors (S1a-b). Le ou les signaux de grille initialement fournis sont basés sur une ou plusieurs conditions associées au convertisseur, telles que la RdsOn associée à l'élément de commutation et/ou la température. De cette manière, un transistor de commutation qui est dimensionné de manière adaptative sur la base de la ou des conditions est initialement commuté pour amortir la suroscillation, et un transistor de commutation plus grand (par exemple, tous les transistors en parallèle) est ensuite commuté pour une faible perte de conduction.
PCT/US2023/026189 2022-06-27 2023-06-26 Adaptation d'alimentation électrique de commutation à transistor divisé sur la base d'une condition WO2024006183A1 (fr)

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WO2018158726A1 (fr) * 2017-03-02 2018-09-07 HELLA GmbH & Co. KGaA Commande de commutation hybride
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