WO2024000891A1 - Display panel, display device, and method for preparing display panel - Google Patents

Abstract

The present application discloses a display panel, a display device, and a method for preparing a display panel. The display panel comprises a substrate; an insulating layer which is arranged on the substrate and which is formed with a plurality of vias; lap joint portions which are formed in the vias and which cover at least a portion of each sidewall of the vias where the lap joint portions are located; and a signal connection wire, at least a portion of the signal connection wire comprising a body portion which is located at a layer of the first insulating layer distant from the substrate, and extension portions which extend from the body portion into the vias and which are mutually connected to the lap joint portions. According to an embodiment of the present application, by means of forming a metal lap joint portion in a via, at least portions of a signal connecting wire located on two sides of the via communicate with each other by means of the lap joint portion, thereby increasing the yield of the signal connecting wire.

Description

Display panel, display device and preparation method of display panel

This application claims priority to the Chinese patent application filed with the China Patent Office on June 30, 2022, with application number 202210760355.5 and the application title "Display panel, display device and method for preparing display panel", the entire content of which is incorporated by reference. in this application.

Technical field

The present application relates to the field of display, and specifically to a display panel, a display device, and a method for preparing a display panel.

Background technique

With the rapid development of electronic devices, users have higher and higher requirements for screen-to-body ratio, which makes the full-screen display of electronic devices attract more and more attention from the industry.

Traditional electronic devices such as mobile phones and tablets need to integrate front-facing cameras, earpieces, and infrared sensing elements. In the prior art, external light can enter the photosensitive element located below the screen by notching or openings on the display screen. However, these electronic devices are not truly full-screen and cannot display in all areas of the entire screen. For example, the corresponding area of the front camera cannot display images.

In order to increase the screen-to-body ratio, some display panels will place the driving circuit outside the light-transmitting area, and connect the pixel electrodes in the light-transmitting area and the driving circuit outside the light-transmitting area through wiring. However, the wiring is easy to break, resulting in The display is poor.

Contents of the invention

Embodiments of the present application provide a display panel, a display device, and a method for manufacturing a display panel, aiming to reduce defects in the display panel.

An embodiment of the first aspect of the present application provides a display panel. The display panel includes: a substrate; an insulating layer located on one side of the substrate and formed with a number of via holes; an overlapping portion formed in the via hole, and the overlapping portion covers At least part of the sidewall of the via hole where it is located; signal connection line, at least part of the signal connection line includes a main body part located on the side of the insulating layer facing away from the substrate, an extension part extending from the main body part into the via hole and interconnected with the overlap part .

According to an embodiment of the first aspect of the present application, the insulating layer includes a first insulating layer and a second insulating layer located on a side of the first insulating layer facing away from the substrate, and the via hole includes a first via hole formed in the first insulating layer, a second via hole formed in the second insulating layer;

The display panel also includes a metal wiring layer located between the first insulating layer and the second insulating layer,

Wherein, the overlapping part covers at least part of the side wall of the first via hole where it is located, and the overlapping part and the metal wiring layer are made of the same material.

According to any of the aforementioned embodiments of the first aspect of the present application, the size of the first via hole is smaller than the size of the second via hole.

According to any of the aforementioned embodiments of the first aspect of the present application, the metal wiring layer further includes a transition portion located on the surface of the first insulating layer toward the second insulating layer and surrounding at least one first via hole, and the transition portion and the overlap portion are connected to each other. , the extension part is connected to each other through the transition part and the overlapping part, or the extension part, the transition part and the overlapping part are connected to each other.

According to any of the aforementioned embodiments of the first aspect of the present application, the transition portion is located on the surface of the first insulating layer exposed by the second via hole.

According to any of the aforementioned embodiments of the first aspect of the present application, the extension size of the transition portion in the first via hole diameter direction is 1.5 μm˜5 μm.

According to any of the aforementioned embodiments of the first aspect of the present application, the pore diameter of the first via hole is 2 μm to 4 μm, and the pore diameter of the second via hole is 4 μm to 6 μm.

According to any of the aforementioned embodiments of the first aspect of the present application, the display panel further includes an active layer disposed between the substrate and the insulating layer, the active layer further includes pads, and at least part of the first via holes faces the side of the substrate. The opening does not extend beyond the spacer.

According to any of the aforementioned embodiments of the first aspect of the present application, the display panel has a first display area and a second display area, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the display panel further includes:

The pixel electrode layer includes a first pixel electrode located in the first display area and connected to the signal connection line;

The driving circuit includes a first driving circuit for driving the first pixel electrode, and the first driving circuit is connected to the first pixel electrode through a signal connection line.

According to any of the aforementioned embodiments of the first aspect of the present application, at least part of the orthographic projection of the via hole on the substrate and the orthographic projection of the first pixel electrode on the substrate are at least partially overlapped.

According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of at least part of the via hole on the substrate is located within the orthographic projection of the first pixel electrode on the substrate.

According to any of the aforementioned embodiments of the first aspect of the present application, the signal connection line is a light-transmitting wiring.

According to any of the aforementioned embodiments of the first aspect of the present application, at least part of the via holes is located in the first display area.

According to any of the aforementioned embodiments of the first aspect of the present application, at least some of the via holes are disposed in the first display area close to the second display area.

According to any of the aforementioned embodiments of the first aspect of this application, the second display area includes a main display area and a transition display area. The transition display area is located between the main display area and the first display area, and at least some of the via holes are located in the transition display area.

According to any of the aforementioned embodiments of the first aspect of the present application, at least some of the via holes are provided in the transition display area close to the first display area.

According to any of the aforementioned embodiments of the first aspect of the present application, the radial dimension of the orthographic projection of the overlapping portion on the substrate is 2 μm to 3 μm.

According to any of the aforementioned embodiments of the first aspect of the present application, the signal connection line includes a first signal connection line and a second signal connection line, the first signal connection line includes an extension, and the orthographic projection of the second signal connection line on the substrate and The orthographic projection of the via hole on the substrate is at least partially offset.

According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the second signal connection line on the substrate and the orthographic projection of the via hole on the substrate are completely misaligned.

A second aspect embodiment of the present application also provides a display device, including the display panel of any of the above-mentioned first aspect embodiments.

A third embodiment of the present application also provides a method for manufacturing a display panel, including:

Prepare an insulating layer on the substrate, and pattern the insulating layer to form via holes;

Deposit metal material in the via hole to form an overlap;

Prepare a wiring layer on the insulating layer. The wiring layer includes signal connection lines. At least part of the signal connection lines include a main body part located on the side of the insulating layer facing away from the substrate, extends from the main body part into the via hole, and is connected to the overlapping part. extension.

In the display panel provided by the embodiment of the present application, the display panel includes a substrate, an insulating layer, an overlapping portion and a signal connection line provided on the substrate. A via hole is formed on the insulating layer, and an overlap portion is formed in the via hole and covers at least part of the side wall. The extension portion of the signal connection line and the overlap portion are connected to each other, so that at least part of the main body of the signal connection line can pass through the overlap portion. Interconnection, that is, the signal connection lines located on both sides of the overlap can be connected to each other through the overlap, which can improve the problem of easy breakage of the signal connection lines caused by the opening of the insulation layer, ensure the yield of the signal connection lines, and thereby improve the display Panel yield. Therefore, the embodiment of the present application forms an overlap portion in the via hole, so that at least some of the signal connection lines located on both sides of the via hole are connected to each other through the overlap portion, thereby improving the yield of the signal connection line.

Description of drawings

Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals designate the same or similar features, Figure is not drawn to actual scale.

Figure 1 is a schematic top view of a display panel according to an embodiment of the present application;

Figure 2 is an enlarged structural schematic diagram of Q in Figure 1;

Figure 3 is a cross-sectional view at B-B in Figure 2;

Figure 4 is a partial enlarged structural schematic diagram of Figure 3;

Figure 5 is a partially enlarged structural schematic diagram of Figure 3 in another example;

Figure 6 is a schematic diagram of the partially enlarged structure in Figure 3 in yet another example;

Figure 7 is a schematic diagram of the partially enlarged structure in Figure 3 in yet another example;

Figure 8 is a schematic diagram of the partially enlarged structure in Figure 3 in yet another example;

Figure 9 is an enlarged structural schematic diagram of Q in Figure 1 in another embodiment;

Figure 10 is a top view of a partial layer structure of a display panel provided by another embodiment of the present application;

Figure 11 is a schematic top view of a display device according to an embodiment of the present application;

Figure 12 is a cross-sectional view along the D-D direction in Figure 11;

Figure 13 is a schematic flow chart of a method for preparing a display panel provided by an embodiment of the present application;

Figure 14 is a schematic flow chart of a method for preparing a display panel provided by another embodiment of the present application;

FIG. 15 is a schematic flowchart of a method for manufacturing a display panel according to another embodiment of the present application.

Explanation of reference symbols:

100. Display panel; 200. Photosensitive module; S1, first surface; S2, second surface;

01. Substrate; 024. Insulating layer; 024a. Via hole;

02. First insulating layer; 20a, first sub-layer; 20b, second sub-layer; 210, first via hole;

03. Metal wiring layer; 310. Overlap part; 320. Transition part;

04. Second insulation layer; 410. Second via hole;

05. Wiring layer; 510. Signal connection line; 511. Main body part; 512. Extension part; 510a, first signal connection line; 510b, second signal connection line;

06. Pixel electrode layer; 610. First pixel electrode; 620. Second pixel electrode; 630. Interconnection structure;

07. Active layer; 710. Pad;

08. The first metal layer;

09. Second metal layer;

10. Pixel definition layer; K1, first opening; 110, first light-emitting unit; K2, second opening; 120, second light-emitting unit; 130, support column;

11. Common electrode layer;

12. Driving circuit; 121. First driving circuit; 122. Second driving circuit;

AA1, first display area; AA2, second display area; ZA, main display area; TA, transition display area.

Detailed ways

Features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations are mutually exclusive. any such actual relationship or sequence exists between them. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in a process, method, article, or device that includes the stated element.

It will be understood that when describing the structure of components, when one layer or region is referred to as being "on" or "over" another layer or region, it can mean being directly on the other layer or region, or There are other layers or areas between it and another layer, another area. And if the part is turned over, that layer, one area, will be "under" or "under" another layer, area.

On electronic devices such as mobile phones and tablets, light-sensitive components such as front cameras, infrared light sensors, and proximity light sensors need to be integrated on one side of the display panel. In some embodiments, a light-transmitting display area can be provided on the above-mentioned electronic device, and the photosensitive component can be arranged on the back of the light-transmitting display area, so as to achieve a full-screen display of the electronic device while ensuring the normal operation of the photosensitive component.

In some related technologies, in order to improve the light transmittance of the light-transmitting area, an opaque pixel driving circuit is usually placed in the transition area between the normal display area and the light-transmitting area, and the pixel electrodes in the light-transmitting area are routed through light-transmitting wiring Pixel drive circuitry connected to the transition region. In order to prevent the stress of the large-area inorganic film layer in the light-transmitting area from being transmitted to the transition area and causing a deviation in the characteristics of the thin film transistor device in the transition area, such as the difference in hydrogen content of the thin film transistor device in the transition area, it is necessary to open an opening on the inorganic insulating layer in the light-transmitting area. Stress relief holes are used to release the stress of the inorganic film layer in the light-transmitting area to the maximum extent, and to ensure that the hydrogen content is equivalent to ensure that the thin film transistor device is equivalent.

As the pixel density in the light-transmitting area increases significantly, the density of light-transmitting wiring used to connect the pixel electrodes in the light-transmitting area and the pixel driving circuit in the transition area gradually increases. At this time, the light-transmitting wiring may pass through stress relief holes. The existence of stress relief holes may lead to the risk of circuit breakage in light-transmitting traces, thereby affecting the yield of the display panel.

In addition, the inventor found that due to the presence of multiple inorganic insulating layers, it is necessary to use two processes to pattern the inorganic insulating layer to form stress relief holes, and a metal layer must be prepared above the inorganic insulating layer, which may cause stress relief above the inorganic insulating layer. During the preparation of the metal layer, metal residues are formed in the stress relief holes. These metal residues eventually lead to the breakage of the insulating layer above the metal layer, which ultimately leads to breakage of the uppermost light-transmitting traces, resulting in poor connection between the pixel electrodes in the light-transmitting area and the pixel driving circuit in the transition area, and ultimately leads to display dark spots in the light-transmitting area. Defects.

In order to solve the above problems, embodiments of the present application provide a display panel and a display device. Each embodiment of the display panel and the display device will be described below with reference to the accompanying drawings.

An embodiment of the present application provides a display panel, which may be an organic light emitting diode (OLED) display panel.

Please refer to FIGS. 1 to 4 together. FIG. 1 shows a schematic top view of the display panel 100 according to an embodiment of the present application. FIG. 2 is an enlarged structural schematic view of Q in FIG. 1 . FIG. 3 is B-B of FIG. 2 , Figure 4 is a partial enlarged structural schematic diagram of Figure 3 .

As shown in FIGS. 1 to 4 , the display panel 100 provided by the embodiment of the present application includes: a substrate 01 , an insulating layer 024 , an overlapping portion 310 and a signal connection line 510 . The insulating layer 024 is provided on the substrate 01 and is formed with a number of via holes 024a; the overlap portion 310 is formed in the via hole 024a, and the overlap portion 310 covers at least part of the sidewall of the via hole 024a where it is located; at least part of the signal connection line 510 includes The main body portion 511 is located on the side of the insulating layer 024 facing away from the substrate 01 , and the extension portion 512 extends from the main body portion 511 into the via hole 024 a and is connected to the overlapping portion 310 .

In the display panel 100 provided in the embodiment of the present application, the display panel 100 includes a substrate 01 , an insulating layer 024 , an overlapping portion 310 and a wiring layer 05 . A via hole 024a is formed on the insulating layer 024. The overlap portion 310 is formed in the via hole 024a and covers at least part of the side wall. The extension portion 512 of the signal connection line 510 and the overlap portion 310 are connected to each other, so that at least part of the signal connection line 510 The main body portions 511 can be connected to each other through the overlap portion 310, that is, the signal connection lines 510 located on both sides of the overlap portion 310 can be connected to each other through the overlap portion 310, and the extension portion 512 of the signal connection line 510 and the overlap portion 310 are connected to each other. , so that at least part of the signal connection lines 510 located on both sides of the via hole 024a and the overlap portion 310 are connected to each other, that is, the signal connection lines 510 located on both sides of the overlap portion 310 can be connected to each other through the overlap portion 310, which can improve the insulation layer 024 The problem that the signal connection line 510 is easily broken due to the opening can ensure the yield of the signal connection line 510 and thereby improve the yield of the display panel 100 . Therefore, the embodiment of the present application forms an overlapping portion 310 in the via hole 024a so that at least some of the signal connection lines 510 on both sides of the via hole 024a are connected to each other through the overlapping portion 310, thereby improving the yield of the signal connection lines 510.

The substrate 01 can be made of glass, polyimide (PI) or other light-transmitting materials. The number of insulation layers may be one or more. The material of the overlapping portion 310 can be metal or other conductive materials. Optionally, the material of the overlapping portion 310 includes a metal material, which can improve the conductive performance of the overlapping portion 310 . Optionally, the material of the signal connection line 510 includes a light-transmitting material, and the signal connection line 510 is a light-transmitting wiring, which can improve the light transmittance of the display panel. For example, the material of the signal connection line 510 includes indium tin oxide (Indium Tin Oxide, ITO) material. Optionally, the display panel 100 includes a wiring layer 05 , and the signal connection lines 510 are located on the wiring layer 05 .

In some embodiments, the insulating layer 024 includes a first insulating layer 02 and a second insulating layer 04 located on a side of the first insulating layer 02 facing away from the substrate. The via hole 024a includes a first via hole 210 formed in the first insulating layer 02 and a second via hole 410 formed in the second insulation layer 04 . The display panel also includes a metal wiring layer 03 located between the first insulating layer 02 and the second insulating layer 04 . The overlapping portion 310 covers at least part of the sidewall of the first via hole 210 where it is located, and the overlapping portion 310 and the metal wiring layer 03 are made of the same material.

In these embodiments, the insulating layer 024 includes a stacked first insulating layer 02 and a second insulating layer 04 . A metal wiring layer 03 is also disposed between the first insulating layer 02 and the second insulating layer 04 . The overlapping portion 310 is made of the same material as metal wiring layer 03. During the preparation process of the display panel 100 , the metal wiring layer 03 can be prepared and shaped using the same material in the same preparation process step, so that part of the metal material falls into the first via hole 210 and covers at least part of the side of the first via hole 210 The walls form an overlap 310 .

Optionally, the side of the first via hole 210 facing away from the second insulating layer 02 also has a bottom wall, and the overlap portion 310 can cover the bottom wall of the first via hole 210 to increase the distribution area of the overlap portion 310 so that through The connection of the signal connection lines 510 connected to each other by the overlapping portion 310 is more stable, further improving the yield of the signal connection lines 510 .

In some optional embodiments, the size of the first via hole 210 is smaller than the size of the second via hole 410 , which can ensure that a sufficient area of the overlap 310 is exposed by the second via hole 410 and prevent the second via hole 410 from being oversized. The mutual connection between the signal connection line 510 and the overlapping portion 310 is little affected.

In some optional embodiments, please continue to refer to FIGS. 3 and 4 , the orthographic projection of the first via hole 210 on the substrate 01 is located within the orthographic projection of the second via hole 410 on the substrate 01 , ensuring overlap. The connecting portion 310 can completely expose the second via hole 410, ensuring the stability of the connection between the signal connection line 510 and the overlapping portion 310.

There are many ways to set the size of the overlapping portion 310 in the first via hole 210. As shown in Figure 4, the extension size of the overlapping portion 310 in the thickness direction of the display panel is smaller than that of the first via hole 210 in the thickness direction of the display panel. The extended size of the overlapping portion 310 does not completely cover the inner wall surface of the first via hole 210 .

Alternatively, as shown in FIG. 5 , the extension size of at least part of the overlapping portion 310 in the thickness direction of the display panel is equal to the extension size of the first via hole 210 in the thickness direction of the display panel, and the overlapping portion 310 completely covers the first via hole 210 inner wall surface.

Optionally, as shown in FIG. 6 , the metal wiring layer 03 also includes a transition portion 320 located on the surface of the first insulating layer 02 facing the second insulating layer 04 and surrounding at least one first via hole 210 . The transition portion 320 is connected to the transition portion 320 . The connecting portions 310 are connected to each other. By forming the transition portion 320 on the surface of the first insulating layer 02 facing the second insulating layer 04 , the distribution area of the metal material in the via hole 024 a can be increased, and the breakage failure of the signal connection line 510 can be better improved. Optionally, the transition portion 320 and the overlapping portion 310 are connected through at least part of the sidewall via holes of the first via hole 210 .

Optionally, the transition part 320 and the overlap part 310 are integrally formed. For example, the transition portion 320 and the overlap portion 310 can be prepared and formed in the same process step. For example, when preparing the metal wiring layer 03 , at least part of the metal material falls on the surface of the first insulating layer 02 surrounding the first via hole 210 to form a transition. portion 320 , at least part of the metal material falls into the first via hole 310 to form an overlapping portion 310 .

As shown in FIG. 6 , at least part of the transition portion 320 may be disposed between the first insulating layer 02 and the second insulating layer 04 .

In some other embodiments, as shown in FIG. 7 , the aperture of the second via hole 410 is larger than the aperture of the first via hole 210 , at least part of the first insulating layer 02 is exposed by the second via hole 410 , and the transition portion 320 is disposed between The surface of the first insulation layer 02 exposed by the second via hole 410 , that is, the orthographic projection of the transition portion 320 on the substrate 01 is smaller than the orthographic projection of the opening of the second via hole 410 toward the first insulation layer 02 on the substrate 01 within, so that the extension portion 512 can be connected to the transition portion 320 via the second via hole 210 .

When the display panel 100 includes the transition portion 320, the extension portion 512 and the overlap portion 310 can be connected to each other in various ways. As shown in FIGS. 6 and 7, the extension portion 512 can be connected to the overlap portion 310 through the transition portion 320. , or as shown in FIG. 8 , the extension portion 512 can also be connected to the transition portion 320 and the overlap portion 310 at the same time, that is, at least part of the extension portion 512 extends into the first via hole 210 and overlaps with the first via hole 210 . The parts 310 are connected to each other.

Optionally, the extension size of the transition portion 320 on the aperture of the first via hole 210 is 1.5 μm˜5 μm. When the size of the transition portion 320 is within the above range, it can not only improve the beneficial effect of the transition portion 320 on the breakage of the signal connection line 510 due to the excessive size of the transition portion 320 , but also improve the effectiveness of the transition portion 320 due to the excessive size of the transition portion 320 . , the transition part 320 protrudes outside the second via hole 210 , causing part of the transition part 320 to be unable to be connected to the extension part 512 , and part of the transition part 320 to be unable to perform its function.

Optionally, the first via hole 210 has a pore diameter of 2 μm to 4 μm, and the second via hole 410 has a pore diameter of 4 μm to 6 μm. When the apertures of the first via hole 210 and the second via hole 410 are within the above range, it can avoid the impact of the first via hole 210 and the second via hole 410 on the first insulating layer 02 or the second via hole 410 due to too small apertures. The stress improvement effect of the insulating layer 04 can also prevent the first via hole 210 and the second via hole 410 from being too large in diameter and affecting the structural strength of the first insulating layer 02 or the second insulating layer 04 .

In some optional embodiments, please continue to refer to FIGS. 4 to 8 , the display panel 100 further includes an active layer 07 disposed between the substrate and the insulating layer 024 , and the active layer 07 further includes a spacer 710 , at least The opening of part of the first via hole 210 towards the substrate 01 does not exceed the pad 710 , that is, the orthogonal projection of at least part of the opening of the first via hole 210 towards the substrate 01 on the substrate 01 is located at the position of the pad 710 on the substrate 01 Within the orthographic projection.

In these optional embodiments, the spacer 710 can be provided to prevent the first via hole 210 from being over-engraved and affecting the shape and performance of the layer structure below the first insulating layer 02 . The spacer 710 is located on the active layer 07 , so that the spacer 710 and the semiconductor part can be prepared and formed in the same process step, which can simplify the preparation of the display panel 100 .

Optionally, the bottom wall of the first via hole 210 is a surface of the pad 710 facing the first via hole 210 , and at least part of the surface of the pad 710 is provided with an overlapping portion 310 .

Please continue to refer to FIG. 1. In some optional embodiments, the display panel 100 has a first display area AA1, a second display area AA2, and a non-display area NA surrounding the first display area AA1 and the second display area AA2. The light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2. In other embodiments, the display panel 100 may not include the non-display area NA.

Here, it is preferred that the light transmittance of the first display area AA1 is greater than or equal to 15%. In order to ensure that the light transmittance of the first display area AA1 is greater than 15%, even greater than 40%, or even has a higher light transmittance, the light transmittance of each functional film layer of the display panel 100 in this embodiment is greater than 80%. Or the light transmittance of at least part of the functional film layers of the display panel 100 is greater than 90%.

According to the display panel 100 according to the embodiment of the present application, the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2, so that the display panel 100 can integrate a photosensitive component on the back of the first display area AA1 to implement, for example, a camera. The photosensitive components are integrated under the screen, and at the same time, the first display area AA1 can display images, thereby increasing the display area of the display panel 100 and realizing a full-screen design of the display device.

Please continue to refer to FIGS. 2 to 8 . In some optional embodiments, the display panel 100 further includes: a pixel electrode layer 06 and a driving circuit 12 . The pixel electrode layer 06 is located in the first display area AA1 and connected to the signal connection line 510 The connected first pixel electrode 610; the driving circuit 12 is located in the second display area AA2. The driving circuit 12 includes a first driving circuit 121 for driving the first pixel electrode 610. The first driving circuit 121 is connected to the first pixel electrode 610 through a signal connection line 510. A pixel electrode 610.

In the display panel 100 provided by the embodiment of the present application, the first driving circuit 121 for driving the first pixel electrode 610 of the first display area AA1 is located in the second display area AA2, which can reduce the metal material in the first display area AA1. The distribution area further improves the light transmittance of the first display area AA1 and facilitates the under-screen integration of photosensitive components. The first driving circuit 121 and the first pixel electrode 610 are connected to each other through the signal connection line 510, which can also improve the yield of the connection between the first driving circuit 121 and the first pixel electrode 610 and improve the display dark spot problem in the first display area AA1.

Optionally, please continue to refer to FIG. 2. The display panel 100 also includes a second pixel electrode 620 and a second driving circuit 122. The second pixel electrode 620 and the second driving circuit 122 are both located in the second display area AA2. The second driving circuit 122 is used to drive the second pixel electrode 620. FIG. 2 only illustrates a set of first driving circuits 121 and a set of second driving circuits 122. The number of the first driving circuits 121 and the second driving circuits 122 can be set according to requirements. Optionally, the second display area AA2 also includes a transition display area TA and a main display area ZA. The transition display area TA is located between the main display area ZA and the first display area AA1. The first driving circuit 121 may be located in the transition display area TA. .

Optionally, please continue to refer to FIGS. 3 to 8 . The display panel 100 also includes a pixel definition layer 10 . The pixel definition layer 10 is located on the side of the pixel electrode layer 06 away from the substrate 01 . The pixel definition layer 10 may include a pixel definition layer 10 located on the first display screen. The first opening K1 of the area AA1 and the second opening K2 located in the second display area AA2, the first light-emitting unit 110 can be disposed in the first opening K1, and the second light-emitting unit 120 can be disposed in the second opening K2. The first driving circuit 121 is used to drive the first light-emitting unit 110 to emit light through the first pixel electrode 610, and the second driving circuit 122 is used to drive the second light-emitting unit 120 to emit light through the second pixel electrode 620.

Optionally, the display panel 100 further includes a common electrode layer 11 located on a side of the pixel definition layer 10 facing away from the substrate 01 . The common electrode layer 11 is used to cooperate with the pixel definition layer 10 to drive the first light-emitting unit 110 and/or the first light-emitting unit 110 . The two light-emitting units 120 emit light.

Optionally, the display panel 100 may also include a support pillar 130 disposed between the pixel definition layer 10 and the common electrode, and the support pillar 130 is used to support components such as the cover plate.

In some optional embodiments, at least part of the orthographic projection of the via hole 024 a on the substrate 01 and the orthographic projection of the first pixel electrode 610 on the substrate 01 are at least partially overlapped. In these optional embodiments, when the orthographic projection of the via hole 024a on the substrate 01 and the orthographic projection of the first pixel electrode 610 on the substrate 01 at least partially overlap, the first pixel electrode 610 can block part of the through hole 024a. The hole 024a can further block the overlap portion 310 located in the via hole 024a, further reducing the distribution area of metal in the first display area AA1, and improving the light transmittance of the first display area AA1.

Optionally, when the overlapping portion 310 is located in the first via hole 210, the orthographic projection of the first via hole 210 on the substrate 01 and the orthographic projection of the first pixel electrode 610 on the substrate 01 are arranged to at least partially overlap. .

Optionally, the orthographic projection of the maximum radial size of the via hole 024a on the substrate 01 is located within the orthographic projection of the first pixel electrode 610 on the substrate 01, so that the first pixel electrode 610 can completely block the via hole 024a. , the first pixel electrode 610 can completely block the overlapping portion 310, that is, the first pixel electrode 610 and the overlapping portion 310 overlap along the thickness direction, which can further reduce the distribution area of metal in the first display area AA1 and improve the first display area. AA1 light transmittance.

Optionally, when the overlapping portion 310 is located within the first via hole 210 , the orthographic projection of the first via hole 210 on the substrate 01 is located within the orthographic projection of the first pixel electrode 610 on the substrate 01 .

The inventor found that placing the first driving circuit 121 for connecting the first pixel electrode 610 after the second display area AA2 will cause the structural strength of the first display area AA1 and the second display area AA2 to be different, and the stress may pass through the insulation The layer is transferred to the second display area AA2 to affect the characteristics of the first driving circuit 121 .

Please refer to FIG. 9 , which is an enlarged structural schematic diagram of Q in FIG. 1 in another embodiment.

In some optional embodiments, as shown in Figure 9, at least part of the via hole 024a is located in the first display area AA1. The via hole 024a can absorb the stress of the first display area AA1 and improve the stress transfer to the second display area AA2. Affects the characteristics of the first driving circuit 121.

Optionally, at least part of the via hole 024a is provided in the first display area AA1 close to the second display area AA2. It can better improve the stress transmission to the second display area AA2 to affect the characteristics of the first driving circuit 121.

Optionally, as mentioned above, the first display area AA1 includes a transition display area TA, and at least part of the via hole 024a is located in the transition display area TA.

In these optional embodiments, the via hole 024a in the transition display area TA can absorb the stress transferred from the first display area AA1, thereby preventing the stress from affecting the characteristics of the first driving circuit 121.

Optionally, at least part of the via hole 024a is disposed close to the first display area AA1 in the transition display area TA. In these optional embodiments, the distance between the via hole 024a in the transition display area TA and the first display area AA1 is relatively close, which can better absorb the stress transferred from the first display area AA1, thereby preventing the stress from affecting the second display area AA1. A characteristic of the driving circuit 121.

In some optional embodiments, please continue to refer to FIGS. 3 to 8 , the first insulating layer 02 includes a first sub-layer 20 a and a second sub-layer 20 b located on the side of the first sub-layer 20 a facing away from the substrate 01 . A via hole 210 includes a first hole segment opened in the first sub-layer 20a and a second hole segment opened in the second sub-layer 20b.

The inventor found that when the second hole section and the first hole section are prepared successively using different processes, there may be a slight difference in the size of the first hole section and the second hole section. When continuing to prepare the metal wiring layer 03, the size difference between the first hole section and the second hole section will cause the metal wiring layer 03 to easily generate metal residues in the first hole section. The sharp tip of the metal residue may cause the second insulating layer 04 to easily break in the first via hole 210 , and further cause the signal connection line 510 to easily break at the second via hole 410 , thereby affecting the yield of the signal connection line 510 .

In some optional embodiments, the overlapping portion 310 at least covers the inner wall surface of the first sub-layer 20a facing the first hole section.

In these optional embodiments, when the overlap portion 310 covers the inner wall surface of the first hole section, there is no need to pattern the metal in the first hole section, so the pattern of the metal wiring layer 03 can be effectively improved. By minimizing the problem that metal residue is easily formed in the first hole section, the problem that the second insulating layer 04 is easily broken in the first via hole 210 caused by the metal residue can be effectively improved, and the size of the overlapping portion 310 can be made smaller. The signal connection line 510 can penetrate into the second via hole 410 and connect with the overlapping portion 310 .

Optionally, the overlapping portion 310 can also cover at least part of the inner wall surface of the second sub-layer 20b facing the second hole section to further increase the size of the overlapping portion 310 and ensure that the signal connection line 510 and the overlapping portion 310 are connected to each other. Connection stability.

In some optional embodiments, please continue to refer to FIGS. 3 to 8 , the display panel 100 further includes a first metal layer 08 located on the side of the active layer 07 away from the substrate 01 , and the first sub-layer 20 a is located on the active layer 07 07 and the first metal layer 08, the second sub-layer 20b is located on the side of the first metal layer 08 facing away from the substrate 01.

Optionally, please continue to refer to Figures 3 and 4. The first driving circuit 121 includes a thin film transistor. The thin film transistor includes a semiconductor part, a gate electrode, a source electrode and a drain electrode. The semiconductor part is located in the active layer 07. The semiconductor part includes a source region. , the drain region and the channel region located between the source region and the drain region. The gate electrode is located on the first metal layer 08 , and the orthographic projections of the gate electrode and the channel region on the substrate 01 are at least partially overlapped. The source electrode and the drain electrode may be located on the metal wiring layer 03, the source electrode and the source region are connected to each other, and the drain electrode and the drain region are connected to each other.

In these optional embodiments, the first sub-layer 20a is located between the active layer 07 and the first metal layer 08 as an inter-gate insulating layer, that is, the first via hole 210 extends to the active layer 07 and the first metal layer. 08 on the inter-gate insulating layer, making the hole depth of the first via hole 210 larger, ensuring that the first via hole 210 can better improve the problem of stress transmission from the first display area AA1 to the second display area AA2.

Optionally, the material of the first sub-layer 20a may include inorganic materials such as silicon oxide. The thickness of the first sub-layer 20a may be

For example, the thickness of the first sub-layer 20a is

wait.

In some optional embodiments, please continue to refer to FIGS. 3 to 8 , the display panel 100 further includes a second metal layer 09 located on the side of the first metal layer 08 facing away from the substrate 01 , and the number of second sub-layers 20 b is There are two, one of the two second sub-layers 20b is located between the first metal layer 08 and the second metal layer 09, and the other is located between the second metal layer 09 and the metal wiring layer 03.

Optionally, the first driving circuit 121 also includes a capacitor. The capacitor includes two capacitor plates arranged oppositely. At least one capacitor plate is located on the second metal layer 09, and the other capacitor plate can be located on the first metal layer 08 or the metal layer. Routing layer 03.

The material of the two second sub-layers 20b can be the same, so the two second sub-layers 20b can be patterned using the same process step to form the second hole section. For example, the material of the second sub-layer 20b can include silicon nitride. The thickness of the second sub-layer 20b between the first metal layer 08 and the second metal layer 09 may be

For example, the thickness of the second sub-layer 20b between the first metal layer 08 and the second metal layer 09 is

Optionally, please continue to refer to FIGS. 3 to 8 . The display panel 100 further includes a third insulating layer. The third insulating layer is located between the wiring layer 05 and the pixel electrode layer 06 .

In some embodiments, please continue to refer to FIGS. 3 to 8 , each predetermined number of first pixel electrodes 610 are electrically connected to each other through the interconnection structure 630 , so that the first light-emitting units 110 interconnected by the first pixel electrodes 610 form a pixel merge. structure, the interconnection structure 630 can be electrically connected to the same first driving circuit 121, thereby driving a predetermined number of first light-emitting units 110 to display through one first driving circuit 121, further reducing the actual PPI of the first display area AA1, reducing the first The driving wiring in the display area AA1 improves its light transmittance.

In some embodiments, the above-mentioned predetermined number is 2 to 8, such as 4, that is, every four first pixel electrodes 610 are electrically connected to each other through the interconnection structure 630 . In some embodiments, the interconnection structure 630 and the first pixel electrode 610 are arranged in the same layer. Optionally, the first interconnection structure 630 is a light-transmissive conductive structure, such as made of ITO.

In some optional embodiments, the wiring layer 05 is provided with multiple signal connection lines 510, and there are multiple first via holes 210 and second via holes 410. The extension paths of these signal connection lines 510 can pass through the second via hole 210. The via hole 410 and each signal connection line 510 are connected to each other through the second via hole 410 and the overlapping portion 310 . The extension path of the same signal connection line 510 may pass through multiple second via holes 410 , or the extension path of the same signal connection line 510 may pass through one second via hole 410 .

Please refer to FIG. 10 , which is a top view of a partial layer structure of a display panel 100 provided by another embodiment of the present application.

In other optional embodiments, the signal connection line 510 includes a first signal connection line 510a and a second signal connection line 510b. The first signal connection line 510a includes an extension 512, and the second signal connection line 510b is on the substrate 01 The orthographic projection on the substrate 01 and the orthographic projection of the via 024a on the substrate 01 are at least partially offset.

In these optional embodiments, the extension portion 512 of the first signal connection line 510a and the overlapping portion 310 are connected to each other. At least part of the second signal connection line 510b is offset from the via hole 024a, so that the second connection signal line can have good connectivity performance without passing through the overlapping portion 310 in the hole 024a.

Optionally, the orthographic projection of the second signal connection line 510b on the substrate 01 and the orthographic projection of the via hole 024a on the substrate 01 are completely misaligned. The second signal connection line 510b and the via hole 024a are completely misaligned, which can ensure the connection yield of the second signal connection line 510b.

In any of the above embodiments, optionally, the circuit structure of the first driving circuit 121 is any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit. In this article, "2T1C circuit" refers to the drive circuit 12 including two thin film transistors (T) and one capacitor (C). Other "7T1C circuits", "7T2C circuits", "9T1C circuits", etc. are deduced in turn. .

In any of the above embodiments, optionally, the size of the first light-emitting unit 110 is smaller than the size of the second light-emitting unit 120 of the same color, so that the non-light-emitting area in the first display area AA1 is larger, which facilitates further improvement. The light transmittance of the first display area AA1.

The first light-emitting unit 110 and the second light-emitting unit 120 may each include an OLED light-emitting layer. According to the design requirements of the first light-emitting unit 110 and the second light-emitting unit 120, each may further include a hole injection layer, a hole transport layer, and an electron layer. At least one of an injection layer or an electron transport layer.

In any of the above embodiments, optionally, the first pixel electrode 610 is a light-transmitting electrode. In some embodiments, the first pixel electrode 610 includes an indium tin oxide (Indium Tin Oxide, ITO) layer or an indium zinc oxide layer. In some embodiments, the first pixel electrode 610 is a reflective electrode, including a first light-transmissive conductive layer, a reflective layer located on the first light-transmissive conductive layer, and a second light-transmissive conductive layer located on the reflective layer. The first light-transmitting conductive layer and the second light-transmitting conductive layer can be ITO, indium zinc oxide, etc., and the reflective layer can be a metal layer, for example, made of silver.

In any of the above embodiments, optionally, the common electrode layer 11 includes a magnesium-silver alloy layer.

In any of the above embodiments, optionally, the orthographic projection of each first light-emitting unit 110 on the substrate 01 consists of one first graphic unit or two or more first graphic units. The first graphic unit Including at least one selected from the group consisting of a circle, an oval, a dumbbell, a gourd, and a rectangle.

In any of the above embodiments, optionally, the orthographic projection of each first pixel electrode 610 on the substrate 01 consists of one second graphics unit or two or more second graphics units. The second graphics unit Including at least one selected from the group consisting of a circle, an oval, a dumbbell, a gourd, and a rectangle.

Exemplarily, the display panel 100 may also include an encapsulation layer, a polarizer and a cover plate located above the encapsulation layer, or a cover plate may be provided directly above the encapsulation layer without providing a polarizer, or at least in the first display area AA1 A cover plate is provided directly above the encapsulation layer without the need for a polarizer to prevent the polarizer from affecting the light collection amount of the photosensitive element provided below the first display area AA1. Of course, a polarizer can also be provided above the encapsulation layer of the first display area AA1.

An embodiment of the present application also provides a display device, which may include the display panel 100 of any of the above embodiments. The following description will take a display device of an embodiment as an example. In this embodiment, the display device includes the display panel 100 of the above embodiment.

FIG. 11 shows a schematic top view of a display device according to an embodiment of the present application, and FIG. 12 shows a cross-sectional view along the D-D direction in FIG. 11 . In the display device of this embodiment, the display panel 100 may be the display panel 100 of one of the above embodiments. The display panel 100 has a first display area AA1 and a second display area AA2. The light transmittance of the first display area AA1 is greater than that of the second display area AA1. 2. Display the light transmittance of area AA2.

The display panel 100 includes an opposing first surface S1 and a second surface S2, where the first surface S1 is a display surface. The display device further includes a photosensitive component 200, which is located on the second surface S2 side of the display panel 100. The photosensitive component 200 is positioned corresponding to the first display area AA1.

The photosensitive component 200 may be an image collection device, used to collect external image information. In this embodiment, the photosensitive component 200 is a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image acquisition device. In other embodiments, the photosensitive component 200 can also be a charge-coupled device (CCD). Image acquisition devices and other forms of image acquisition devices. It can be understood that the photosensitive component 200 is not limited to an image collection device. For example, in some embodiments, the photosensitive component 200 can also be an infrared sensor, a proximity sensor, an infrared lens, a flood light sensing element, an ambient light sensor, and a dot matrix projection. and other light sensors. In addition, the display device can also integrate other components on the second surface S2 of the display panel 100, such as earpieces, speakers, etc.

According to the display device according to the embodiment of the present application, the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2, so that the display panel 100 can integrate the photosensitive component 200 on the back of the first display area AA1 to achieve, for example, images The photosensitive component 200 of the collection device is integrated under the screen, and the first display area AA1 can display images at the same time, thereby increasing the display area of the display panel 100 and realizing a full-screen design of the display device.

Please refer to FIG. 13 , which is a schematic flowchart of a method for manufacturing a display panel 100 according to a third embodiment of the present application.

In the preparation method of the display panel 100 provided by the third embodiment of the present application, the display panel 100 can be the display panel 100 provided by any of the above first embodiments. As shown in FIGS. 3 to 12 , the display panel 100 Preparation methods include:

Step S01: Prepare an insulating layer 024 on the substrate 01, and pattern the insulating layer 024 to form a via hole 024a.

Step S02: Deposit metal material in the via hole 024a to form the overlap portion 310.

Step S03: Prepare a wiring layer 05 on the insulating layer 024. The wiring layer 05 includes signal connection lines 510. At least part of the signal connection lines 510 includes a main body portion 511 located one layer away from the substrate 01 on the insulating layer 024. The extension portion 511 extends into the via hole 024a and is connected to the overlapping portion 310.

In the display panel prepared by the preparation method provided in the embodiment of the present application, the display panel includes a substrate 01 and an insulating layer 024 provided on the substrate 01 , an overlap portion 310 and a signal connection line 510 . A via hole 024a is formed on the insulating layer 024. The overlap portion 310 is formed in the via hole 024a and covers at least part of the side wall. The extension portion 512 of the signal connection line 510 and the overlap portion 310 are connected to each other, so that at least part of the signal connection line 510 The main body portion 511 can be connected to each other through the overlapping portion 310, that is, the signal connecting lines 510 located on both sides of the overlapping portion 310 can be connected to each other through the overlapping portion 310, which can improve the easy breakage of the signal connecting line 510 caused by the opening of the insulating layer 024. problem, the yield rate of the signal connection line 510 can be ensured, thereby improving the yield rate of the display panel. Therefore, the embodiment of the present application forms an overlapping portion 310 in the via hole 024a, so that at least some of the signal connection lines 510 on both sides of the via hole 024 are connected to each other through the overlapping portion 310, thereby improving the yield of the signal connection line 510.

Optionally, the insulating layer 024 includes a first insulating layer 02 and a second insulating layer 04 , and the via hole 024 a includes a first via hole 210 formed in the first insulating layer 02 and a second via hole formed in the second insulating layer 04 . 410. A metal wiring layer 03 is provided between the first insulating layer 02 and the second insulating layer 04.

As shown in Figure 14, the preparation method of the display panel may include:

Step S01': Prepare a first insulating layer 02 on the substrate 01, and pattern the first insulating layer 02 to form a first via hole 210.

Step S02': Set a metal material layer on the side of the first insulating layer 02 facing away from the substrate 01, and pattern the metal material layer to form a metal wiring layer 03. The metal wiring layer 03 includes at least part of the first via hole 210. The overlapping portion 310 inside.

Step S03’: Prepare a second insulating layer 04 on the side of the metal wiring layer 03 facing away from the first insulating layer 02. The second insulating layer 04 includes a second via hole 410, and the overlapping portion 310 is exposed through the second via hole 410.

Step S04': Prepare a wiring layer 05 on the side of the second insulating layer 04 facing away from the metal wiring layer 03. The wiring layer 05 includes signal connection lines 510, and at least part of the signal connection lines 510 is connected to the overlap via the second via hole 410. The parts 310 are connected to each other.

In the process of preparing the display panel 100 by the preparation method provided in the embodiment of the present application, the first via hole 210 and the second via hole 410 will be opened on the first insulating layer 02 and the second insulating layer 04. The first via hole 210 and The second via hole 410 can release stress on the first insulation layer 02 and the second insulation layer 04 . The metal traces form an overlap portion 310 in the first via hole 210, and at least part of the extension path of the signal connection line 510 passes through the second via hole 410, so that at least part of the signal connection line 510 located on both sides of the second via hole 410 is connected to the overlap portion. The connecting parts 310 are connected to each other, that is, the signal connection lines 510 located on both sides of the overlapping part 310 can be connected to each other through the overlapping part 310, which can avoid the connection signal from being easily broken due to the opening of the first insulating layer 02 and the second insulating layer 04. problem, the yield rate of the signal connection line 510 can be ensured, thereby improving the yield rate of the display panel 100 . Therefore, in the embodiment of the present application, a metal overlap portion 310 is formed in the first via hole 210 so that at least part of the signal connection lines 510 on both sides of the second via hole 410 are connected to each other through the overlap portion 310, thereby improving the performance of the signal connection lines 510. Yield.

Please refer to FIG. 3 , FIG. 4 , FIG. 14 and FIG. 15 together. FIG. 15 is a schematic flowchart of a method for manufacturing a display panel 100 according to another embodiment of the third aspect of the present application.

In some optional embodiments, as shown in FIG. 3 , the first insulating layer 02 includes a first sub-layer 20 a and a second sub-layer 20 b located on the side of the first sub-layer 20 a facing away from the substrate 01 , as shown in FIG. 15 As shown, step S01' includes:

Step S011: prepare a first sub-layer 20a and a second sub-layer 20b on the substrate 01.

Optionally, as shown in Figure 3, when the active layer 07 is also provided on the side of the first sub-layer 20a facing the substrate 01, the active layer 07 is also prepared on the substrate 01 before step S011, and The active layer 07 is patterned to form a semiconductor portion. When the active layer 07 includes the pads 710, patterning the active layer 07 also forms the pads 710.

Optionally, as mentioned above, when the display panel 100 includes the first metal layer 08 and the second metal layer 09, in step S011, after the first sub-layer 20a is prepared, a third sub-layer 20a is also prepared on the first sub-layer 20a. A metal layer 08 is patterned to form a gate electrode. A first second sub-layer 20b is prepared on the first metal layer 08, a second metal layer 09 is prepared on the first second sub-layer 20b, and the second metal layer 09 is patterned to form a capacitor plate. Then continue to prepare a second layer of second sub-layer 20b on the second metal layer 09.

Step S012: Pattern the second sub-layer 20b to form a second hole segment.

Optionally, gases such as tetrafluoromethane CF ₄ and oxygen can be used to pattern the second sub-layer 20b.

Step S013: Pattern the first sub-layer 20a exposed by the second hole segment to form a first hole segment, and the first hole segment and the second hole segment are connected to form a first via hole 210.

Optionally, gases such as pentafluoroethane C ₂ F ₅ H, hydrogen H ₂ and argon Ar can be used to pattern the first sub-layer 20 a.

The overlapping portion 310 formed in step S02' at least covers the inner wall surface of the first sub-layer 20a facing the first hole section.

In these optional embodiments, when the overlap portion 310 covers the inner wall surface of the first hole section, there is no need to pattern the metal in the first hole section, so the pattern of the metal wiring layer 03 can be effectively improved. By minimizing the problem that metal residue is easily formed in the first hole section, the problem that the second insulating layer 04 is easily broken in the first via hole 210 caused by the metal residue can be effectively improved, and the size of the overlapping portion 310 can be made smaller. The signal connection line 510 can penetrate into the second via hole 410 and connect with the overlapping portion 310 .

Optionally, when the display panel 100 includes a third insulating layer, a pixel electrode layer 06 , a pixel definition layer 10 and other layer structures, other film layers may be further prepared after step S04 to form the display panel 100 .

According to the above-described embodiments of the present application, these embodiments do not exhaustively describe all the details, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and make modifications based on the present application. This application is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A display panel, characterized by including:

   substrate;

   An insulating layer located on one side of the substrate and formed with several via holes;

   An overlapping portion is formed in the via hole, and the overlapping portion covers at least part of the side wall of the via hole where it is located;

   Signal connection line, at least part of the signal connection line includes a main body part located on the side of the insulating layer facing away from the substrate, an extension part extending from the main body part into the via hole and interconnected with the overlapping part .
2. The display panel according to claim 1, wherein the insulating layer includes a first insulating layer and a second insulating layer located on a side of the first insulating layer facing away from the substrate, and the via hole includes a first insulating layer formed on the first insulating layer. a first via hole in the insulating layer and a second via hole formed in the second insulating layer;

   The display panel further includes a metal wiring layer located between the first insulating layer and the second insulating layer,

   Wherein, the overlapping portion covers at least part of the side wall of the first via hole, and the overlapping portion and the metal wiring layer are made of the same material.
3. The display panel of claim 2, wherein a size of the first via hole is smaller than a size of the second via hole;

   Preferably, the metal wiring layer further includes a transition portion located on the surface of the first insulating layer toward the second insulating layer and surrounding at least one of the first via holes, and the transition portion is connected to the overlapping The extension parts are connected to each other through the transition part and the overlap part, or the extension part, the transition part and the overlap part are connected to each other;

   Preferably, the transition portion is located on the surface of the first insulating layer exposed by the second via hole; preferably, the extension size of the transition portion in the aperture direction of the first via hole is 1.5 μm to 5 μm. ;

   Preferably, the pore diameter of the first via hole is 2 μm to 4 μm, and the pore diameter of the second via hole is 4 μm to 6 μm.
4. The display panel of claim 2, wherein the display panel further comprises an active layer disposed between the substrate and the insulating layer, the active layer further comprising spacers, at least part of the The opening of the first via hole toward the side of the substrate does not extend beyond the spacer block.
5. The display panel according to claim 1, wherein the display panel has a first display area and a second display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area, so The display panel also includes:

   The pixel electrode layer includes a first pixel electrode located in the first display area and connected to the signal connection line;

   A driving circuit, including a first driving circuit for driving the first pixel electrode, the first driving circuit connecting the first pixel electrode through the signal connection line;

   Preferably, at least part of the orthographic projection of the via hole on the substrate and the orthographic projection of the first pixel electrode on the substrate are at least partially overlapped;

   Preferably, at least part of the orthographic projection of the via hole on the substrate is located within the orthographic projection of the first pixel electrode on the substrate;

   Preferably, the signal connection wire is a light-transmitting wire.
6. The display panel according to claim 5, wherein

   At least part of the via holes is located in the first display area;

   Preferably, at least part of the via holes is provided in the first display area close to the second display area;

   Preferably, the second display area includes a main display area and a transition display area, the transition display area is located between the main display area and the first display area, and at least part of the via holes is located in the transition display area. district;

   Preferably, at least part of the via holes is disposed close to the first display area in the transition display area.
7. The display panel according to claim 1, wherein the radial dimension of the orthographic projection of the overlapping portion on the substrate is 2 μm˜3 μm.
8. The display panel according to claim 1, wherein the signal connection line includes a first signal connection line and a second signal connection line, the first signal connection line includes the extension portion, and the second signal connection line The orthographic projection on the substrate and the orthographic projection of the via hole on the substrate are at least partially offset;

   Preferably, the orthographic projection of the second signal connection line on the substrate and the orthographic projection of the via hole on the substrate are completely offset.
9. A display device, comprising the display panel according to any one of claims 1-8.
10. A preparation method for a display panel, including:

    Prepare an insulating layer on the substrate, and pattern the insulating layer to form via holes;

    Depositing metal material in the via hole to form an overlap;

    A wiring layer is prepared on the insulating layer. The wiring layer includes signal connection lines. At least part of the signal connection lines include a main body portion located on the side of the insulating layer facing away from the substrate, extending from the main body portion to An extension portion inside the via hole and interconnected with the overlap portion.

Images