WO2024000646A1

WO2024000646A1 - Semiconductor memory and control method therefor, and memory system

Info

Publication number: WO2024000646A1
Application number: PCT/CN2022/105142
Authority: WO
Inventors: 赵保峰; 李中和
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-06-27
Filing date: 2022-07-12
Publication date: 2024-01-04
Also published as: CN115132246A

Abstract

Provided in the embodiments of the present disclosure is a semiconductor memory, comprising: an input module, which is configured to receive an address/command input signal; a plurality of redundant modules, which are divided into N sets, N being an integer greater than 1, and are configured to receive the address/command input signal and output a first enable signal; N buses, which correspond to the N sets on a one-to-one basis, wherein each bus is directly electrically connected to output ends of a plurality of redundant modules in the corresponding set; and a control module, which is configured to obtain a second enable signal according to signals, which are output by means of the N buses, wherein the first enable signal and the second enable signal are used for instructing to perform redundant decoding or normal decoding.

Description

Semiconductor memory and control method and memory system thereof

Related cross-references

This disclosure is based on a Chinese patent application with application number 202210745136. The entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor memory, a control method thereof, and a memory system.

Background technique

Semiconductor memory chips are important components for storing data in various electronic devices. With the development of integrated circuit technology, the precision and complexity of semiconductor memory chips are increasing day by day. Due to limitations of the production process and production conditions, the semiconductor memory chips produced are not perfect, so there are increasingly higher requirements for memory fault diagnosis and redundancy repair. For memories that have storage failures during actual use, how to improve the processing speed of redundant repair operations has become an urgent problem to be solved.

Contents of the invention

In view of this, the main purpose of the present disclosure is to provide a semiconductor memory, a control method thereof, and a memory system.

In order to achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

An embodiment of the present disclosure provides a semiconductor memory, including:

An input module configured to receive address/command input signals;

Multiple redundant modules, the multiple redundant modules are divided into N sets, where N is an integer greater than 1; the redundant module is configured to receive the address/command input signal and output a first enable signal;

N buses corresponding one-to-one to the N sets, each of the buses being directly electrically connected to the output terminals of a plurality of the redundant modules in the corresponding set;

A control module configured to obtain a second enable signal based on N signals output by the bus; the first enable signal and the second enable signal are used to indicate redundant decoding or normal decoding.

In the above solution, the control module includes a logic unit;

Each of the buses is connected to the logic unit;

The logic unit is configured to perform logical operations on N signals output by the bus to obtain a second enable signal.

In the above solution, the logic unit includes a logic NAND gate and an inverter, the input terminals of the logic NAND gate are respectively connected to the bus, and the output terminal of the logic NAND gate is connected to the inverter. Input connection.

In the above solution, the control module also includes N reset units and N holding units; each bus is connected to a reset unit and a holding unit;

The reset unit is configured to reset the signal of the bus when powered on;

The holding unit is configured to hold the corresponding signal of the bus.

In the above solution, the holding unit includes an inverter and a first transistor; the input end of the inverter is connected to the bus, and the output end of the inverter is connected to the gate of the first transistor;

The reset unit includes a second transistor, the gate of the second transistor is connected to an external power supply, one of the source/drain electrodes of the second transistor and the first transistor is connected to the power supply voltage, and one electrode is connected to the source/drain of the first transistor. Described bus.

In the above solution, the holding unit is configured to keep the signal of the bus at weak logic 1 after the reset unit resets. When multiple redundant modules in the set output multiple When at least one of the first enable signals indicates redundant decoding, the signal of the bus is pulled down from a weak logic 1 to a logic 0.

The above solution also includes: a storage array, the storage array includes multiple storage parts;

The plurality of redundant modules are connected to the plurality of storage parts in a one-to-one correspondence.

The above solution further includes: a decoding module, the output end of the control module is coupled to the input end of the decoding module, the decoding module is configured to input the address/command signal based on the second enable signal. Perform redundant decoding or normal decoding.

In the above scheme, the redundant module includes an address comparison unit configured to compare the address information in the address/command input signal with the redundant address information, and output the first user address based on the comparison result. can signal.

Embodiments of the present disclosure also provide a method for controlling a semiconductor memory. The semiconductor memory includes multiple storage parts. The method includes:

Receive address/command input signals, and output multiple first enable signals corresponding to the multiple storage parts; divide the multiple first enable signals into N sets, where N is an integer greater than 1;

For each of the sets, directly output a plurality of the first enable signals to a corresponding bus;

A second enable signal is obtained according to N signals output by the bus; the first enable signal and the second enable signal are used to indicate redundant decoding or normal decoding.

In the above solution, the method further includes: performing redundant decoding or normal decoding on the address/command input signal according to the second enable signal.

In the above solution, the method further includes: resetting the signal of the bus when powering on.

In the above solution, the method further includes: after resetting, keeping the signal of the bus at weak logic 1, when at least one of the plurality of first enable signals in the set is the first When the enable signal indicates redundant decoding, the signal of the bus is pulled low from a weak logic 1 to a logic 0.

In the above solution, the receiving address/command input signal and outputting multiple first enable signals corresponding to the multiple storage parts include:

The address information in the address/command input signal is compared with the redundant address information, and according to the comparison result, a plurality of first enable signals corresponding to the plurality of storage parts are output.

Embodiments of the present disclosure also provide a memory system, including: at least one semiconductor memory as described above; and

A memory controller coupled to the semiconductor memory and configured to control the semiconductor memory.

In the technical solution provided by the present disclosure, a semiconductor memory is provided. The semiconductor memory includes: an input module configured to receive an address/command input signal; a plurality of redundant modules, and the plurality of redundant modules are divided into N Sets, N is an integer greater than 1; the redundant module is configured to receive the address/command input signal and output the first enable signal; N buses corresponding one-to-one to the N sets, each of which The bus is directly electrically connected to the output terminals of a plurality of the redundant modules in the corresponding set; the control module is configured to obtain a second enable signal based on the signals output by the N buses; the first enable signal The enable signal and the second enable signal are used to indicate redundant decoding or normal decoding. In this way, the output terminals of multiple redundant modules are directly electrically connected to the corresponding bus, which realizes the merging of multiple first enable signals, greatly reduces the number of signal transmission stages, and can quickly obtain instructions for redundancy. The second enable signal of decoding or normal decoding can thereby increase the processing speed of the redundancy repair operation and improve the performance of the memory during actual use of the semiconductor memory. At the same time, the circuit structure is simplified and the area occupied by the circuit structure is reduced.

Description of drawings

Figure 1 is a schematic diagram of a redundant signal generation circuit provided in the related art;

Figure 2 is a schematic diagram of a redundant signal generation circuit provided by an embodiment of the present disclosure;

Figure 3 is a schematic diagram of a semiconductor memory provided by an embodiment of the present disclosure;

Figure 4 is a schematic diagram of a circuit of a control module provided by an embodiment of the present disclosure;

Figure 5 is a schematic diagram of a decoding module provided by an embodiment of the present disclosure;

Figure 6 is a schematic flowchart of the implementation of a semiconductor memory control method provided by an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a memory system provided by an embodiment of the present disclosure.

Detailed ways

The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described in more detail, by way of example, in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present disclosure.

It should be understood that spatial relational terms such as "under", "under", "under", "under", "on", "above", etc., are used here It may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others. The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

It should be noted that the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily as long as there is no conflict.

FIG. 1 shows a schematic diagram of a circuit for generating the overall redundancy signal HITTOR in a semiconductor memory. As shown in Figure 1, the storage array of a semiconductor memory includes 64 storage parts as an example. Each storage part is provided with a redundant unit. The redundant unit of each storage part generates a local redundancy signal HITT. The 64 HITT signals HITT<0:63> use cascade logical operations (for example, logical OR operations) to obtain the overall redundant signal HITTOR. Specifically, the first OR gate O1 is used to receive two local redundant signals HITT<0:1> among the first to sixty-fourth local redundant signals HITT<0:63>, and output a first logic signal. The second OR gate O2 is used to receive the above-mentioned first logic signal and the local redundancy signal HITT<2>, and output a second logic signal. By analogy, the sixty-third OR gate O63 is used to receive the logic signal and the local redundancy signal HITT<63> output by the sixty-second OR gate O62, and output the overall redundancy signal HITTOR. When at least one of the 64 local redundancy signals HITT<0:63> is logic 1, the output overall redundancy signal HITTOR is logic 1, which is used to indicate the execution of a redundancy repair operation. The above-mentioned cascade logic operation has the problem that the circuit structure uses too many logic gates and requires 64-level signal transmission step by step. Therefore, signal delay is prone to occur. This delay is not used to improve the processing speed of redundant repair operations.

The embodiment of the present disclosure provides a schematic diagram of a circuit for generating the overall redundancy signal HITTOR in a semiconductor memory. Please refer to Figure 2. For illustration, a storage array of a semiconductor memory including 32 storage parts is used as an example. The redundancy of each storage part is The unit generates a local redundant signal HITT, and uses the dichotomy method to perform logical operations on the 32 HITT signals HITT<0:31>. Specifically, the schematic diagram of the overall redundant signal HITTOR generation circuit shown in Figure 2 includes: first to The thirty-second AND gates A1 to A32, wherein each of the first to sixteenth AND gates A1 to A16 is used to respond to two of the first to thirty-second local redundant signals HITT<0:31> The partial repair signal outputs the first to sixteenth logic signals respectively; the seventeenth to twenty-fourth AND gates A17 to A24 are used to receive the first to sixteenth logical signals output from the first to sixteenth AND gates A1 to A16. Sixteen logic signals, in which each AND gate A17 to A24 receives two of the first to sixteenth logic signals; the twenty-fifth to twenty-eighth AND gates A25 to A28 are used to receive the tenth logic signal. The output signals of the seventh to twenty-fourth AND gates A17 to A24, wherein each AND gate in A25 to A28 receives two logic signals from the output signals of A17 to A24; the twenty-ninth to thirtieth AND gates A29 to A30 is used to receive the output signals of the twenty-fifth to twenty-eighth AND gates A25 to A28, where each AND gate in A29 to A30 receives two logic signals from the output signals of A25 to A28; Thirty-one AND gate A31 generates the overall redundant signal HITTOR by receiving the output signals of AND gates A29 and A30. When at least one of the 32 local redundant signals HITT<0:31> is logic 0, the output overall redundant signal HITTOR is logic 0 to indicate redundancy repair operations. The above-mentioned dichotomy logical operation reduces the number of transmission levels of the 32 local redundant signals HITT<0:31> to 5, reducing the delay in the signal transmission process. However, the above-mentioned dichotomy circuit structure includes 31 AND gates. This circuit structure occupies a large area and has complicated connections between logic gates at all levels, which is not conducive to improving the performance of semiconductor memory, so further improvements are needed.

Based on this, the present disclosure proposes the following embodiments.

3 shows a schematic diagram of an exemplary semiconductor memory 30 provided in accordance with the present disclosure. In one example, the semiconductor memory may include dynamic random access memory (Dynamic Random Access Memory, DRAM). As shown in Figure 3, the semiconductor memory 30 includes: an input module 310 configured to receive an address/command input signal; a plurality of redundant modules 320, the plurality of redundant modules 320 are divided into N sets, where N is an integer greater than 1; The redundancy module 320 is configured to receive an address/command input signal and output a first enable signal; N buses 330 correspond one-to-one to N sets, and each bus 330 is associated with a plurality of redundancy modules 320 in the corresponding set. The output end is directly electrically connected; the control module 340 is configured to obtain a second enable signal according to the signals output by the N buses 330; the first enable signal and the second enable signal are used to indicate redundant decoding or normal decoding. It should be noted that Figure 3 takes N equal to 2 as an example for illustration.

By directly electrically connecting each bus 330 to the output terminals of the multiple redundant modules 320 in the corresponding set, the first enable signals output by the multiple redundant modules 320 are controlled without using logic gates. Merging greatly reduces the number of signal transmission stages, shortens the signal transmission time, and can quickly obtain the second enable signal indicating redundant decoding or normal decoding, thus improving the processing speed of redundant repair operations. At the same time The circuit structure is simplified and the occupied area of the circuit structure is reduced.

In the embodiment of the present disclosure, the control module 340 includes a logic unit 341; each bus 330 is connected to the logic unit 341; the logic unit 341 is configured to perform logical operations on the signals output by the N buses 330 to obtain the second enable signal.

Figure 4 is a schematic circuit diagram of a control module provided by an embodiment of the present disclosure. As shown in Figure 4, the logic unit 341 includes a logic NAND gate 3411 and an inverter 3412. The input terminals of the logic NAND gate 3411 are respectively connected to the bus 330. The output terminal of the logic NAND gate 3411 is connected to the input terminal of the inverter 3412. In a specific example, the logic NAND gate 3411 receives the signal from the bus, performs a logical operation on the signal output from the bus and outputs it to the inverter 3412, and outputs the second enable signal through the inverter 3412. When the signal of at least one bus among the bus signals input to the logic unit 341 is logic 0, the second enable signal obtained after the logic operation is performed by the logic unit 341 is also logic 0. At this time, the second enable signal indicates to proceed. Redundant decoding.

In the embodiment of the present disclosure, the control module also includes N reset units and N holding units; each bus is connected to a reset unit 342 and a holding unit 343; the reset unit 342 is configured to reset the corresponding bus when powered on. The signal is reset; the holding unit 343 is configured to hold the signal of the corresponding bus.

In the embodiment of the present disclosure, the holding unit 343 includes an inverter 3431 and a first transistor 3432; the input terminal of the inverter 3431 is connected to the bus, and the output terminal of the inverter 3431 is connected to the gate of the first transistor 3432; reset The unit 342 includes a second transistor 3421. The gate of the second transistor 3421 is connected to the external power supply PWRB. One of the source and drain electrodes of the second transistor 3421 and the first transistor 3432 is connected to the power supply voltage VDD, and the other electrode is connected to the bus 330.

In some embodiments, the source of the second transistor 3421 is connected to the power supply voltage VDD. When the external power supply PWRB connected to the gate of the second transistor 3421 of the reset unit 342 provides a logic low voltage (eg, ground or 0V), the second transistor 3421 is connected to the power supply voltage VDD. Transistor 3421 will turn on, resetting the signal on bus 330 to a logic one.

In some embodiments, in order to maintain the signal state of the bus 330, a holding unit 343 is provided. When the signal of the bus 330 is reset to logic 1, the inverter 3431 outputs logic 0 to the gate of the first transistor 3432, and Because the source of the first transistor 3432 is connected to the power supply voltage VDD, the first transistor 3432 is turned on, causing the bus 330 signal to maintain or maintain a logic 1. In a preferred embodiment, the first transistor 3432 is a P-type metal oxide semiconductor (Positive Channel Metal Oxide Semiconductor, PMOS) transistor. The ratio of the width to the length of the channel of the PMOS transistor is set to be small, so the drive of the PMOS transistor The capability is weak, and the current is small after the PMOS transistor is turned on. When the first transistor 3432 is set as a PMOS transistor in the holding unit 343, the signal of the bus 330 will be maintained at weak logic 1. It should be noted that in the above embodiment, logic 1 corresponds to the situation where the output voltage of the PMOS transistor is a high voltage, and weak logic 1 corresponds to the situation where the output voltage of the PMOS transistor is a weak high voltage. Here, the weak high voltage is smaller than the high voltage and Greater than half of the high voltage. For example, when the output voltage of a PMOS transistor is 1V, it is in a logic 1 state. When the output voltage of a PMOS transistor is 0.7V, it is in a weak logic 1 state.

In the embodiment of the present disclosure, the holding unit 343 is configured to keep the signal of the bus at weak logic 1 after the reset unit 342 performs the reset. When the plurality of first enable signals output by the plurality of redundant modules 320 in the set When at least one of the first enable signals indicates redundant decoding, the signal of the bus is pulled down from a weak logic 1 to a logic 0. In the embodiment of the present disclosure, by setting the holding unit, when receiving the first enable signal indicating redundant decoding, the signal of the bus can be quickly pulled down from weak logic 1 to logic 0, thereby further reducing the delay time. Improved processing speed for redundancy repair operations.

In the embodiment of the present disclosure, the redundancy module 320 includes an address comparison unit configured to compare the address information in the address/command input signal with the redundant address information, and output the first enable signal according to the comparison result. . Specifically, when the address information in the address/command input signal matches the redundant address information, the first enable signal is 0, indicating redundant decoding, and when one of the plurality of first enable signals output to the corresponding bus 330 When at least one first enable signal indicates redundant decoding, the signal of the bus 330 will be quickly pulled down from a weak logic 1 to a logic 0, then at least one of the signals input to the logic unit 341 is a logic 0, regardless of other buses. Whether the signal on is logic 1 or logic 0, the second enable signal obtained is both 0. At this time, the second enable signal indicates redundant decoding; when the address information in the address/command input signal does not match the redundant address information When matching, the first enable signal is 1, indicating normal decoding, and the signal on the bus is always maintained at a weak logic 1, then the signals input to the logic unit 341 are all logic 1, and the obtained second enable signal is 1, so When the second enable signal indicates normal decoding.

It can be understood that when at least one of the multiple first enable signals input to the corresponding bus is 0, the signal of the corresponding bus will quickly pull down from a weak logic 1 to a logic 0 and output to Logic unit 341. Since the logic unit 341 performs logical AND operations on the received bus signals, once it receives a logic 0 signal transmitted from one bus, the logic unit 341 can directly output the second signal indicating redundant decoding no matter what state the other bus signals are in. enable signal. Therefore, the time at which the logic unit 341 outputs the second enable signal indicating redundancy decoding will not be affected by signals from other buses, and the output speed of the signal can be increased overall and the delay reduced, thereby improving the processing speed of the redundancy repair operation. In a specific example, the address comparison unit may include an Array Rupture Electricalfuse (ARE). The Array Rupture Electricalfuse may store information about addresses that have failed, that is, redundant address information. The redundant address information collected during the semiconductor memory test may be temporarily stored in a storage device of the semiconductor memory tester, and then applied to the semiconductor memory to blow the electrical fuse corresponding to the corresponding address, so that the redundant address Information is stored permanently in semiconductor memory.

In the embodiment of the present disclosure, the semiconductor memory further includes: a decoding module 350. The output terminal of the control module is coupled to the input terminal of the decoding module 350. The decoding module 350 is configured to perform redundant processing on the address/command input signal based on the second enable signal. Decoding or normal decoding.

FIG. 5 shows a schematic diagram of the decoding module 350. As shown in FIG. 5, the decoding module 350 includes a redundant decoding unit 351 and a normal decoding unit 352. When the second enable signal is 1, the second enable signal indicates normal decoding, thus enabling the normal decoding unit 352 to normally decode the address information in the address/command input signal to obtain the address of the normal storage unit. When the second enable signal is 0, the second enable signal indicates redundant decoding, thereby enabling the redundant decoding unit 351 to redundantly decode the address information in the address/command input signal to obtain a replacement for the defective address. The address of the redundant storage unit. Both the redundant decoding unit 351 and the normal decoding unit 352 include two decoding units, namely a row decoding unit for decoding row addresses and a column decoding unit for decoding column addresses.

In the embodiment of the present disclosure, the semiconductor memory further includes a storage array 360. The storage array 360 includes a plurality of storage parts; a plurality of redundant modules 320 are connected to the plurality of storage parts in a one-to-one correspondence. The storage part can be a memory bank (Bank) or a memory array tile (Memory Arrary Tile, Mat), and each memory bank or each memory array tile can include multiple storage units.

The embodiment of the present disclosure also provides a method for controlling a semiconductor memory. The semiconductor memory includes multiple storage parts. Figure 6 is a schematic flowchart of a specific implementation of the method for controlling the semiconductor memory provided by the embodiment of the present disclosure. As shown in Figure 6, the control method The method specifically includes the following steps:

Step S610: Receive address/command input signals, and output multiple first enable signals corresponding to multiple storage parts; divide the multiple first enable signals into N sets, where N is an integer greater than 1.

In the above step S610, receiving the address/command input signal and outputting multiple first enable signals corresponding to multiple storage parts includes: comparing the address information in the address/command input signal with the redundant address information, and According to the comparison result, a plurality of first enable signals corresponding to the plurality of storage parts are output. Specifically, when the address information in the address/command input signal matches the redundant address information, the first enable signal is 0, indicating redundant decoding; when the address information in the address/command input signal matches the redundant address information When there is a mismatch, the first enable signal is 1, indicating normal decoding.

Step S620: For each set, directly output multiple first enable signals to a corresponding bus.

In the above step S620, the method also includes: resetting the signal of the bus when powering on. Specifically, the source of the second transistor 3421 is connected to the power supply voltage VDD. When the external power supply PWRB connected to the gate of the second transistor 3421 in the reset unit 342 provides a logic low voltage (eg, ground or 0V), the second transistor 3421 will turn on and the signal on bus 330 is reset to logic 1.

After the reset is performed, the signal of the bus 330 is maintained at weak logic 1. When at least one first enable signal among the plurality of first enable signals in the set indicates redundant decoding, the signal of the bus 330 is changed from weak logic 1 to weak logic 1. 1 pulled low to logic 0. In a specific example, when the address information in the address/command input signal matches the redundant address information, the first enable signal is 0, indicating redundant decoding. When multiple first enable signals output to the corresponding bus When at least one of the first enable signals in the signal is 0, the signal on the bus will be pulled down from weak logic 1 to logic 0; when the address information in the address/command input signal does not match the redundant address information, the first enable signal will The energy signal is 1, indicating normal decoding, and the bus signal is always maintained at weak logic 1.

Step S630: Obtain the second enable signal according to the signals output by the N buses; the first enable signal and the second enable signal are used to indicate redundant decoding or normal decoding.

In a specific example, the logical operation on the signals output by N buses is implemented through the logic unit 341. The logic NAND gate 3411 receives the signals output by the N buses and outputs them to the inverter 3412, and outputs the second operation signal via the inverter 3412. can signal. When the signal of at least one bus among the bus signals input to the logic unit 341 is logic 0, the second enable signal obtained after the logic operation is performed by the logic unit 341 is also logic 0. At this time, the second enable signal indicates to proceed. Redundant decoding.

In some embodiments, when the address information in the address/command input signal matches the redundant address information, the first enable signal is 0, indicating redundant decoding, and is output to multiple first enable signals of the corresponding bus. At least one of them is logic 0, and the signal on the bus will be quickly pulled down from weak logic 1 to logic 0. Then at least one of the signals input to the logic unit 341 is logic 0, regardless of whether the signals on other buses are logic 1 or logic 0. 0, the obtained second enable signals are all 0. At this time, the second enable signal indicates redundant decoding; when the address information in the address/command input signal does not match the redundant address information, the first enable signal is 1, indicating normal decoding, and the bus signal is always maintained at a weak logic 1, then the bus signals input to the logic unit 341 are all logic 1, and the obtained second enable signal is 1. At this time, the second enable signal Indicates normal decoding.

According to the second enable signal, the address/command input signal is redundantly decoded or normally decoded. When the second enable signal is 1, it indicates normal decoding, and the address information in the address/command input signal is normally decoded to obtain the address of the normal storage unit. When the second enable signal is 0, it indicates redundant decoding, performs redundant decoding on the address information in the address/command input signal, and obtains the address of the redundant storage unit that replaces the defective address.

Figure 7 is a schematic diagram of a memory system according to an exemplary embodiment. Based on the above semiconductor memory structure, embodiments of the present disclosure provide a memory system. As shown in FIG. 7 , the memory system includes at least one semiconductor memory as above; and a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory.

Memory system 700 includes mobile phones, smartphones, desktop computers, laptop computers, tablet computers, personal digital assistants (PDAs), portable multimedia players (PMP), digital cameras, camcorders, personal computers (PC), server computers, Workstation, digital TV, set-top box, portable game console, navigation system, wearable electronic device, Internet of Things (IoT) device, Internet of Everything (IoE) device, e-book, virtual reality (VR) device, augmented reality (AR) device or Any other suitable electronic device having a semiconductor memory therein.

As shown in FIG. 7 , memory system 700 may include a host 708 and a storage subsystem 702 having one or more semiconductor memories 704 , which also includes a memory controller 706 . The host 708 may be a processor (eg, a central processing unit (CPU)) or a system-on-a-chip (SoC) (eg, an application processor (AP)) of the electronic device. Host 708 may access memory subsystem 702 in conjunction with or running execution of one or more applications 712 of one or more operating systems 710 . Semiconductor memory 704 may be any semiconductor memory disclosed in this disclosure.

According to some implementations, memory controller 706 is also coupled to host 708 . The memory controller 706 may provide an interface to the semiconductor memory 704 to manage data stored in the semiconductor memory 704 and may be configured through various interface protocols (e.g., USB, MMC, PCIe, Serial ATA, Parallel ATA, SCSI). At least one of the hosts 708 communicates. Memory controller 706 may be implemented as a separate chip or may be integrated with semiconductor memory 704 . Memory controller 706 may be implemented on the motherboard, and may be implemented as an integrated memory controller (IMC) included in a microprocessor.

In some implementations, memory controller 706 may send and receive command/address signal C/A, clock signal CLK, control signal CTRL, data DQ, and/or data strobe signal DQS to and from semiconductor memory 704 . Memory controller 706 may be configured to control operations of semiconductor memory 704, such as read and write operations.

It can be understood that the memory controller 706 can perform the control method provided by any embodiment of the present disclosure.

Embodiments of the present disclosure provide a semiconductor memory that directly electrically connects the output terminals of multiple redundant modules to corresponding buses, thereby reducing the number of signal transmission stages and enabling faster instructions for redundant decoding or The normally decoded second enable signal can improve the processing speed of the redundancy repair operation, and can improve the performance of the memory during actual use of the semiconductor memory.

It will be understood that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present disclosure. The implementation process constitutes any limitation. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Claims

A semiconductor memory including:

An input module configured to receive address/command input signals;

Multiple redundant modules, the multiple redundant modules are divided into N sets, where N is an integer greater than 1; the redundant module is configured to receive the address/command input signal and output a first enable signal;

N buses corresponding one-to-one to the N sets, each of the buses being directly electrically connected to the output terminals of a plurality of the redundant modules in the corresponding set;

A control module configured to obtain a second enable signal based on N signals output by the bus; the first enable signal and the second enable signal are used to indicate redundant decoding or normal decoding.
The semiconductor memory according to claim 1, wherein

The control module includes a logic unit;

Each of the buses is connected to the logic unit;

The logic unit is configured to perform logical operations on N signals output by the bus to obtain a second enable signal.
The semiconductor memory according to claim 2, wherein

The logic unit includes a logic NAND gate and an inverter. The input terminals of the logic NAND gate are respectively connected to the bus, and the output terminal of the logic NAND gate is connected to the input terminal of the inverter.
The semiconductor memory according to claim 2, wherein

The control module also includes N reset units and N holding units; each bus is connected to a reset unit and a holding unit;

The reset unit is configured to reset the signal of the bus when powered on;

The holding unit is configured to hold the corresponding signal of the bus.
The semiconductor memory according to claim 4, wherein

The holding unit includes an inverter and a first transistor; the input end of the inverter is connected to the bus, and the output end of the inverter is connected to the gate of the first transistor;

The reset unit includes a second transistor, the gate of the second transistor is connected to an external power supply, one of the source and drain of the second transistor and the first transistor is connected to the power supply voltage, and the other is connected to the bus.
The semiconductor memory according to claim 4 or 5, wherein

The holding unit is configured to maintain the signal of the bus at weak logic 1 after the reset unit performs a reset. When at least one of the first enable signals in the enable signals indicates redundant decoding, the signal of the bus is pulled down from a weak logic 1 to a logic 0.
The semiconductor memory of claim 1, further comprising:

A storage array including a plurality of storage portions;

The plurality of redundant modules are connected to the plurality of storage parts in a one-to-one correspondence.
The semiconductor memory of claim 1, further comprising:

a decoding module, the output end of the control module is coupled to the input end of the decoding module, the decoding module is configured to perform redundant decoding or normal decoding on the address/command input signal based on the second enable signal .
The semiconductor memory according to claim 1, wherein

The redundant module includes an address comparison unit configured to compare the address information in the address/command input signal with the redundant address information, and output a first enable signal according to the comparison result.
A control method of a semiconductor memory, the semiconductor memory includes multiple storage parts, the method includes:

Receive address/command input signals, and output multiple first enable signals corresponding to the multiple storage parts; divide the multiple first enable signals into N sets, where N is an integer greater than 1;

For each of the sets, a plurality of the first enable signals are directly output to a corresponding bus;

A second enable signal is obtained according to N signals output by the bus; the first enable signal and the second enable signal are used to indicate redundant decoding or normal decoding.
The control method according to claim 10, wherein the method further includes:

According to the second enable signal, the address/command input signal is redundantly decoded or normally decoded.
The control method according to claim 11, wherein the method further includes: resetting the signal of the bus when powering on.
The control method according to claim 12, wherein the method further includes: after resetting, keeping the signal of the bus at weak logic 1, when a plurality of the first enablers in the set are When at least one of the first enable signals in the signals indicates redundant decoding, the signal of the bus is pulled down from a weak logic 1 to a logic 0.
The control method according to claim 10, wherein the receiving address/command input signal and outputting a plurality of first enable signals corresponding to the plurality of storage parts include:

The address information in the address/command input signal is compared with the redundant address information, and according to the comparison result, a plurality of first enable signals corresponding to the plurality of storage parts are output.
A memory system including:

At least one semiconductor memory according to any one of claims 1 to 9; and

A memory controller coupled to the semiconductor memory and configured to control the semiconductor memory.