WO2023287407A1 - Initialisation de composant matériel - Google Patents

Initialisation de composant matériel Download PDF

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Publication number
WO2023287407A1
WO2023287407A1 PCT/US2021/041545 US2021041545W WO2023287407A1 WO 2023287407 A1 WO2023287407 A1 WO 2023287407A1 US 2021041545 W US2021041545 W US 2021041545W WO 2023287407 A1 WO2023287407 A1 WO 2023287407A1
Authority
WO
WIPO (PCT)
Prior art keywords
volatile memory
memory device
instructions
electronic device
initialization
Prior art date
Application number
PCT/US2021/041545
Other languages
English (en)
Inventor
Mason Gunyuzlu
Rosilet Retnamoni BRADUKE
Khoa HUYNH
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to PCT/US2021/041545 priority Critical patent/WO2023287407A1/fr
Publication of WO2023287407A1 publication Critical patent/WO2023287407A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification

Abstract

Un exemple de la présente invention concerne un dispositif électronique. Un dispositif électronique illustratif comprend un dispositif de mémoire volatile et un dispositif de mémoire non volatile. Le dispositif électronique illustratif comprend également un contrôleur servant à écrire une partie d'instructions d'initialisation pour un composant matériel du dispositif électronique à partir du dispositif de mémoire non volatile jusqu'au dispositif de mémoire volatile par l'intermédiaire d'un accès direct à la mémoire. Le dispositif électronique illustratif comprend également un système d'entrée/sortie de base (BIOS) pour initialiser le composant matériel du dispositif électronique en fonction de la partie des instructions d'initialisation écrites dans le dispositif de mémoire volatile.
PCT/US2021/041545 2021-07-14 2021-07-14 Initialisation de composant matériel WO2023287407A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2021/041545 WO2023287407A1 (fr) 2021-07-14 2021-07-14 Initialisation de composant matériel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2021/041545 WO2023287407A1 (fr) 2021-07-14 2021-07-14 Initialisation de composant matériel

Publications (1)

Publication Number Publication Date
WO2023287407A1 true WO2023287407A1 (fr) 2023-01-19

Family

ID=84920348

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2021/041545 WO2023287407A1 (fr) 2021-07-14 2021-07-14 Initialisation de composant matériel

Country Status (1)

Country Link
WO (1) WO2023287407A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230051446A1 (en) * 2020-01-30 2023-02-16 Dell Products L.P. Computing system initialization system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070216696A1 (en) * 2006-03-16 2007-09-20 Toshiba (Australia) Pty. Limited System and method for document rendering employing bit-band instructions
US20090091564A1 (en) * 2007-10-03 2009-04-09 Raju Thevan System and method for rendering electronic documents having overlapping primitives
US20130138873A1 (en) * 2001-09-28 2013-05-30 Micron Technology, Inc. Memory systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130138873A1 (en) * 2001-09-28 2013-05-30 Micron Technology, Inc. Memory systems
US20140244913A1 (en) * 2001-09-28 2014-08-28 Micron Technology, Inc. Memory systems
US20070216696A1 (en) * 2006-03-16 2007-09-20 Toshiba (Australia) Pty. Limited System and method for document rendering employing bit-band instructions
US20090091564A1 (en) * 2007-10-03 2009-04-09 Raju Thevan System and method for rendering electronic documents having overlapping primitives

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230051446A1 (en) * 2020-01-30 2023-02-16 Dell Products L.P. Computing system initialization system
US11675680B2 (en) * 2020-01-30 2023-06-13 Dell Products L.P. Computing system initialization system

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