WO2023283891A1

WO2023283891A1 - Simulation method, apparatus, and device

Info

Publication number: WO2023283891A1
Application number: PCT/CN2021/106565
Authority: WO
Inventors: 张炜铭; 黄宇; 张印; 王乃行; 丁晓天
Original assignee: 华为技术有限公司
Priority date: 2021-07-15
Filing date: 2021-07-15
Publication date: 2023-01-19
Also published as: CN117377961A

Abstract

The present disclosure relates to a logic circuit simulation method and device. The method comprises dividing a logic circuit into different levels depending on the type of logic gates, a first-level circuit comprising sequential logic gates, raw inputs, and raw outputs, a second level circuit comprising combinational logic gates; calculating logic values of clock ports of the sequential logic gates in an event-driven manner to determine whether the sequential logic gates are triggered, and then traversing, by means of hard coding, output logic values of all logic gates comprising the sequential logic gates and combinational logic gates. Because the state of the sequential logic gates at each time frame has been determined before traversing by means of hard coding, it is unnecessary to repeatedly calculate the logic output of the logic circuit by means of hard coding, thereby greatly saving computing resources and shortening simulation time.

Description

Method, device and equipment for simulation

technical field

The present disclosure relates to the field of electronics, and more particularly to methods, apparatus and apparatus for simulation of integrated circuits.

Background technique

A variety of electronic design automation (EDA) tools have been developed to complete the functional design, synthesis, verification, and physical design (including layout, wiring, layout, and design) of very large scale integration (VLSI) chips. rule checking, etc.) and other design processes. In the design process of integrated circuits such as digital integrated circuits, an important stage is the simulation of logic circuits, which can verify the correctness of circuit design before tape-out. The simulation of logic circuit usually includes two stages of logic simulation and fault simulation. In logic simulation, the simulation device reads the netlist file and receives test vectors, and generates logic simulation results after performing logic operations. In fault simulation, the simulation device receives a set of fault vectors and uses the logic simulation results generated by the logic simulation as a background to determine which faults can be detected.

Conventional logic simulation includes, for example, hard-coded-based logic simulation and event-driven technology-based logic simulation. The fault simulation takes the simulation results of the logic simulation as the background. Conventional fault simulation includes, for example, fault simulation based on single fault vector parallel simulation technology (PPSFP) and fault simulation based on Hope technology. Integrated circuits usually include tens of thousands of logic gates, and conventional logic simulation or fault simulation consumes a considerable amount of simulation time.

Contents of the invention

In view of the above problems, the embodiments of the present disclosure aim to provide a simulation method, storage medium, program product and electronic device, which are used for logic simulation and/or fault simulation of digital circuits.

According to a first aspect of the present disclosure, a method for simulation is provided. The method includes staging the logic circuit to determine a first level circuit comprising a plurality of sequential logic gates and a plurality of primitive inputs and a second level circuit comprising a plurality of combinational logic gates. The method further includes determining a set of clock logic values of clock input ports of the plurality of sequential logic gates of the first level circuit in the plurality of time frames based on the time frame data representing the plurality of time frames and the original clock input set. The method further includes determining a set of logic simulation outputs based on the set of clocked logic values and the set of raw data inputs. The logic simulation output set includes: the output logic values of the output ports of the multiple sequential logic gates in the first-level circuit in multiple time frames, and the output ports of the multiple combinational logic gates in the second-level circuit in multiple time frames Output logical value in frame. Since logic gates in a logic circuit are classified by type, the data of logic gates of the same type are thus largely located in adjacent or close storage areas, eg in adjacent or close areas in a memory. When the processor reads the data of one or some logic gates from the memory into the cache, due to the spatial locality design principle of the cache, the data of adjacent or nearby logic gates will be read into the cache together . After the data of adjacent or similar logic gates are read into the cache, when the processor calculates the logic value of the next logic gate after calculating the logic value of the current logic gate, due to the correlation of the next logic gate Data has already been read into the cache, so memory accesses do not need to be re-addressed. In this way, the number of cache memory accesses can be greatly reduced, thus saving a lot of simulation time. On the other hand, in some embodiments, since the trigger states of the sequential logic gates have been determined, each logic gate (including sequential logic gates and combinational logic gates) is traversed in a hard-coded manner to calculate each logic gate When outputting logic values of , there is no need to repeatedly traverse all logic gates as in conventional hard-coded logic simulation. This can further significantly reduce logic simulation time for logic circuits.

In a possible implementation manner of the first aspect, classifying the logic circuit to determine the first-level circuit and the second-level circuit includes: classifying the logic circuit to determine the first-level circuit, the first sub-level circuit, and the second-level circuit Two sub-level circuits. The first level of subcircuits includes combinational logic gates of the plurality of combinational logic gates in the second level of circuitry that are directly coupled to the first level of circuitry. The second sub-circuit level includes combinational logic gates of the plurality of combinational logic gates in the second level circuit that are directly coupled to the first sub-circuit level. The accuracy and efficiency of logic simulation can be improved by further dividing the second-level circuit according to the connection relationship of combinational logic gates.

In a possible implementation manner of the first aspect, the method further includes receiving simulation period data; and determining time frame data based on the simulation period data.

In a possible implementation of the first aspect, based on the time frame data representing the multiple time frames and the original clock input set, the clock input ports of the multiple sequential logic gates of the first-level circuit in the multiple time frames are determined The clock logic value set includes: adding the original clock input port in multiple time frames to the event queue; adding the combinational logic gate between the original clock input port and multiple sequential logic gates to the event queue; computing (compute) the combinational logic gate outputting logic values; and determining clock logic value sets of clock ports of the plurality of sequential logic gates in the first level circuit in a plurality of time frames based on the output logic values of the combinational logic gates. Since the sequential logic gates generally only occupy a relatively small proportion in a logic circuit, the clock ports of the sequential logic gates to be calculated are correspondingly less. Even when calculated in an event-driven manner, this generally has little impact on logic simulation time. Furthermore, since the logic circuit is staged and there are no other sequential logic gates between the original clock input port and the sequential logic gate, the logic value of the clock port can be directly determined. After the clock logic values of the clock ports of all sequential logic gates in the first-level circuit in each time frame are calculated in an event-driven manner, multiple times indicated by the time frame data of the clock input ports of the sequential logic gate can be obtained Set of clock logic values in a frame. By using a set of clocked logic values, the output logic values of sequential logic gates can be made deterministic, and thus the time for logic simulation is further significantly reduced as described above.

In a possible implementation manner of the first aspect, determining the logic simulation output set based on the clock logic value set and the original data input set includes using the clock logic value set and the original data input set to sequentially determine the first level according to the order of the level circuits The plurality of output logic values of the plurality of logic gates in the circuit and the second level circuit, the logic simulation output set includes the plurality of output logic values. By sequentially determining the output logic values of the logic gates, the simulation time can be further reduced and the simulation accuracy can be improved.

In a possible implementation manner of the first aspect, classifying the logic circuits to determine the first-level circuits and the second-level circuits includes storing data of the first-level circuits in the first area of the memory according to the levels of the logic circuits, and Data for the second level of circuitry is stored in a second area of the memory, the second area being different from the first area. By partitioning and storing the first-level circuits and the second-level circuits, adjacent logic gates are basically located in adjacent positions, which can significantly increase the use probability of spatial locality and further reduce the simulation time.

In a possible implementation of the first aspect, the method further includes receiving a logic simulation output set and a fault input set for the logic circuit; at least based on the logic simulation output set, determining in the logic circuit in multiple time frames a plurality of transfer logic gates that may pass signals; and determining a set of fault simulation outputs based at least on the determined plurality of transfer logic gates and the set of fault inputs. By determining the number of transmitting logic gates that can pass the signal in various time frames, it is possible to calculate the output value of only the logic gates in the transmission path of the passable fault signal, but not the output value of the logic gate in the path of the non-transferable signal . This significantly reduces the calculation load of fault simulation and greatly saves the time of fault simulation.

In a possible implementation manner of the first aspect, at least based on the logic simulation output set, determining a plurality of transmission logic gates in the logic circuit that can transmit signals in multiple time frames includes: based on the logic simulation output set, according to time Frame determines whether the sequential logic gates in the logic circuit are correspondingly triggered in at least one time frame in the plurality of time frames; and in response to the first group of sequential logic gates in the logic circuit being triggered in at least one time frame, will The combinational logic gates associated with the inputs of the first set of sequential logic gates and the first set of sequential logic gates are defined as a plurality of transfer logic gates. By determining that a sequential logic gate is triggered in a time frame, it can be determined in an easy manner whether the sequential logic gate is a transmission logic gate. This can further reduce the time of fault simulation and improve the efficiency of fault simulation.

In a possible implementation manner of the first aspect, determining whether each sequential logic gate in the logic circuit is correspondingly triggered in multiple time frames based on the logic simulation output set includes: based on the logic simulation output set, and each timing The clock logic values corresponding to the clock ports of the logic gate determine whether each sequential logic gate in the logic circuit is triggered in multiple time frames.

In a possible implementation manner of the first aspect, determining the failure simulation output set based at least on the determined plurality of transmission logic gates and failure input sets includes: determining whether the logic gate to be calculated is a transmission logic gate; and in response to determining The logic gate to be calculated is a transfer logic gate, and the logic value derived from the fault input set is used to determine the fault output logic value of the logic gate to be computed, and the fault simulation output set includes the fault output logic value. By determining the transmission logic gate and calculating the corresponding fault output logic value, the calculation amount of fault simulation can be reduced, and the time of fault simulation can be reduced.

In a possible implementation manner of the first aspect, determining at least based on the logic simulation output set a plurality of transmission logic gates in the logic circuit that can transmit signals in multiple time frames includes: based on the logic simulation output set and the fault input set, determine whether the original fault input corresponding to the fault input port in the logic circuit in the fault input set is excited; A plurality of transmission logic gates that may pass signals in multiple time frames among the logic gates associated with the fault input port. By determining whether to be activated, the observable transmission logic gates can be traced back, so that the observable logic gates can be determined in a simple manner to reduce the calculation amount of fault simulation and correspondingly reduce the simulation time.

In a possible implementation manner of the first aspect, at least based on the logic simulation output set, determining the multiple transmission logic gates in the logic circuit that can transmit signals in multiple time frames includes: at least based on the logic simulation output set, Multiple transmit logic gates in a logic circuit that can transmit signals in multiple time frames are determined in parallel in a multi-threaded manner. Since the data of each logic gate is not modified during the process of determining the transmission logic gate, the data of each logic gate can be simultaneously accessed by multiple threads. The fault simulation time can be further reduced by using multi-threaded fault mode.

According to a second aspect of the present disclosure, there is provided a computer-readable storage medium storing a plurality of programs. A plurality of programs are configured to be executed by the one or more processors, the plurality of programs including instructions for performing the method according to the first aspect.

According to a third aspect of the present disclosure, a computer program product is provided. The computer program product comprises a plurality of programs configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method according to the first aspect.

According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device comprises one or more processors; a memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method according to the first aspect.

According to a fifth aspect of the present disclosure, an electronic device is provided. The electronic device includes a logic circuit classification unit for classifying the logic circuit to determine a first-level circuit and a second-level circuit, the first-level circuit includes a plurality of sequential logic gates and a plurality of original inputs, and the second-level circuit includes a plurality of a combinational logic gate; a clock logic value determining unit, configured to determine the clock input ports of the multiple sequential logic gates of the first-level circuit in multiple time frames based on the time frame data representing multiple time frames and the original clock input set The clock logic value set; and a logic simulation output set determining unit, configured to determine a logic simulation output set based on the clock logic value set and the original data input set. The logic simulation output set includes: the output logic values of the output ports of the multiple sequential logic gates in the first-level circuit in multiple time frames, and the output ports of the multiple combinational logic gates in the second-level circuit in multiple time frames Output logical value in frame. Since logic gates in a logic circuit are classified by type, the data of logic gates of the same type are thus largely located in adjacent or close storage areas, for example in adjacent or close areas in a memory. When the processor reads the data of one or some logic gates from the memory into the cache, due to the spatial locality design principle of the cache, the data of adjacent or nearby logic gates will be read into the cache together . After the data of adjacent or similar logic gates are read into the cache, when the processor calculates the logic value of the next logic gate after calculating the logic value of the current logic gate, due to the correlation of the next logic gate Data has already been read into the cache, so memory accesses do not need to be re-addressed. In this way, the number of cache memory accesses can be greatly reduced, thus saving a lot of simulation time. On the other hand, in some embodiments, since the trigger states of the sequential logic gates have been determined, each logic gate (including sequential logic gates and combinational logic gates) is traversed in a hard-coded manner to calculate each logic gate When outputting logic values of , there is no need to repeatedly traverse all logic gates as in conventional hard-coded logic simulation. This can further significantly reduce logic simulation time for logic circuits.

In a possible implementation manner of the fifth aspect, the logic circuit classification unit is further configured to classify the logic circuit to determine a first-level circuit, a first sub-level circuit, and a second sub-level circuit, and the first sub-circuit level includes The combinational logic gates of the plurality of combinational logic gates in the second level circuit that are directly coupled to the first level circuit, and the second sub-circuit level includes the combinational logic gates of the plurality of combinational logic gates in the second level circuit that are directly coupled to the first level circuit. Directly coupled combinational logic gates at the subcircuit level. The accuracy and efficiency of logic simulation can be improved by further dividing the second-level circuit according to the connection relationship of combinational logic gates.

In a possible implementation of the fifth aspect, the clock logic value determination unit is further used to add the original clock input ports in multiple time frames to the event queue; The combinational logic gate is added to the event queue; the output logic value of the combinational logic gate is calculated; and the clock logic value of the clock port of the plurality of sequential logic gates in the first-level circuit in multiple time frames is determined based on the output logic value of the combinational logic gate set. Since the sequential logic gates generally only occupy a relatively small proportion in a logic circuit, the clock ports of the sequential logic gates to be calculated are correspondingly less. Even when calculated in an event-driven manner, this generally has little impact on logic simulation time. Furthermore, since the logic circuit is staged and there are no other sequential logic gates between the original clock input port and the sequential logic gate, the logic value of the clock port can be directly determined. After the clock logic values of the clock ports of all sequential logic gates in the first-level circuit in each time frame are calculated in an event-driven manner, multiple times indicated by the time frame data of the clock input ports of the sequential logic gate can be obtained Set of clock logic values in a frame. By using a set of clocked logic values, the output logic values of sequential logic gates can be made deterministic, and thus the time for logic simulation is further significantly reduced as described above.

In a possible implementation of the fifth aspect, the logic simulation output set determining unit is further used to use the clock logic value set and the original data input set to sequentially determine the first-level circuits and the second-level circuits according to the order of the level circuits. The plurality of output logic values of the plurality of logic gates, the logic simulation output set includes the plurality of output logic values. By sequentially determining the output logic values of the logic gates, the simulation time can be further reduced and the simulation accuracy can be improved.

In a possible implementation manner of the fifth aspect, the logic circuit grading unit is further configured to store the data of the first-level circuits in the first area of the memory and store the data of the second-level circuits in the memory according to the levels of the logic circuits The second area of , the second area is different from the first area. By partitioning and storing the first-level circuits and the second-level circuits, adjacent logic gates are basically located in adjacent positions, which can significantly increase the use probability of spatial locality and further reduce the simulation time.

In a possible implementation manner of the fifth aspect, the electronic device further includes: a receiving unit, configured to receive a logic simulation output set and a fault input set for a logic circuit; a transmission logic gate determination unit, configured to at least based on the logic simulation output a plurality of transmission logic gates in the set determination logic circuit capable of transmitting signals in a plurality of time frames; and a failure simulation output set determination unit for determining a failure simulation based at least on the determined plurality of transmission logic gates and failure input sets output set. By determining the number of transmitting logic gates that can pass the signal in various time frames, it is possible to calculate the output value of only the logic gates in the transmission path of the passable fault signal, but not the output value of the logic gate in the path of the non-transferable signal . This significantly reduces the calculation load of fault simulation and greatly saves the time of fault simulation.

In a possible implementation manner of the fifth aspect, the transmission logic gate determination unit is further configured to determine, based on the logic simulation output set, the sequential logic gate in the logic circuit in at least one of the multiple time frames according to the time frame is triggered accordingly; and in response to the first set of sequential logic gates in the logic circuit being triggered in at least one time frame, combining the combinational logic gates associated with the inputs of the first set of sequential logic gates and the first set of sequential logic gates identified as multiple transfer logic gates. By determining that a sequential logic gate is triggered in a time frame, it can be determined in an easy manner whether the sequential logic gate is a transmission logic gate. This can further reduce the time of fault simulation and improve the efficiency of fault simulation.

In a possible implementation of the fifth aspect, the transmission logic gate determination unit is further configured to determine each timing in the logic circuit based on the clock logic values in the logic simulation output set that correspond to the clock ports of each sequential logic gate. Whether the logic gate is triggered in multiple timeframes.

In a possible implementation manner of the fifth aspect, the transfer logic gate determining unit is further configured to determine whether the logic gate to be calculated is a transfer logic gate; and in response to determining that the logic gate to be calculated is a transfer logic gate, using the source from The logic value of the fault input set is used to determine the fault output logic value of the logic gate to be calculated, and the fault simulation output set includes the fault output logic value. By determining the transmission logic gate and calculating the corresponding fault output logic value, the calculation amount of fault simulation can be reduced, and the time of fault simulation can be reduced.

In a possible implementation of the fifth aspect, the transfer logic gate determination unit is further configured to determine the original fault in the fault input set corresponding to the fault input port in the logic circuit based on the logic simulation output set and the fault input set whether the input is activated; and in response to the original fault input being activated at the fault input port, based on the set of logic simulation outputs, determining how many of the logic gates in the logic circuit that are associated with the fault input port can transmit signals in the plurality of time frames transmission logic gates. By determining whether to be activated, the observable transmission logic gates can be traced back, so that the observable logic gates can be determined in a simple manner to reduce the calculation amount of fault simulation and correspondingly reduce the simulation time.

In a possible implementation manner of the fifth aspect, the transmission logic gate determination unit is further configured to determine in parallel in a multi-threaded manner the transferable signals in the logic circuit in multiple time frames based on at least the logic simulation output set multiple transfer logic gates. Since the data of each logic gate is not modified during the process of determining the transmission logic gate, the data of each logic gate can be simultaneously accessed by multiple threads. The fault simulation time can be further reduced by using multi-threaded fault mode.

According to a sixth aspect of the present disclosure, a method for simulation is provided. The method includes receiving a set of logic simulation outputs and a set of fault inputs for a logic circuit; determining, based at least on the set of logic simulation outputs, a plurality of transmission logic gates in the logic circuit that can transmit signals in a plurality of time frames; and based at least on the set of logic simulation outputs; The determined plurality of transmission logic gates and fault input sets determine the fault simulation output set. By determining the number of transmitting logic gates that can pass the signal in various time frames, it is possible to calculate the output value of only the logic gates in the transmission path of the passable fault signal, but not the output value of the logic gate in the path of the non-transferable signal . This significantly reduces the calculation load of fault simulation and greatly saves the time of fault simulation.

In a possible implementation manner, at least based on the logic simulation output set, determining the multiple transmission logic gates in the logic circuit that can transmit signals in multiple time frames includes: based on the logic simulation output set, determining the logic circuit according to the time frame whether the sequential logic gates in the logic circuit are correspondingly triggered in at least one of the plurality of time frames; and in response to the first group of sequential logic gates in the logic circuit being triggered in at least one time frame, will The combinational logic gates associated with the inputs of the sequential logic gates and the first group of sequential logic gates are determined as a plurality of transfer logic gates. By determining that a sequential logic gate is triggered in a time frame, it can be determined in an easy manner whether the sequential logic gate is a transmission logic gate. This can further reduce the time of fault simulation and improve the efficiency of fault simulation.

In a possible implementation manner, determining whether each sequential logic gate in the logic circuit is correspondingly triggered in multiple time frames based on the logic simulation output set includes: based on the logic simulation output set and the clock of each sequential logic gate The clock logic values corresponding to the ports respectively determine whether each sequential logic gate in the logic circuit is triggered in multiple time frames.

In a possible implementation manner, determining the fault simulation output set based at least on the determined plurality of transmission logic gates and the fault input set includes: determining whether the logic gate to be calculated is a transmission logic gate; and determining the logic gate to be calculated in response to The gates are transmission logic gates, and a fault output logic value of the logic gate to be calculated is determined using a logic value derived from a fault input set, the fault simulation output set including the fault output logic value. By determining the transmission logic gate and calculating the corresponding fault output logic value, the calculation amount of fault simulation can be reduced, and the time of fault simulation can be reduced.

In a possible implementation manner, at least based on the logic simulation output set, determining a plurality of transmission logic gates in the logic circuit that can transmit signals in multiple time frames includes: based on the logic simulation output set and the fault input set, determining the fault Whether the original fault input corresponding to the fault input port in the logic circuit in the input set is excited; and in response to the original fault input being excited at the fault input port, based on the logic simulation output set, determine the relationship between the fault input port in the logic circuit Multiple transmission logic gates in a logic gate that can pass signals in multiple time frames. By determining whether to be activated, the observable transmission logic gates can be traced back, so that the observable logic gates can be determined in a simple manner to reduce the calculation amount of fault simulation and correspondingly reduce the simulation time.

In a possible implementation manner, at least based on the logic simulation output set, determining a plurality of transmission logic gates in the logic circuit that can transmit signals in multiple time frames includes: at least based on the logic simulation output set, using a multi-threaded The method determines in parallel multiple transmission logic gates in a logic circuit that can transmit signals in multiple time frames. Since the data of each logic gate is not modified during the process of determining the transmission logic gate, the data of each logic gate can be simultaneously accessed by multiple threads. The fault simulation time can be further reduced by using multi-threaded fault mode.

According to a seventh aspect of the present disclosure, there is provided a computer-readable storage medium storing a plurality of programs. A plurality of programs are configured to be executed by the one or more processors, the plurality of programs including instructions for performing the method according to the seventh aspect.

According to an eighth aspect of the present disclosure, a computer program product is provided. The computer program product comprises a plurality of programs configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method according to the seventh aspect.

According to a ninth aspect of the present disclosure, there is provided an electronic device. The electronic device comprises: one or more processors; a memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method according to the seventh aspect.

According to a tenth aspect of the present disclosure, an electronic device is provided. The electronic device includes: a receiving unit, configured to receive a logic simulation output set and a fault input set for the logic circuit; a transmission logic gate determination unit, configured to determine the logic circuit in multiple time frames based on at least the logic simulation output set. a plurality of transmission logic gates transmitting signals; and a failure simulation output set determining unit for determining a failure simulation output set based at least on the determined plurality of transmission logic gates and the failure input set. By determining the number of transmitting logic gates that can pass the signal in various time frames, it is possible to calculate the output value of only the logic gates in the transmission path of the passable fault signal, but not the output value of the logic gate in the path of the non-transferable signal . This significantly reduces the calculation load of fault simulation and greatly saves the time of fault simulation.

In a possible implementation manner of the tenth aspect, the transmission logic gate determination unit is further configured to determine, based on the logic simulation output set, the sequential logic gate in the logic circuit in at least one of the multiple time frames according to the time frame is triggered accordingly; and in response to the first set of sequential logic gates in the logic circuit being triggered in at least one time frame, combining the combinational logic gates associated with the inputs of the first set of sequential logic gates and the first set of sequential logic gates identified as multiple transfer logic gates. By determining that a sequential logic gate is triggered in a time frame, it can be determined in an easy manner whether the sequential logic gate is a transmission logic gate. This can further reduce the time of fault simulation and improve the efficiency of fault simulation.

In a possible implementation of the tenth aspect, the transmission logic gate determination unit is further configured to determine each timing in the logic circuit based on the clock logic values in the logic simulation output set corresponding to the clock ports of each sequential logic gate. Whether the logic gate is triggered in multiple timeframes.

In a possible implementation manner of the tenth aspect, the transfer logic gate determination unit is further configured to determine whether the logic gate to be calculated is a transfer logic gate; and in response to determining that the logic gate to be calculated is a transfer logic gate, using the source from The logic value of the fault input set is used to determine the fault output logic value of the logic gate to be calculated, and the fault simulation output set includes the fault output logic value. By determining the transmission logic gate and calculating the corresponding fault output logic value, the calculation amount of fault simulation can be reduced, and the time of fault simulation can be reduced.

In a possible implementation of the tenth aspect, the transmission logic gate determination unit is further configured to determine the original fault in the fault input set corresponding to the fault input port in the logic circuit based on the logic simulation output set and the fault input set whether the input is activated; and in response to the original fault input being activated at the fault input port, based on the set of logic simulation outputs, determining how many of the logic gates in the logic circuit that are associated with the fault input port can transmit signals in the plurality of time frames transmission logic gates. By determining whether to be activated, the observable transmission logic gates can be traced back, so that the observable logic gates can be determined in a simple manner to reduce the calculation amount of fault simulation and correspondingly reduce the simulation time.

In a possible implementation manner of the tenth aspect, the transmission logic gate determination unit is further configured to determine in parallel in a multi-threaded manner the transferable signals in the logic circuit in multiple time frames based on at least the logic simulation output set multiple transfer logic gates. Since the data of each logic gate is not modified during the process of determining the transmission logic gate, the data of each logic gate can be simultaneously accessed by multiple threads. The fault simulation time can be further reduced by using multi-threaded fault mode.

It should be understood that what is described in the Summary of the Invention is not intended to limit the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, identical or similar reference numerals denote identical or similar elements, wherein:

FIG. 1 shows a schematic diagram of a logic circuit simulation system 100 according to some embodiments of the present disclosure.

FIG. 2 shows a schematic block diagram of a simulation process of a logic circuit according to some embodiments of the present disclosure.

FIG. 3 shows an example circuit diagram of an illustrative logic circuit according to some embodiments of the present disclosure.

FIG. 4 shows a hierarchical schematic diagram of the logic circuit in FIG. 3 .

FIG. 5 shows a schematic diagram of the logic circuit in FIG. 3 expanded in time frames.

Fig. 6 shows a schematic flowchart of a simulation method according to some embodiments of the present disclosure.

Fig. 7 shows a schematic flowchart of a simulation method according to some embodiments of the present disclosure.

FIG. 8 shows a schematic diagram of a logic circuit with logic simulation background values according to some embodiments of the present disclosure.

FIG. 9 shows a schematic diagram of a logic circuit with transferable flags according to some embodiments of the present disclosure.

FIG. 10 shows a schematic diagram of a logic circuit for describing fault excitation according to some embodiments of the present disclosure.

Fig. 11 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure.

Fig. 12 shows a schematic block diagram of an electronic device according to other embodiments of the present disclosure.

Figure 13 shows a block diagram of an example device that may be used to implement some embodiments of the present disclosure.

detailed description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.

It should be understood that for the technical solutions provided by the embodiments of the present application, in the introduction of the following specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have been referred to each other and can be combined with each other.

As mentioned above, conventional logic simulation or fault simulation both consume considerable simulation time. For example, in a conventional hard-coded logic simulation, the hard-coded logical values of each logic gate in the computational logic circuit are sequentially traversed from the original input. However, some sequential logic gates are usually included in the logic circuit, and the calculation of the logical value of the sequential logic gate does not only depend on the original input or the output of the combinational logic gate coupled with the sequential logic gate, but also depends on the state of the sequential logic gate, such as the sequential logic The clock input of the clock port of the gate and the connection relationship between the sequential logic gates. Therefore, hard coding cannot obtain a complete and accurate logic value at one time, but repeatedly calculates the logic values of all the logic gates of the logic circuit for multiple states of the sequential logic gates in the logic circuit. This consumes a lot of computing resources and computing time.

In conventional event-driven logic simulation, breadth-first logic simulation is usually performed from raw input. Since the data of each logic gate of the logic circuit is not stored in the memory in a breadth-first search manner when the processor reads the netlist file describing the logic circuit, the cache of the processor needs to frequently access different locations of the memory to obtain data for each logic gate. This consumes a lot of access time. As used herein, "sequential logic gate" means a logic gate with a clocked input. The output of a sequential logic gate at any moment not only depends on the input signal at that time, but also depends on the clock signal and the original state of the sequential logic gate, in other words, it can also be related to the previous input. Sequential logic gates include, for example, flip-flops, registers, and latches. In contrast, "combinational logic gate" means a logic gate that does not have a clocked input. The output of a combinational logic gate at any moment depends only on the input at that moment, and has nothing to do with the original state of the combinational logic gate. Combination logic gates include, for example, AND gates, OR gates, NAND gates, XOR gates, NOT gates, and buffers. In logic circuits, usually sequential logic gates only account for a small proportion, while most of the logic gates in logic circuits are combinational logic gates.

In some embodiments of the present disclosure, after reading the netlist file, the processor classifies the logic gates in the logic circuit described in the netlist file according to the types of logic gates, so as to classify the sequential logic gates, original input ports and original The output ports are placed into the first level of circuitry, and the combinational logic gates are placed into the second level of circuitry. Further, the data of the logic gates in the logic circuit can be stored in the memory according to the hierarchical levels. For example, data for logic gates in various levels of circuitry may be stored in adjacent or nearby locations in memory. The processor can access the memory by addressing to obtain the data of the logic gate to be calculated.

The processor uses the ATPG data from the automatic test pattern generation (ATPG) device, specifically, the raw clock input for the clock port of each sequential logic gate in the ATPG data, to determine the clock port of the sequential logic gate Logical value in each timeframe. By calculating the logic value of the clock port of the sequential logic gate, the state of each sequential logic gate in multiple time frames can be determined, for example, whether it is triggered or not. Herein, "triggered" means that the sequential logic gate is turned on to output a logic output at the output port of the sequential logic gate depending on the input of the sequential logic gate and the previous state of the sequential logic gate. When the sequential logic gate is not triggered, the sequential logic gate maintains (stores) the current logic output regardless of the logic input of the sequential logic gate. By determining the triggered sequential logic gate, the logic output of the sequential logic gate and the logic output of the combinational logic gate can be correctly calculated, thereby realizing logic simulation.

In some embodiments of the present disclosure, since the logic gates in the logic circuit are classified by type, the data of the logic gates of the same type are largely located in adjacent or close storage areas, for example, in adjacent or close storage areas in the memory. nearby area. When the processor reads the data of one or some logic gates from the memory into the cache (cache), due to the space locality design principle of the cache, the data of adjacent or nearby multiple logic gates will be read into the cache together. After the data of adjacent or similar logic gates are read into the cache, when the processor calculates the logic value of the next logic gate after calculating the logic value of the current logic gate, due to the correlation of the next logic gate Data has already been read into the cache, so memory accesses do not need to be re-addressed. In this way, the number of cache memory accesses can be greatly reduced, thus saving a lot of simulation time. On the other hand, in some embodiments, since the trigger states of the sequential logic gates have been determined, each logic gate (including sequential logic gates and combinational logic gates) is traversed in a hard-coded manner to calculate each logic gate When outputting logic values of , there is no need to repeatedly traverse all logic gates as in conventional hard-coded logic simulation. This can further significantly reduce logic simulation time for logic circuits.

In some embodiments of the present disclosure, the processor first calculates the logic value of the clock port of the sequential logic gate in an event-driven manner, and then calculates the logic output of the sequential logic gate and the combinational logic gate in a hard-coded manner. Since sequential logic gates usually represent only a small fraction of the number of logic gates in a logic circuit, even computing the logic value of the clock port of a sequential logic gate in an event-driven manner does not cause the cache to be always high during logic simulation Frequent access to memory, which can reduce the time of logic simulation. In addition, when the processor calculates the logic output of the sequential logic gate and the combinational logic gate, since the logic output of the sequential logic gate and the combinational logic gate is calculated sequentially in the manner of a hierarchical circuit, and the state of the sequential logic gate passes through the logic of the previous clock port The output calculations are already determined, so there is no need to recalculate all logic values for all logic gates multiple times. This further reduces logic simulation time.

FIG. 1 shows a schematic diagram of a logic circuit simulation system 100 according to some embodiments of the present disclosure. In one embodiment, the simulation system 100 includes, for example, an electronic device 10 and an ATPG device 20 . In one embodiment, the electronic device 10 is, for example, a computer. Electronic device 10 includes processor 14 and memory 12 , wherein processor 14 includes cache memory 16 . Alternatively, in some embodiments, the cache memory 16 may also be independent of the processor 14, and the scope of the present disclosure is not limited thereto. The ATPG device 20 is configured to generate ATPG data for logic simulation and transmit the ATPG data to the electronic device 10 . Although the electronic device 10 and the ATPG device 20 are limited independently in FIG. 1 , in some embodiments, the ATPG device 20 may be integrated with the electronic device 10 , which is not limited by the present disclosure. The electronic device 10 may include input devices, communication devices, displays, audio devices and other components not shown here. The electronic device 10 may include, for example, devices with computing functions such as desktop computers, notebooks, workstations, and servers. The netlist file used to describe the logic circuit can be transmitted to the electronic device 10 in various wired or wireless ways. Alternatively, the electronic device 10 may also use a storage medium storing the netlist file to read the netlist file. The ATPG device 20 can generate different ATPG data for different logic circuits. In one embodiment, the ATPG data includes, for example, simulation cycle data, raw data input, fault simulation data, and the like. Simulation cycle data includes, for example, tick data, ie, data representing a time frame in which a processor is executed for logic simulation and/or fault simulation. The time frames of logic simulation and fault simulation may be the same or different, which is not limited in the present disclosure. The original input includes, for example, the original data input for each original data input port in the logic circuit in the logic simulation and the original clock input corresponding to the original clock port used to calculate the logic value of the clock port of the sequential logic gate. Since a time frame is usually multiple time frames, the raw data input for a single raw data input port may be a raw data input set for the multiple time frames, which includes a series of bit values, eg 64-bit bit values. It will be appreciated that, depending on the time frame, there may be more or fewer bit values, eg 32 or 128 bit values. The fault simulation data includes, for example, fault data inputs for fault data inputs. Similarly, since time frames in fault simulation are usually multiple time frames, the raw fault data input for a single fault input can be a fault input set that includes a series of bit values for the multiple time frames, e.g. 64-bit bit value. There can be more or fewer bit values.

FIG. 2 shows a schematic diagram of a simulation process 200 according to some embodiments of the present disclosure. In one embodiment, the simulation process 200 is executed by the electronic device 10 in FIG. 1 , so the content described for the electronic device 10 can be applied to the simulation process 200 . The simulation process may include logic simulation 210 and fault simulation 220 , for example. The logic simulation 210 uses the ATPG data 202 from the ATPG device 20 and the netlist file 204 obtained through wireless, wired or reading storage media. The netlist file 204 includes data for describing various logic gates (including sequential logic gates and combinational logic gates), original inputs, original outputs, and coupling relationships among various components in the logic circuit. Electronic device 10 may perform logic simulation 210 to generate a set of logic simulation outputs. The specific process of the logic simulation 210 can be referred to below. This set of logic simulation outputs can be used in fault simulation 220 . Fault simulation 220 uses a set of fault inputs 222 from ATPG device 20 in addition to the set of logic simulation outputs. Fault simulation 220 has a set of fault inputs 222 and a set of logic simulation outputs to generate a set of fault simulation outputs 224 . Alternatively, fault simulation 220 may also use a set of logic simulation outputs and a set of fault inputs 222 independent of logic simulation 210 to generate set of fault simulation outputs 224 . Fault simulation 220 may also generate test vectors for automatic test equipment (ATE). After generating set of fault simulation outputs 224 , electronic device 10 may generate fault coverage include 228 based on set of fault simulation outputs 224 and expected fault outcomes. The specific process of fault simulation 220 can be referred to below.

FIG. 3 shows an example circuit diagram of an illustrative logic circuit 30 according to some embodiments of the present disclosure. The logic circuit 30 is only used to illustrate the principle of the present disclosure, but not to limit the scope of the present disclosure. It is understood that other configurations of logic circuits are also possible. The logic circuit 30 may include, for example, a first original data input PI1, an AND gate 31, a first flip-flop U1, a second original data input PI2, an inverter 32, a second flip-flop U2, a first buffer 33, a second buffer device 34 and the original output PO. The input of the AND gate 31 is coupled to the first raw data input PI1 and the output of the first flip-flop U1. The clock port C1 of the first flip-flop U1 is configured to receive the first clock signal, the reset terminal of the first flip-flop U1 is coupled to the output of the second buffer 34 , and the output of the first flip-flop U1 is coupled to the original output PO. The input of the inverter 32 is coupled to the second raw data input PI2, and the output of the inverter 32 is coupled to the input of the second flip-flop U2. The clock port C2 of the second flip-flop U2 is configured to receive the second clock signal, and the output of the second haptic U2 is coupled to the input of the first buffer 33, and the output of the first buffer 33 is coupled to the second buffer 34 inputs. The logic circuit 30 includes a first type of sequential logic gate and a second type of combinational logic gate. The first type of sequential logic gates includes a first buffer U1 and a second buffer U2 , and the second type of combinational logic gates includes an AND gate 31 , an inverter 32 , a first buffer 33 and a second buffer 34 .

FIG. 4 shows a hierarchical schematic diagram of the logic circuit in FIG. 3 . In some embodiments of the present disclosure, during the logic simulation process, the processor splits the logic circuit into two levels of circuits according to the coupling relationship of each logic gate in the logic circuit described in the netlist file, wherein the first level The circuits include sequential logic gates, primitive inputs and primitive outputs, and the second level circuits include combinational logic gates. In some other embodiments, the second-level circuits can be further classified with respect to the relationship between the combinational logic gates and the first-level circuits and the relationship between the combinational logic gates. For example, the second-level circuit includes a first sub-level circuit, a second sub-level circuit...Nth sub-level circuit, where N represents an integer greater than 1, and the specific value of N depends on the logic circuit to be simulated. In one embodiment, the first sub-level circuit includes combinational logic gates directly coupled to the first sub-level circuit, the second sub-level circuit includes combinational logic gates directly coupled to the first sub-level circuit, and so on.

In the embodiment shown in FIG. 4, the logic circuit 30 can be divided into three levels, wherein level 0 shown in FIG. 4 corresponds to the first level circuit, and level 1 corresponds to the first sublevel of the second level circuit circuit, and level 2 corresponds to the second sub-level circuit of the second level circuit. The first level circuit includes an original output PO, a first original data input PI1, a second original data input PI2, a first flip-flop U1 and a second flip-flop U2. The first sub-level circuit includes an AND gate 31 , a first buffer 33 and an inverter 32 . The second sub-level circuit includes a second buffer 34 . In some cases, the clock signal is not directly applied to the clock port of the sequential logic gate, but is applied to the clock port of the sequential logic gate of the first level circuit via one or more combinational logic gates. In this case, the second level circuit may not include combinational logic gates between the original clock input port to the clock port of the sequential logic gate.

FIG. 5 shows a schematic diagram of the logic circuit in FIG. 3 expanded in time frames. Fig. 4 shows a hierarchical diagram of a logic circuit in a time frame, but logic simulation usually does not target a single time frame, but multiple time frames to simulate logic outputs under different inputs. In addition, for sequential logic gates, usually a single logic level on the clock port does not reflect whether it is triggered, but requires multiple consecutive logic levels to determine. For example, a register requires a low (logic "0") to high (logic "1") transition on the clock port to trigger. Therefore, for logic circuits with sequential logic gates, multiple time frames are required to determine whether a trigger is present.

The clock signal is usually provided in the form of pulses and includes a series of high and low pulses such as "...10101010...", as shown in the upper part of Figure 5. In one embodiment, a segment of the clock signal of "010" can be used to Determine if a trigger exists. For example, you can select the second half of the period when the clock signal is "0" (low level) as the first "0" of the above "010" segment, and use the successive complete "1" (high level) of the clock signal as The "1" of the above "010" segment, and use the first half period of successive "0"s of the clock signal as the second "0" of the above "010" segment. Thus, one clock cycle corresponds to one cycle for determining the presence or absence of a trigger. This clock cycle consists of three logic values and thus corresponds to 3 time frames. Alternatively, a segment of the clock signal of "101" may also be used to determine whether a trigger exists.

FIG. 5 shows a time frame expansion schematic diagram of three time frames corresponding to one cycle of the logic circuit 30 . Frame 0 corresponds to the first "0" of the aforementioned "010" segment, frame 1 corresponds to the "1" of the aforementioned "010" segment, and frame 2 corresponds to the second "0" of the aforementioned "010" segment. Since the logic simulation usually includes a plurality of original input sets to determine the simulation results of the logic circuit under different inputs, for example, the logic input value for the first original data input PI1 is, for example, the first logic input set, which may include, for example, a 64-bit bit value . Therefore, M cycles may be required for simulation, where M represents an integer greater than 1, such as 64. For the frame expansion of FIG. 5 , it is necessary to expand the logic circuit 30 into 3M time frames. The expansion of the logic circuit 30 in each time frame has basically the same hierarchical form, so the description will not be repeated here.

Fig. 6 shows a schematic flowchart of a simulation method 600 according to some embodiments of the present disclosure. The simulation method 600 is used for logic simulation, for example, it can be an implementation of the logic simulation 210 in FIG. 2 , so the various aspects described above with respect to FIGS. 1-5 can be applied to the simulation method 600 , which will not be repeated here. The processor 14 may receive, for example, a netlist file describing a logic circuit via wire, wirelessly, or by reading a storage medium. The netlist file includes various data used to describe each logic gate, original input and original output, and connection relationship between various components. At 602, processor 14 may rank logic circuits based on a netlist file representing the logic circuits to determine first-level circuits and second-level circuits. The first level of circuitry includes a plurality of sequential logic gates and a plurality of primitive inputs, and the second level of circuitry includes a plurality of combinational logic gates. In one embodiment, the first level circuit is, for example, the level 0 circuit in FIG. 4 , and the second level circuit includes, for example, the level 1 circuit and the level 2 circuit in FIG. 4 . In another embodiment, the second-level circuit includes, for example, a first sub-level circuit and a second sub-level circuit, wherein the first sub-level circuit includes the level 1 circuit in FIG. 4 , and the second sub-level circuit includes the circuit in FIG. 4 2-level circuit. In one embodiment, data corresponding to a first level of circuitry is stored in an adjacent or adjacent first area of memory 12, and data corresponding to a second level of circuitry is stored in an adjacent or adjacent area of memory 12. of the second area. Furthermore, the data corresponding to the first sub-level circuit in the second level circuit is stored in the adjacent or close first sub-region in the second area, and corresponds to the first sub-level circuit in the second level circuit The data are stored in adjacent or similar second sub-areas in the second area. When the processor 14 performs addressing access to the memory 12 to obtain the data of a certain logic gate, due to the design principle of the spatial locality of the cache memory 16, the processor 14 can read the data near the data of the logic gate into the high-speed Cache16. When the processor 14 needs to process the data of the next logic gate after the data processing of the logic gate is completed, since the data of the next logic gate has been read into the cache memory 16, there is no need to address and access the memory 12 again, which saves Lots of access times.

It can be understood that limited by the physical layout of the memory 12 and the large number of logic gates, in some embodiments, when the first region or the second region cannot accommodate all the data of the corresponding hierarchical circuit, a part of the hierarchical circuit can be Data is stored elsewhere. This only increases the number of addressing accesses to the memory 12 by a small number of processors, and has no significant impact on the total time of logic simulation. By grading the logic circuit, the logic gates in the logic circuit can be stored according to the level, and the processor 14 is prevented from frequently accessing the memory 12 when processing the data of the logic gate according to the level circuit, which can significantly reduce the time of logic simulation.

As described above, the processor 14 uses the time frame data to perform logic simulations by time frame. In some embodiments, processor 14 determines the time frame data based on simulation cycle data in the automated test vector generation data. As mentioned above, since logic simulation typically provides multiple logic input values, such as 64-bit bit values, at the raw data input, multiple cycles, such as 64 cycles, are required to perform the logic simulation. Correspondingly, more time frames (for example, 64*3=192 time frames) than the number of cycles are needed to calculate the logic simulation value of the logic gate. Processor 14 receives ATPG data from ATPG device 20 . APTG data may include simulation cycle data, eg, data representing 64 test cycles. Alternatively, the APTG data may directly include multiple time frame data, for example, data representing 192 time frames. In this case, processor 14 may directly determine the data as time frame data. In an embodiment of the present disclosure, the logic values of each logic gate (including sequential logic gates and combinational logic gates) in each time frame can be sequentially calculated according to the order of the time frames, such as the logic value and output of the clock port logical value. After the time frame is calculated, the logic values of each logic gate (including sequential logic gates and combinational logic gates) in the next time frame are calculated, such as the logic value and output logic value of the clock port. Alternatively, after calculating the logic value of each level circuit in all time frames, the logic value of the next level circuit in all time frames may be calculated.

At 604, the processor 14 determines clock logic value sets of clock input ports of the plurality of sequential logic gates in the plurality of time frames based on the original clock input data set and the time frame data in the ATPG data. A logic circuit typically includes a raw clock input port for a clock port of a sequential logic gate that receives, for example, a raw clock input set from a raw data input set. In some embodiments, the logic circuit may have one or more combinational logic gates (not shown in FIG. 3 ) between the raw clock input port and the clock port of the sequential logic gate.

In one embodiment, the clock logic value of the clock port of the sequential logic gate at each time can be determined from the original clock input port in an event-driven manner. For example, in one time frame, the processor 14 adds the original data input port to the event queue, and adds the combinational logic gate between the original clock input port and multiple sequential logic gates to the event queue.

The processor 14 then sequentially calculates the output logic values of the combinatorial logic gates between the original clock input port and the multiple sequential logic gates in a first-in-first-out order. After that, the processor 14 determines a set of clock logic values of the clock ports of the plurality of sequential logic gates in the first-level circuit based on the output logic values. For example, the processor 14 judges whether the current logic gate to be calculated is a sequential logic gate. If it is not a sequential logic gate, the output logic value of the logic gate is calculated, and the logic gate of the subsequent node of the logic gate is added to the event queue. If it is a sequential logic gate, it can be determined that it has been calculated from the original clock input port to the sequential logic gate. The output logic value of each combinatorial logic gate from the next original clock input port to the clock port of the next sequential logic gate can be calculated, and then the clock logic value of the clock port of the next sequential logic gate can be determined. By analogy, until the clock logic values of the clock ports of all sequential logic gates are calculated. After the current time frame is calculated, the above process is repeated to calculate the next time frame until the clock logic values of all clock ports in all time frames are calculated to determine the clock logic value set.

Since the sequential logic gates generally only occupy a relatively small proportion in a logic circuit, the clock ports of the sequential logic gates to be calculated are correspondingly less. Even when calculated in an event-driven manner, this generally has little impact on logic simulation time. Furthermore, since the logic circuit is staged and there are no other sequential logic gates between the original clock input port and the sequential logic gate, the logic value of the clock port can be directly determined. After the clock logic values of the clock ports of all sequential logic gates in the first-level circuit in each time frame are calculated in an event-driven manner, multiple times indicated by the time frame data of the clock input ports of the sequential logic gate can be obtained Set of clock logic values in a frame.

In the embodiment of FIG. 3, the clock logic values of the clock ports of the first flip-flop U1 and the second flip-flop U2 in each time frame can be calculated, and based on this, the first flip-flop U1 and the second flip-flop U2 can be judged Whether to be triggered during this time. For example, if the clock port of the first flip-flop U1 is determined to be "0" at frame 0, "1" at frame 1, and "0" at frame "2", then the first flip-flop can be determined U1 is toggled during the clock cycle including Frame 0-Frame 2. If the clock port of the second flip-flop U2 is always determined to be "0" during frame 0-frame 2, it can be determined that the second flip-flop U2 is not triggered during the clock period including frame 0-frame 2. Accordingly, processor 14 may further determine whether a sequential logic gate is triggered within a clock cycle comprising a plurality of time frames.

At 606, processor 14 determines a set of logic simulation outputs based on the set of clocked logic values and the set of raw data inputs. The logic simulation output set includes the output logic values of the output ports of the multiple sequential logic gates in the first-level circuit and the multiple combinational logic gates in the second-level circuit in the time frame indicated by the time frame data. In one embodiment, after the processor 14 has calculated the clock logic values of the clock ports of all the sequential logic gates, the logic gates may be put into a queue to be calculated in the order of the hierarchical circuits. Then the processor 14 traverses all the logic gates in a hard-coded manner to sequentially calculate the output logic values of each logic gate in the queue in each time frame, so as to obtain a logic simulation output set for the logic circuit.

In one embodiment, determining the logic simulation output set based on the clock logic value set and the original data input set includes: using the clock logic value set and the original data input set to sequentially determine the first-level circuit and the second-level circuit according to the order of the level circuits Multiple output logic values for multiple logic gates in . The logic simulation output set includes the plurality of output logic values. For example, referring to FIG. 4 , assuming that frame 0 is the first frame indicated by the time frame data, since the original data input of the original input port included in the first-level circuit need not be calculated here, the calculation of the processor 14 is directly related to the original input port. The first sub-level circuits (ie, the AND gate 31 , the first buffer 33 and the inverter 32 ) in the second level of circuits are connected. Since each logic gate in the first sub-level circuit is stored adjacently or close to each other, the processor 14 can, for example, read the data of the AND gate 31 from the memory 12 into the cache, and can invert the sum of the first buffer 33 and The data of the device 32 is also read into the cache together. When the processor 14 calculates the output logic value of the first buffer 33 and the inverter 32 after calculating the output logic value of the AND gate 31, since the data of the first buffer 33 and the inverter 32 have been read into the high-speed cache so that memory does not need to be accessed again, which reduces simulation time. This advantage becomes even more pronounced when the number of logic circuits increases significantly. For example, when the first sub-level circuit includes 100 logic gates, assuming that the processor 14 reads data of 10 adjacent logic gates from the memory 12 each time, the processor 14 only needs to access the memory 12 ten times. Compared with conventional event-driven, the processor 14 frequently accesses the memory (for example, for 100 logic gates, the memory may be accessed at most 100 times), which may reduce the access time by 90%.

After that, the processor 14 calculates the output logic value of the logic gate (that is, the second buffer 34 ) in the second sub-level circuit in frame 0, the first-level circuit in frame 1 (that is, the first trigger U1 and second flip-flop U2), the output logic value of the first sub-level circuit (ie, AND gate 31, first buffer 33 and inverter 32) in frame 1... and so on , until the output logic values of all logic gates in all time frames are calculated to obtain a logic simulation output set for the logic circuit.

To sum up, by classifying the logic circuit and storing the data of the logic gates hierarchically, and by first determining the clock logic value of the clock port of the sequential logic gate and then traversing all the logic gates to calculate all the logic gates in each time frame The output logic value can significantly reduce the time of logic simulation.

After obtaining the logic simulation output set, the processor 14 can use the logic simulation output set to perform fault simulation. Alternatively, a logic simulation output set independent from method 600 may also be used as a background for fault simulation for fault simulation. Fault simulation uses the results of logic simulation as the background to determine which faults can be detected in the input fault set.

Conventional fault simulation includes single fault vector parallel simulation technology (parallel pattern single fault propagation, PPSFP) and so on. PPSFP is based on event-driven and machine word parallel algorithm ideas. During logic simulation, a breadth-first search is performed from the original input and timing gates until the calculation of the logic values of all gates in the netlist is completed. During the fault simulation, the fault is triggered at the corresponding position of the fault, and the breadth-first search is performed based on this, and the search queue ends when it is empty. Since PPSFP uses an event-driven method for fault simulation, when a fault propagates from a fault input node to subsequent nodes, the outputs of all subsequent nodes are calculated, which consumes a lot of simulation time. The study found that in the process of propagating the fault backward from the fault input node, the calculation of many logic gates is actually unnecessary, because the output logic values of these logic gates will not be observed by the fault observation node. In some embodiments of the present disclosure, by determining the number of transmission logic gates that can transmit signals in each time frame, it is possible to calculate only the output values of logic gates in the transmission path of the transmittable fault signal, and not to calculate the non-transmittable signal The output values of the logic gates in the path of . This significantly reduces the calculation load of fault simulation and greatly saves the time of fault simulation.

FIG. 7 shows a schematic flowchart of a simulation method 700 for performing fault simulation on logic circuits according to some embodiments of the present disclosure. The simulation method 700 may be, for example, a specific implementation of the fault simulation 220 in FIG. 2 . Various aspects described with respect to FIGS. 1-5 may therefore be applicable to the simulation method 700 . At 702, processor 14 receives a set of logic simulation outputs and a set of fault inputs for a logic circuit. The logic simulation output set may be, for example, the logic simulation output set generated by the method 600 . Alternatively, a logic simulation output set generated by other logic simulation methods may also be used, which is not limited in the present disclosure. FIG. 8 shows a schematic diagram of a specific logic simulation output set. A fault input set includes a set of logical input values representing a particular fault type provided for each fault input node or port. Common fault inputs include, for example, "stuck at 1 fault", "stuck at 0 fault", bridging fault, and the like. Fault simulation determines whether a fault can be detected by entering a logical input representing a fault type at a fault input node or port, retrieving the corresponding logical output at a downstream observation point, and comparing the logical output with the expected output.

At 704, based at least on the set of logic simulation outputs, a plurality of transmission logic gates in the logic circuit that can transmit signals in the plurality of time frames are determined. As mentioned above, in the process of propagating the fault backward from the fault input node, the calculation of many logic gates is actually unnecessary, because the output logic value of these logic gates will not be observed by the fault observation node and will not have actual significance. Therefore, by excluding logic gates that are not observed, the calculation amount and simulation time of fault simulation can be reduced.

In one embodiment, the processor 14 determines whether the sequential logic gates in the logic circuit are correspondingly triggered in at least one of the plurality of time frames based on the set of logic simulation outputs, eg, in time frames. For example, during a time frame, processor 14 responds to one or more sequential logic gates in the logic circuit being triggered (e.g., by determining the logic value of a clock port, e.g., by determining whether the current time frame and the next time frame exist transition from logic "0" to logic "1"), the one or more sequential logic gates and the one or more combinational logic gates associated with their data input ports are determined as a plurality of transfer logic gates. Specifically, processor 14 may backtrack to logic gates upstream of the one or more sequential logic gates until all valid logic gates are marked in the time frame. The effective logic gates represent all logic gates (including the sequential logic gates to which the data input terminals belong) from the data input port of each sequential logic gate to the upstream sequential logic gate or the original input port. In this context, transmitting logic gates represent logic gates that can pass signals in the current time frame, including sequential logic gates that are triggered and combinational logic gates that have inputs, while non-signaling logic gates are included in the current time frame Sequential logic gates that are not triggered and combinational logic gates that have no inputs.

In addition, the processor 14 also marks other sequential logic gates in the time frame as well as combinational logic gates associated with their data input ports as logic gates that cannot transmit signals. After processor 14 determines that the time frame is complete, the next time frame may be determined. By traversing each sequential logic gate in each time frame, processor 14 can determine a first set of sequential logic gates, that is, sequential logic gates that can pass signals, and can determine how many sequential logic gates can pass signals based on the first set of sequential logic gates. transmission logic gates. In one embodiment, processor 14 may generate a transfer flag set to mark a first group of logic gates and one or more combinatorial logic gates connected to their data input ports as transfer logic gates, and to mark other untriggered Sequential logic gates and the active combinational logic gates coupled to them are marked as logic gates that do not transmit signals.

After the processor 14 determines that the transmission logic gate of the current time frame is completed, the processor 14 may similarly determine the transmission logic gate of the next time frame in the above-mentioned manner until all time frames have been determined to be completed. Although the determination of the transmission logic gates in each time frame by time frame is described here in a serial manner, this is only for illustration and not to limit the scope of the present disclosure. Since the data of each logic gate is not modified during the process of determining the transmission logic gate, the data of each logic gate can be accessed by multiple threads at the same time, thus it is also possible to determine the corresponding multiple in each time frame in parallel in a multi-threaded manner. Portal. This further reduces the time for fault simulation. Alternatively, it is also possible to first determine whether the sequential logic gate is a transmission logic gate in each time frame, and then determine whether other valid logic gates are transmission logic gates in each time frame. In one embodiment, the processor 14 may establish a corresponding transfer flag in each time frame for each valid logic gate in the logic circuit, so as to mark whether the logic gate is a transfer logic gate in a certain time frame.

At 706, a set of fault simulation outputs is determined based at least on the determined plurality of transmission logic gates and the set of fault inputs. In one embodiment, processor 14 determines fault simulation outputs in an event-driven manner using data from fault input sets for transfer logic gates. The set of fault simulation outputs includes multiple simulation outputs for multiple faults in multiple time frames derived in this manner. For example, for a faulty input in a time frame, processor 14 determines whether the logic gate connected to the faulty input node is a transmission logic gate in the time frame, starting from the faulty input node. If the logic gate is a transmission logic gate, calculate the fault logic output of the logic gate and confirm whether the subsequent logic gate is a transmission logic gate, and so on until the fault simulation output of the fault observation point is calculated. In some embodiments, the failure observation point is usually the output of a certain sequential logic gate.

If the processor 14 finds that a logic gate extending downstream from the faulty input node is not a transmission logic gate, the processor 14 skips the faulty transmission path and starts processing the next faulty input. After the calculation of one time frame is completed, the processor 14 may calculate the fault simulation outputs of observation points for multiple fault inputs in the next time frame until the fault simulation outputs of all time frames are obtained. Since the processor 14 gives up the transmission path that cannot transmit the fault excitation signal and does not perform logic calculations on the logic gates in the transmission path during the fault simulation process, the calculation amount of the fault simulation is significantly reduced and the time of the fault simulation is shortened.

In some embodiments, the processor 14 can further reduce the fault simulation calculation amount and fault simulation time by judging whether the fault can be triggered. The processor 14 determines whether a plurality of original fault inputs in the fault input set corresponding to fault input nodes in the logic circuit are activated based on the logic simulation output set and the fault input set. In response to the original fault input being active at the fault input node, the processor 14 determines, based on the set of logic simulation outputs, a number of transferable signals in logic gates associated with the fault input node in the logic circuit that can deliver signals in multiple time frames logic gate. If the original fault input is not activated at the fault input node, processor 14 skips fault simulation calculations for that fault. For example, if the fault is a "stuck at 1" fault, but the logical background value of the fault input port indicates a logic value of "0", this indicates that the "stuck at 1" fault cannot be fired here. Therefore, the processor 14 may skip the calculation of the failure, that is, the processor 14 does not calculate the logic output value of the logic gate starting from the failure input port in the time frame. In this way, computing resources and time can be further saved.

FIG. 8 shows a schematic diagram of a logic circuit 800 with logic simulation background values according to some embodiments of the present disclosure. It can be understood that the logic circuit 800 is only used to describe the fault simulation according to the present disclosure, but not to limit the scope of the present disclosure. Logic circuits may have other circuit structures, and the fault simulation method according to the embodiments of the present disclosure is also applicable to other logic circuits. The logic circuit 800 includes a first flip-flop 802 , a second flip-flop 804 , an OR gate 806 , an inverter 808 , a buffer 810 and an AND gate 812 . The data input port of the first flip-flop 802 is connected to the output of the OR gate 806, and the two input ports of the OR gate 806 are respectively connected to the output port of the buffer 810 and the output port of the AND gate 812. The data input port of the second flip-flop 804 is connected to the output port of the inverter 808 , and the input port of the inverter 808 is connected to the output port of the AND gate 812 . The input port of the buffer 810 and the input port of the AND gate 812 may be connected to the original input port.

In Figure 8, the numbers in the boxes at the input ports of each logic gate show the logic simulation values of the input ports in two time frames, where the right box represents the logic simulation value of the previous time frame, and the left box Boxes represent logical simulation values for the next timeframe. Although only logic simulation values for two time frames are shown, this is for illustration only and not to limit the present disclosure. Other numbers of time frames are possible, eg each input port can have consecutive 32-bit, 64-bit or 128-bit bit values as logic emulation values. These logic simulation values may be, for example, logic simulation results obtained by the method 600 . Alternatively, it can also be provided by other logic simulation methods.

In one embodiment, the processor 14 may first determine whether the first flip-flop 802 and the second flip-flop 804 , which are sequential logic gates, are triggered within a time frame. Since the clock port of the first flip-flop 802 is "1" in the current time frame and the next time frame, there is no transition from "0" to "1", so the first flip-flop 802 is not activated in the current time frame trigger. Correspondingly, the valid logic gates traced back from the first flip-flop 802 to the original input port are logic gates that cannot transmit signals in the current time frame, including the first flip-flop 802 , the OR gate 806 and the buffer 810 . On the other hand, since the clock port of the second flip-flop 804 is respectively "0" and "1" in the current time frame and the next time frame, there is a jump from "0" to "1", so the second flip-flop 804 is triggered in the current timeframe. Correspondingly, the valid logic gates traced back from the second flip-flop 804 to the original input port in the current time frame are transmission logic gates, which include the second flip-flop 804 , the inverter 808 and the AND gate 812 .

FIG. 9 shows a schematic diagram of a logic circuit with transferable flags according to some embodiments of the present disclosure. As the processor 14 sequentially determines each logic gate, the processor 14 may generate a corresponding transfer flag set to indicate whether each logic gate is a transfer logic gate in the time frame. The logic circuit 900 in FIG. 9 corresponds to the logic circuit 800 , but the numbers at each input port indicate that the input port of the logic gate can transmit signals, that is, transmit events. As mentioned above, the second flip-flop 804 is a transfer logic gate in the first time frame, so the transfer flags on the data input port and the clock port of the second flip-flop 804 are shown with "1". Similarly, the input ports of other logic gates traced back from the second flip-flop 804 to the original input ports are correspondingly shown with transfer flags "1". In the later time frame, since the second flip-flop 804 is not triggered, the transfer flags of the input ports of other logic gates where the second flip-flop 804 traces back to the original input port are shown with "0". In contrast, since the first flip-flop 802 is not triggered in the two time frames, the transmission flags of the input ports of other logic gates traced back from the first flip-flop 802 to the original input ports are not triggered in the two time frames. Shown as "0". Although the transmission flags are shown as "1" and "0", it is understood that this is for illustration only and not limiting the scope of the present disclosure. Other markings are possible, such as "0" for passing a signal and "1" for not passing a signal.

When performing fault simulation, the processor 14 may decide whether to perform subsequent calculation of the transmission path based on the transmission flag. For example, assume that the input port of the buffer 810 is connected to a fault input node, and the output port of the first flip-flop 802 is a fault observation node. When the processor 14 determines that the transfer flag of the input port of the buffer 810 is "0", it may abandon the subsequent calculation of the fault, but turn to the next fault. For example, assume that one input port of the AND gate 812 is connected to a fault input node, and the output port of the second flip-flop 804 is a fault observation node. Processor 14 determines that the transfer flags of both input ports of AND gate 812 are "1" in this time frame, so processor 14 computes the logical output of AND gate 812, and then turns to subsequent logic gates (i.e., inverter 808). Processor 14 similarly determines that the transfer flag of the input port of inverter 808 is "1" and performs the calculation for inverter 808 . By analogy, until the logic output of the second flip-flop 804 is calculated, and the logic output is compared with a predetermined output to determine whether the fault is detected.

FIG. 10 shows a schematic diagram of a logic circuit for describing fault excitation according to some embodiments of the present disclosure. The logic circuit 1000 in FIG. 10 corresponds to the logic circuit 800 , and the same logic simulation values as those in FIG. 8 are similarly shown on each input port. Therefore, various aspects described in relation to FIG. 8 can be applied to FIG. 10 , and will not be repeated here. As mentioned above, the processor 14 can further reduce the fault simulation calculation amount and fault simulation time by judging whether the fault can be triggered. As shown in FIG. 10 , the fault input node is located, for example, at the first input port of the AND gate 812 , and the fault to be input is a "fixed at 1" fault. However, the logical values of the input port in the two time frames are "1" and "0" sequentially. When the logical value is "0", the "Stick at 1" fault cannot be fired here. Since this fault cannot be activated, the calculation of the logic value of the subsequent logic gate is also unambiguous. In some embodiments, processor 14 may thus determine whether a plurality of original fault inputs in the fault input set corresponding to fault input nodes in the logic circuit are activated based on the set of logic simulation outputs and the set of fault inputs. In response to the original fault input being active at the fault input node, the processor 14 determines, based on the logic simulation output set, a plurality of transmission logics in logic gates associated with the fault input node in the logic circuit that can transmit signals in multiple time frames Door. If it cannot be activated, the processor 14 may skip the calculation of the logic values of the logic gates from the fault input point to the observation point to save computing resources and fault simulation time.

FIG. 11 shows a schematic block diagram of an electronic device 1100 according to some embodiments of the present disclosure. The electronic device 1100 may be implemented as or included in the electronic device 10 of FIG. 1 .

The electronic device 1100 may include a plurality of modules for performing corresponding steps in the method 600 as discussed in FIG. 6 . As shown in FIG. 11 , the electronic device 1100 includes a logic circuit classification unit 1102 configured to classify logic circuits to determine a first-level circuit and a second-level circuit. The first level of circuitry includes a plurality of sequential logic gates and a plurality of primitive inputs, and the second level of circuitry includes a plurality of combinational logic gates. The electronic device 1100 further includes a clock logic value determination unit 1104, configured to determine the clock input ports of the multiple sequential logic gates of the first-level circuit in the multiple time frames based on the time frame data representing the multiple time frames and the original clock input set. The set of clock logic values in . The electronic device 1100 further includes a logic simulation output set determining unit 1106, configured to determine a logic simulation output set based on the clock logic value set and the original data input set. The logic simulation output set includes the output logic values of the output ports of the multiple sequential logic gates in the first-level circuit and the multiple combinational logic gates in the second-level circuit in multiple time frames.

In some embodiments, the logic circuit classifying unit 1102 is further used to classify the logic circuit to determine the first-level circuit, the first sub-level circuit and the second sub-level circuit, the first sub-circuit level includes the second level circuit combinational logic gates of the plurality of combinational logic gates directly coupled to the first level of circuitry, and the second subcircuit level includes those of the plurality of combinational logic gates in the second level of circuitry directly coupled to the first subcircuit level Combination logic gates.

In some embodiments, the clock logic value determination unit 1104 is further used to add the original clock input port in multiple time frames to the event queue; add the combinational logic gate between the original clock input port and multiple sequential logic gates to the event queue ; calculating output logic values of the combinational logic gates; and determining clock logic value sets of clock ports of the plurality of sequential logic gates in the first level circuit in a plurality of time frames based on the output logic values of the combinational logic gates.

In some embodiments, the logic simulation output set determination unit 1106 is further configured to use the clock logic value set and the original data input set to sequentially determine the multiple logic gates in the first-level circuit and the second-level circuit in sequence according to the order of the level circuits A plurality of output logic values, the logic simulation output set includes a plurality of output logic values.

In some embodiments, the logic circuit grading unit 1102 is further configured to store the data of the first-level circuits in the first area of the memory and store the data of the second-level circuits in the second area of the memory according to the levels of the logic circuits. The second area is different from the first area.

Fig. 12 shows a schematic block diagram of an electronic device 1200 according to some embodiments of the present disclosure. The electronic device 1200 may be implemented as or included in the electronic device 10 of FIG. 1 .

The electronic device 1200 may include a plurality of modules for performing corresponding steps in the method 700 as discussed in FIG. 7 . As shown in FIG. 11 , the electronic device 1200 includes a receiving unit 1202 configured to receive a logic simulation output set and a fault input set for a logic circuit. The electronic device 1200 further includes a transmission logic gate determination unit 1204 configured to determine a plurality of transmission logic gates in the logic circuit that can transmit signals in a plurality of time frames based at least on the logic simulation output set. The electronic device 1200 further includes a fault simulation output set determining unit 1206, configured to determine a fault simulation output set based at least on the determined plurality of transmission logic gates and the fault input set.

In some embodiments, the transmission logic gate determination unit 1204 is further configured to determine whether the sequential logic gates in the logic circuit are correspondingly triggered in at least one of the multiple time frames according to the time frame based on the logic simulation output set; and in response to the first set of sequential logic gates in the logic circuit being triggered in at least one time frame, determining combinational logic gates associated with inputs to the first set of sequential logic gates and the first set of sequential logic gates as a plurality of transfer logic Door.

In some embodiments, the transfer logic gate determination unit 1204 is further configured to determine the timing of each sequential logic gate in the logic circuit at multiple times based on the clock logic values in the logic simulation output set corresponding to the clock ports of each sequential logic gate. Whether to trigger in frame.

In some embodiments, the transmission logic gate determination unit 1204 is further configured to determine whether the logic gate to be calculated is a transmission logic gate; and in response to determining that the logic gate to be calculated is a transmission logic gate, using the logic value derived from the fault input set To determine the fault output logic value of the logic gate to be calculated, the fault simulation output set includes the fault output logic value.

In some embodiments, the transmission logic gate determination unit 1204 is further used to determine whether the original fault input corresponding to the fault input port in the logic circuit in the fault input set is activated based on the logic simulation output set and the fault input set; and In response to the original fault input being activated at the fault input port, based on the set of logic simulation outputs, a plurality of transmission logic gates of the logic circuit associated with the fault input port that can transmit signals in a plurality of time frames is determined.

FIG. 13 shows a schematic block diagram of an example device 1300 that may be used to implement embodiments of the present disclosure. The device 1300 may be used to implement the

electronic device

10 , 1100 or 1200 . As shown, device 1300 includes computing unit 1301, which may be loaded into RAM and/or ROM according to computer program instructions stored in random access memory (RAM) and/or read only memory (ROM) 1302 or from storage unit 1307 1302 to perform various appropriate actions and processes. In the RAM and/or ROM 1302, various programs and data necessary for the operation of the device 1300 may also be stored. The computing unit 1301 and the RAM and/or ROM 1302 are connected to each other via a bus 1303. An input/output (I/O) interface 1304 is also connected to the bus 1303 .

Multiple components in the device 1300 are connected to the I/O interface 1304, including: an input unit 1305, such as a keyboard, a mouse, etc.; an output unit 1306, such as various types of displays, speakers, etc.; a storage unit 1307, such as a magnetic disk, an optical disk, etc. ; and a communication unit 1308, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1308 allows the device 1300 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.

The computing unit 1301 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 1301 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1301 executes various methods and processes described above, such as method 600 and/or method 700 . For example, in some embodiments, method 600 and/or method 700 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 1307 . In some embodiments, part or all of the computer program may be loaded and/or installed onto device 1300 via RAM and/or ROM and/or communication unit 1308 . When a computer program is loaded into RAM and/or ROM and executed by computing unit 1301, one or more steps of method 600 and/or method 700 described above may be performed. Alternatively, in other embodiments, the computing unit 1301 may be configured to execute the method 600 and/or the method 700 in any other suitable manner (for example, by means of firmware).

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

In addition, while operations are depicted in a particular order, this should be understood to require that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations should be performed to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while the above discussion contains several specific implementation details, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

A method for simulating, comprising:

Hierarchizing logic circuits to determine a first level of circuitry including a plurality of sequential logic gates and a plurality of primitive inputs and a second level of circuitry comprising a plurality of combinational logic gates;

determining a set of clock logic values for clock input ports of a plurality of sequential logic gates of the first level circuit in the plurality of time frames based on the time frame data representing the plurality of time frames and the original clock input set; and

Based on the clock logic value set and the original data input set, a logic simulation output set is determined, and the logic simulation output set includes: the output ports of the multiple sequential logic gates in the first-level circuit are in the multiple output logic values in time frames, and output logic values of output ports of the plurality of combinational logic gates in the second level circuit in the plurality of time frames.
The method of claim 1, wherein staging logic circuits to determine first-level circuits and second-level circuits comprises: staging the logic circuits to determine the first-level circuits, first sub-level circuits, and A second sub-level circuit, the first sub-circuit level comprising a combinational logic gate of a plurality of combinational logic gates in the second level circuit that is directly coupled to the first level circuit, and the second sub-level The circuit level includes a combinational logic gate of the plurality of combinational logic gates in the second level circuit that is directly coupled to the first sub-circuit level.
The method according to claim 1 or 2, further comprising:

receiving simulation cycle data; and

The time frame data is determined based on the simulation period data.
The method according to any one of claims 1-3, wherein it is determined based on the time frame data representing a plurality of time frames and the original clock input set that the clock input ports of the plurality of sequential logic gates of the first-level circuit are in the The set of clock logic values in the multiple time frames includes:

adding the original clock input ports in the plurality of time frames to an event queue;

adding combinational logic gates between the original clock input port and the plurality of sequential logic gates to the event queue;

calculating an output logic value of the combinational logic gate; and

A set of clock logic values of clock ports of the plurality of sequential logic gates in the first level circuit in the plurality of time frames is determined based on the output logic values of the combinational logic gates.
The method according to any one of claims 1-4, wherein determining a logic simulation output set based on the clock logic value set and the original data input set comprises:

using the clock logic value set and the original data input set to sequentially determine a plurality of output logic values of logic gates in the first hierarchy circuit and the second hierarchy circuit in the order of the hierarchy circuits, the The logic simulation output set includes the plurality of output logic values.
The method according to any one of claims 1-5, wherein staging the logic circuits to determine the first level circuits and the second level circuits comprises:

According to the level of the logic circuit, the data of the first level circuit is stored in a first area of the memory and the data of the second level circuit is stored in a second area of the memory, the second area is different from the first region.
A computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including a method for executing the method described in any one of claims 1-6 method directive.
A computer program product, the computer program product comprising a plurality of programs, the plurality of programs configured to be executed by one or more processors, the plurality of programs comprising a method for performing any one of claims 1-6 Instructions for the method described.
An electronic device comprising:

one or more processors;

A memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of any one of claims 1-6.
An electronic device comprising:

A logic circuit grading unit, configured to classify the logic circuit to determine a first-level circuit and a second-level circuit, the first-level circuit includes a plurality of sequential logic gates and a plurality of original inputs, and the second-level circuit includes Multiple combinational logic gates;

A clock logic value determining unit, configured to determine the clock input ports of the multiple sequential logic gates of the first-level circuit in the multiple time frames based on the time frame data representing the multiple time frames and the original clock input set set of clock logic values; and

A logic simulation output set determining unit, configured to determine a logic simulation output set based on the clock logic value set and the original data input set, the logic simulation output set including: the plurality of sequential logic gates in the first-level circuit The output logic values of the output ports of the plurality of time frames in the plurality of time frames, and the output logic values of the output ports of the plurality of combinational logic gates in the second level circuit in the plurality of time frames.
The electronic device according to claim 10, wherein the logic circuit grading unit is further used to classify the logic circuit to determine the first level circuit, the first sub-level circuit and the second sub-level circuit, the second A sub-circuit level includes a combinational logic gate of the plurality of combinational logic gates in the second level circuit that is directly coupled to the first level circuit, and the second sub-circuit level includes the second level circuit A combinatorial logic gate of the plurality of combinatorial logic gates directly coupled to the first sub-circuit level.
The electronic device according to claim 10 or 11, wherein the clock logic value determination unit is further configured to add the original clock input ports in the multiple time frames to an event queue;

adding combinational logic gates between the original clock input port and the plurality of sequential logic gates to the event queue;

calculating an output logic value of the combinational logic gate; and

A set of clock logic values of clock ports of the plurality of sequential logic gates in the first level circuit in the plurality of time frames is determined based on the output logic values of the combinational logic gates.
The electronic device according to any one of claims 10-12, wherein the logic simulation output set determining unit is further configured to use the clock logic value set and the original data input set to sequentially determine in the order of hierarchical circuits A plurality of output logic values of the plurality of logic gates in the first level circuit and the second level circuit, the logic simulation output set includes the plurality of output logic values.
The electronic device according to any one of claims 10-13, wherein the logic circuit grading unit is further configured to store the data of the first-level circuit in the first area of the memory according to the level of the logic circuit and Data for the second level of circuitry is stored in a second area of the memory, the second area being different from the first area.
A method for simulating, comprising:

Receive a logic simulation output set and a fault input set for a logic circuit;

determining, based at least on the set of logic simulation outputs, a number of transmission logic gates in the logic circuit that can transmit signals in a number of time frames; and

A set of fault simulation outputs is determined based at least on the determined plurality of transmission logic gates and the set of fault inputs.
The method of claim 15 , wherein determining, based at least on the set of logic simulation outputs, a plurality of transmission logic gates in the logic circuit that can transmit signals in a plurality of time frames comprises:

Based on the set of logic simulation outputs, determining whether sequential logic gates in the logic circuit are correspondingly triggered in at least one of the plurality of time frames according to time frames; and

Responsive to a first set of sequential logic gates in the logic circuit being toggled in the at least one time frame, combining combinational logic gates associated with inputs to the first set of sequential logic gates with the first set of sequential logic gates A gate is determined as the plurality of transmission logic gates.
The method according to claim 16, wherein determining whether each sequential logic gate in the logic circuit is correspondingly triggered in the plurality of time frames based on the set of logic simulation outputs comprises:

Based on the clock logic values respectively corresponding to the clock ports of the respective sequential logic gates in the logic simulation output set, it is determined whether each sequential logic gate in the logic circuit is triggered in the plurality of time frames.
The method of any one of claims 15-17, wherein determining the set of fault simulation outputs based at least on the determined plurality of transmission logic gates and the set of fault inputs comprises:

determining whether the logic gate to be calculated is a transfer logic gate; and

In response to determining that the logic gate to be computed is a transmission logic gate, determining a fault output logic value for the logic gate to be computed using logic values derived from the set of fault inputs, the set of fault simulation outputs comprising the Fault output logic value.
The method of any one of claims 15-18, wherein determining, based at least on the set of logic simulation outputs, a plurality of transmission logic gates in the logic circuit that can transmit signals in a plurality of time frames comprises:

determining, based on the set of logic simulation outputs and the set of fault inputs, whether an original fault input in the set of fault inputs corresponding to a fault input port in the logic circuit is activated; and

in response to the original fault input being activated at the fault input port, based on the set of logic simulation outputs, determining, in the logic gate associated with the fault input port in the logic circuit, during the plurality of time frames Multiple transfer logic gates in which signals can be passed.
The method of any one of claims 15-19, wherein determining, based at least on the set of logic simulation outputs, a plurality of transmission logic gates in the logic circuit that can transmit signals in a plurality of time frames comprises:

Based at least on the set of logic simulation outputs, a plurality of transmission logic gates in the logic circuit that can transmit signals in a plurality of time frames are determined in parallel in a multi-threaded manner.
A computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including a program for executing the method described in any one of claims 15-20 method directive.
A computer program product, the computer program product comprising a plurality of programs, the plurality of programs configured to be executed by one or more processors, the plurality of programs comprising a method for performing any one of claims 15-20 Instructions for the method described.
An electronic device comprising:

one or more processors;

A memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of any one of claims 15-20.
An electronic device comprising:

a receiving unit, configured to receive a logic simulation output set and a fault input set for a logic circuit;

a transmission logic gate determination unit configured to determine a plurality of transmission logic gates in the logic circuit that can transmit signals in a plurality of time frames based at least on the set of logic simulation outputs; and

A fault simulation output set determining unit, configured to determine a fault simulation output set based at least on the determined plurality of transmission logic gates and the fault input set.
The electronic device according to claim 24, wherein the transmission logic gate determining unit is further used for

Based on the set of logic simulation outputs, determining whether sequential logic gates in the logic circuit are correspondingly triggered in at least one of the plurality of time frames according to time frames; and

In response to a first set of sequential logic gates in the logic circuit being triggered in the at least one time frame, combining combinational logic gates associated with inputs of the first set of sequential logic gates with the first set of sequential logic gates A gate is determined as the plurality of transmission logic gates.
The electronic device according to claim 25, wherein the transmission logic gate determination unit is further configured to determine the logic circuit based on the clock logic values respectively corresponding to the clock ports of each sequential logic gate in the logic simulation output set Whether each sequential logic gate in is triggered in the plurality of time frames.
The electronic device according to any one of claims 24-26, wherein the transmission logic gate determining unit is further configured to

determining whether the logic gate to be calculated is a transfer logic gate; and

In response to determining that the logic gate to be computed is a transmission logic gate, determining a fault output logic value for the logic gate to be computed using logic values derived from the set of fault inputs, the set of fault simulation outputs comprising the Fault output logic value.
The electronic device according to any one of claims 24-27, wherein the transmission logic gate determining unit is further configured to

determining, based on the set of logic simulation outputs and the set of fault inputs, whether an original fault input in the set of fault inputs corresponding to a fault input port in the logic circuit is activated; and

in response to the original fault input being activated at the fault input port, based on the set of logic simulation outputs, determining, in the logic gate associated with the fault input port in the logic circuit, during the plurality of time frames Multiple transfer logic gates in which signals can be passed.