WO2023277881A1

WO2023277881A1 - Instruction updates to hardware devices

Info

Publication number: WO2023277881A1
Application number: PCT/US2021/039582
Authority: WO
Inventors: Chin-Yu Wang; Bing-hao CHENG; Chun Chang; Yi-Chen Chen; Chien-Pai Lai
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2023-01-05

Abstract

In some examples, an electronic device includes memory to store a firmware update, a processor, and a controller. In some examples, the controller detects a power state change by the processor. In some examples, the controller receives a power message. In some examples, the controller executes the firmware update. In some examples, the controller processes the power message by the controller when execution of the firmware update is complete.

Description

INSTRUCTION UPDATES TO HARDWARE DEVICES

BACKGROUND

[0001] Electronic technology has advanced to become virtually ubiquitous in society and has been used for many activities in society. For example, electronic devices are used to perform a variety of tasks, including work activities, communication, research, and entertainment. Different varieties of electronic circuitry may be utilized to provide different varieties of electronic technology.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] FIG. 1 is a block diagram illustrating an example of an electronic device that may be used to provide instruction updates to hardware devices; [0003] FIG. 2 is a block diagram illustrating an example of a computing device that may be used to provide instruction updates to hardware devices; [0004] FIG. 3 is a block diagram illustrating an example of memory that may be used to provide instruction updates to hardware devices;

[0005] FIG. 4 is a flow diagram illustrating an example of a method to provide instruction updates to hardware devices; and

[0006] FIG.5 is a flow diagram illustrating an example of a method to provide instruction updates to hardware devices.

DETAILED DESCRIPTION

[0007] Some examples of the techniques described herein may be related to instruction updates to electronic hardware devices. An electronic device may be a device that includes electronic circuitry (e.g., integrated circuitry). Examples of electronic devices may include computing devices, laptop computers, desktop computers, smartphones, tablet devices, game consoles, etc. In some examples, electronic devices may utilize circuitry (e.g., controller(s), processor(s), etc., or a combination thereof) to perform an operation. In some examples, electronic devices may execute instructions stored in memory to perform the operation(s). Instructions may be code, programming, or a combination thereof that specifies functionality or operation of the circuitry. In some examples, instructions may be stored in non-volatile memory (e.g., Read- Only Memory (ROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, Non-Volatile Random-Access Memory (NVRAM), etc.). In some examples, different circuitries in an electronic device may store or utilize separate instructions for operation.

[0008] In some examples, instruction updates may be updates to the firmware for a computing device. In some examples, when new firmware is provided to the computing device to be updated, the computing device may have a longer than normal boot time because of the new firmware update being installed. The techniques described herein may install a firmware update when the computing device is shutting down or powering down to avoid the firmware update being installed before booting the computing device to an operating system. In some examples this may decrease the longer than normal boot time. [0009] Throughout the drawings, similar reference numbers may designate similar or identical elements. When an element is referred to without a reference number, this may refer to the element generally, with or without limitation to any particular drawing or figure. In some examples, the drawings are not to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples in accordance with the description. The description is not limited to the examples provided in the drawings.

[0010] FIG. 1 is a block diagram illustrating an example of an electronic device 102 that may be used to provide instruction updates to hardware devices. The electronic device 102 may include or may be coupled to a processor 106 in communication with memory 104 and a basic input/output system (BIOS) 108. A firmware update 110 may be stored in the memory 104. The electronic device 102 may include a controller 112 and a first controller 114 having firmware 116.

[0011] In some examples, the controller 112 may control instruction updates or firmware updates 110 to the first controller 114. The controller 112 may detect a power state change by the processor 106. The controller 112 may receive a power message. In some examples the power message may be a power-related command for the first controller 114 to shut down or power down. The controller 112 may trap or intercept the power message. Before sending the power message on to the first controller 114, the controller 112 may execute the firmware update 110 by obtaining the firmware update 110 from the memory 104 and sending it to the first controller 114 along with a command to update the first controller’s 114 firmware 116 using the firmware update 110. The controller 112 may then process the power message when execution of the firmware update 110 is complete. The controller 112 may process the power message by sending the power message to the first controller 114. In some examples, the controller 112 may release the power message to send it to the first controller 114.

[0012] Examples of the electronic device 102 may include a computer (e.g., laptop computer or desktop computer), a smartphone, a tablet computer, a portable game console, etc. In some examples, portions of the electronic device 102 may be coupled via an interface (e.g., bus(es), wire(s), connector(s), etc.). For example, portions of the electronic device 102 or circuitries of the electronic device 102 may be coupled via an inter-integrated circuit (I2C) interface. The portions or circuitries may communicate via the interface.

[0013] In some examples, the memory 104 may include memory circuitry. The memory circuitry may be electronic, magnetic, optical, or other physical storage device(s) that contains or stores electronic information (e.g., instructions, data, or a combination thereof). In some examples, the memory circuitry may store instructions for execution (by the processor 106, controller 112, BIOS 108, the first controller 114, other component(s) of the electronic device 102, or a combination thereof). The memory circuitry may be integrated into or separate from the element(s) described in FIG. 1 . The memory circuitry may be, for example, Random Access Memory (RAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), storage device(s), optical disc(s), or the like. In some examples, the memory circuitry may be volatile memory, non-volatile memory, or a combination thereof. Examples of memory circuitry may include Dynamic Random Access Memory (DRAM), EEPROM, magnetoresistive random-access memory (MRAM), phase change RAM (PCRAM), memristor, flash memory, or the like. In some examples, the memory circuitry may be non-transitory tangible machine-readable or computer-readable storage media, where the term “non-transitory” does not encompass transitory propagating signals.

[0014] The processor 106 may be a processor to perform an operation on the electronic device 102. Examples of the processor 106 may include a general-purpose processor, an application-specific integrated circuit, a microprocessor, etc. In some examples, the processor 106 may be an application processor. The processor 106 may execute instructions (e.g., an application) on the electronic device 102.

[0015] The controller 112 may be circuitry (e.g., integrated circuitry, semiconductor circuitry, electronic component(s), etc.) to control an aspect of the electronic device 102 operation or to control an aspect of a peripheral device in communication with the electronic device 102. For example, the controller 112 may include digital logic circuitry (e.g., a controller processor), transistors, memory, etc. In some examples, the controller 112 may execute instructions or code to perform an operation.

[0016] In some examples, the first controller 114 may be circuitry (e.g., integrated circuitry, semiconductor circuitry, electronic component(s), etc.) to control an aspect of the electronic device 102 operation or to control an aspect of a peripheral device connected to the electronic device 102. For example, the first controller 114 may include digital logic circuitry (e.g., a controller processor), transistors, memory, etc. In some examples, the first controller 114 may execute instructions, firmware, or code to perform an operation relating to the electronic device 102 or to a peripheral device connected to the electronic device 102. [0017] As used herein, firmware may be instructions stored on a hardware device or electronic circuitry to operate the hardware device or electronic circuitry. Instructions included in firmware may be code or programming that defines or controls functionality or operation of the hardware device or electronic circuitry. For example, some hardware devices or electronic circuitries may execute firmware to perform an operation(s). For instance, firmware may be executed to initialize, control, and/or operate the hardware device or electronic circuitry. In some examples, firmware may include instructions to control communication and/or interaction between the hardware device or electronic circuitry and other hardware or circuitry(ies) (e.g., a host electronic device). In some examples, firmware may be stored in non-volatile memory (e.g., Read- Only Memory (ROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, etc.). In some examples, different circuitries in an electronic device may store and/or utilize separate firmware for operation.

[0018] In some examples, a firmware update may be an updated, new, or different version of firmware. For example, a first controller 114 may have firmware 116 version 1.0 installed. A firmware update 110 may be downloaded where the firmware update 110 is version 2.0.

[0019] The electronic device 102 may include a BIOS 108. As used herein, a basic input/output system (BIOS) refers to hardware or hardware and instructions to initialize, control, or operate a computing device (e.g., electronic device 102) prior to execution of an operating system (OS) of the computing device. Instructions included within a BIOS may be software, firmware, microcode, or other programming that defines or controls functionality or operation of a BIOS. In one example, a BIOS may be implemented using instructions, such as platform firmware of a computing device, executable by a processor. A BIOS may operate or execute prior to the execution of the OS of a computing device. A BIOS may initialize, control, or operate components such as hardware components of a computing device and may load or boot the OS of the computing device.

[0020] In some examples, a BIOS may provide or establish an interface between hardware devices or platform firmware of the computing device and an OS of the computing device, via which the OS of the computing device may control or operate hardware devices or platform firmware of the computing device. In some examples, a BIOS may implement the Unified Extensible Firmware Interface (UEFI) specification or another specification or standard for initializing, controlling, or operating a computing device.

[0021] In some examples when the BIOS 108 is updated, new firmware 116 may be updated. The new or updated BIOS 108 may be provided to the electronic device 102 in the same download or image file as the firmware update 110. The firmware update 110 may be a newer or different version of firmware 116 for the first controller 114.

[0022] The electronic device 102 may include additional portions (e.g., components, circuitries, etc.) (not shown) or some of the portions described herein may be removed or modified without departing from the scope of this disclosure. In some examples, the electronic device 102 may include input/output (I/O) circuitry (e.g., port(s), interface circuitry, etc.), memory circuitry, input device(s), output device(s), etc., or a combination thereof. Examples of output devices include a display panel(s), speaker(s), headphone(s), etc. Examples of input devices include a keyboard, a mouse, a touch screen, camera, microphone, etc. In some examples, a user may input instructions or data into the electronic device 102 using an input device or devices.

[0023] FIG. 2 is a block diagram illustrating an example of a computing device 202 that provides instruction updates to hardware devices. In some examples, the computing device 202 may perform an aspect of the operations described in FIG. 1. The computing device 202 may be an example of the electronic device 102 described in FIG. 1. In some examples, the computing device 202 may include or may be coupled to a processor 206 in communication with memory 204, a controller 212, a first controller 214, a second controller 240, a third controller 244, and a power state and power control component 234. In some examples, portions of the computing device 202 may be coupled via an interface (e.g., bus(es), wire(s), connector(s), etc.). For example, portions of the computing device 202 or circuitries of the computing device 202 may be coupled via an inter-integrated circuit (I2C) interface. The portions or circuitries may communicate via the interface. Examples of the computing device 202 include a desktop computer, smartphone, laptop computer, tablet device, mobile device, etc. In some examples, one, some, or all of the components or elements of the computing device 202 may be structured in hardware or circuitry. In some examples, the computing device 202 may perform one, some, or all of the operations described in FIGS. 1-5.

[0024] The processor 206 may execute instructions on the computing device 202 to perform an operation (e.g., execute application(s)). For instance, the processor 206 may be an example of the processor 106 described in FIG. 1. In other examples, the processor 206 may be an APU (i.e., in the AMD architecture a CPU with an integrated graphics controller), or a PCH (i.e., in the Intel architecture a Platform Controller Hub).

[0025] The processor 206 may be in electronic communication with the memory 204 via a first memory communications bus 248. In some examples, the processor 206 may communicate with the memory 204 over a Serial Peripheral Interface (SPI) bus.

[0026] The processor 206 may include a power interface 228 to perform power management 230. The power interface 228 may be used to communicate power management 230 messages and to perform status monitoring. In one example, the processor 206 may communicate to the controller 212 a power state change by the processor 206. In some examples, the power state change message sent over the power interface 228 may indicate that the processor 206 is entering standby mode, modern standby mode, suspend mode, hibernate mode, sleep mode, or power-down mode. In one example, the power interface 228 may be compliant with the Advanced Configuration and Power Interface (ACPI) standard or specification. For the example where the power interface 228 follows the ACPI standard, standby mode may correspond to the SOix state of the ACPI standard, modern standby mode may also correspond to the SOix state, suspend mode may correspond to the S1 state of the ACPI standard, hibernate mode may correspond to the S4 state of the ACPI standard, sleep mode may correspond to the S3 state of the ACPI standard, and power-down mode may correspond to the S5 state of the ACPI standard.

[0027] The memory 204 may store a priority table 216. In some examples, the priority table 216 may identify the firmware updates that are to be applied or executed before the computing device 202 boots to an operating system. The priority table 216 may be generated at the BIOS 208 compile time, and a BIOS manager may register or set an indicator to indicate if a particular firmware update is to be applied or executed before the computing device 202 boots to an operating system. The priority table 216 may be read by the controller 212. In some examples, the priority table 216 may be read by the controller 212 so that the controller 212 can execute firmware updates having a priority indicating the firmware updates should be applied or executed before the computing device 202 boots to the operating system or before the BIOS 208 initializes the controller that is to be updated. An example of a priority table 216 is illustrated in FIG. 3.

[0028] In some examples, the memory 204 may store a lock table 218. The lock table 218 may identify firmware versions that are locked. Locked versions are versions of firmware that have been set to not be updated. In one example, if the computing device 202 downloads a new third controller firmware update 226 for a third controller 244, the new third controller firmware update 226 may be skipped and not be applied if the lock table 218 indicates that the third controller firmware 246 is locked. The lock table 218 may be read by the controller 212. In some examples, the lock table 218 may be read by the controller 212 so that the controller 212 can determine whether a firmware update should be executed or if a firmware update should not be executed because it has been locked. An example of a lock table is illustrated in FIG. 3. In some examples, the lock table 218 may be stored in a Non-volatile random- access memory (NVRAM) area of SPI ROM. The lock table 218 may be programmed by the BIOS 208.

[0029] The computing device 202 may include a BIOS 208. In one example, the BIOS 208 may be an example of the BIOS 108 described in FIG. 1 .

[0030] In some examples, the memory 204 may store controller firmware 220. The controller firmware 220 may be a newer or different version of firmware for the controller 212. The controller firmware 220 may include a firmware updater 210. In some examples, the firmware updater 210 is the set of instructions for the controller 212 that, when executed by the controller 212, cause the controller 212 to provide instruction updates to hardware devices as described in relation to aspects of FIGS. 1 -5 herein.

[0031] In some examples, the memory 204 may store a first controller firmware update 222 that includes an update to the first controller firmware 238. The memory 204 may also store a second controller firmware update 224 that includes an update to the second controller firmware 242. Further, the memory 204 may store a third controller firmware update 226 that includes an update to the third controller firmware 246. Additional firmware updates for additional controllers may also be stored in the memory.

[0032] The controller 212 may be in electronic communication with the memory 204 via a second memory communications bus 256. In some examples, the controller 212 may communicate with the memory 204 over a Serial Peripheral Interface (SPI) bus. The controller 212 may read from the memory 204 to access the different firmware updates stored on the memory 204.

[0033] Electronic peripheral devices may be connected to the computing device 202. For example, a first controller 214 may be part of a peripheral device, such as a webcam, and may be in electronic communication with the computing device 202. The first controller 214 may include first controller firmware 238. The first controller 214 may be circuitry (e.g., integrated circuitry, semiconductor circuitry, electronic component(s), etc.) to control an aspect of the first controller 214 or a peripheral associated with the first controller 214. For example, the first controller 214 may include digital logic circuitry (e.g., a controller processor), transistors, memory, etc. In some examples, the first controller 214 may execute the first controller firmware 238 to perform an operation.

[0034] In some examples, a peripheral device may be a webcam, a touchpad, a clickpad, a USB type-C power delivery device, an accelerometer, a printer, a scanner, etc. In other examples, the peripheral device may be a sensor including a light sensor, a voice/noise sensor, a thermal sensor, etc. In further examples, the peripheral device may be a part of or associated with a finger-print reader, a Trusted Platform Module (TPM), or any firmware programmable controller or micro controller unit (MCU) such as Raspberry Pi®, etc.

[0035] The first controller 214 may be in electronic communication with the processor 206 through a first communications connection 250. In some examples, the communications connection 250 may be a Universal Serial Bus (USB) port, a serial port, a parallel port, an audio port, a video port, a digital video interface (DVI) port, a display port, an HDMI (High-Definition Multimedia Interface) port, an Ethernet port, a System Management Bus (SMBus) port, an inter-integrated circuit (I2C) port, etc.

[0036] A second controller 240 may be part of a peripheral device, such as a touchpad, and may be in electronic communication with the computing device 202. The second controller 240 may include second controller firmware 242. The second controller 240 may be in electronic communication with the processor 206 through a second communications connection 252. In one example, the second controller 240 may be an example of the controller described in relation to the first controller 214.

[0037] A third controller 244 may be part of a peripheral device, such as a printer, and may be in electronic communication with the computing device 202. The third controller 244 may include third controller firmware 246. The third controller 244 may be in electronic communication with the processor 206 through a third communications connection 254. In one example, the third controller 244 may be an example of the controller described in relation to the first controller 214. [0038] The computing device 202 may include a controller 212. In one example, the controller 212 may be an example of the controller 112 described in FIG. 1.

[0039] The controller 212 may include a bus interface 232 to communicate with the first controller 214, the second controller 240, and the third controller 244. The bus interface 232 may be a serial communication bus interface 232 including a serial bus controller. In some examples, the bus interface 232 may be a System Management Bus (SMBus) interface or an inter-integrated circuit (I2C) interface.

[0040] The controller 212 may include a power management interface 230 to perform power management. The power management interface 230 may be used to communicate power management messages and to perform status monitoring. In one example, the processor 206 may communicate to the controller 212 a power state change by the processor 206 through the power management interface 230. In some examples, the controller 212 through the power management interface 230 may detect a power state change such as standby mode, modern standby mode, suspend mode, hibernate mode, or power-down mode. The power messages communicated through the power management interface 230 may relate to the processor 206, the first controller 214, the second controller 240, or the third controller 244. In one example, a power down message may be sent by the processor 206 for the first controller 214. The controller 212 may trap or intercept this message via the power management interface 230, perform firmware updates, and then send or release the power-down message or power-down command to the first controller 214 after the firmware updates are complete. In other examples, power messages may be sent by the processor 206 for the second controller 240 and the third controller 244. The controller 212 may trap or intercept these messages via the power management interface 230, perform firmware updates, and then send or release the messages to the second controller 240 and the third controller 244. [0041] The computing device 202 may include a power state and power control component 234. The power state and power control component 234 may be hardware power circuitry used in the computing device 202. The power state and power control component 234 may provide power to the first controller 214, the second controller 240, and the third controller 244. The power state and power control component 234 may be controlled by the power management interface 230 on the controller 212. When the controller 212 is to send a power down message to the second controller 240, for example, it may send the power down message using the power management interface 230 to the power state and power control component 234.

[0042] Power 236 may be provided to the power state and power control component 234. In some examples, the power 236 may be provided by a battery or by a wall outlet.

[0043] FIG. 3 is a block diagram illustrating an example of memory 304 that may be used in providing instruction updates to hardware devices. In some examples, the memory 304 may store a firmware priority table 316, a firmware version lock table 318, controller firmware 320, a first controller firmware update 322, a second controller firmware update 324, a third controller firmware update 326, and a fourth controller firmware update 328.

[0044] In some examples, the priority table 316 may identify the firmware updates that are to be applied or executed before the computing device 202 boots to an operating system or when the computing device 202 is in a pre-boot state. The priority table 316 may be generated at the BIOS compile time, and a BIOS manager may register or set an indicator to indicate if a particular firmware update is to be applied or executed before the computing device 202 boots to an operating system. The priority table 316 may be read by the controller 212. The priority table 316 may be an example of the priority table 216 described in FIG. 2.

[0045] In some examples, the priority table 316 may be read by the controller 212 so that the controller 212 can execute firmware updates having a priority indicating the firmware updates should be applied or executed before the computing device 202 boots to the operating system. The firmware priority table 316 may include a first controller identification 330 with an associated first priority 338. When the first priority 338 is set, the first controller identified by the first controller identification 330 is to have a firmware update applied before the computing device 202 boots to an operating system or when it is in a pre-boot state. When the first priority 338 is not set, the first controller identified by the first controller identification 330 does not have a firmware update applied before the computing device 202 boots to an operating system or when it is in a pre boot state. When the first priority 338 is not set, the first controller identified by the first controller identification 330 may have a firmware update when a power state change occurs at the processor 106, such as, by way of examples, when the processor 106 is to enter suspend mode, standby mode, hibernate mode or to shut down.

[0046] The firmware priority table 316 may include a second controller identification 332 with an associated second priority 340, a third controller identification 334 with an associated third priority 342, and a fourth controller identification 336 with an associated fourth priority 344. The second controller identification 332, the third controller identification 334, and the fourth controller identification 336, may be used and operate in a similar fashion as the first controller identification 330. The second priority 340, the third priority 342, and the fourth priority 344 may be used and operate in a similar fashion as the first priority 338.

[0047] In some examples, the memory 304 may store a firmware version lock table 318. The firmware version lock table 318 may identify firmware versions that are locked. A firmware version that has a lock may be referred to as having a firmware lock. The firmware version lock table 318 may be an example of the lock table 218 described in FIG. 2.

[0048] In some examples, the first controller identification 346 in the firmware version lock table 318 identifies the first controller. The first controller version 354 may identify the version of the firmware in the first controller. A firmware version may be data (e.g., a number, characters, a string, etc.) indicating a version (e.g., release, version number, date, etc.) of the firmware. The firmware version may provide an indication of an age or variant of the firmware (relative to another firmware version(s), for example). For instance, a higher version number may indicate newer firmware relative to a lower version number, which may indicate older firmware. [0049] A first lock 362 may indicate whether the first controller version 354 of the first controller firmware should be locked or in other words not changed or updated. In some examples, when the first lock 362 is set, it may be an indication that the first controller version 354 should not be updated. When the first lock 362 is not set, it may be an indication that the firmware identified by the first controller version 354 may be updated or changed.

[0050] The firmware version lock table 318 may store a second controller identification 348 with a second controller version 356 and a second lock 364. The firmware version lock table 318 may also store a third controller identification 350, a third controller version 358, and a third lock 366. The firmware version lock table 318 may further store a fourth controller identification 352, a fourth controller version 360, and a fourth lock 368. The second, third, and fourth identifications, versions, and locks may be used and operate in a similar fashion as described with respect to the first controller identification 346, the first controller version 354, and the first lock 362.

[0051] In some examples, before the controller 212 executes or applies a firmware update, the controller 212 may read the firmware version lock table 318 to determine whether the firmware updates are locked or whether they are not locked. If a firmware version is not locked, then the controller 212 may execute the firmware update. If a firmware version is locked, the controller 212 may skip or not apply the firmware update.

[0052] In some examples, a user many manage the firmware version lock table 318 through the BIOS. The firmware version lock table 318 may be protected by a BIOS administrator password.

[0053] The memory 304 may store the controller firmware 320 having the firmware updater 310 instructions. The controller firmware 320 and the firmware updater 310 instructions may be examples of the controller firmware 320 and firmware updater 210 described in FIG. 2.

[0054] The memory 304 may store the first controller firmware update 322, the second controller firmware update 324, the third controller firmware update 326, and the fourth controller firmware update 328. The firmware updates in FIG. 3 may be examples of the firmware updates described in FIG. 2. [0055] FIG. 4 is a flow diagram illustrating an example of a method 400 for providing instruction updates to hardware devices. The method 400 or a method 400 element(s) may be performed by an electronic device or apparatus (e.g., electronic device 102, apparatus, desktop computer, laptop computer, smartphone, tablet device, etc.). For example, the method 400 may be performed by the electronic device 102 described in FIG. 1 or by the computing device 202 described in FIG. 2.

[0056] At 402, a computing device 202 may detect a power state change by the processor 106. In some examples, the power state change may be when the processor 106 enters standby mode, modern standby mode, suspend mode, hibernate mode, power-down mode, etc.

[0057] At 404, the computing device 202 may receive a power message. In some examples, a controller 112 may receive a power message for a first controller 114 intending to instruct the first controller 114 to change a power state.

[0058] At 406, the computing device 202 may execute the firmware update 110. In some examples, the controller 112 may execute the firmware update 110 by obtaining the firmware update 110 from the memory 104 and sending it to the first controller 114 along with a command to update the first controller’s firmware using the firmware update 110.

[0059] At 408, the power message may be processed by the controller 112 when execution of the firmware update 110 is complete. In some examples, the controller 112 may process the power message by sending the power message to the first controller 114. In some examples, the controller 112 may release the power message to send it to the first controller 114.

[0060] FIG. 5 is a flow diagram illustrating an example of a method 500 for providing instruction updates to hardware devices. The method 500 or a method 500 element(s) may be performed by an electronic device, computing device or apparatus (e.g., electronic device 102, apparatus, desktop computer, laptop computer, smartphone, tablet device, etc.). For example, the method 500 may be performed by the electronic device 102 described in FIG. 1 or by the computing device 202 described in FIG. 2. [0061] At 502, the firmware version lock table may be updated. In some examples, the firmware version lock table may be updated when a user sets a particular version of firmware for a first controller 114 as locked. A user may edit the firmware version lock table using the system BIOS 208.

[0062] At 504, an updated BIOS is downloaded. In some examples, new firmware updates for controllers may be downloaded with the updated BIOS 208. In other examples, the firmware updates for controllers may be downloaded separately from an updated BIOS.

[0063] At 506, the BIOS 208 may be updated using the updated BIOS. For example, the updated BIOS 208 may be flashed. When the BIOS 208 is updated, firmware updates may also be programmed or flashed into memory 204. In some examples, an update to the controller firmware 220 having a new firmware updater 210 may be stored into memory 204. In addition, a first controller firmware update 222, a second controller firmware update 224, and a third controller firmware update 226 may also be stored into memory 204 when the BIOS 208 is being stored into memory.

[0064] At 508, the computing device 202 may be rebooted. In some examples, the reboot may be an automatic reboot that is part of the BIOS 208 update process.

[0065] At 510, the controller 212 may determine whether firmware that is to be updated has priority to be updated before the computing device 202 boots to an operating system. In one example, this determination 510 may be made during the new BIOS power-on-self-test time, which means before the BIOS 208 initializes the first controller 214. In some examples, the controller 212 may read the priority table 216 to make this determination. If firmware has priority, the method proceeds to 512. If no firmware has priority, the method proceeds to 516. In one example, if the firmware lacks priority, the method proceeds to 516. [0066] At 512, the controller 212 may determine whether firmware that is to be updated has been locked. In one example, if the firmware for the first controller 214 has been locked, then the firmware for the first controller 214 will not be updated even if a newer version has been downloaded and stored in the memory 204 for updating. In some examples, the controller 212 may read the lock table 218 to make this determination. If firmware has been locked, the method proceeds to 516. If the firmware has not been locked, the method proceeds to 514.

[0067] At 514, the controller 212 may update the firmware for any controllers having priority and not having been locked before the computing device 202 boots to the operating system. In some examples, the controller 212 may update the unlocked firmware having priority during a pre-boot state of the computing device 202.

[0068] At 516, the computing device 202 may boot to an operating system. The BIOS 208 may complete the system initialization and then may run an OS loader to load the operating system. After the computing device 202 boots, the computing device 202 may be used for some period of time by the user, in a stand-alone capacity, or in any other use of a computing device 202.

[0069] At 518, the controller 212 may detect a power management event. In some examples, a power management event may be when the processor 206 is to stop executing instructions including modern standby, suspend to RAM, hibernate, and power off or shut down.

[0070] At 520, the controller 212 may trap a power down command. In some examples, the controller 212 may trap or intercept the power down message intended for a controller. Before sending the power down message on to the first controller 214, for example, the controller 212 may determine whether any firmware updates should be executed.

[0071] At 522, the controller 212 may determine whether firmware that is to be updated has been locked. The controller 212 may read the lock table 218 to determine whether firmware has been locked. In one example, if the firmware for the first controller 214 has been locked, then the firmware for the first controller 214 will not be updated even if a newer version has been downloaded and stored in the memory 204 for updating. If firmware has been locked, the method proceeds to 526. If the firmware has not been locked, the method proceeds to 524.

[0072] At 524, the controller 212 may execute the firmware update. In some examples, the controller 212 may execute the firmware update by obtaining the firmware update from the memory 204 and sending it to the first controller 214 along with a command to update the first controller’s firmware 238 using the firmware update 222. In some examples, performing firmware updates after a user is done using a computing device 202 decreases the initial boot time because some of the firmware update may be accomplished after the user is done using the computing device 202 rather than before.

[0073] At 526, the controller 212 may process the power down message when execution of the firmware update is complete. In some examples, the controller 212 may process the power down message by sending the power down message to the first controller 214. In some examples, the controller 212 may release the power down message to send it to the first controller 214. In other examples, the controller 212 may process power down messages for the second controller 240 and the third controller 244 by sending the power-down messages to the second controller 240 and the third controller 244, respectively. [0074] At 528, the controllers may enter a new power state. In one example, the controllers entering a new power state may be the controller parking to its proper power state and the first controller 214, the second controller 240, and the third controller 244 going into their proper power states. If the power message was to power down, then the proper power state may be a powered down state.

[0075] As used herein, items described with the term “or a combination thereof” may mean an item or items. For example, the phrase “A, B, C, or a combination thereof” may mean any of: A (without B and C), B (without A and C), C (without A and B), A and B (without C), B and C (without A), A and C (without B), or all of A, B, and C.

[0076] While various examples are described herein, the described techniques are not limited to the examples. Variations of the examples are within the scope of the disclosure. For example, operation(s), aspect(s), or element(s) of the examples described herein may be omitted or combined.

Claims

1 . An electronic device, comprising: memory; a processor; a controller to: detect a power state change by the processor; receive a power message; execute a firmware update stored in the memory; and process the power message by the controller when execution of the firmware update is complete.

2. The electronic device of claim 1 , wherein executing the firmware update comprises sending the firmware update over a serial communication bus.

3. The electronic device of claim 1 , wherein the controller is to determine whether a firmware lock is set before executing the firmware update.

4. The electronic device of claim 1 , wherein the controller is to process the power message by the controller sending a power down command.

5. The electronic device of claim 1 , wherein the processor stops executing instructions after the power state change is detected.

6. The electronic device of claim 1 , wherein the power state change is when the processor is to power down.

7. The electronic device of claim 1 , wherein the power state change is detected through a power interface of the processor.

8. A computing device, comprising: memory to store a firmware update; a processor; a controller to: detect a power state change by the processor; send the firmware update to a first controller using a serial communication bus; and send a power-down message to the first controller using the serial communication bus after the firmware update.

9. The computing device of claim 8, wherein the controller reads a lock table from the memory before sending the firmware update.

10. The computing device of claim 9, further comprising a basic input/output system (BIOS) to program the lock table.

11 . The computing device of claim 8, further comprising a basic input/output system (BIOS) to program a priority table in the memory, wherein the priority table comprises a priority for the firmware update.

12. A computing device, comprising: memory to store a first firmware update and a second firmware update; a processor; a controller having a serial bus controller for a serial bus, the controller to: send the first firmware update to a first controller using the serial bus before booting to an operating system; boot to the operating system; trap a power-down command at the controller; send the second firmware update to a second controller using the serial bus after booting to the operating system; and release the power-down command to the second controller.

13. The computing device of claim 12, wherein the second firmware update is sent to the second controller during or after a shut down of the operating system.

14. The computing device of claim 12, wherein the controller is to read a priority table in the memory to determine that the first firmware update has priority to be applied before booting to the operating system.

15. The computing device of claim 12, wherein the controller is to read a priority table in the memory to determine that the second firmware update lacks priority to be applied before booting to the operating system.