WO2023245626A1 - 用于电子设计自动化的方法和设备 - Google Patents

用于电子设计自动化的方法和设备 Download PDF

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Publication number
WO2023245626A1
WO2023245626A1 PCT/CN2022/101152 CN2022101152W WO2023245626A1 WO 2023245626 A1 WO2023245626 A1 WO 2023245626A1 CN 2022101152 W CN2022101152 W CN 2022101152W WO 2023245626 A1 WO2023245626 A1 WO 2023245626A1
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Prior art keywords
netlist
optimization
logic
circuit
computer
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PCT/CN2022/101152
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English (en)
French (fr)
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李钘
陈磊
杨帆
袁明轩
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华为技术有限公司
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Priority to PCT/CN2022/101152 priority Critical patent/WO2023245626A1/zh
Publication of WO2023245626A1 publication Critical patent/WO2023245626A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Definitions

  • Embodiments of the present disclosure relate to Electronic Design Automation (EDA), and more specifically to methods and devices for electronic design automation.
  • EDA Electronic Design Automation
  • logic synthesis is a key link between the previous and the next and is related to circuit performance (smaller, faster, and more energy-saving).
  • Logic synthesis converts the high-abstract description of the designed digital circuit into a circuit connection netlist at the logic gate level after Boolean function simplification and optimization.
  • the existing logic synthesis process converts the register conversion level circuit described in the hardware description language into a Boolean circuit and then optimizes it while satisfying the design constraints. Circuit delay and area are two important optimization goals, and delay and area are closely related to the circuit level and the number of nodes respectively.
  • the optimization process of logic synthesis usually includes logic optimization, mapping and netlist optimization. These optimizations are all NP-hard problems, and most existing methods achieve the optimization goals of each stage by iteratively calling different local or global optimization operators. The designs of these operators themselves are different, and the optimization target effects are also different. The final logical synthesis optimization effect depends very much on the operator sequence used and its parameters, and the space for permutations and combinations of operators and their parameters is huge.
  • Embodiments of the present disclosure provide an electronic design automation solution, particularly a logic synthesis solution.
  • a method for electronic design automation is provided.
  • logic optimization is performed on the Boolean logic representing the circuit to obtain the optimized Boolean logic.
  • Process map Boolean logic to obtain a netlist representing the circuit.
  • the local optimal netlist is replaced with the optimized netlist, and a process map is performed on the optimized netlist.
  • the convergence speed can be accelerated and the optimization effect of logic synthesis can be improved through process mapping and inner iterations of netlist optimization oriented to the final netlist performance.
  • the operator sequence can be specified through expert experience, or operator combinations and parameters can be dynamically recommended with the help of data-driven and other algorithms.
  • refined circuit features are designed to accurately model circuit states for dynamic operator recommendation.
  • the disclosure provides an apparatus.
  • the apparatus includes: a processor; and a memory coupled to the processor and containing instructions stored thereon that, when executed by the processor, cause the apparatus to perform the first aspect of the present disclosure. method.
  • a computer-readable storage medium having a computer program/instructions stored thereon, which when executed by a processor implements the steps of the method in the first aspect of the present disclosure.
  • a computer program product comprising a computer program/instructions that when executed by a processor implements the steps of the method in the first aspect of the disclosure.
  • Figure 1 illustrates a flowchart of a method for designing an integrated circuit in accordance with some embodiments of the present disclosure.
  • Figure 2 shows a schematic flowchart of a logic synthesis method according to some embodiments of the present disclosure.
  • Figure 3 shows a schematic flowchart of a logic synthesis method according to some embodiments of the present disclosure.
  • Figure 4 shows a schematic flowchart of a logic synthesis method according to some embodiments of the present disclosure.
  • Figure 5 shows a schematic block diagram of a device that may be used to implement embodiments of the present disclosure.
  • Method 100 illustrates a flowchart of a method 100 for designing a semiconductor chip in accordance with some embodiments of the present disclosure.
  • Method 100 may be implemented, at least in part, by an Electronic Design Automation (EDA) tool.
  • EDA Electronic Design Automation
  • the functional requirements of the chip are defined.
  • the chip can be a processor, a memory chip, or a system on chip (SoC) with multiple components. Functional requirements can include the nature of the chip and the performance goals of the chip.
  • SoC system on chip
  • an electronic system level (ESL) description is generated based on the functional requirements of the chip.
  • ESL electronic system level
  • Electronic system-level descriptions focus on higher levels of abstraction without considering lower-level implementations.
  • the goal of ESL description is to increase the likelihood of successful implementation of functionality.
  • a Register Transfer Level (RTL) description is generated based on the ESL description.
  • RTL description is a description of a semiconductor chip design in terms of its operation. Specifically, the behavior of the circuit is defined in terms of the signal flow between hardware registers in the RTL description.
  • HDL Hardware Description Language
  • HDL can be used to create a high-level representation of a circuit, from which the low-level representation and ultimately the actual discrete components and wiring can be derived.
  • the RTL description of the chip is logically synthesized, for example, the RTL description of the chip in HDL form is converted into a gate-level description of the chip.
  • the gate-level description is a discrete netlist of logic gate primitives, ie, netlist 110 .
  • the netlist 110 can be simulated to determine whether the design realizes the predetermined function or design intent. This simulation is also called "pre-simulation" or "pre-layout simulation”.
  • the chip is physically designed based on the netlist 110 to construct the physical layout of the chip. For example, components such as logic gates can be placed and the placed components routed to provide interconnections between the component's signal and power terminals. In this way, the layout 114 of the chip can be constructed.
  • the layout 114 is physically verified.
  • Design Rule Check DRC
  • the layout must be drawn according to design rules, which can be provided by the fab.
  • design rule check it is checked whether the drawing of the layout 114 satisfies the corresponding design rules.
  • the layout 114 can also be compared with the schematic (Layout Versus Schematic, LVS), also known as consistency check.
  • LVS Logical Schematic
  • the netlist is extracted from the layout 114 and compared with the netlist 110 to ensure that the extracted netlist is consistent with the netlist 110 .
  • parasitic extraction PEX
  • parasitic parameter extraction parasitic parameters such as resistance and capacitance can be extracted from the layout 114, and a netlist containing these parasitic parameters is output, also called a parasitic parameter netlist.
  • the netlist containing the parasitic parameters is simulated, which is also called "post-simulation” or "post-layout simulation.” Therefore, the parasitic parameter netlist used for post-simulation is also called a post-simulation netlist.
  • post-simulation the response of an actual digital circuit and/or analog circuit is simulated by constructing an accurate simulation model of the circuit.
  • layout 114 may be subjected to layout post-processing. For example, you can add structures such as sealing rings, apply resolution enhancement technology, etc. After layout post-processing, mask data 120 may be generated for final chip fabrication.
  • FIG. 1 only shows a schematic flow chart of IC design. In some embodiments, some steps may be added, deleted, or the order of some steps modified.
  • Figure 2 illustrates a schematic flow diagram of a logic synthesis method 200 in accordance with some embodiments of the present disclosure.
  • logic synthesis method 200 may be implemented at block 108 as shown in FIG. 1 .
  • the initial netlist 202 may be an RTL description of the chip, for example, a representation in HDL language.
  • the initial netlist 202 may be determined based on an RTL description (eg, HDL description) of the chip.
  • logic optimization is performed on the initial netlist 202.
  • Logic optimization means optimizing and simplifying the logic of Boolean circuits, which is a process-independent optimization.
  • the logic of a Boolean circuit can be represented by Boolean functions, logic diagrams, etc. Examples of logic diagrams include NAND-Inverter Graph (AIG), Majority-Inverter Graph (MIG), etc.
  • the initial netlist 202 may first be converted into a logical representation of a Boolean circuit, for example, a Boolean function, a logic diagram, etc. representation. Then, the logic of the Boolean circuit is optimized using one or more logic optimization operators.
  • a Boolean circuit for example, a Boolean function, a logic diagram, etc. representation.
  • a sequence of logic optimization operators may be invoked to optimize the logic graph.
  • Operators can represent optimization methods and their parameters.
  • the sequence of logical optimization operators can be set empirically, or can be dynamically determined with the help of algorithms such as random search, simulated annealing, reinforcement learning, and Bayesian optimization given the operator set and parameter range.
  • a process mapping is performed on the Boolean logic representing the circuit to determine a netlist representing the circuit.
  • Technology mapping equivalently maps the logic structure of a Boolean circuit into an achievable gate-level circuit structure.
  • process mapping can be lookup table (LUT) mapping, standard unit mapping, etc.
  • a sequence of process mapping operators may be invoked to perform process mapping.
  • the process mapping operator sequence can be set empirically or dynamically determined with the help of algorithms such as random search, simulated annealing, reinforcement learning, and Bayesian optimization given the operator set and parameter range.
  • a netlist optimization is performed on the netlist representing the circuit to obtain an optimized netlist.
  • a sequence of netlist optimization operators may be invoked to perform netlist optimization.
  • the netlist optimization operator sequence can be set empirically or dynamically determined with the help of algorithms such as random search, simulated annealing, reinforcement learning, and Bayesian optimization given the operator set and parameter range.
  • mapping iterations it is determined whether to proceed with mapping iterations. For example, whether to continue executing the iterative cycle of process mapping-netlist optimization can be determined based on preset configurations such as historical circuit characteristics, operator operating status, and iteration termination conditions. This loop is also called the inner loop.
  • the performance, power, and area (Performance, Power, Area, PPA) of the mapped netlist are used as the main optimization goals to speed up the convergence speed.
  • the netlist obtained after executing block 206 or 208 is better than the local optimal netlist 216, then use this netlist to replace the local optimal netlist 216 to update Locally optimal netlist216.
  • circuit characteristics of the final netlist of previous inner layer iterations and the current netlist may be analyzed to determine whether to continue performing inner layer iterations. If it is determined in block 210 to continue the inner iteration, the current netlist is passed to block 206 to continue executing the inner loop. If it is determined at block 210 that no more inner iterations are to be performed, the local optimal netlist is passed to block 212 .
  • the number of search deterioration times when the current netlist is worse than the local optimal netlist or the number of cycles preset in advance can be counted. If the number of search deteriorations or the number of cycles reaches the threshold, the output is No, otherwise the output is Yes.
  • whether to continue to execute the outer layer iteration is determined by analyzing the circuit characteristics of the local optimal netlist in previous outer layer iterations and the current local optimal netlist. If the current local optimal netlist is better than the global optimal netlist, use the current local optimal netlist to replace the global optimal netlist. If its output is yes, the globally optimal netlist is passed to block 204. If not, the global optimal netlist is output as the final comprehensive netlist 214 .
  • all run configuration files required to perform process-independent logic synthesis may be included in the configuration file 218 .
  • Operator and parameter settings, constraints, and process library 220 include the operator pool and its related parameters in the logic optimization stage, process mapping stage, and netlist optimization stage, the rough correspondence between the related parameters and the optimization effect, the maximum area, the maximum delay, etc.
  • the optimization objectives and iteration termination conditions 222 include the weight of key optimization objectives such as delay, area, and running time, and iteration termination conditions such as running time, number of iterations, optimization objective constraints, and relaxation of constraint conflicts.
  • Feature extraction and operator recommendation 224 can obtain the current circuit status from block 204, 206 or 208, and determine the operator sequence in the next iteration based on the optimization results of the historical operator sequence to recommend to block 204, 206 or 208 respectively. 208.
  • Refined circuit characteristics include circuit statistical characteristics such as the number of circuit nodes, critical path length, and fine-grained operator revenue distribution.
  • feature extraction and operator recommendation 224 can obtain relevant configuration information in the configuration file 218, such as operator and parameter settings, constraints, process library 220, and optimization goals and iteration termination conditions 222.
  • the feature extraction and operator recommendation 224 can dynamically determine the next iteration with the help of algorithms such as random search, simulated annealing, reinforcement learning, Bayesian optimization, etc., given the operator set and parameter range. time sequence of operators.
  • Figure 3 shows a schematic flow diagram of a logic synthesis method 300 in accordance with some embodiments of the present disclosure.
  • Method 300 may be a specific embodiment of method 200.
  • logic optimization includes blocks 303 and 304, wherein, in block 303, area-first logic optimization is performed, for example, area-first logic optimization uses a sequence of area-first logic optimization operators to optimize the Boolean logic of the circuit, and in block 304 , perform level-first logic optimization, for example, level-first logic optimization uses a sequence of level-first logic optimization operators to optimize the Boolean logic of the circuit.
  • block 303 can optimize the area of the logic diagram without deteriorating the hierarchy.
  • block 303 may simultaneously optimize the area and level of the logic diagram.
  • block 304 may optimize logic graph hierarchy, but may degrade logic graph area.
  • block 304 may simultaneously optimize the area and level of the logic diagram.
  • process mapping includes blocks 305 and 306.
  • area-first process mapping is performed.
  • area-first process mapping uses a sequence of area-first process mapping operators to perform process mapping.
  • area-first process mapping is performed.
  • Level-first process mapping 306, for example, level-first process mapping uses a sequence of level-first process mapping operators to perform process mapping.
  • block 305 may be area-first LUT netlist process mapping, but may degrade hierarchy.
  • Block 306 may be a layer-first LUT netlist process mapping, but may degrade area. In some cases, block 306 may optimize both area and level.
  • netlist optimization includes blocks 307 and 308, wherein in block 307, area-first netlist optimization is performed, for example, area-first netlist optimization uses a sequence of area-first netlist optimization operators to perform netlist optimization, At block 308, a hierarchy-first netlist optimization is performed. For example, the hierarchy-first netlist optimization uses a sequence of hierarchy-first netlist optimization operators to perform the netlist optimization.
  • operator combinations can be set based on expert experience, or given operator sets and parameter ranges, dynamic search algorithms such as random search, simulated annealing, reinforcement learning, and Bayesian optimization can be called in dynamic search boxes 303-308. operator sequence in any box of .
  • the outer loop includes logic optimization, process mapping and netlist optimization, where the optimization target of the logic optimization is the relevant indicators of the logic diagram, and the optimization target of the process mapping and netlist optimization is the PPA of the netlist.
  • the inner loop of process mapping and netlist optimization is oriented towards the final optimization goal, that is, the PPA of the netlist.
  • the outer loops of logic optimization, process mapping, and netlist optimization use logic optimization to modify the logic diagram to adjust the starting optimization points of process mapping and netlist optimization, thereby introducing a certain degree of randomness or recklessness. Stickiness, jumping out of the local minimum when searching.
  • area optimization and hierarchical optimization may be performed alternately to search for better points.
  • Figure 4 illustrates a flow diagram of a logic synthesis method 400 in accordance with some embodiments of the present disclosure.
  • block 402 operators and parameter settings, constraint conditions, process library modules, optimization objectives, iteration termination conditions, etc. are set in the configuration file.
  • circuit file is input, and the operator sequence and final circuit netlist file are automatically searched and generated.
  • the final circuit netlist file and report are analyzed. If it is determined in block 408 that various constraints are met, the method 400 ends and the netlist is passed to the next stage. If it is determined at block 408 that the partial constraint cannot be satisfied, the method 400 proceeds to block 410 , and if it is determined at block 410 that the conflict is acceptable or a runtime upper bound has been reached, the method 400 proceeds to the next stage. If it is determined in box that the conflict is unacceptable and the runtime upper limit has not been reached, then return to box 402 to adjust the configuration file accordingly.
  • Figure 5 shows a schematic block diagram of a device 500 that may be used to implement embodiments of the present disclosure.
  • the methods 100-400 shown in Figures 1-4 can be implemented by the device 500.
  • the device 500 includes a central processing unit (CPU) 501, which can be loaded into the computer according to computer program instructions stored in a read-only memory (Read-Only Memory, ROM) 502 or from a storage unit 508.
  • Computer program instructions in Random Access Memory (RAM) 503 to perform various appropriate actions and processes.
  • RAM 503 various programs and data required for the operation of the device 500 can also be stored.
  • CPU 501, ROM 502 and RAM 503 are connected to each other through bus 504.
  • An input/output (I/O) interface 505 is also connected to bus 504.
  • I/O interface 505 Multiple components in the device 500 are connected to the I/O interface 505, including: input unit 506, such as a keyboard, mouse, etc.; output unit 507, such as various types of displays, speakers, etc.; storage unit 508, such as a magnetic disk, optical disk, etc. ; and communication unit 509, such as a network card, modem, wireless communication transceiver, etc.
  • the communication unit 509 allows the device 500 to exchange information/data with other devices through computer networks such as the Internet and/or various telecommunications networks.
  • methods 100-400 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 508.
  • part or all of the computer program may be loaded and/or installed onto device 500 via ROM 502 and/or communication unit 509.
  • CPU 501 may be configured to perform methods 100-400 in any other suitable manner (e.g., by means of firmware).
  • the disclosure may be a method, apparatus, system and/or computer program product.
  • a computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for performing various aspects of the present disclosure.
  • Computer-readable storage media may be tangible devices that can retain and store instructions for use by an instruction execution device.
  • the computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above.
  • Non-exhaustive list of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory (EPROM) or flash memory, static random access memory (Static Random Access Memory, SRAM), portable compact disk read-only memory (Compact Disc Read-Only Memory, CD-ROM), digital versatile disk (Digital Video Disc, DVD), memory stick, floppy disk, mechanical encoding device, such as a punched card or a raised structure in a groove with instructions stored thereon, and any suitable combination of the above.
  • RAM random access memory
  • ROM read-only memory
  • EPROM Erasable Programmable Read-Only Memory
  • flash memory static random access memory
  • SRAM static random access memory
  • portable compact disk read-only memory Compact Disc Read-Only Memory
  • CD-ROM Compact Disc Read-Only Memory
  • DVD digital versatile disk
  • memory stick floppy disk
  • computer-readable storage media are not to be construed as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or through electrical wires. transmitted electrical signals.
  • Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to various computing/processing devices, or to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and/or a wireless network.
  • the network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers.
  • a network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium in the respective computing/processing device .
  • Computer program instructions for performing operations of the present disclosure may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or in one or more Source code or object code written in any combination of programming languages, including object-oriented programming languages—such as Python, C++, etc., and conventional procedural programming languages—such as the “C” language or similar programming languages.
  • the computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server implement.
  • the remote computer can be connected to the user's computer through any kind of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or it can be connected to an external computer (such as Use an Internet service provider to connect via the Internet).
  • electronic circuits are customized by utilizing state information of computer-readable program instructions, such as programmable logic circuits, field programmable gate arrays (Field Programmable Gate Array, FPGA) or programmable logic arrays (Programmable Logic Array, PLA), the electronic circuit can execute computer readable program instructions, thereby implementing various aspects of the present disclosure.
  • These computer-readable program instructions may be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, thereby producing a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, the computer-readable program instructions , resulting in an apparatus that implements the functions/actions specified in one or more blocks in the flowchart and/or block diagram.
  • These computer-readable program instructions can also be stored in a computer-readable storage medium. These instructions cause the computer, programmable data processing device and/or other equipment to work in a specific manner. Therefore, the computer-readable medium storing the instructions includes An article of manufacture that includes instructions that implement aspects of the functions/acts specified in one or more blocks of the flowcharts and/or block diagrams.
  • Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other equipment, causing a series of operating steps to be performed on the computer, other programmable data processing apparatus, or other equipment to produce a computer-implemented process , thereby causing instructions executed on a computer, other programmable data processing apparatus, or other equipment to implement the functions/actions specified in one or more blocks in the flowcharts and/or block diagrams.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions that embody one or more elements for implementing the specified logical function(s).
  • Executable instructions may occur out of the order noted in the figures. For example, two consecutive blocks may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved.
  • each block of the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration can be implemented by special purpose hardware-based systems that perform the specified functions or acts. , or can be implemented using a combination of specialized hardware and computer instructions.

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Abstract

本公开的实施例涉及电子设计自动化领域，提供了用于电子设计自动化的方法和设备。对表示电路的布尔逻辑进行逻辑优化，以获得优化布尔逻辑。将布尔逻辑进行工艺映射，以获得表示电路的网表。对网表进行网表优化，以获得优化网表。响应于确定优化网表优于表示电路的局部最优网表，用优化网表来替换局部最优网表，并且对优化网表进行工艺映射。以这种方式，可以显著地提高逻辑综合的效率。

Description

用于电子设计自动化的方法和设备 技术领域
本公开的实施例涉及电子设计自动化(Electronic Design Automation,EDA)，并且更具体地涉及用于电子设计自动化的方法和设备。
背景技术
在集成电路设计流程中，逻辑综合是承上启下，关乎电路性能(更小、更快、更节能)的关键环节。逻辑综合将所设计数字电路的高抽象级描述，经过布尔函数化简、优化后，转换到逻辑门级别的电路连接网表。现有逻辑综合过程在将硬件描述语言描述的寄存器转换级电路转化为布尔电路后，在满足设计约束的前提下，进行优化。电路的延迟和面积是两个重要的优化目标，而延迟和面积分别与电路层级和节点数密切相关。
逻辑综合的优化过程通常包括逻辑优化、映射和网表优化。这些优化都是NP难的问题，现有方法多为通过迭代调用不同的局部或全局优化算子来实现各阶段的优化目的。这些算子本身设计不同，优化目标效果也不尽相同。最终的逻辑综合优化效果非常依赖所用的算子序列以及其参数，而算子及其参数的排列组合空间巨大。
发明内容
本公开的实施例提供了一种电子设计自动化的方案，特别是一种逻辑综合方案。
在本公开的第一方面，提供了一种电子设计自动化的方法。在该方法中，对表示电路的布尔逻辑进行逻辑优化，以获得优化布尔逻辑。将布尔逻辑进行工艺映射，以获得表示电路的网表。对网表进行网表优化，以获得优化网表。响应于确定优化网表优于表示电路的局部最优网表，用优化网表来替换局部最优网表，并且对优化网表进行工艺映射。
除了传统的逻辑优化、工艺映射、网表优化的外层迭代之外，通过面向最终网表性能的工艺映射和网表优化的内层迭代，可以加快收敛速度，提高逻辑综合的优化效果。
每轮迭代中，算子序列可通过专家经验指定，或借助于数据驱动等算法动态推荐算子组合与参数。同时，设计了细化的电路特征以准确建模电路状态，用于算子动态推荐。
在本公开的第二方面，本公开提供了一种设备。所述设备包括：处理器；以及存储器，耦合至所述处理器并且包含存储于其上的指令，所述指令在由所述处理器执行时使所述设备执行本公开的第一方面中的方法。
在本公开的第三方面，提供了一种计算机可读存储介质，其上存储有计算机程序/指令，该计算机程序/指令被处理器执行时实现本公开的第一方面中的方法的步骤。
在本公开的第四方面，提供了一种计算机程序产品，包括计算机程序/指令，该计算机程序/指令被处理器执行时实现本公开的第一方面中的方法的步骤。
提供发明内容部分是为了以简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开的关键特征或主要特征，也无意限制本公开的范围。
附图说明
通过结合附图对本公开示例性实施例进行更详细的描述，本公开的上述以及其他目的、特征和优势将变得更加明显，其中，在本公开示例性实施例中，相同的附图标记通常代表相同部件。
图1示出了根据本公开的一些实施例的用于设计集成电路的方法的流程图。
图2示出了根据本公开的一些实施例的逻辑综合方法的示意性流程图。
图3示出了根据本公开的一些实施例的逻辑综合方法的示意性流程图。
图4示出了根据本公开的一些实施例的逻辑综合方法的示意性流程图。
图5示出了一个可以用来实施本公开的实施例的设备的示意性框图。
根据通常的做法，附图中示出的各种特征可能未按比例绘制。因此，为了清楚起见，可以任意地扩展或减小各种特征的尺寸。另外，一些附图可能未描绘给定的系统、方法或设备的所有部件。最后，在整个说明书和附图中，类似的附图标号可用于表示类似的特征。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。例如“A和/或B”表示A、B，或者A和B。下文还可能包括其他明确的和隐含的定义。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
图1示出了根据本公开的一些实施例的用于设计半导体芯片的方法100的流程图。方法100可以至少部分地由电子设计自动化(Electronic Design Automation,EDA)工具来实现。在框102，定义芯片的功能要求。该芯片可以是处理器、存储器芯片或具有多个部件的片上系统(System on Chip,SoC)。功能要求可以包括芯片的性质和芯片的性能目标。
在框104，基于芯片的功能要求生成电子系统级(Electronic System Level,ESL)描述。电子系统级描述专注于更高的抽象级别而不考虑较低级别的实现。ESL描述的目标是提高成功实现功能的可能性。使用适当的抽象来生成对要设计的芯片的全局级别的理解。
在框106，根据ESL描述生成寄存器转换级(Register Transfer Level,RTL)描述。RTL描述是对半导体芯片设计在其操作方面的描述。具体而言，电路的行为是根据RTL描述中硬件寄存器之间的信号流定义的。例如，可以使用硬件描述语言(Hardware Description Language,HDL)来创建电路的高级表示，从中可以导出低级表示以及最终的实际分立器件和布线。
在框108，对芯片的RTL描述进行逻辑综合，例如，将芯片的HDL形式的RTL描述转换为芯片的门级描述。具体来说，门级描述是逻辑门基元的离散网表，即，网表110。在获得网表110之后，可以对网表110进行仿真，以确定设计是否实现了预定的功能或者设计意图，该仿真也称为“前仿真”或“版图前仿真”。
在框112，基于网表110对芯片进行物理设计，以构造芯片的物理布局。例如，可以放置逻辑门等部件，并对放置的部件进行布线，以提供部件的信号和电源端子之间的互连。以这种方式，可以构造出芯片的版图114。
在框116，对版图114进行物理验证。例如，可以对版图114进行设计规则检查(Design Rule Check,DRC)。版图要根据设计规则来进行绘制，这些设计规则可以由晶圆厂来提供。在设计规则检查中，检查版图114的绘制是否满足相应的设计规则。
在版图114通过设计规则检查之后，版图114中有可能还存在错误，这些错误不是由于违反了设计规则所造成的，而是可能与电路图不一致所造成的。例如，版图114可能缺少一根连线，这种小缺陷对整个芯片而言也是致命的。因此，还可以对版图114进行布局与原理图比较(Layout Versus Schematic,LVS)，又称为一致性检查。在一致性检查中，从版图114抽取网表，并将抽取出的网表与网表110进行比较，以确保抽取的网表与网表110一致。此外，还可以对版图114进行寄生参数抽取(parasitic extraction,PEX)。在寄生参数抽取中，可以从版图114中抽取电阻和电容等寄生参数，并输出包含这些寄生参数的网表，也称寄生参数网表。
在框118，对包含寄生参数的网表进行仿真，该仿真也称为“后仿真”或“版图后仿真”。因此，用于后仿真的寄生参数网表也称为后仿网表。在后仿真中，通过构造电路的精确模拟模型来模拟实际数字电路和/或模拟电路的响应。
在框118，可以对版图114进行版图后处理。例如，可以添加封环等结构，应用分辨率增强技术等。在版图后处理之后，可以产生掩模数据120，以用于最终的芯片制造。
应当理解，图1仅仅示出了IC设计的示意性流程图。在一些实施例中，可以增加、删除一些步骤，或者修改一部分步骤的顺序。
图2示出了根据本公开的一些实施例的逻辑综合方法200的示意性流程图。例如，逻辑综合方法200可以在如图1所示的框108处实现。
初始网表202可以是芯片的RTL描述，例如，HDL语言的表示。例如，可以根据芯片的RTL描述(例如，HDL描述)来确定初始网表202。
在框204，对初始网表202执行逻辑优化。逻辑优化表示对布尔电路的逻辑进行优化、化简等，属于工艺无关优化。例如，布尔电路的逻辑可以通过布尔函数、逻辑图等表示，其中，逻辑图的示例包括与非图(And-Inverter Graph,AIG)、多数反相器图(Majority-Inverter Graph,MIG)等。
在对初始网表202执行逻辑优化时，可以将初始网表202首先转换为布尔电路的逻辑的表示，例如，布尔函数、逻辑图等表示。然后，使用一个或多个逻辑优化算子对布尔电路的逻辑进行优化。
在一些实施例中，在框204，可以调用逻辑优化算子序列来优化逻辑图。算子可以表示优化方法及其参数。例如，逻辑优化算子序列可以通过经验设置，也可以在给定算子集合和参数范围的情况下，借助于如随机搜索、模拟退火、强化学习、贝叶斯优化等算法动态确定。
在框206，对表示电路的布尔逻辑执行工艺映射，以确定表示电路的网表。工艺映射将布尔电路的逻辑结构等价映射成可实现的门级电路结构。例如，工艺映射可以是查找表(Lookup Table,LUT)映射、标准单元映射等。在一些实施例中，可以调用工艺映射算子序列来执行工艺映射。例如，工艺映射算子序列可以通过经验设置，也可以在给定算子集合和参数范围的情况下，借助于如随机搜索、模拟退火、强化学习、贝叶斯优化等算法动态确定。
在框208，对表示电路的网表执行网表优化，以获得优化网表。在一些实施例中，可以调用网表优化算子序列来执行网表优化。例如，网表优化算子序列可以通过经验设置，也可以在给定算子集合和参数范围的情况下，借助于如随机搜索、模拟退火、强化学习、贝叶斯优化等算法动态确定。
在框210，确定是否进行映射迭代。例如，可以根据历史电路特征、算子运行状态和迭代终止条件等预设配置来确定是否继续执行工艺映射-网表优化的迭代循环。该循环也称为内层循环。
在内层循环中，以映射后网表的性能、功率、面积(Performance,Power,Area,PPA)为主要优化目标，进而加快收敛速度。在执行工艺映射和网表优化的内层循环时，若执行框206或208之后获得的网表优于局部最优网表216，则使用该网表来代替局部最优网表216，以更新局部最优网表216。
在框210，可以分析以往内层迭代最终网表和当前网表的电路特征，以确定是否继续执行内层迭代。若在框210确定继续进行内层迭代，则将当前网表传递给框206，继续执行内层循环。若在框210确定不再进行内层迭代，则将局部最优网表传递给框212。
在一些实施例中，在框210，可以通过统计当前网表差于局部最优网表的搜索恶化次数或提前预设的循环次数等。若搜索恶化次数或循环次数达到阈值，则输出为否，否则输出为是。
在框212，根据历史电路特征、算子运行状态和迭代终止条件等预设配置来判断是否继续执行外层循环。在一些实施例中，通过分析在以往外层迭代的局部最优网表和当前局部最优网表的电路特征，来判断是否继续执行外层迭代。若当前局部最优网表优于全局最优网表，则使用当前局部最优网表来替换全局最优网表。若其输出是，则将全局最优网表传递给框204。若否，则将全局最优网表作为最终的综合网表214输出。
在一些实施例中，可以在配置文件218中包含了所有执行工艺无关逻辑综合所需的运行配置文件，尤其是算子和参数设置、约束条件、工艺库220，以及优化目标和迭代终止条件222。算子和参数设置、约束条件、工艺库220包含逻辑优化阶段、工艺映射阶段和网表优化阶段的算子池及其相关参数、相关参数与优化效果的大致对应关系、最大面积、最大延迟等约束条件、映射和网表优化所需的工艺器件库。优化目标和迭代终止条件222包括延迟、面积、运行时间等关键优化目标的权重及运行时间、迭代次数、优化目标约束、对约束冲突的松弛度等迭代终止条件。
特征提取和算子推荐224可以从框204、206或208获取目前的电路状态，并且根据历史算子序列的优化结果来确定下一次迭代时的算子序列，以分别推荐给框204、206或208。细化的电路特征包括电路节点数、关键路径长度等电路统计特征，以及细粒度算子收益分布等。在确定算子序列时，特征提取和算子推荐224可以获得配置文件218中的相关配置信息，例如，算子和参数设置、约束条件、工艺库220，以及优化目标和迭代终止条件222。在一个实施例中，特征提取和算子推荐224可以在给定算子集合和参数范围的情况下，借助于如随机搜索、模拟退火、强化学习、贝叶斯优化等算法动态确定下一次迭代时的算子序列。
图3示出了根据本公开的一些实施例的逻辑综合方法300的示意性流程图。方法300可以是方法200的一个具体实施例。
在图3中，逻辑优化包括框303和框304，其中，在框303，执行面积优先逻辑优化，例如，面积优先逻辑优化使用面积优先逻辑优化算子序列来优化电路的布尔逻辑，在框304， 执行层级优先逻辑优化，例如，层级优先逻辑优化使用层级优先逻辑优化算子序列来优化电路的布尔逻辑。例如，框303可以在层级不恶化的条件下，优化逻辑图面积。在一部分情况下，框303可以同时优化逻辑图的面积和层级。例如，框304可以优化逻辑图层级，但可能恶化逻辑图面积。在一部分情况下，框304可以同时优化逻辑图的面积和层级。
在图3中，工艺映射包括框305和框306，其中，在框305，执行面积优先工艺映射，例如，面积优先工艺映射使用面积优先工艺映射算子序列来执行工艺映射，在框306，执行层级优先工艺映射306，例如，层级优先工艺映射使用层级优先工艺映射算子序列来执行工艺映射。例如，框305可以是面积优先的LUT网表工艺映射，但可能恶化层级。框306可以是层级优先的LUT网表工艺映射，但可能恶化面积。在一部分情况下，框306可以同时优化面积和层级。
在图3中，网表优化包括框307和框308，其中，在框307，执行面积优先网表优化，例如，面积优先网表优化使用面积优先网表优化算子序列来执行网表优化，在框308，执行层级优先网表优化，例如，层级优先网表优化使用层级优先网表优化算子序列来执行网表优化。
在框303-308中，可以根据专家经验设置算子组合，或给定算子集合和参数范围，调用如随机搜索、模拟退火、强化学习、贝叶斯优化等算法动态搜索框303-308中的任一框中的算子序列。
在方法300中，外层循环包括逻辑优化、工艺映射和网表优化，其中，逻辑优化的优化目标为逻辑图的相关指标，而工艺映射和网表优化的优化目标为网表的PPA。换言之，工艺映射和网表优化的内层循环面向最终优化目标，即，网表的PPA。逻辑优化、工艺映射和网表优化(框303-框308)的外层循环借助于逻辑优化修改逻辑图的方式来调整工艺映射和网表优化的起始优化点，从而引入一定随机性或鲁棒性，跳出搜索时的局部最小值。而且，在方法300中，面积优化和层级优化可以交替执行以搜索到更优点。
图4示出了根据本公开的一些实施例的逻辑综合方法400的流程图。在框402，在配置文件中设置算子及参数设置、约束条件、工艺库模块和优化目标及迭代终止条件等。
在框404，输入电路文件，自动搜索生成算子序列和最终电路网表文件。
在框406，分析最终电路网表文件和报告。如果在框408确定满足各类约束条件，则方法400结束，将网表传递给下一阶段。如果在框408确定无法满足部分约束条件，则方法400前进至框410，如果在框410确定冲突可接受或达到运行时上限，则进入下一阶段。如果在框确定冲突无法接受且未达到运行时上限，则返回框402，针对性调整配置文件。
图5示出了一个可以用来实施本公开的实施例的设备500的示意性框图。如图1-图4所示的方法100-400可以由设备500来实现。
如图5所示，设备500包括中央处理单元(Central Processing Unit,CPU)501，其可以根据存储在只读存储器(Read-Only Memory,ROM)502中的计算机程序指令或者从存储单元508加载到随机访问存储器(Random Access Memory,RAM)503中的计算机程序指令，来执行各种适当的动作和处理。在RAM 503中，还可存储设备500操作所需的各种程序和数据。CPU 501、ROM 502以及RAM 503通过总线504彼此相连。输入/输出(Input/Output,I/O)接口505也连接至总线504。
设备500中的多个部件连接至I/O接口505，包括：输入单元506，例如键盘、鼠标等；输出单元507，例如各种类型的显示器、扬声器等；存储单元508，例如磁盘、光盘等；以及通信单元509，例如网卡、调制解调器、无线通信收发机等。通信单元509允许设备500通 过诸如因特网的计算机网络和/或各种电信网络与其他设备交换信息/数据。
上文所描述的各个过程和处理，例如方法100-400，可由处理单元501执行。例如，在一些实施例中，方法100-400可被实现为计算机软件程序，其被有形地包含于机器可读介质，例如存储单元508。在一些实施例中，计算机程序的部分或者全部可以经由ROM 502和/或通信单元509而被载入和/或安装到设备500上。当计算机程序被加载到RAM 503并由CPU 501执行时，可以执行上文描述的方法100-400的一个或多个步骤。备选地，在其他实施例中，CPU 501可以通过其他任何适当的方式(例如，借助于固件)而被配置为执行方法100-400。
本公开可以是方法、设备、系统和/或计算机程序产品。计算机程序产品可以包括计算机可读存储介质，其上载有用于执行本公开的各个方面的计算机可读程序指令。
计算机可读存储介质可以是可以保持和存储由指令执行设备使用的指令的有形设备。计算机可读存储介质例如可以是――但不限于――电存储设备、磁存储设备、光存储设备、电磁存储设备、半导体存储设备或者上述的任意合适的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括：便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(Erasable Programmable Read-Only Memory,EPROM)或闪存、静态随机存取存储器(Static Random Access Memory,SRAM)、便携式压缩盘只读存储器(Compact Disc Read-Only Memory,CD-ROM)、数字多功能盘(Digital Video Disc,DVD)、记忆棒、软盘、机械编码设备、例如其上存储有指令的打孔卡或凹槽内凸起结构、以及上述的任意合适的组合。这里所使用的计算机可读存储介质不被解释为瞬时信号本身，诸如无线电波或者其他自由传播的电磁波、通过波导或其他传输媒介传播的电磁波(例如，通过光纤电缆的光脉冲)、或者通过电线传输的电信号。
这里所描述的计算机可读程序指令可以从计算机可读存储介质下载到各个计算/处理设备，或者通过网络、例如因特网、局域网、广域网和/或无线网下载到外部计算机或外部存储设备。网络可以包括铜传输电缆、光纤传输、无线传输、路由器、防火墙、交换机、网关计算机和/或边缘服务器。每个计算/处理设备中的网络适配卡或者网络接口从网络接收计算机可读程序指令，并转发该计算机可读程序指令，以供存储在各个计算/处理设备中的计算机可读存储介质中。
用于执行本公开操作的计算机程序指令可以是汇编指令、指令集架构(Instruction Set Architecture,ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码，所述编程语言包括面向对象的编程语言—诸如Python、C++等，以及常规的过程式编程语言—诸如“C”语言或类似的编程语言。计算机可读程序指令可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络—包括局域网(Local Area Network,LAN)或广域网(Wide Area Network,WAN)—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。在一些实施例中，通过利用计算机可读程序指令的状态信息来个性化定制电子电路，例如可编程逻辑电路、现场可编程门阵列(Field Programmable Gate Array,FPGA)或可编程逻辑阵列(Programmable Logic Array,PLA)，该电子电路可以执行计算机可读程序指令，从而实现本公开的各个方面。
这里参照根据本公开实施例的方法、装置(系统)和计算机程序产品的流程图和/或框图 描述了本公开的各个方面。应当理解，流程图和/或框图的每个方框以及流程图和/或框图中各方框的组合，都可以由计算机可读程序指令实现。
这些计算机可读程序指令可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理单元，从而生产出一种机器，使得这些指令在通过计算机或其他可编程数据处理装置的处理单元执行时，产生了实现流程图和/或框图中的一个或多个方框中规定的功能/动作的装置。也可以把这些计算机可读程序指令存储在计算机可读存储介质中，这些指令使得计算机、可编程数据处理装置和/或其他设备以特定方式工作，从而，存储有指令的计算机可读介质则包括一个制造品，其包括实现流程图和/或框图中的一个或多个方框中规定的功能/动作的各个方面的指令。
也可以把计算机可读程序指令加载到计算机、其他可编程数据处理装置、或其他设备上，使得在计算机、其他可编程数据处理装置或其他设备上执行一系列操作步骤，以产生计算机实现的过程，从而使得在计算机、其他可编程数据处理装置、或其他设备上执行的指令实现流程图和/或框图中的一个或多个方框中规定的功能/动作。
附图中的流程图和框图显示了根据本公开的多个实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或指令的一部分，所述模块、程序段或指令的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或动作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所公开的各实施例。在不偏离所说明的各实施例的范围的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其他普通技术人员能理解本文公开的各实施例。

Claims (9)

  1. 一种电子设计自动化的方法，包括：
    对表示电路的布尔逻辑进行逻辑优化，以获得优化布尔逻辑；
    将所述布尔逻辑进行工艺映射，以获得表示所述电路的网表；
    对所述网表进行网表优化，以获得优化网表；和
    响应于确定所述优化网表优于表示所述电路的局部最优网表，用所述优化网表来替换所述局部最优网表，并且对所述优化网表进行工艺映射。
  2. 根据权利要求1所述的方法，还包括：
    响应于确定所述优化网表差于所述局部最优网表，确定所述局部最优网表是否优于全局最优网表；和
    响应于确定所述局部最优网表优于全局最优网表，对所述局部最优网表进行逻辑优化。
  3. 根据权利要求2所述的方法，还包括：
    响应于确定所述局部最优网表差于所述全局最优网表，将所述全局最优网表确定为表示所述电路的综合网表。
  4. 根据权利要求1所述的方法，其中所述逻辑优化包括以下至少一项：
    对所述布尔逻辑执行面积优先逻辑优化；和
    对所述布尔逻辑执行层级优先逻辑优化。
  5. 根据权利要求1所述的方法，其中所述工艺映射包括以下至少一项：
    对所述布尔逻辑执行面积优先工艺映射；和
    对所述布尔逻辑执行层级优先工艺映射。
  6. 根据权利要求1所述的方法，其中所述网表优化包括以下至少一项：
    对所述网表执行面积优先网表优化；和
    对所述网表执行层级优先网表优化。
  7. 一种设备，包括：
    处理器；以及
    存储器，耦合到所述处理器并且存储指令，所述指令在被所述处理器执行时使得所述设备实现根据权利要求1-6中任一项所述的方法。
  8. 一种存储计算机可执行指令的计算机可读存储介质，其中，所述计算机可执行指令在由至少一个处理器执行时使所述至少一个处理器执行根据权利要求1-6中任一项所述的方法。
  9. 一种计算机程序，其中，所述计算机程序在由至少一个处理器执行时使所述至少一个处理器执行根据权利要求1-6中任一项所述的方法。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160267204A1 (en) * 2014-09-19 2016-09-15 Synopsys, Inc. Management of placement constraint regions in an electronic design automation (eda) system
CN110457868A (zh) * 2019-10-14 2019-11-15 广东高云半导体科技股份有限公司 Fpga逻辑综合的优化方法及装置、系统
CN113408224A (zh) * 2021-05-19 2021-09-17 无锡中微亿芯有限公司 利用网表局部再综合实现布局合法化的fpga布局方法

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Publication number Priority date Publication date Assignee Title
US20160267204A1 (en) * 2014-09-19 2016-09-15 Synopsys, Inc. Management of placement constraint regions in an electronic design automation (eda) system
CN110457868A (zh) * 2019-10-14 2019-11-15 广东高云半导体科技股份有限公司 Fpga逻辑综合的优化方法及装置、系统
CN113408224A (zh) * 2021-05-19 2021-09-17 无锡中微亿芯有限公司 利用网表局部再综合实现布局合法化的fpga布局方法

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