WO2023245441A1

WO2023245441A1 - A method and device for optimising structural choices in logic synthesis

Info

Publication number: WO2023245441A1
Application number: PCT/CN2022/100218
Authority: WO
Inventors: Antoine GROSNIT; Xiaohang TANG; Ziyan Wang; Rasul TUTUNOV; Lei Chen; Xing Li; Mingxuan YUAN; Haitham BOU AMMAR
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2022-06-21
Filing date: 2022-06-21
Publication date: 2023-12-28
Also published as: CN117616417A

Abstract

A method of processing nodes of an augmented and-inverter graph, AIG, for representing a Boolean function obtained through a structural choices, dch, operation, the method comprising locking one or more nodes of the AIG such that multiple nodes can be processed in parallel processing operations to identify and merge equivalent nodes.

Description

A METHOD AND DEVICE FOR OPTIMISING STRUCTURAL CHOICES IN LOGIC SYNTHESIS

FIELD OF THE INVENTION

This invention relates to technology independent logic synthesis and mapping of Boolean functions.

BACKGROUND

Logic synthesis aims at simplifying a Boolean function network representation as an And-Inverter Graph (AIG) , reducing the number of nodes and levels of the AIG. Computation of structural choices (dch) is used to help heuristic mapping algorithms get out of local minima by building one or more new representations with equivalent classes of nodes. This grants more flexibility when performing technology mapping of the AIG and avoids possible missed matches located outside of the local minima. Dch operation involves a synthesis step and a sweep step, both of which are typically implemented in single-thread in ABC codebase. However, the dch operation can be slow. Even once an optimised AIG has been created, the process of removing or consolidating equivalent nodes is typically done in sequence, one node at a time, to avoid conflicting editing of the AIG.

Optimising logical synthesis to create circuits with the best logic paths for the problem at hand is the subject of much research. Similarly, reducing the computational overheads and memory usage of logic synthesis operations has also been tackled in many ways.

CN 113255258 -Logic synthesis method and device, electronic equipment and storage medium; EP 20190206620 -System and method for encryption and decryption using logic synthesis; CN 201911378431 -Method, device and system for realizing fan-out optimization in FPGA logic synthesis; CN 201911106124 -Logic balance control method, device and system in FPGA logic synthesis; CN 110457868 B -FPGA logic synthesis optimization method, device and system; CN 110765710 B -General logic synthesis method and device based on nonvolatile device; US 2017344670 A1 -Method for providing logic synthesis of pipeline circuit; US 5287289 A Logic synthesis method; US 5029102 A Logical synthesis; US 2017177750 A1 Majority Logic Synthesis; CN 113255258 A -Logic synthesis method and device, electronic equipment and storage medium; CN 111371451 A -Lock detection method for phase-locked loop, phase-locked loop, and frequency-locked detection controller thereof; and US 5805462 A -Automatic synthesis of integrated circuits employing Boolean decomposition; all address aspects of logic synthesis but do not address the problem of structural bias.

CN 112541309 -Logic synthesis implementation control method and device; US 201916264091 -Concurrent formal verification of logic synthesis; “Unlocking Fine-Grain Parallelism for AIG Rewriting” by V. Possani, et. al.; “An Open-Source EDA Flow for Asynchronous Logic” by S. Ataei, et. al.; “AParallelised Iterative Improvement Approach to Area Optimisation for LUT-Based Technology Mapping” by G. Liu, et. al.; “Parallel Combinatorial Equivalence Checking” by V. Possani et. al.; and “Parallel Logic Simulation: Myth or Reality” by K. Chang et. al. all address logic synthesis with some parallel implementation used to reduce the processing time, but all fail to address the problem of structural bias.

It is desirable to increase the speed at which the dch processing can be executed and in particular reduce the computational overheads of performing the sweep operation of dch.

SUMMARY OF THE INVENTION

According to one aspect there is provided a method of processing nodes of an augmented and-inverter graph, AIG, for representing a Boolean function obtained through a structural choices, dch, operation, the method comprising locking one or more nodes of the AIG such that multiple nodes can be processed in parallel executing operations to identify and merge equivalent nodes.

The parallel processing operations may be sweep operations implemented by a function which abides by the Galois parallelisation paradigm. This may allow for the efficient running of processing operations in parallel.

The method may comprise locking one or more nodes and subsequently processing a particular node comprising reading or modifying a set of nodes, where the one or more nodes to be locked are all nodes of the AIG comprised in the set of nodes. This may allow for safe processing of nodes in parallel by avoiding node data editing conflicts.

The said locking step may comprise read locking one or more nodes by preventing modifying node data but allowing reading node data. Read locking may permit a parallel processing operation to have read access to the node data of the read locked node and prevents the parallel processing operation from modifying the node data of the read locked node until the node is unlocked. This may allow for safe processing of nodes in parallel by avoiding node data editing conflicts.

The said locking step may comprise write locking one or more nodes by preventing both modifying node data and reading node data. Write locking may prevent a parallel processing operation from reading or modifying the node data of the write locked node until the node is unlocked. This may allow for safe processing of nodes in parallel by avoiding node data editing conflicts.

The said locking step may comprise write locking the particular node. The said locking step may comprise write locking a representer node of the class of the particular node. This may allow for safe processing of nodes in parallel by avoiding node data editing conflicts.

The said locking step may comprise for each fanout node of the particular node, write locking the fanout node and read locking a representer node of the class of the fanout node. This may allow for safe processing of nodes in parallel by avoiding node data editing conflicts or the reading of data which is subsequently edited.

The method may comprise, if the particular node is a representer node, read locking all the nodes of the same class as the particular node. This may allow for safe processing of nodes in parallel by avoiding node data editing conflicts or the reading of data which is subsequently edited.

The method may comprise scheduling the processing of the one or more nodes of the AIG according to a Galois worklist. This may assist in the efficient scheduling of parallel processes.

Processing operations may be scheduled to be executed in parallel according to the Galois worklist and an activity status of the node. This may assist in preventing scheduling and editing conflicts.

The processing operations may be scheduled to be executed in parallel and such that they do not operate on respective nodes of the same class at the same time. This may assist in preventing scheduling and editing conflicts.

The processing operations may be scheduled to be executed in parallel and such that they do not modify the same node data at the same time. This may assist in preventing editing conflicts.

Each node of the augmented AIG may comprise a status field whose value represents the activity status of the node. This may assist in preventing scheduling and editing conflicts.

Distinct values of the status field may represent the following states:

. This may assist in scheduling parallel processing operations.

The method may comprise incrementing the status field as activity is undertaken in relation to the node, and wherein successive values of the status field represent the states listed in claim 17 in that order. This may assist in efficient scheduling of parallel processing operations.

The method may comprise locking nodes in order of representer node, fanin nodes, fanout nodes, class nodes. This may assist in preventing editing conflicts.

According to another aspect there is provided a device configured to execute the method as claimed in any of claims 1 to 19.

According to another aspect there is provided a data carrier storing code executable by a computer to cause the computer to execute the method as claimed in any of claims 1 to 19.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

Figure 1 shows an example of the process of technology mapping.

Figure 2 shows an example netlist match which is not found by technology mapping of the AIG in Figure 1.

Figure 3 shows an example of the synthesis step of the dch operation.

Figure 4 shows illustrates the sequential dch operation routine.

Figure 5 shows the two steps of the structural choices procedure.

Figure 6 shows the difference between the standard sequential dch operation and an example of the proposed method.

Figure 7 shows an example algorithm for implementing the proposed.

Figure 8 shows an example algorithm for implementing the proposed safe-locking mechanism.

Figure 9 shows illustrates the proposed multi-thread architecture.

Figure 10 shows a computing system configured to execute the proposed method.

DETAILED DESCRIPTION OF THE INVENTION

Logic circuits can be used to represent Boolean functions and can be represented as And-Inverted Graphs (AIG) . An AIG is a directed acyclic graph containing four types of nodes: the constant, primary inputs (PI) , primary outputs (PO) , and two-input AND gates. The graph edges play the role of direct or complemented interconnections.

The set of nodes connected to the inputs of a given AIG node is called its fanins. The set of nodes connected to the outputs of a given AIG node is called its fanouts. A maximum fanout free cone (MFFC) of a given node v in AIG is a subset S of the predecessors of v such that every path from any node in S to a PO passes through v. A cut C with root v in AIG is a set of nodes, such that every path from PI nodes to the root node v contains at least one node from the cut C. A cut is called k-feasible if it contains k nodes or less. A k-feasible cut is associated with a local Boolean function, which is defined by the logic cone rooted at v and formed by nodes from this cut.

The aim of the dch operation is to solve the problem of structural bias caused by performing technology mapping based on only one version of a Boolean function network.

Figure 1 shows an example of the process of technology mapping 100 of a Boolean function into a netlist. The input is a Boolean function network 102 in the form of an And-Inverter Graph and the output is a netlist of k number of Look-Up-Tables (LUTs) 104 covering logic node groups of the AIG. The groups of nodes ‘m’ , ‘p’ , and ‘f’ are mapped to the LUTs having the same labels.

Figure 2 shows the same Boolean function network 102 and resulting netlist 104 as in figure 1. However, figure 2 also shows a netlist match 202 which is not found by technology mapping of the AIG on the left, but which could be used to represent the same Boolean function. Since the point ‘q’ is not present in the input AIG 102 the netlist match 202 on the right comprising ‘q’ will not be found via technology mapping when executed on the example input AIG 102 alone. That is, the output netlist relies on the structure of the input AIG network.

Figure 3 shows an example of the synthesis step of the dch operation. The synthesis step comprises building different AIGs which can all be used to represent the same Boolean function. On the left of figure 3 is an example input AIG 302. The input nodes or fanins of the AIG are ‘a’ , ‘b’ , ‘c’ , and ‘d’ . The output nodes or fanouts of the AIG are ‘x’ and ‘y’ . On the right of figure 3 is an example of an equivalent AIG 304 which still represents the same Boolean function and still has input nodes of ‘a’ , ‘b’ , ‘c’ , and ‘d’ and output nodes of ‘x’ and ‘y’ .

Figure 4 illustrates the sequential dch operation routine. Logic synthesis aims at simplifying the Boolean network representation, reducing the number of nodes and levels. The structural choices operation can be simplified to: given an AIG, build a new representation with equivalence classes of nodes to help technology mapping algorithms get out of local minima. The equations in box 406 represent the transformation of the original subject graph to a Boolean network with specified classes of equivalent nodes (with respect to the assignment of the associated descendant nodes) . Figure 4 shows an example input to the dch operation of a Boolean network represented as an And-Inverter Graph (AIG) 402 and an output of a Boolean network representation as an And-Inverter Graph with classes of equivalent nodes 404. It can be seen that the output AIG 404 comprises all of the possible different paths from input nodes ‘abcd’ to output nodes ‘xy’ from both of

AIGs

302 and 304 shown in figure 3 but with some equivalent nodes.

Figure 5 shows the two steps of the structural choices procedure. Firstly, on the left side of figure 5, building different AIGs representing the same Boolean function as the input AIG 502. Secondly, on the right side of figure 5, identifying and merging the equivalent nodes to form a combined AIG, called the sweep operation 504.

The core idea of the proposed method is to identify and reduce the bottlenecks of the sweep step of dch. It has been recognised that bottlenecks can be reduced by parallelising the processing of nodes in the sweep operation where possible using a Galois data-centric programming model. The proposed method therefore consists of a multicore implementation of the sweep step which leverages the Galois library data-centric programming model to process several nodes of the AIG in parallel. The processing one or more nodes of the combined AIG comprises determining whether an equivalent node exists in the combined AIG. That is, when processing the nodes of the combined AIG it is determined whether nodes in the AIG are logically the same or similar enough such that two or more nodes may be represented by a single node without substantively altering the logic of the AIG.

There is therefore presented herein a method of processing nodes of an augmented and-inverter graph, AIG, for representing a Boolean function obtained through a structural choices, dch, operation wherein the method comprises locking one or more nodes of the AIG such that multiple nodes can be processed in parallel processing operations to identify and merge equivalent nodes. By locking and scheduling the processing of nodes of the augmented or optimised AIG in the correct order of combination it is possible to perform parts of the sweep operation of dch simultaneously without creating editing errors. The structural choices, dch, operation may be a synthesis operation.

The proposed method specifically targets fine-grained parallel version of dch operation to reduce execution time by implementing a Galois data-centric programming model. The above discussed structural bias problem arises when the subject graph representing the Boolean function is transformed into a mapped netlist via technology mapping. Specifically, every input of every LUT in the mapped netlist must be present in the subject graph, otherwise technology mapping will not find the match. This is illustrated in figure 1 and described above. Hence, a better netlist match containing variables not presented in the original subject graph might not be found as shown in figure 2. Therefore, the quality of the technology mapping depends on the structure of the subject graph it is applied to. This constitutes the structural bias problem.

DCH operation aims to construct equivalent alternatives of the subject graph to contain structure enabling more efficient technology mapping. In a nutshell, dch operation reduces the structural bias during the technology mapping by combining different logic networks produced by multi-level logic optimisation into a single network and running a sweep operation on each node of the total network to detect equivalence classes.

The sweep operation runs sequentially on each node one by one and is therefore computationally costly. The proposed method enables an accelerated dch operation by scheduling and locking the nodes so that multiple nodes can be processed at the same time. Further, the method involves designing the relationships between the thread-local and shared data structures.

Galois is a system that supplies a data-centric programming model to use amorphous data parallelism in graph algorithms by using an abstraction for these algorithms called an operator formulation. The Galois system provides thread-safe data structures (sets, graphs) implemented in C++ and parallel executors such as for_each and do_all. In the proposed method thread-safe data structures are used to execute worklists to store active nodes. Parallel executors take the nodes from the worklists and dynamically assign threads to them. The scheduling in the Galois system is non-deterministic but can be adjusted to deterministic execution. It also resolves thread conflicts between the owners of locks on particular graph elements. Processing threads keep the abstract lock until the end of an activity or until a conflict is determined.

Therefore, as described above, the processing operations performed in parallel are sweep operations of the dch operation. The parallel sweep operations are implemented by a function which abides by the Galois parallelisation paradigm. Thus, the method comprises locking one or more nodes and subsequently processing a particular node comprising reading or modifying a set of nodes, where the one or more nodes to be locked are all nodes of the AIG comprised in the set of nodes. The set of nodes may comprise the neighbourhood of nodes of the particular node. That is, the immediate neighbouring nodes, e.g. the fanin and fanout nodes, of the particular node.

Figure 6 shows the difference between standard sequential dch operation 602 and the proposed method 604. The typical standard sequential dch operation from ABC open sourced library is shown on the left-hand side 602. In the typical implementation the sweep step of dch involves a for loop over all the nodes of the entire AIG and therefore each node is processed sequentially. However, in the proposed implementation, a worklist is maintained of active nodes which is carefully scheduled to enable safe processing of nodes in parallel 604. Before pushing a node to the worklist it is required that: both fanins to that node have already been processed; and the representer node of the class of that node has already been processed. An example of the proposed implementation 604 is illustrated on the right-hand side of figure 6, where a for_each parallel executor is shown.

Figure 7 shows an example algorithm for implementing the proposed parallel AIG dch and the proposed two steps of the structural choices procedure. In this example embodiment, algorithm 700 presents a suggested parallelised sweep routine for dch operation. Box 702 outlines a pre-sweep synthesis step which assess the input AIG and produces optimised equivalent AIGs which can be merged. The pre-sweep subroutine 702 can be parallelised by using existing implementations of basic logic synthesis operators, for example parallel rewriting of AIGs.

The proposes parallelization of the sweep step is shown at line 14 of algorithm 700, where it states:

/*Run Parallel For Loop

GaloisForEach (GaloisWorklist, dchMan) ;

Figure 8 shows an example algorithm 800 for implementing the GaloisForEach () function routine containing the proposed safe-locking mechanism 802. Specifically, the parallel sweep operation is implemented via a function called GaloisForEach () . The function comprises a safe-locking mechanism provided in box 802 which allows the parallel sweep operations to avoid conflict between the simultaneously executing threads.

the safe locking mechanism in algorithm 800 is illustrated in the following chronology and Figure 8.

4 The procedure first locks the representer node of the class of the particular node being processed -lockRepresenterNode (node)

5 The procedure then locks the fanin nodes of the particular node -lockFaninNodes (node)

6 then for all fanout nodes of the particular node -forall fanoutNode of node do

7 the fanout node (s) are locked -lockNode (fanoutNode)

8 the representer node of the class of the fanout node (s) is locked -lockRepresenterNode (fanoutNode)

9 if the particular node being processed is a class representer node of its class then

10 lock all the nodes of that class -lockClassNodes (node)

In particular, the proposed Galois system allows two levels of graph node locking. That is, when a node is being processed, any node which may require reading or modifying as a result of processing this node may be locked in an appropriate manner. The types of locking are read locking or write locking.

Read locking is where another thread can have read access to the node data of the locked node, but no other thread can modify the node data of the locked node until the node is unlocked. Thus, the said locking step may comprise read locking one or more nodes by preventing modifying node data but allowing reading node data.

Write locking is where no other thread can read or modify the node data of the locked node. Write locking is used when the current thread needs to modify the node data. Thus, the said locking step may comprise write locking one or more nodes by preventing both modifying node data and reading node data.

The current thread is tasked with processing a particular node, and any other node which comprises node data which will need to be read or modified as a result of processing the particular node may be locked as part of the above mentioned set of nodes. Read locking permits a parallel processing operation to have read access to the node data of a read locked node and prevents the parallel processing operation from modifying the node data of the read locked node until the node is unlocked. The parallel processing operation here is any processing thread performing a sweep operation on a node of the AIG which is not the particular node, and is thus being executed in parallel. Similarly, write locking prevents a parallel processing operation from reading or modifying the node data of the write locked node until the node is unlocked. As a general rule, the proposed method comprises locking nodes associated with the particular node being processed in the order of representer node, fanin nodes, fanout nodes, class nodes.

For example, let thread t start processing node n. The proposed safe locking mechanism consists of upfront locking of all nodes whose data will need to be read or modified in the course of the processing of node n. Doing the locking upfront prevents running partial processing on node n and having to abort due to a locking conflict with another thread later on.

An example of the procedure required for the locking of nodes as necessary to process node n comprises the following steps:

a) write lock n itself (the n. fraigNode may potentially be modified during the sweep) . Therefore, the locking step may comprise write locking the particular node.

b) write lock the representer node of the class of nodes n belongs to (so that no other node of this class will be processed concurrently as the sweep operation can lead to a split of the class of node n) . Therefore, the locking step may comprise write locking a representer node of the class of the particular node.

c) for each fanout node n_fo of n (i.e. each fanout node of the particular node) :

e) write lock n_fo in order to prevent the other fanin of n_fo to be processed at the same time (anode has only two fanins at most) . A n_fo. counter describing the activity status of n_fo will need to be modified (the activity status counter value is described herein below) ;

f) read lock the representer node of the class n_fo belongs to. The activity status counter field of this node will need to be read in order to know if n_fo can be pushed to the worklist.

d) if the node n is the representer of a class c:

g) read lock of all the nodes n_c belonging to the class c. n_c. counter indicating the activity status will need to be read in order to determine whether n_c can be pushed to the worklist. As an example of the possible activity status counter value: if both fanins are processed - n_c. counter == 2, if both fanins are not processed - n_c. counter < 2. Therefore, the locking step may comprise, if the particular node is a representer node, read locking all the nodes of the same class as the particular node.

In an embodiment, there is provided a data-centric parallelisation of the dch sweep operation where the dch sweep routine has a multi-thread architecture, as shown in Figure 9. Processing operations are scheduled to be executed in parallel according to the Galois worklist and an activity status of the node.

Figure 9 illustrates the proposed muti-thread architecture 900 and comprises a plurality of processing threads 902, each able to process a particular node of the AIG as part of the dch sweep operation. The proposed parallel sweep operation utilises thread-local data structures and shared-memory 904 data structures. The thread context or memory pool 906 stores SAT solver-related variables 908 and node markers 910 which are used for class refinement. The threads each have access to the memory pool relative to that particular thread for DchManager.

Shared memory 904 contains the AIG graphs (total and fraig) 912, a candidate equivalence classes map 914, the worklist of active nodes to process 916, and the class and dch managers. The candidate equivalence classes map is used for mapping a representer node to the nodes that are potentially equivalent to it. The proposed method comprises scheduling the processing of the one or more nodes of the AIG according to the worklist 916 which is a Galois worklist.

As mentioned above, the proposed method comprises scheduling and locking mechanisms. The scheduling and locking mechanisms abide the following rules.

· Two processing threads shall not process respective nodes belonging to the same class at the same time.

· Two threads shall not modify the same node data concurrently. For example, node data such as the activity status counter value, the decentralised fanout map, etc.

· Each node has a status field to track its activity status. That is, a numerical value or counter may be assigned a specific status and the counter value can be used to specify this status. For example, 0: unprocessed node; 1: only one fanin processed; 2: both fanins processed but node not in worklist; 3: node in worklist but not processed; 4: node processed but need to push fanouts to the worklist; 5: node fully processed.

Therefore the processing threads may be scheduled to be executed in parallel and such that they do not operate on respective nodes of the same class at the same time and that they do not modify the same node data at the same time. The status field value represents the activity status of the node. The value dictates whether a node of the augmented AIG may be passed to the worklist for processing in parallel or not or is in the worklist when it shouldn’t be.

Distinct values of the status field represent the following states: The node is unprocessed; Only one fanin node of the node has been processed; Both fanin nodes of the node have been processed but the node is not in the worklist; The node is in the worklist but not processed; The node is processed but the fanout nodes are not in the worklist; The node has been fully processed.

The status field value may be incremented as activity is undertaken in relation to the node. Successive values of the status field may represent the states listed above in that order.

There may be provided a device configured to execute the proposed method as described herein above. Figure 10 shows a computing system 1001 comprising a processing entity 1002 and a program store 1003. The processing entity 1002 comprises one or more processors. The program store 1003 stores in non-transient form program code executable by the processing entity 1002 to perform the algorithmic functions described herein. The computing system 1001 may be a single computer or multiple computers. It may be in a single location or distributed between multiple locations. There may also be provided a data carrier storing code executable by a computer to cause the computer to execute the method as described herein above.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

A method of processing nodes of an augmented and-inverter graph, AIG, for representing a Boolean function obtained through a structural choices, dch, operation, the method comprising locking one or more nodes of the AIG such that multiple nodes can be processed in parallel processing operations to identify and merge equivalent nodes.
The method of claim 1, wherein the parallel processing operations are sweep operations implemented by a function which abides by the Galois parallelisation paradigm.
The method of claim 1 or 2, wherein the method comprises locking one or more nodes and subsequently processing a particular node comprising reading or modifying a set of nodes, where the one or more nodes to be locked are all nodes of the AIG comprised in the set of nodes.
The method of any preceding claim, wherein the said locking step comprises read locking one or more nodes by preventing modifying node data but allowing reading node data.
The method of any preceding claim, wherein the said locking step comprises write locking one or more nodes by preventing both modifying node data and reading node data.
The method of claim 4, wherein read locking permits a parallel processing operation to have read access to the node data of the read locked node and prevents the parallel processing operation from modifying the node data of the read locked node until the node is unlocked.
The method of claim 5, wherein write locking prevents a parallel processing operation from reading or modifying the node data of the write locked node until the node is unlocked.
The method according to any of claims 3 to 7, wherein the said locking step comprises write locking the particular node.
The method according to any of claims 3 to 8, wherein the said locking step comprises write locking a representer node of the class of the particular node.
The method according to any of claims 3 to 9, wherein the said locking step comprises for each fanout node of the particular node, write locking the fanout node and read locking a representer node of the class of the fanout node.
The method according to any of claims 3 to 10, wherein the method comprises, if the particular node is a representer node, read locking all the nodes of the same class as the particular node.
The method of any proceeding claim, wherein the method comprises scheduling the processing of the one or more nodes of the AIG according to a Galois worklist.
The method of claim 12, wherein processing operations are scheduled to be executed in parallel according to the Galois worklist and an activity status of the node.
The method of claim 12 or 13, wherein the processing operations are scheduled to be executed in parallel and such that they do not operate on respective nodes of the same class at the same time.
The method of any of claims 12 to 14, wherein the processing operations are scheduled to be executed in parallel and such that they do not modify the same node data at the same time.
The method of any preceding claim, wherein each node of the augmented AIG comprises a status field whose value represents the activity status of the node.
The method of claim 16, wherein distinct values of the status field represent the following states:
The method of claim 17, comprising incrementing the status field as activity is undertaken in relation to the node, and wherein successive values of the status field represent the states listed in claim 17 in that order.
The method of any preceding claim, wherein the method comprises locking nodes in order of representer node, fanin nodes, fanout nodes, class nodes.
A device configured to execute the method as claimed in any of claims 1 to 19.
A data carrier storing code executable by a computer to cause the computer to execute the method as claimed in any of claims 1 to 19.