WO2023241279A1 - 芯片故障分析方法和装置 - Google Patents

芯片故障分析方法和装置 Download PDF

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WO2023241279A1
WO2023241279A1 PCT/CN2023/094168 CN2023094168W WO2023241279A1 WO 2023241279 A1 WO2023241279 A1 WO 2023241279A1 CN 2023094168 W CN2023094168 W CN 2023094168W WO 2023241279 A1 WO2023241279 A1 WO 2023241279A1
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circuit data
fault
circuit
data
sub
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PCT/CN2023/094168
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English (en)
French (fr)
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甄慧玲
王乃行
黄俊华
毛辉
袁明轩
黄宇
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华为技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/24—Classification techniques
    • G06F18/241—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods

Definitions

  • the embodiments of the present application relate to the technical field of integrated circuit testing, and specifically to a chip fault analysis method and device.
  • Embodiments of the present application provide a chip fault analysis method and device, which can improve the efficiency and accuracy of chip fault analysis.
  • a chip fault analysis method includes: obtaining first circuit data.
  • the first circuit data includes a plurality of circuit nodes and relationships between the plurality of circuit nodes.
  • the plurality of circuit data include: The circuit nodes include circuit nodes affected by faults in the circuit; second circuit data is generated according to the first circuit data, and the similarity between the second circuit data and the first circuit data is greater than a first preset threshold; A fault type classifier is trained according to the first circuit data and the second circuit data; and a test vector of the first fault is determined according to the fault type classifier and the first fault to be detected.
  • circuit nodes include various types of logic gates in the circuit, and logic gates include “AND” gates, “OR” gates, “NOT” gates, “XOR”, etc.
  • logic gates include “AND” gates, “OR” gates, “NOT” gates, “XOR”, etc.
  • the relationship between circuit nodes includes the relationship between logic gates.
  • the first circuit data may be constructed based on a plurality of local circuits affected by fault excitation and propagation.
  • each logic gate in the local circuit can be regarded as a node, and the connections of different logic gates can be regarded as the edges of the directed graph, with the direction from the primary input (PI) to the primary output (PO) direction is consistent.
  • the adjacency matrix is obtained according to the directed graph, and the types of different logic gates in the matrix are represented by the same or different weights.
  • Element 0 in the matrix indicates that there is no connection relationship between the two logic gates.
  • the local circuit can also be converted into a Boolean satisfiability (SAT) expression, and then the SAT expression can be converted into a bipartite graph.
  • SAT Boolean satisfiability
  • the connection relationship of the graph represents the implication of fault excitation and propagation. Connection features.
  • the second circuit data is data similar to the first circuit data generated according to the first circuit data.
  • the second circuit data may be generated through generative adversarial networks (GAN).
  • GAN generative adversarial networks
  • the first circuit data can be regarded as original circuit data
  • the second circuit data can be regarded as supplementary circuit data of the first circuit data.
  • a fault type classifier is trained according to the first circuit data and the second circuit data, and the fault type classifier is used to predict the fault type of the first fault to be detected.
  • the fault types may include measurable faults and unmeasurable faults.
  • the fault types may be further divided into several specific categories. This application does not limit this.
  • the first sequence can also be called the first vector, and the first sequence includes a set of predicted values of PI.
  • This application determines a test vector based on the fault type and the predicted value in the first sequence, and tests the faulty circuit based on the test vector.
  • This application provides a chip fault analysis method that can perform data enhancement on original circuit data to obtain supplementary circuit data, then train a fault type classifier based on the original circuit data and supplementary circuit data, and guide chip fault analysis based on the fault classification results. , improve the efficiency and accuracy of chip failure analysis.
  • generating second circuit data according to the first circuit data includes: decomposing the first circuit data to obtain a plurality of first sub-circuit data. Circuit data; generate a plurality of second sub-circuit data according to the plurality of first sub-circuit data, the plurality of first sub-circuit data correspond to the plurality of second sub-circuit data, each second The sub-circuit data is generated based on the corresponding first sub-circuit data, and the similarity between the corresponding second sub-circuit data and the first sub-circuit data is greater than the second preset threshold; according to the combined prediction model and the multiple The second sub-circuit data is used to determine the second circuit data.
  • the merge prediction model is used to predict the probability that the input circuit data can be merged to obtain the circuit data in the first circuit data.
  • the merge prediction model is based on The first circuit data and the plurality of first sub-circuit data are trained.
  • the first circuit data can be decomposed according to the relationship between the multiple circuit nodes to obtain the multiple first sub-circuit data.
  • the second sub-circuit data is data similar to the first sub-circuit data generated based on the first sub-circuit data.
  • the second sub-circuit data can be generated through a GAN.
  • a merging prediction model can be trained based on the first circuit data and the first sub-circuit data.
  • the probability that the input circuit data can be merged to obtain the circuit data in the first circuit data can be obtained.
  • the first sub-circuit data obtained by decomposing the first circuit data A includes A1, A2 and A3
  • the first sub-circuit data obtained by decomposing the first circuit data B includes B1, B2, B3 and B4, then A1 and A2
  • the predicted probability of merging to obtain the first circuit data is higher than the predicted probability of merging A1 and B3 to obtain the first circuit data.
  • This application provides a chip fault analysis method that can decompose the original circuit data and then enhance the data, and then predict and merge the enhanced data to obtain supplementary circuit data, which can reduce the impact of the fault scale and thereby Improve the efficiency and accuracy of chip failure analysis.
  • determining the second circuit data based on the combined prediction model and the plurality of second sub-circuit data includes: based on the combined prediction model and the plurality of second sub-circuit data.
  • the plurality of second sub-circuit data determines a first prediction probability value, and the first prediction probability value is a probability value that predicts that the second sub-circuit data can be combined to obtain the circuit data in the first circuit data; If the first prediction probability value is greater than the third preset threshold, the plurality of second sub-circuit data are merged according to the relationship between the circuit nodes in the plurality of second sub-circuit data to obtain the first Two circuit data; if the first prediction probability value is less than or equal to the third preset threshold, use the plurality of second sub-circuit data as the second circuit data.
  • the second sub-circuit data is input into the trained combined prediction model to obtain a first prediction probability value.
  • the first prediction probability value is the probability that the second sub-circuit data can be combined to obtain the circuit data in the first circuit data.
  • first prediction probability value is greater than the third preset threshold, then merge the second subcircuit data according to the relationship between the circuit nodes in the second subcircuit data; if the first prediction probability value is less than or equal to the third preset threshold , then the second sub-circuit data is used as the second circuit data.
  • This application provides a chip fault analysis method that can decompose the original circuit data and then enhance the data, and then predict and merge the enhanced data to obtain supplementary circuit data, which can reduce the impact of the fault scale and thereby Improve the efficiency and accuracy of chip failure analysis.
  • determining the test vector of the first fault according to the fault type classifier and the first fault to be detected includes: according to the fault type A classifier and the first fault to be detected determine a fault type and a first sequence of the first fault, where the first sequence includes predicted values of all or part of the inputs in the circuit where the first fault is located; according to the The test vector of the first fault is determined based on the fault type of the first fault and the first sequence.
  • the fault types may include measurable faults and unmeasurable faults.
  • the fault types may be further divided into several specific categories. This application does not limit this.
  • the first sequence can also be called the first vector, and the first sequence includes a set of predicted values of PI.
  • This application determines a test vector based on the fault type and the predicted value in the first sequence, and tests the faulty circuit based on the test vector.
  • Embodiments of the present application provide a chip fault analysis method that can perform data enhancement on original circuit data to obtain supplementary circuit data, then train a fault type classifier based on the original circuit data and supplementary circuit data, and guide the chip according to the fault classification results. Fault analysis, improve the efficiency and accuracy of chip fault analysis.
  • determining the test vector of the first fault according to the fault type of the first fault and the first sequence includes: if The fault type of the first fault is a measurable fault, the predicted value in the first sequence is converted into a specified assignment according to a fourth preset threshold, and the first sequence is determined according to the converted first sequence.
  • the test vector of a fault if the fault type of the first fault is an unmeasured fault, determine the test vector of the first fault according to the descending order of the predicted values in the first sequence.
  • the embodiment of the present application returns the first sequence for both measurable faults and unmeasurable faults, and the first sequence includes a set of PI prediction values. If it is a testable fault, a threshold will be given, this set of predicted values will be converted into specified assignments, and the test vector will be initialized based on the converted assignments.
  • the predicted value can be converted to 1; if the predicted value is less than the fourth preset threshold, the predicted value can be converted to 1. Convert to 0. It can also be used when the predicted value is greater than Or when it is equal to the fourth preset threshold, the predicted value is converted to 0; when the predicted value is less than the fourth preset threshold, the predicted value is converted to 1. This application does not limit this.
  • the first fault is a measurable fault
  • the first sequence is A: 0.85; B: 0.66; C: 0.21
  • A, B and C are PI.
  • the fourth preset threshold is 0.7. Predicted values greater than or equal to the preset threshold are converted to 1, and predicted values less than the preset threshold are converted to 0. Then the corresponding assignments of A, B, and C after conversion are A:1; B:0;C:0. Use this set of values as the test vector for the first fault.
  • the first fault is an unmeasured fault
  • suggestions for the circuit branch sequence are returned from large to small based on this set of PI prediction values. For example, A: 0.85; B: 0.66; C: 0.21.
  • This descending sorting result can be used as a decision-making sequence suggestion for determining the first fault test vector. For example, first use the test vectors A:1; Assignment of PI to determine the test vector.
  • the embodiment of the present application provides a chip fault analysis method, which guides ATPG calculation according to the fault classification results.
  • the fault type classification results can not only be used to initialize the test vector, but can also be used as a basis for selecting a solution method. According to different Predict results and select appropriate solution methods to further enhance solution performance.
  • training a fault type classifier according to the first circuit data and the second circuit data includes: determining third circuit data, the third circuit data The second circuit data includes the same fault type as the first circuit data; and the fault type classifier is trained according to the first circuit data and the third circuit data.
  • the circuit data whose fault type is the measurable fault in the second circuit data can be filtered out as supplementary circuit data.
  • the fault type of the first circuit data is an unmeasurable fault
  • circuit data whose fault type is an unmeasurable fault in the second circuit data can be filtered out as supplementary circuit data.
  • the filtered supplementary circuit data is the third circuit data, and the fault type classifier is trained based on the first circuit data and the third circuit data.
  • Embodiments of the present application provide a chip fault analysis method that can perform data enhancement on the original circuit data, obtain supplementary circuit data, and then screen the fault types of the supplementary circuit data.
  • Supplementary circuit data of the same type is used to train the fault type classifier, and guide chip fault analysis based on the fault classification results to improve the efficiency and accuracy of chip fault analysis.
  • obtaining the first circuit data includes: obtaining multiple local circuits affected by faults in the target fault list, where the multiple local circuits include multiple Logic gates are wired to a plurality of circuits; the first circuit data is constructed based on the plurality of local circuits.
  • the target fault list includes the identification (identity document, ID) of the logic gate in the circuit and the ID of the line.
  • Fault triggering refers to the assignment of values to nodes in the circuit that are assumed to cause faults.
  • Fault propagation includes two parts, one is from the input to the output of the circuit, and the other is from the output to the input of the circuit.
  • the target fault list For example, you can read the target fault list, select a fault from it, find the output cone corresponding to the fault and the fan-in cone involved in the circuit, and then you can obtain the local circuit affected by the excitation and propagation of the fault.
  • Multiple affected local circuits obtained based on multiple faults in the target fault list are the multiple local circuits in this application.
  • each logic gate in the local circuit can be regarded as a node, and the connections of different logic gates can be regarded as edges of the directed graph.
  • the adjacency matrix is obtained according to the directed graph.
  • the types of different logic gates in the matrix are represented by the same or different weights.
  • the element 0 in the matrix represents There is no connection between the two logic gates.
  • the local circuit can also be converted into a SAT expression, and then the SAT expression can be converted into a bipartite graph.
  • the connection relationship of the graph represents the implicit connection characteristics of the fault in the excitation and propagation.
  • Embodiments of the present application provide a chip fault analysis method that can perform data enhancement on original circuit data to obtain supplementary circuit data, then train a fault type classifier based on the original circuit data and supplementary circuit data, and guide the chip according to the fault classification results. Fault analysis, improve the efficiency and accuracy of chip fault analysis.
  • embodiments of the present application provide a computer device, which includes a unit for implementing the first aspect or any possible implementation of the first aspect.
  • inventions of the present application provide a computer device.
  • the computer device includes a processor, the processor being coupled to a memory, reading and executing instructions and/or program codes in the memory to execute the first aspect or Any possible implementation of the first aspect.
  • inventions of the present application provide a chip system.
  • the chip system includes a logic circuit that is coupled to an input/output interface and transmits data through the input/output interface to perform the first aspect or the first aspect. any possible implementation.
  • embodiments of the present application provide a computer-readable storage medium that stores program code.
  • the computer storage medium When the computer storage medium is run on a computer, it causes the computer to execute the first aspect or the first aspect. any possible implementation.
  • inventions of the present application provide a computer program product.
  • the computer program product includes: computer program code.
  • the computer program code When the computer program code is run on a computer, it causes the computer to execute the first aspect or any of the first aspects.
  • FIG. 1 is a schematic diagram of a digital circuit provided by an embodiment of the present application.
  • FIG. 2 is an exemplary flow chart of a chip fault analysis method provided by an embodiment of the present application.
  • FIG. 3 is an exemplary flow chart of chip failure analysis provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of fault excitation and propagation provided by an embodiment of the present application.
  • Figure 5 is an exemplary flow chart of a fault analysis provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of a bipartite diagram provided by an embodiment of the present application.
  • Figure 7 is a schematic diagram of different fault propagation scales provided by the embodiment of the present application.
  • Figure 8 is a schematic diagram of node decomposition and prediction merging provided by an embodiment of the present application.
  • Figure 9 is an exemplary flow chart of fault data enhancement provided by an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of a generation model provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of a D2 discriminator provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of a fault type classifier provided by an embodiment of the present application.
  • Figure 13 is an exemplary flow chart for training a fault type classifier provided by an embodiment of the present application.
  • Figure 14 is a schematic diagram of generating a node vector representation provided by an embodiment of the present application.
  • Figure 15 is a schematic diagram of a node update provided by an embodiment of the present application.
  • Figure 16 is a schematic diagram of data generation provided by the embodiment of the present application.
  • Figure 17 is a structural example diagram of a computer device provided by an embodiment of the present application.
  • Figure 18 is a structural example diagram of another computer device provided by an embodiment of the present application.
  • Figure 19 is an example diagram of a computer program product provided by an embodiment of the present application.
  • ATPG automatic test vector generation
  • ATPG is the process of applying corresponding core algorithms to generate test vectors. It provides excellent "ammunition" for process-based testing of chips and is the absolute core of the chip testing EDA tool chain. It is widely used in testing logic circuits in chip production testing.
  • the ATPG algorithm studies the logical modeling of physical defects that may occur in the chip, and generates targeted test vectors for the modeled logic faults. Due to its importance in the field of chip testing, the ATPG core algorithm also determines to a certain extent the core competitiveness of the chip testing EDA tool chains of major EDA manufacturers.
  • EDA Electronic design automation
  • Automatic test vector generation is an important part of the EDA process. Its main function is to complete test vectors for the input sequence in the testing process of digital circuits that can distinguish the behavior of correct circuits from faulty circuits caused by defects. The generated vectors can be used to assist and test the production of semiconductor devices, or to help locate the cause of a fault.
  • Boolean satisfiability problem (boolean satisfactory, SAT): Used to solve whether there is a set of variable assignments in a given truth value equation, making the problem satisfiable. If such an assignment exists, the formula is satisfiable, otherwise it is unsatisfiable.
  • the Boolean satisfiability problem is a deterministic problem, and it is also the first problem proven to be non-deterministic polynomial (NP) complete with polynomial complexity.
  • CNF Conjunctive normal form
  • Generative adversarial networks a generative network model.
  • GAN Generative adversarial networks
  • two models are trained simultaneously, a generative model G that captures the data distribution, and a discriminative model D. estimate The probability that the sample comes from the training data rather than G.
  • the training process of G is to maximize the possibility of D making an error.
  • This framework can be simply viewed as a game process between two networks.
  • Graph neural networks refers to the use of neural networks to learn graph-structured data, extract and explore features and patterns in graph-structured data. For example, learning a low-dimensional vector space representation of nodes, edges, or subgraphs in a graph.
  • Testable fault It means that a set of test vectors can be found so that the outputs of the correct circuit and the wrong circuit (the faulty circuit) are not equal, so that the fault can be identified.
  • SAT it is an SAT problem, that is, the mathematical model has one or more solutions.
  • Unmeasurable fault No input can distinguish between correct and incorrect circuits. Corresponding to the SAT, it is an UNSAT problem, that is, the mathematical model has no solution. It should be understood that unmeasurable faults do not mean that faults do not exist.
  • Branch and bound method Usually the entire feasible solution space is repeatedly divided into smaller and smaller subsets, which are called branches; a target lower bound (for minimum problems) is calculated for the solution set in each subset, which is called Delimitation. After each branch, those subsets whose boundaries exceed the target value of the known feasible solution set will not branch further. In this way, many subsets can be ignored, which is called pruning.
  • Directed graph A directional graph, consisting of a set of vertices and a set of directional edges. Each directional edge is connected to a pair of vertices.
  • Adjacency matrix A matrix that represents the adjacent relationship between vertices.
  • Directed acyclic graph If a directed graph cannot start from any vertex and return to that point through several edges, then the graph is a directed acyclic graph.
  • Logical cone A logical cone is a set of signals that can drive comparison points. It has multiple inputs (basic input, state point) and one output (basic output, state point). It can also contain other logical cones. .
  • Logic gates are the basic components on integrated circuits. Simple logic gates can be made of transistors. The combination of these transistors can produce a high-level or low-level signal after passing through them, representing the high and low levels of the two signals. High and low levels can respectively represent logical "true” and “false” or 1 and 0 in binary, thereby realizing logical operations.
  • Fan-in The maximum amount of digital signal input that a single logic gate can accept.
  • Graph embedding Represent the nodes of the graph into a low-dimensional vector space while retaining the topological structure and node information of the network so that machine learning algorithms can be directly used in subsequent graph analysis tasks.
  • Random walk also known as random walk or random walk, is a mathematical statistical model. It is composed of a series of trajectories, each of which is random. It can be used to represent irregular changes and is a basic statistical model for recording random activities.
  • Primary input (PI) The input affected by a circuit fault can be all the input of the circuit or part of the input of the circuit.
  • Primary output (PO) The output affected by a circuit fault can be the entire output of the circuit or part of the output of the circuit.
  • ATPG calculation methods are divided into two categories:
  • One type is the structured ATPG algorithm.
  • This type of ATPG algorithm mainly includes two parts of tasks. The first is to activate the target error. The second is to transmit the fault effect of the target fault to at least one observation point.
  • the structured ATPG algorithm continuously determines the state of the circuit nodes (net) in the circuit. Therefore, in some cases, you may be faced with a situation where the current required state of the circuit is not unique, which means that a decision needs to be made to determine the state of the circuit.
  • One type is represented by the D-algorithm.
  • This type of algorithm traces the demand back to the primary input (PI) and makes a decision at PI.
  • SAT Triangulation-based algorithm
  • the SAT method needs to first convert the circuit into a Boolean expression CNF.
  • CNF expressions variables and their negations are called literals. Different literals are connected through logical symbols such as AND or NOT to form clauses, which can also be called constraints. Then use the SAT solver to solve the CNF. If the solution is SAT, it means that the target fault is detectable, and the obtained solution is the test vector. If the solution is UNSAT, it means that the target fault is undetectable. Errors that cannot be determined within a given time are considered aborted faults or unobserved faults. Because the overall solution process relies on the symbolic expression CNF. Therefore, the SAT method needs to consider the time to convert the circuit into CNF.
  • circuit analysis module In order to improve the calculation efficiency of ATPG, in traditional technology, a circuit analysis module is added before the execution of the ATPG calculation process, which is intended to use the structural information of the circuit to provide assistance for subsequent decision-making.
  • circuit analysis modules in the prior art often directly use the static characteristics of the circuit, and the efficiency of this kind of fault analysis is very low.
  • FIG. 1 is a schematic diagram of a digital circuit provided by an embodiment of the present application.
  • a circuit that uses digital signals to perform arithmetic and logical operations on digital quantities is called a digital circuit, or digital system. Because it has logical operations and logic processing functions, it is also called a digital logic circuit.
  • Chip production testing mainly includes testing of logic circuits. Among them, A, B, C are the inputs of the circuit, and K is the output of the circuit.
  • L1, L2, L3, L4 and L5 are lines. G1 is the OR gate, G2 is the AND gate, G3 is the NOT gate, and G4 is the NOR gate.
  • FIG. 2 is an exemplary flow chart of a chip fault analysis method provided by an embodiment of the present application.
  • the first circuit data includes multiple circuit nodes affected by multiple faults and relationships between the multiple circuit nodes.
  • the first circuit data can be constructed according to the local circuits affected by multiple fault excitation and propagation, Each logic gate in the local circuit is regarded as a node, and the connections of different logic gates are regarded as the edges of the directed graph.
  • the adjacency matrix is obtained according to the directed graph.
  • the types of different logic gates in the matrix are represented by the same or different weights.
  • the element 0 in the matrix indicates that there is no connection relationship between the two logic gates.
  • the local circuit can also be converted into a SAT expression, and then the SAT expression can be converted into a bipartite graph.
  • the connection relationship of the graph represents the implicit connection characteristics of the fault in the excitation and propagation.
  • the second circuit data is data similar to the first circuit data generated according to the first circuit data.
  • the first circuit data can be regarded as original circuit data, and the second circuit data can be regarded as supplementary circuit data of the first circuit data.
  • the second circuit data may be generated through a GAN.
  • a fault type classifier is trained according to the first circuit data and the second circuit data, and the fault type classifier is used to predict the fault type of the first fault to be detected.
  • the fault types may include measurable faults and unmeasurable faults.
  • the fault types may be further divided into several specific categories. This application does not limit this.
  • the fault type of the first fault is determined according to the fault type classifier. It should be understood that the embodiment of the present application will return the first sequence for different fault types.
  • the first sequence may also be called the first vector, and the first sequence includes a set of predicted values of PI. This application determines a test vector based on the fault type and the predicted value in the first sequence, and tests the faulty circuit based on the test vector.
  • the first fault is a measurable fault
  • the first sequence is A: 0.85; B: 0.66; C: 0.21
  • A, B and C are PI.
  • the fourth preset threshold is 0.7. Predicted values greater than or equal to the preset threshold are converted to 1, and predicted values less than the preset threshold are converted to 0. Then the corresponding assignments of A, B, and C after conversion are A:1; B:0;C:0. Use this set of values as the test vector for the first fault.
  • the first fault is an unmeasured fault
  • suggestions for the circuit branch sequence are returned from large to small based on this set of PI prediction values. For example, A: 0.85; B: 0.66; C: 0.21.
  • This descending sorting result can be used as a decision-making sequence suggestion for determining the first fault test vector. For example, first use the test vectors A:1; Assignment of PI to determine the test vector.
  • FIG. 3 is an exemplary flow chart of chip failure analysis provided by an embodiment of the present application.
  • the target fault list 200 select a fault from it, find the output cone (output cone) corresponding to the fault and the involved fan-in cone (transitive fanin cone) in the circuit, and obtain the local circuit affected by the excitation and propagation of the fault.
  • the target fault list 200 includes the identification (identity document, ID) of the logic gate in the circuit and the ID of the line.
  • Fault triggering refers to the assignment of values to nodes in the circuit that are assumed to cause faults.
  • Fault propagation includes two parts, one is from the input to the output of the circuit, and the other is from the output to the input of the circuit. The reason for the latter part is that different logic gates may fix the input value based on the value of the output.
  • Figure 4 is a schematic diagram of fault excitation and propagation provided by an embodiment of the present application.
  • an output cone (output cone) is formed.
  • the involved fan-in cone (transitive fanin cone) is formed.
  • AIG graph (and inverter graph, AIG) is a directed acyclic graph widely used in logic synthesis and optimization.
  • a circuit can be represented by AND and NOT gates.
  • the original circuit data in step 210 is represented by AIG, and then the AIG is simplified. This method can achieve graph compression and optimization of logic functions, laying the foundation for subsequent fault analysis.
  • the classification prediction results of faults include measurable faults and unmeasurable faults.
  • the embodiment of the present application constructs a multi-stage generation model to implement data enhancement relying on the multi-stage generation model.
  • the multi-stage generative model is enabled to generate data similar to the local circuit involved in the real fault, thus supplementing the original circuit data.
  • a fault type classifier is trained to improve the accuracy of fault classification.
  • the fault classification prediction results can not only be used to initialize the SAT solution, but can also be used as a basis for selecting the solution method. According to different prediction results, the appropriate SAT solution method can be selected to further enhance the SAT solution performance.
  • the embodiment of the present application can return the predicted value 201 of PI for measurable faults. A sequence of suggested PIs 203 is returned for unmeasured faults, and this sequence serves as an initial suggestion for the decision sequence of the subsequent branch-and-bound method.
  • this embodiment of the present application returns a set of PI prediction values for both measurable faults and unmeasurable faults. If it is a measurable fault, a threshold will be given, and this set of predicted values will be converted into a specified assignment of 0 or 1, and this set of assignments will be used as the initialization of the SAT solution. For example, A: 0.85; B: 0.66; C: 0.21, the preset threshold is 0.7, PI greater than or equal to the preset threshold is converted to 1, and PI less than the preset threshold is converted to 0, then the converted A
  • the predicted values corresponding to , B and C are A:1; B:0; C:0.
  • suggestions for the branch sequence are returned from largest to smallest based on this set of assignments. For example, A: 0.85; B: 0.66; C: 0.21, this order serves as the initial suggestion for the decision order of the subsequent branch-and-bound method. For example, first use the test vectors A:1; Assignment of PI to determine the test vector.
  • the solution mode of the SAT solver is set according to the predicted fault type. If the fault classification result is a measurable fault, then the SAT solution mode in the embodiment of the present application is set to the SAT mode. If the fault classification result is an unmeasurable fault, , then the SAT solution mode in the embodiment of this application is set to UNSAT mode.
  • the SAT solver is used to solve the fault problem.
  • a directed graph can be constructed based on the original circuit data: each logic gate in the local circuit is regarded as a node, and the connections of different logic gates are regarded as the edges of the directed graph, with the direction from PI The direction to PO is the same.
  • the adjacency matrix is obtained according to the directed graph.
  • the types of different logic gates in the matrix are represented by the same or different weights.
  • the element 0 indicates that there is no connection relationship between the two logic gates.
  • Figure 7 is a schematic diagram of different fault propagation scales provided by the embodiment of the present application.
  • different sector-shaped areas represent the range of the number of logic gates in the sub-circuit where the fault propagates, and the percentage represents the proportion of the current-scale sub-circuit in the overall circuit.
  • faults with the number of logic gates between 0 and 200 account for 2% of the entire circuit
  • faults with the number of logic gates between 200 and 500 account for 4% of the entire circuit
  • faults with the number of logic gates between 500 and 1000 account for 2% of the entire circuit.
  • Faults with 1,000-5,000 logic gates account for 34% of the entire circuit.
  • Faults with 5,000-10,000 logic gates account for 42% of the entire circuit.
  • the embodiment builds a multi-stage generation model to enhance the data based on the characteristics of the original fault, and reduces the impact of the fault scale by decomposing nodes and predicting and merging them.
  • the multi-stage generation model constructed in the embodiment of this application can generate data similar to the local circuit involved in the real fault, thereby supplementing the original circuit data and obtaining enhanced data.
  • the subcircuit involved in Fault 1 includes 4000 logic gates
  • the multi-stage generation model can generate data similar in size and structure to the circuit involved in Fault 1.
  • the generated Fault Data 2 includes 3995 logic gates.
  • Fault data 3 includes 4005 logic gates
  • fault data 4 includes 4010 logic gates
  • the generated fault data 2, 3, and 4 have similar logical structures to fault 1.
  • the embodiment of the present application can complete screening on the data generated in step 243, add data with the same fault type as the original circuit data to the original circuit data, complete data enhancement, and train the fault type classifier on the enhanced data.
  • the SAT solver or the traditional ATPG method can be used to filter the supplementary circuit data generated by the multi-order generative model. That is, the classification label is given by the traditional ATPG method or the SAT solver. If the fault type of the original circuit data is acceptable, If faults are detected, the measurable faults are filtered out from the generated supplementary circuit data and added to the original circuit data to complete data enhancement.
  • fault 1 is a measurable fault
  • fault data 2 generated based on fault 1 is a measurable fault
  • fault data 3 is a measurable fault
  • fault data 4 is an unmeasurable fault. Then fault data 2 and fault data 3 are added to the original circuit data to complete the enhancement of fault data 1.
  • the fault type classifier can be used to predict the type of fault to be detected. Compose the fault to be tested according to 241 steps and use it as the input of the fault type classifier to obtain the fault classification prediction results. For example, the new fault to be tested can be converted into a directed graph and the corresponding neighbor The adjacency matrix corresponding to the new fault is input into the trained fault type classifier, and the classification prediction result of the fault can be obtained, that is, the fault is a measurable fault or an unmeasurable fault.
  • Figure 9 is an exemplary flow chart of fault data enhancement provided by an embodiment of the present application.
  • Figure 9 corresponds to the 243-step multi-stage generation model of Figure 5.
  • a graph convolutional network can be used to extract features from the subgraphs decomposed in step 410 to obtain the embedded representation of each subgraph. Then, according to the embedded representation data of the subgraph, a machine learning method is used to train the merged prediction model 440.
  • the merged prediction model 440 can be a fully connected neural network (full connect neural network).
  • the probability that the input circuit data can be merged to obtain the circuit data in the original circuit diagram data 400 can be obtained.
  • the subgraphs obtained by decomposing the original image A include A1, A2 and A3
  • the subgraphs obtained by decomposing the original image B include B1, B2, B3 and B4.
  • the predicted probability of the original image obtained by merging A1 and A2 is higher than that of A1. Combined with B3 to obtain the predicted probability of the original image.
  • Figure 10 is a schematic structural diagram of a generation model provided by an embodiment of the present application.
  • D1 and D2 are discriminators
  • G is the generator
  • Solver is the solver
  • f real-1 and f real-2 are the generated data judged to be true
  • f fake-1 and f fake-2 are the generated data judged to be false.
  • Data X real is the real data of the original input, that is, the subgraph data decomposed by the original circuit diagram data 400
  • X fake is the subgraph data generated by the generator G.
  • z is a random vector
  • p z refers to the distribution that z conforms to, such as Gaussian distribution.
  • X fake based on the input random vector z
  • X fake can be represented by a matrix. It should be understood that f real-1 and f real-2 appear in pairs, and f fake-1 and f fake-2 appear in pairs.
  • S1 is the output of D1 after integrating the results of f real-1 and f fake-1
  • S2 is the output of D2 after integrating the results of f real-2 and f fake-2
  • S1 and S2 are generated subgraphs 450.
  • the calculation expressions of S1 and S2 can be as shown in formula (1), and H is the information entropy of p and q.
  • H is the information entropy of p and q.
  • p(x) is the distribution of f real-1 and q(x) is the distribution of f fake-1
  • p(x) is the distribution of f fake-1
  • q(x) is f real -1 distribution
  • p(x) is the distribution of f real-2 and q(x) is the distribution of f fake-2
  • p(x) is the distribution of f fake-2 and q(x) is f real -2 distribution.
  • X is the data distribution generated by G.
  • the input of GAN is the adjacency matrix of a bipartite graph or a directed graph, and the termination condition of the output is determined by the loss function of the judge.
  • This loss function measures the difference between the generated data of the generator and the original data.
  • This application does not limit the selection of the loss function.
  • the Wasserstain loss function can be used.
  • the terrorismstain loss function is as shown in formula (2), where p r is the distribution of real data, p g is the distribution of generated data, and K is The number of nodes, that is, the number of variables, L is the dimension of each variable, is the supremum bound of the two distributions p r and p g , and W represents the iganstain distance of the two distributions.
  • the specific loss function used should not be construed as a limitation of this application.
  • the Wasserstain generative adversarial networks (WGAN) in Figure 10 can include two sub-networks:
  • D1 can adopt a structure that is dual to the generator G. It is mainly used to determine whether the generated data distribution is similar to the distribution of the input data. It should be understood that the original input real data X real has natural structural information. To judge whether the generated data distribution is similar to the distribution of the input data is to judge whether the data structures of X fake and X real are similar. The generated data judged by D1 to be similar to the distribution of the input data X real is f real-1 , and the generated data judged to be dissimilar to the distribution of the input data X real is f fake-1 .
  • D2 can adopt the NeuroSAT structure relying on the graph neural network to learn the core conflict information in SAT solving and judge the similarity between generated data and real data. Taking X fake as input, the Solver can output the generated data f real-2 that is judged to be true, and f real-2 can be a conflict vector. D2 can judge the similarity between the generated data and f real-2 , and determine the similarity with f real-2 that is less than the preset threshold as f fake-2 , and output it after integrating f real-2 and f fake-2 .
  • FIG 11 is a schematic structural diagram of a D2 discriminator provided by an embodiment of the present application.
  • D2 is the NeuroSAT structure based on graph neural network.
  • the input data 510 can be converted into an embedding representation of the graph 520, and then the embedding representation of the graph 520 can be converted into a vector representation of nodes 530, and a deep classifier 540 (fully connected neural network) can be used to classify the converted vectors.
  • output the classification prediction result 550 (SAT or UNSAT).
  • D1 and D2 do not share parameters during training, and the training order of D1 and D2 is not limited in any way.
  • the generator G is responsible for outputting subgraph data similar to the input data 510, and the discriminators D1 and D2 are responsible for minimizing the difference between the data distribution generated by the generator G and the input original data distribution.
  • the subgraph 450 generated in step 430 is input into the merged prediction model 440 trained in step 420 for merged prediction. If the output prediction probability value is greater than the preset threshold, the subgraph is merged according to the node merging process shown in Figure 8 450. Merge nodes to obtain supplementary circuit diagram data 490; if the output prediction probability value is less than or equal to the preset threshold, then use the subgraph 450 as supplementary circuit diagram data 490. It can be seen that the data enhancement in the embodiment of the present application is based on the structural characteristics of the original circuit diagram data 400 .
  • Figure 12 is a schematic structural diagram of a fault type classifier provided by an embodiment of the present application.
  • Figure 12 corresponds to the fault type classifier for fault classification prediction at step 245 in Figure 5.
  • This application does not place any restrictions on the specific selection of fault type classifiers. It should be understood that although the structure of the fault type classifier in Figure 12 is similar to D2 in the generative model, they use completely different data and undertake completely different functions, so they are two completely different networks.
  • the fault type classifier provided by the embodiment of the present application is a variant model of GNN. It can construct a bipartite graph 610 based on the local circuit data of fault excitation and propagation, and then convert the bipartite graph 610 into an embedded representation 620 of the graph. Then, the embedding representation 620 of the graph is converted into the vector representation 630 of the node, the deep classifier 540 (fully connected neural network) is used to classify the converted vector, and the classification prediction result 650 (measurable fault or unmeasurable fault) is output.
  • Figure 13 is an exemplary flow chart for training a fault type classifier provided by an embodiment of the present application.
  • Figure 13 corresponds to step 245 of Figure 5.
  • a graph neural network is used to generate a vector representation corresponding to each node.
  • Figure 14 is a schematic diagram of generating a node vector representation provided by an embodiment of the present application. Black dots can represent variable nodes, and the connections between black dots can represent constraints.
  • the input to this step is a graph data structure and the output is a vector representation of each variable node.
  • Figure 15 is a schematic diagram of a node update provided by an embodiment of the present application.
  • this embodiment of the present application divides the nodes in the training process into constraint nodes and variable nodes, and updates them respectively.
  • the coefficient matrix represents the connection relationship between variable nodes and constraint nodes, that is, which variable belongs to which constraint.
  • the update of the constraint node will update the coefficient matrix synchronously, and the update of the variable node will also update the coefficient matrix synchronously.
  • the constraint nodes can be updated first, and then the variable nodes can be updated.
  • the update of the variable node includes flipping the variable, that is, converting the variable x to the negative of the variable x Then proceed to update the variable node.
  • Node classification is done based on the vector representation of the node. It should be understood that the training process of the fault type classifier in the embodiment of this application is supervised learning, and the labels include measurable faults and unmeasurable faults. For other industrial scenarios, this classification can be further refined and divided into several specific categories. This application does not limit this.
  • this application adds an attention mechanism.
  • the attention mechanism allows processing of variable-sized inputs, focusing attention on the most relevant input parts, and can reflect the relationship between nodes and node neighbors into vectors, improving the accuracy of vectors.
  • the trained fault type classifier After completing the training, the trained fault type classifier can be obtained.
  • the fault type classifier trained in step 720 is used to classify and predict the new fault to be tested, and obtain the fault type of the fault and a set of PI prediction values.
  • the predicted value corresponding to the PI exceeding the threshold is converted to 1, otherwise it is converted to 0, and the test vector is initialized to test the fault.
  • the descending sorting results can be used as decision-making sequence suggestions for determining test vectors for new faults to be tested.
  • Figure 16 is a schematic diagram of data generation provided by the embodiment of the present application. Among them, -lit represents negative variables, and +lit represents positive variables. In the embodiment of this application, the CNF sparsity is 0.013.
  • Figure 16(a) is the original SAT expression model The generation result
  • Figure 16(b) is the generation result of the multi-stage generative model of this application iteratively trained for 10,000 times
  • Figure 16(c) is the generation result of the multi-stage generative model of this application iteratively trained for 20,000 times
  • Figure 16(d) ) is the generation result of 30,000 times of iterative training of the multi-stage generation model of this application.
  • the embodiment of this application is aimed at data enhancement in ATPG scenarios.
  • the data used in the experiment is the data of the public data set ITC’99.
  • the implementation process of the technical solution for this application is as follows:
  • (1) Construct a training set First, use SAT expressions to express the excitation and propagation of faults in the circuit one by one in the fault list. Methods for converting subcircuits into SAT expressions can include TG-Pro, PASSAT, and TIGUAN, etc. Subsequently, the bipartite graph corresponding to each SAT expression and the adjacency matrix corresponding to each bipartite graph are constructed to form the original training set. To facilitate evaluation, the embodiment of this application divides the original training set into two types: measurable faults and unmeasurable faults.
  • GAN is selected, and auto-encoder or Bayesian network can also be selected.
  • the iganstain loss function is used in the embodiment of this application.
  • bipartite graph selected in the embodiment of this application include: adjacency matrix, degrees of different nodes, classification of variable nodes and constraint nodes, etc.
  • the bipartite graphs can also be grouped according to sparsity, and each group can be trained separately, or they can be put together to complete the training.
  • the multi-stage generation model can gradually generate generated data similar to the original circuit data (real fault data).
  • the embodiment of this application selects a SAT solver or the traditional ATPG method, randomly selects 10,000 data generated by measurable faults and unmeasurable faults, divides them into ten groups from g1 to g10 according to the size of the gate, and evaluates the performance of maintaining the fault classification properties.
  • the probability,results are shown in Table 1, where k represents the unit,thousand.
  • modularity is a statistically significant variable that measures the connection relationships between nodes in a graph.
  • Modularity is a measure of the structure of a network or graph, and it measures the strength of dividing the network into modules.
  • a network with high modularity has dense connections between nodes within modules and sparse connections between nodes within different modules. Modularity is often used in optimization methods to detect community structures in networks, that is, structures with high connectivity relationships.
  • the embodiment of the present application uses a multi-stage generation model to generate data, rather than using rules or random methods to complete the generation. This generation method makes it easier to ensure the consistency of the properties of the data set, thereby facilitating the implementation of subsequent machine learning algorithms.
  • the embodiment of this application is to complete fault classification for scenarios in ATPG.
  • the execution process of this application embodiment is as follows:
  • Extract data from real circuits Extract logic cones corresponding to fault excitation and propagation from the public data set ITC’99 and industrial circuits, and group them according to the size of the logic cones. Select the SAT expressions corresponding to the logical cones with a size less than 300 as the original training set, and the logical cones with a size not exceeding 1000 as the test data set. The training set of labeled real data is used as training set 1.
  • Table 2 shows the impact of different data enhancement methods on prediction accuracy.
  • the first column represents the identification of different circuits.
  • the last three columns are: classifiers on the original data, classifiers with random data enhancement on the original data, And the classifier after data enhancement is performed on the original data using the multi-stage generative model provided in this application. It can be seen from the experimental results that the accuracy of the fault type classifier after data augmentation based on the multi-stage generative model increased from 60.4% to 88.7%, while the training model on the randomly enhanced data dropped to 59.4%, indicating that random data augmentation The nature of the obtained data is different from the original data. Not only can the randomly enhanced data not maintain the nature of the original data, it is also difficult to maintain its own nature.
  • the embodiment of the present application trains a multi-stage generative model on the randomly enhanced data, continues to realize data enhancement relying on the multi-stage generative model, and improves the classification accuracy from 60.4% to 88.7%. Therefore, the embodiments of the present application prove the effectiveness of the technical solution of the present application.
  • Table 3 shows the impact of different data enhancement methods on fault analysis time in SAT-based ATPG.
  • the embodiment of this application integrates the multi-stage generation model and subsequent fault type classifier into SAT-based ATPG.
  • the impact on the solving time of the SAT expression, and ATPG represent the impact on the solving time of the end-to-end ATPG system.
  • the first column represents the identification of different circuits.
  • the "negative sign” represents the proportion of reduced running time (i.e., improved solution performance), while the "positive sign” represents the proportion of increased running time.
  • the fault type classifier based on the multi-stage generative model can not only improve the accuracy of fault type prediction, but also reduce the solution time by 34.79% on average, and 7.43% for ATPG. Solution time. Both of these ratios of reducing solution time are much higher than the results without any data augmentation and the results with random data augmentation.
  • Table 4 shows the fusion of multi-stage generative models and subsequent fault type classifiers into SAT-based ATPG.
  • the fault type classification results provided by the embodiments of this application can not only be used to initialize SAT, but can also be used as a basis for selecting a solution method. According to different prediction results, an appropriate solution method can be selected to further enhance the solution performance.
  • the above describes the chip fault analysis method according to the embodiment of the present application.
  • the method provided by the present application can be used as an independent fault analysis module to serve design for testing (DFT) engineers, complete fault analysis before fault detection, and assist Circuit inspection and design.
  • the method provided by this application is embedded into the ATPG module of the existing EDA process, as shown in Figure 2, for example.
  • the ATPG process is executed, faults are initially screened and classified, and the prediction results are decoded for different types of faults: for measurable faults, the predicted assignments of different PIs are returned to reduce the search space; for unmeasurable faults, the predictions of different logic gates are returned Sort results.
  • the multi-stage generation model provided by this application can serve ATPG scenarios as an independent solution for data enhancement.
  • the fault type classifier provided in this application can also be used as an independent solution and embedded in other data-driven analysis scenarios to provide a preliminary screening of fault classification for ATPG scenarios.
  • Embodiments of the present application also provide a computer storage medium.
  • Program instructions are stored in the computer storage medium.
  • the program When executed, it may include the chips in the corresponding embodiments of Figures 2, 3, 5, and 8-15. Some or all steps of a failure analysis method.
  • FIG. 17 is an example structural diagram of a computer device 1000 provided by an embodiment of the present application.
  • the computer device 1000 includes an acquisition module 1010 and a processing module 1020.
  • the acquisition module 1010 is used for original circuit data and executes 110 in the method of Figure 2.
  • Figure 18 is a structural example diagram of another computer device 1300 provided by an embodiment of the present application.
  • Computer device 1300 includes a processor 1302, a communication interface 1303, and memory 1304.
  • One example of computer device 1300 is a chip.
  • Another example of computer device 1300 is a computing device.
  • the methods disclosed in the above embodiments of the present application can be applied to the processor 1302 or implemented by the processor 1302.
  • the processor 1302 can be a central processing unit (CPU), or other general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or an on-site processor.
  • a general-purpose processor can be a microprocessor or any conventional processor, etc.
  • each step of the above method can be completed by instructions in the form of hardware integrated logic circuits or software in the processor 1302 .
  • Each method, step and logical block diagram disclosed in the embodiment of this application can be implemented or executed.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the steps of the method disclosed in conjunction with the embodiments of the present application can be directly implemented by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor.
  • Memory 1304 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically removable memory. Erase electrically programmable read-only memory (EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double data rate SDRAM double data rate SDRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous link dynamic random access memory
  • direct rambus RAM direct rambus RAM
  • the executable code in the memory 1304 is used to implement the methods shown in Figures 2, 3, 5, and 8-15.
  • the processor 1302 reads the executable code in the memory 1304 to execute Figures 2 and 3. , the method shown in Figure 5 and Figure 8-15.
  • example computer program product 1400 is provided using signal bearing medium 1401.
  • the signal bearing medium 1401 may include one or more program instructions 1402, which when executed by one or more processors may provide the methods described above with respect to FIGS. 2, 3, 5, and 8-15. function or part of the function.
  • FIGS. 2, 3, 5, 8-15 one or more features thereof may be performed by one or more instructions associated with signal bearing medium 1401.
  • signal bearing media 1401 may include computer readable media 1403 such as, but not limited to, a hard drive, a compact disk (CD), a digital video disc (DVD), a digital tape, memory, read only memory (read-only storage memory), -only memory, ROM) or random access memory (random access memory, RAM), etc.
  • signal bearing media 1401 may include computer recordable media 1404 such as, but not limited to, memory, read/write (R/W) CDs, R/W DVDs, and the like.
  • signal bearing medium 1401 may include communication media 1405 such as, but not limited to, digital and/or analog communication media (eg, fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code. .
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code. .

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Abstract

本申请实施例提供了一种芯片故障分析方法，其中，该方法包括：获取故障影响的原始电路数据，根据原始电路数据生成与原始电路数据近似的补充电路数据；根据原始电路数据和补充电路数据训练故障类型分类器；根据所述故障类型分类器和待检测的第一故障，确定所述第一故障的测试向量。本申请技术方案能够根据原始电路数据和补充电路数据来训练故障类型分类器，并根据故障分类结果指导分析芯片故障，可以提高芯片故障分析的效率和准确率。

Description

芯片故障分析方法和装置
本申请要求于2022年06月15日提交中国专利局、申请号为202210671592.4、申请名称为“芯片故障分析方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及集成电路测试技术领域，具体涉及一种芯片故障分析方法和装置。
背景技术
得益于半导体先进工艺节的高速发展，在过去的几十年中，芯片尺寸进一步缩小，同时功耗大大降低。芯片工艺进入到亚微米(sub-micron)时代以来，微小的工艺尺寸对复杂版图形状的刻蚀造成了极大的影响。因此，芯片测试相关的电子设计自动化(electronic design automation，EDA)工具变得越来越重要。在整个EDA工具链中，自动测试向量生成(automatic-test-pattern-generation，ATPG)是极为重要的一个环节。它广泛应用于芯片生产测试中对逻辑电路的测试和故障分析。
现有的芯片故障分析方法在执行完电路解析后，直接进入ATPG计算模块，逐一的完成目标故障列表(fault list)上的每个故障的检测。这种方式的计算效率和准确率都很低，会浪费大量计算资源。
因此，如何构建一种高效的芯片故障分析方法是一个亟待解决的技术问题。
发明内容
本申请实施例提供一种芯片故障分析方法和装置，能够提高芯片故障分析的效率和准确率。
第一方面，提供了一种芯片故障分析方法，该方法包括：获取第一电路数据，所述第一电路数据包括多个电路节点及所述多个电路节点之间的关系，所述多个电路节点包括被电路中的故障影响的电路节点；根据所述第一电路数据，生成第二电路数据，所述第二电路数据与所述第一电路数据的相似度大于第一预设阈值；根据所述第一电路数据和所述第二电路数据训练故障类型分类器；根据所述故障类型分类器和待检测的第一故障，确定所述第一故障的测试向量。
应理解，电路节点包括电路中各种类型的逻辑门，逻辑门包括“与”门，“或”门，“非”门，“异或”等。电路节点之间的关系包括逻辑门之间的关系。
应理解，可以根据多个故障激发和传播所影响的局部电路来构造第一电路数据。示例性的，可以将局部电路中每个逻辑门作为一个节点，不同逻辑门的连接当作有向图的边，方向与从主要输入(primary input，PI)到主要输出(primary output，PO)的方向一致。同时，依照有向图得到邻接矩阵，矩阵中不同逻辑门的类型表示成相同或者不同的权重， 矩阵中的元素0表示两个逻辑门之间没有连接关系。可选的，也可以将局部电路转换成布尔可满足性(boolean satisfactory，SAT)表达式，然后将SAT表达式转换成二部图，图的连接关系表示了故障在激发和传播中的隐含连接特征。
应理解，第二电路数据为根据第一电路数据生成的与第一电路数据类似的数据。示例性地，可以通过生成对抗网络(generative adversarial networks，GAN)来生成第二电路数据。也可以根据本申请构建的多阶段生成模型来生成数据。第一电路数据可以看作是原始电路数据，第二电路数据可以看作是第一电路数据的补充电路数据。根据所述第一电路数据和所述第二电路数据训练故障类型分类器，该故障类型分类器用于预测待检测的第一故障的故障类型。示例性的，故障类型可以包括可测故障和不可测故障，故障类型可以进一步划分，具体分成几类本申请对此不做限制。
应理解，本申请针对不同的故障类型都会返回第一序列，第一序列也可以称为第一向量，第一序列包括一组PI的预测值。本申请根据故障类型和第一序列中的预测值来确定测试向量，并根据该测试向量来对故障电路进行测试。
本申请提供了一种芯片故障分析方法，能够对原始电路数据进行数据增强，获得补充电路数据，然后根据原始电路数据和补充电路数据来训练故障类型分类器，并根据故障分类结果指导芯片故障分析，提高芯片故障分析的效率和准确率。
结合第一方面，在第一方面的某些实现方式中，所述根据所述第一电路数据，生成第二电路数据，包括：将所述第一电路数据进行分解，得到多个第一子电路数据；根据所述多个第一子电路数据，生成多个第二子电路数据，所述多个第一子电路数据与所述多个第二子电路数据一一对应，每个第二子电路数据是根据所对应的第一子电路数据生成的，彼此对应的第二子电路数据与第一子电路数据之间的相似度大于第二预设阈值；根据合并预测模型和所述多个第二子电路数据，确定所述第二电路数据，所述合并预测模型用于预测输入的电路数据能够合并得到所述第一电路数据中的电路数据的概率，所述合并预测模型是根据所述第一电路数据和所述多个第一子电路数据训练得到的。
应理解，在ATPG场景下的故障数据有非常大的结构多样性，即使针对同一个电路，不同的故障的激发和传播所涉及到的逻辑锥的拓扑结构的差别可能非常大，因此本申请通过将第一电路数据进行分解、增强和预测合并来降低故障规模带来的影响。
可选的，可以根据所述多个电路节点之间的关系对所述第一电路数据进行分解，得到所述多个第一子电路数据。
第二子电路数据为根据第一子电路数据生成的与第一子电路数据类似的数据，示例性地，可以通过GAN来生成第二子电路数据。
示例性的，可以基于第一电路数据和第一子电路数据来训练合并预测模型，根据合并预测模型可以得到输入的电路数据能够合并得到第一电路数据中电路数据的概率。示例性地，第一电路数据A分解得到的第一子电路数据包括A1、A2和A3，第一电路数据B分解得到的第一子电路数据包括B1、B2、B3和B4，则A1和A2合并得到第一电路数据的预测概率要高于A1和B3合并得到第一电路数据的预测概率。
本申请提供了一种芯片故障分析方法，能够将原始电路数据进行分解后再进行数据增强，然后再将增强后的数据进行预测合并来获得补充电路数据，可以降低故障规模带来的影响，进而提高芯片故障分析的效率和准确率。
结合第一方面，在第一方面的某些实现方式中，所述根据合并预测模型和所述多个第二子电路数据，确定所述第二电路数据，包括：根据所述合并预测模型和所述多个第二子电路数据，确定第一预测概率值，所述第一预测概率值为预测所述第二子电路数据能够合并得到所述第一电路数据中的电路数据的概率值；若所述第一预测概率值大于第三预设阈值，则根据所述多个第二子电路数据中电路节点之间的关系对所述多个第二子电路数据进行合并，得到所述第二电路数据；若所述第一预测概率值小于或者等于所述第三预设阈值，则将所述多个第二子电路数据作为所述第二电路数据。
将第二子电路数据输入到训练得到的合并预测模型，得到第一预测概率值，第一预测概率值为第二子电路数据能够合并得到所述第一电路数据中的电路数据的概率。
若第一预测概率值大于第三预设阈值，则根据第二子电路数据中电路节点之间的关系对第二子电路数据进行合并；若第一预测概率值小于或者等于第三预设阈值，则将第二子电路数据作为第二电路数据。
本申请提供了一种芯片故障分析方法，能够将原始电路数据进行分解后再进行数据增强，然后再将增强后的数据进行预测合并来获得补充电路数据，可以降低故障规模带来的影响，进而提高芯片故障分析的效率和准确率。
结合第一方面，在第一方面的某些实现方式中，所述根据所述故障类型分类器和待检测的第一故障，确定所述第一故障的测试向量，包括：根据所述故障类型分类器和待检测的所述第一故障，确定所述第一故障的故障类型和第一序列，所述第一序列包括所述第一故障所在电路中全部或者部分输入的预测值；根据所述第一故障的故障类型和所述第一序列，确定所述第一故障的所述测试向量。
示例性的，故障类型可以包括可测故障和不可测故障，故障类型可以进一步划分，具体分成几类本申请对此不做限制。
应理解，本申请可以针对不同的故障类型都会返回第一序列，第一序列也可以称为第一向量，第一序列包括一组PI的预测值。本申请根据故障类型和第一序列中的预测值来确定测试向量，并根据该测试向量来对故障电路进行测试。
本申请实施例提供了一种芯片故障分析方法，能够对原始电路数据进行数据增强，获得补充电路数据，然后根据原始电路数据和补充电路数据来训练故障类型分类器，并根据故障分类结果指导芯片故障分析，提高芯片故障分析的效率和准确率。
结合第一方面，在第一方面的某些实现方式中，所述根据所述第一故障的故障类型和所述第一序列，确定所述第一故障的所述测试向量，包括：若所述第一故障的故障类型为可测故障，将所述第一序列中的所述预测值根据第四预设阈值转换为指定赋值，根据所述转换后的所述第一序列确定所述第一故障的所述测试向量；若所述第一故障的故障类型为不可测故障，根据所述第一序列中所述预测值的降序排序结果确定所述第一故障的所述测试向量。
应理解，本申请实施例针对可测故障和不可测故障都会返回第一序列，第一序列包括一组PI预测值。如果是可测故障，则会给定一个阈值，这组预测值会转换成指定赋值，根据转换后的赋值来初始化测试向量。
可选的，若所述预测值大于或者等于所述第四预设阈值，可以将所述预测值转换为1，若所述预测值小于所述第四预设阈值，可以将所述预测值转换为0。也可以在预测值大于 或者等于所述第四预设阈值时，将所述预测值转换为0，在所述预测值小于所述第四预设阈值时，将所述预测值转换为1。本申请对此不作限定。
示例性地，第一故障为可测故障，第一序列为A:0.85；B:0.66；C:0.21，A、B和C为PI。第四预设阈值为0.7，大于等于该预设阈值的预测值转换为1，小于该预设阈值的预测值转换为0，则转换后的A、B、C对应的赋值为A:1；B:0；C:0。将该组赋值作为第一故障的测试向量。
如果第一故障为不可测故障，则根据这组PI预测值按照由大到小返回对电路分支顺序的建议。示例性地，A:0.85；B:0.66；C:0.21，该降序排序结果可以作为确定第一故障测试向量的决策顺序建议。例如，先利用测试向量A:1；B:0；C:0来进行故障测试，再利用测试向量A:1；B:0；C:1来进行故障测试，即优先改变预测值较低的PI的赋值来确定测试向量。
本申请实施例提供了一种芯片故障分析方法，根据故障的分类结果来指导进行ATPG计算，该故障类型分类结果不仅可以用于初始化测试向量，同时还可以作为求解方法选择的依据，根据不同的预测结果，选择合适的求解方法，进一步增强求解性能。
结合第一方面，在第一方面的某些实现方式中，根据所述第一电路数据和所述第二电路数据训练故障类型分类器，包括：确定第三电路数据，所述第三电路数据包括与所述第一电路数据故障类型相同的所述第二电路数据；根据所述第一电路数据和所述第三电路数据，训练所述故障类型分类器。
示例性地，若第一电路数据的故障类型为可测故障，则可以筛选出第二电路数据中故障类型为可测故障的电路数据作为补充电路数据。若第一电路数据的故障类型为不可测故障，则可以筛选出第二电路数据中故障类型为不可测故障的电路数据作为补充电路数据。该筛选出来的补充电路数据即为第三电路数据，根据第一电路数据和第三电路数据来训练故障类型分类器。
本申请实施例提供了一种芯片故障分析方法，能够对原始电路数据进行数据增强，获得补充电路数据，然后对补充电路数据的故障类型进行筛选，根据原始电路数据和筛选后的与原始电路数据同类型的补充电路数据来训练故障类型分类器，并根据故障分类结果指导芯片故障分析，提高芯片故障分析的效率和准确率。
结合第一方面，在第一方面的某些实现方式中，所述获取第一电路数据，包括：获取目标故障列表中的故障所影响的多个局部电路，所述多个局部电路包括多个逻辑门和多个电路连线；根据所述多个局部电路构建所述第一电路数据。
应理解，目标故障列表包括电路中逻辑门的标识(identity document，ID)和线路的ID。故障激发指的是对电路中假定的导致故障的节点赋值。故障传播包括两部分，一部分是从电路的输入到输出，另一部分是从电路的从输出到输入。
示例性地，可以读取目标故障列表，从其中挑选一个故障，在电路中找到该故障对应的输出锥以及涉及的扇入锥，即可得到该故障的激发和传播所影响的局部电路。根据目标故障列表中的多个故障得到的多个被影响的局部电路即为本申请中的多个局部电路。
根据所述多个局部电路构建第一电路数据可以有多种方式，示例性的，可以将局部电路中每个逻辑门作为一个节点，不同逻辑门的连接当作有向图的边。同时，依照有向图得到邻接矩阵，矩阵中不同逻辑门的类型表示成相同或者不同的权重，矩阵中的元素0表示 两个逻辑门之间没有连接关系。可选的，也可以将局部电路转换成SAT表达式，然后将SAT表达式转换成二部图，图的连接关系表示了故障在激发和传播中的隐含连接特征。
本申请实施例提供了一种芯片故障分析方法，能够对原始电路数据进行数据增强，获得补充电路数据，然后根据原始电路数据和补充电路数据来训练故障类型分类器，并根据故障分类结果指导芯片故障分析，提高芯片故障分析的效率和准确率。
第二方面，本申请实施例提供一种计算机装置，该计算机装置包括用于实现第一方面或第一方面的任一种可能的实现方式的单元。
第三方面，本申请实施例提供一种计算机装置，该计算机装置包括处理器，该处理器用于与存储器耦合，读取并执行该存储器中的指令和/或程序代码，以执行第一方面或第一方面的任一种可能的实现方式。
第四方面，本申请实施例提供一种芯片系统，该芯片系统包括逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过该输入/输出接口传输数据，以执行第一方面或第一方面任一种可能的实现方式。
第五方面，本申请实施例提供一种计算机可读存储介质，该计算机可读存储介质存储有程序代码，当该计算机存储介质在计算机上运行时，使得计算机执行如第一方面或第一方面的任一种可能的实现方式。
第六方面，本申请实施例提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行如第一方面或第一方面的任一种可能的实现方式。
附图说明
图1是本申请实施例提供的一种数字电路的示意图。
图2是本申请实施例提供的一种芯片故障分析方法的示例性流程图。
图3是本申请实施例提供的一种芯片故障分析的示例性流程图。
图4是本申请实施例提供的一种故障激发和传播的示意图。
图5是本申请实施例提供的一种故障分析的示例性流程图。
图6是本申请实施例提供的一种二部图的示意图。
图7是本申请实施例提供的一种不同故障传播规模的示意图。
图8是本申请实施例提供的一种节点分解和预测合并的示意图。
图9是本申请实施例提供的一种故障数据增强的示例性流程图。
图10是本申请实施例提供的一种生成模型的结构示意图。
图11是本申请实施例提供的一种D2判别器的结构示意图。
图12是本申请实施例提供的一种故障类型分类器的结构示意图。
图13是本申请实施例提供的一种训练故障类型分类器的示例性流程图。
图14是本申请实施例提供的一种生成节点向量表示的示意图。
图15是本申请实施例提供的一种节点更新的示意图。
图16是本申请实施例提供的一种数据生成的示意图。
图17是本申请实施例提供的一种计算机装置的结构示例图。
图18是本申请实施例提供的另一种计算机装置的结构示例图。
图19是本申请实施例提供的一种计算机程序产品的示例图。
具体实施方式
在过去的几十年中，半导体技术已经高速发展并渗透到人们生活的方方面面，包括移动电话、电子门锁、智能手表、平板电脑等。总的来说，这种变化得益于半导体先进工艺节的高速发展。先进的工艺往往带来很多优点，例如，集成度更高，从而单位面积的芯片可以完成更多更复杂的功能；芯片尺寸进一步缩小，同时功耗大大降低。但是与此同时，也由于其更加不易控制和伴随规模更大的集成电路等特点，都给芯片的测试环节带来了更大的困难，因此良率爬坡显得更加重要。进入到亚微米(sub-micron)时代以来，特别是当芯片工艺节点发展到28nm以下，微小的工艺尺寸对复杂版图形状的刻蚀造成了极大的影响，在芯片流片生产的初期，良率甚至常常会下探到30％以下。因此，芯片测试相关的EDA工具变得越来越重要，以完成高效的芯片测试和实现快速的良率攀升。另一方面，人工智能的崛起也带动了如智能医疗、数字金融和自动驾驶等新兴技术产业的蓬勃发展。这些新兴产业的发展离不开高质量、高安全性的片上系统(system on a chip，SOC)。
在整个EDA工具链中，自动测试向量生成(automatic-test-pattern-generation，ATPG)是极为重要的一个环节。具体来说，ATPG是应用相应核心算法产生测试向量的过程，其为芯片的流程化测试提供精良的“弹药”，是芯片测试EDA工具链的绝对核心。它广泛应用于芯片生产测试中对逻辑电路的测试。ATPG算法研究的是，针对芯片中可能出现的物理故障(physical defect)进行逻辑建模，并对建模后的逻辑故障(logic faults)产生有针对性的测试向量。由于其在芯片测试领域的重要性，ATPG核心算法也从一定程度上决定了各大EDA厂商芯片测试EDA工具链的核心竞争力。
为便于理解本申请实施例，首先对本申请中涉及的一些定义做简单说明。
1.电子设计自动化(electronic design automation，EDA)：是指利用计算机辅助设计软件，来完成超大规模集成电路芯片的功能设计、综合、验证、物理设计(包括布局、布线、版图、设计规则检查等)等流程的设计方式。
2.自动测试向量生成(automatic-test-pattern-generation，ATPG)：自动测试向量生成是EDA流程的一个重要组成部分。其主要功能是在数字电路的测试环节，针对输入的序列完成可以区分正确电路和由于缺陷引起的故障电路行为的测试向量。生成的向量可以用于辅助和测试半导体器件的生产，或帮助定位故障产生的原因。
3.布尔可满足性问题(boolean satisfactory，SAT)：用来解决在给定的真值方程式中，是否存在一组变量赋值，使问题为可满足。如果存在这样的赋值，这个公式就是可满足的，否则就是不可满足的。布尔可满足性问题属于决定性问题，也是第一个被证明属于多项式复杂程度的非确定性(non-deterministic polynomial，NP)完全的问题。
4.合取范式(conjunctive normal form，CNF)：在布尔逻辑中，如果一个公式是一个或多个子句的连接，它是总和或“与”的乘积，则称为合取表达式。CNF中的公式可以包含的命题连接词包括与(and)，或(or)，和非(not)。当代SAT求解器处理的表达式形式均是CNF。
5.生成对抗网络(generative adversarial networks，GAN)：一种生成网络模型。在该框架中，同时训练两个模型，一个捕获数据分布的生成模型G，一个判别模型D。估计 样本来自训练数据而不是G的概率。G的训练过程是最大化D出错的可能性。此框架可以简单看作是两个网络的博弈过程。
6.图神经网络(graph neural networks，GNN)：指使用神经网络来学习图结构数据，提取和发掘图结构数据中的特征和模式。例如，学习图中节点、边或者子图的低维向量空间表示。
7.可测故障：指的是可以找到一组测试向量使得正确电路和错误电路(带故障的电路)的输出不相等，从而可以识别出故障。对应到SAT上，则是SAT问题，即构成的数学模型存在一组或者更多的解。
8.不可测故障：任何输入都不可以区分正确和错误电路。对应SAT上，则是UNSAT问题，即构成的数学模型无解。应理解，不可测故障不等于不存在故障。
9.分支定界法：通常把全部可行解空间反复地分割为越来越小的子集，称为分支；对每个子集内的解集计算一个目标下界(对于最小值问题)，称为定界。在每次分枝后，凡是界限超出已知可行解集目标值的那些子集不再进一步分枝，这样，许多子集可不予考虑，称为剪枝。
10.有向图：具有方向性的图，由一组顶点和一组有方向的边组成，每条有方向的边都连着一对顶点。
11.邻接矩阵：表示顶点之间相邻关系的矩阵。
12.有向无环图(directed acyclic graph，DAG)：如果一个有向图无法从任意顶点出发经过若干条边回到该点，则这个图就是有向无环图。
13.逻辑锥(logical cone)：逻辑锥是一组可驱动比较点的信号，它有多个输入(基本输入，状态点)和一个输出(基本输出，状态点)，也可以包含其他逻辑锥。
14.逻辑门：逻辑门(logic gates)是在集成电路(integrated circuit)上的基本组件。简单的逻辑门可由晶体管组成。这些晶体管的组合可以使代表两种信号的高低电平在通过它们之后产生高电平或者低电平的信号。高、低电平可以分别代表逻辑上的“真”与“假”或二进制当中的1和0，从而实现逻辑运算。
14.扇入：单个逻辑门能够接受的数字信号输入最大量。
15.图嵌入(graph embedding)：将图的节点表示成一个低维向量空间，同时保留网络的拓扑结构和节点信息，以便在后续的图分析任务中可以直接使用机器学习算法。
16.随机游走(random walk，RW)，又称随机游动或随机漫步，是一种数学统计模型，它是一连串的轨迹所组成，其中每一次都是随机的。它能用来表示不规则的变动形式，是记录随机活动的基本统计模型。
17.上确界：一个实数集合A，若有一个实数M，使得A中任何数都不超过M，那么就称M是A的一个上界。在所有上界中如果有一个最小的上界，就称为A的上确界。
18.主要输入(primary input，PI)：电路故障所影响的输入，可以是电路的全部输入，也可以是电路的部分输入。
19.主要输出(primary output，PO)：电路故障所影响的输出，可以是电路的全部输出，也可以是电路的部分输出。
一般来说，ATPG的计算方法分成两类：
一类是结构化ATPG算法。这类ATPG算法主要包括两部分任务，第一是激活目标故 障，第二是将目标故障的故障效应传递到至少一个观测点。为了达成这两个目的，结构化ATPG算法不断的在电路中决定电路节点(net)应有的状态。因此，在某些情况下，可能会面临着电路当前所需的状态不唯一，这意味着需要做判决来决定电路的状态。根据判决发生的地点不同，目前有两类主流的结构化ATPG方法，一类以D算法(D-algorithm)为代表，该类算法的特点是在逻辑值需求处(判决发生地)做判决；另一类是以路径导向决策法(path oriented decision making，PODEM)为代表，该类算法将需求回溯到主要输入(primary input，PI)，并在PI做判决。
另一类是利用SAT的方法。与D算法或者PODEM算法不同的是，SAT方法需要先将电路转化成布尔表达式CNF。CNF表达式中，变量和变量的非都称作文字(literal)，不同的文字通过与或非等逻辑符号连接起来构成子句(clause)，也可以称为约束。而后利用SAT求解器对CNF求解，如果解是SAT，则表示目标故障是可检测的，得到的解即测试向量。如果解是UNSAT，则表示目标故障不可检测的。给定时间内无法判断的错误则被认为是未完成检测故障(aborted faults)或者是未观察到故障(unobserved faults)。由于整体求解过程是依托符号表达式CNF。因此，SAT方法需要考虑将电路转换成CNF的时间。
两种算法的主要区别在于D算法的搜索和推理更多的考虑到电路的结构信息，而SAT则更多的依托CNF表达式。从理论上来讲，虽然符号计算具有更全局和广泛的推理能力，但是考虑到计算性能，SAT方法更适合在接近全局遍历的难例的求解和判断。
为了提高ATPG的计算效率，传统技术中在ATPG计算流程执行前加入电路分析模块，意在利用电路的结构信息为后续决策提供帮助。不过，现有技术中的电路分析模块往往直接利用电路的静态特征，这种故障分析的效率非常低。
下面将结合附图，对本申请实施例中的技术方案进行描述。显然，所描述的实施例是本申请的一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本申请保护的范围。
图1是本申请实施例提供的一种数字电路的示意图。
用数字信号完成对数字量进行算术运算和逻辑运算的电路称为数字电路，或数字系统。由于它具有逻辑运算和逻辑处理功能，所以又称数字逻辑电路。芯片的生产测试中主要包括对逻辑电路的测试。其中，A、B、C为电路的输入，K为电路的输出。L1、L2、L3、L4和L5为线路。G1为或门，G2为与门，G3为非门，G4为或非门。
示例性地，若A为1、B为0、C为1，则根据逻辑计算结果，L1、L2、L3为1，L4为1，L5为0，L4和L5经过或非门G4得到的结果K为0。
图2是本申请实施例提供的一种芯片故障分析方法的示例性流程图。
110，获取第一电路数据。
第一电路数据包括多个故障影响的多个电路节点及所述多个电路节点之间的关系，示例性地，可以根据多个故障激发和传播所影响的局部电路来构造第一电路数据，将局部电路中每个逻辑门作为一个节点，不同逻辑门的连接当作有向图的边。同时，依照有向图得到邻接矩阵，矩阵中不同逻辑门的类型表示成相同或者不同的权重，矩阵中的元素0表示两个逻辑门之间没有连接关系。可选的，也可以将局部电路转换成SAT表达式，然后将SAT表达式转换成二部图，图的连接关系表示了故障在激发和传播中的隐含连接特征。
120，根据第一电路数据生成第二电路数据。
应理解，第二电路数据为根据第一电路数据生成的与第一电路数据类似的数据。第一电路数据可以看作是原始电路数据，第二电路数据可以看作是第一电路数据的补充电路数据。示例性地，可以通过GAN来生成第二电路数据。
130，训练故障类型分类器。
根据所述第一电路数据和所述第二电路数据训练故障类型分类器，该故障类型分类器用于预测待检测的第一故障的故障类型。示例性的，故障类型可以包括可测故障和不可测故障，故障类型可以进一步划分，具体分成几类本申请对此不做限制。
140，确定第一故障的测试向量。
根据故障类型分类器来判断第一故障的故障类型。应理解，本申请实施例针对不同的故障类型都会返回第一序列，第一序列也可以称为第一向量，第一序列包括一组PI的预测值。本申请根据故障类型和第一序列中的预测值来确定测试向量，并根据该测试向量来对故障电路进行测试。
示例性地，第一故障为可测故障，第一序列为A:0.85；B:0.66；C:0.21，A、B和C为PI。第四预设阈值为0.7，大于等于该预设阈值的预测值转换为1，小于该预设阈值的预测值转换为0，则转换后的A、B、C对应的赋值为A:1；B:0；C:0。将该组赋值作为第一故障的测试向量。
如果第一故障为不可测故障，则根据这组PI预测值按照由大到小返回对电路分支顺序的建议。示例性地，A:0.85；B:0.66；C:0.21，该降序排序结果可以作为确定第一故障测试向量的决策顺序建议。例如，先利用测试向量A:1；B:0；C:0来进行故障测试，再利用测试向量A:1；B:0；C:1来进行故障测试，即优先改变预测值较低的PI的赋值来确定测试向量。
图3是本申请实施例提供的一种芯片故障分析的示例性流程图。
210，故障激发和传播。
读取目标故障列表200，从其中挑选一个故障，在电路中找到故障对应的输出锥(output cone)以及涉及的扇入锥(transitive fanin cone)，得到故障的激发和传播所影响的局部电路。
应理解，目标故障列表200包括电路中逻辑门的标识(identity document，ID)和线路的ID。故障激发指的是对电路中假定的导致故障的节点赋值。故障传播包括两部分，一部分是从电路的输入到输出，另一部分是从电路的输出到输入。后一部分的原因是不同逻辑门可能会根据输出的值，固定了输入值。
图4是本申请实施例提供的一种故障激发和传播的示意图。从故障点(fault site)330出发，沿着从输入到输出不同逻辑门的连接关系传播到PO，则构成了输出锥(output cone)。从相关的PO出发，沿着从输出到输入逻辑门的连接关系传播到PI，则构成了涉及的扇入锥(transitive fanin cone)。
根据目标故障列表200遍历整个电路，得到每个故障的激发和传播所涉及的局部电路，将这些局部电路作为原始电路数据。
220，逻辑优化。
AIG图(and inverter graph，AIG)是一种广泛应用于逻辑综合与优化的有向无环图， 可以通过与门和非门来表示电路。将210步骤中的原始电路数据通过AIG来表示，然后再对AIG进行化简。这种方式可以实现图的压缩和逻辑函数的优化，为后续的故障分析奠定基础。
230，将电路转换为CNF。
在SAT中，任务是确定命名公式在对其变量进行某种赋值的情况下是否可以评估为真。为了利用SAT确定电路中的故障，首先需要把电路转为SAT可以接受的输入形式。其中，将电路转为CNF是比较方便的编码方式。
240，故障分类预测。
在ATPG的计算流程执行之前进行，返回故障的初筛分类。故障的分类预测结果包括可测故障和不可测故障。
本申请实施例构造多阶段生成模型，实现依托多阶段生成模型的数据增强。使得多阶段生成模型生成与真实故障所涉及到的局部电路相似的数据，从而补充原始电路数据。在多阶段生成模型实现数据增强后，训练故障类型分类器，从而提升故障分类的准确率。
250，自适应方法选择。
故障的分类预测结果不仅可以用于SAT求解的初始化，同时还可以作为选择求解方法的依据，根据不同的预测结果，选择合适的SAT求解方法，进一步增强SAT求解性能。本申请实施例可以针对可测故障返回PI的预测值201。针对不可测故障返回建议PI的排序203，该顺序作为后续分支定界方法的决策顺序的初始建议。
以图1为例，本申请实施例针对可测故障和不可测故障都会返回一组PI的预测值。如果是可测故障，则会给定一个阈值，这组预测值会转换成指定赋值0或者1，将这组赋值作为SAT解的初始化。示例性地，A:0.85；B:0.66；C:0.21，预设阈值为0.7，大于等于该预设阈值的PI转换为1，小于该预设阈值的PI转换为0，则转换后的A、B、C对应的预测值为A:1；B:0；C:0。
如果是不可测故障，则根据这组赋值按照由大到小返回对分支顺序的建议。示例性地，A:0.85；B:0.66；C:0.21，该顺序作为后续分支定界方法的决策顺序的初始建议。例如，先利用测试向量A:1；B:0；C:0来进行故障测试，再利用测试向量A:1；B:0；C:1来进行故障测试，即优先改变预测值较低的PI的赋值来确定测试向量。
260，设置SAT求解模式。
根据预测得到的故障类型来设置SAT求解器的求解模式，若故障的分类结果为可测故障，则将本申请实施例中的SAT求解模式设置为SAT模式，若故障的分类结果为不可测故障，则将本申请实施例中的SAT求解模式设置为UNSAT模式。
270，解决故障。
根据260步骤中设置的不同求解模式，利用SAT求解器来对故障问题求解。
图5是本申请实施例提供的一种故障分析的示例性流程图。图5对应图3的240步骤。
241，根据原始电路数据构图。
根据目标故障列表200遍历电路，得到每个故障的激发和传播所涉及的局部电路，将这些局部电路作为原始电路数据。
可选的，可以选择多种构图方法。示例性的，可以根据原始电路数据构建有向图：将局部电路中每个逻辑门作为一个节点，不同逻辑门的连接当作有向图的边，方向与从PI 到PO的方向一致。同时，依照有向图得到邻接矩阵，矩阵中不同逻辑门的类型表示成相同或者不同的权重，元素0表示两个逻辑门之间没有连接关系。
可选的，也可以将子电路转换成SAT表达式，转换方法包括具有有效传播约束的基于SAT的测试模式生成(SAT-based test pattern generation with efficient propagation constraints，TG-Pro)、PASSAT方法、TIGUAN方法等。然后将SAT表达式转换成二部图(也可以称为二分图)，图6是本申请实施例提供的一种二部图的示意图。其中变量(也可以称为文字)和约束均用节点表示，a、b、c、d为变量节点，约束1、约束2、约束3为约束节点。如果该变量在该约束中存在则连边。二部图是一个无向图，图的连接关系表示了故障在激发和传播中的隐含连接特征。
243，构建多阶段生成模型增强数据。
图7是本申请实施例提供的一种不同故障传播规模的示意图。其中，不同扇形区域表示故障传播的子电路中逻辑门个数的范围，百分比表示的是当前规模的子电路占整体电路的比例。其中，逻辑门个数在0-200的故障占整体电路的2％，逻辑门个数在200-500的故障占整体电路的4％，逻辑门个数在500-1000的故障占整体电路的8％，逻辑门个数在1000-5000的故障占整体电路的34％，逻辑门个数在5000-10000的故障占整体电路的42％，逻辑门个数在10000以上的故障占整体电路的10％。可以看出，在ATPG场景下的故障数据有非常大的结构多样性，即使针对同一个电路，不同的故障的激发和传播所涉及到的逻辑锥的拓扑结构的差别可能非常大，因此本申请实施例根据原有故障的特征来构建多阶段生成模型增强数据，通过将节点进行分解和预测合并来降低故障规模带来的影响。
图8是本申请实施例提供的一种节点分解和预测合并的示意图。从左至右可以看作是节点的分解过程，从右至左可以看作是节点的合并过程。其中a、-a、m和n为变量节点，c1、c2、c3、c11、c12、c21、c22、c23、c31、c32为约束节点。
本申请实施例构建的多阶段生成模型可以生成与真实故障所涉及到的局部电路相似的数据，从而补充原始电路数据，得到增强后的数据。示例性地，故障1所涉及的子电路包括4000个逻辑门，多阶段生成模型能够生成与故障1所涉及到的电路规模和结构相似的数据，例如，生成的故障数据2包括3995个逻辑门、故障数据3包括4005个逻辑门、故障数据4包括4010个逻辑门，且生成的故障数据2、3、4的逻辑结构与故障1类似。
245，故障分类预测。
可选的，本申请实施例可以在243步骤生成的数据上完成筛选，将与原有故障类型相同的数据添加到原始电路数据，完成数据增强，并在增强的数据上训练故障类型分类器。示例性地，可以利用SAT求解器或者传统ATPG方法对多阶生成模型生成的补充电路数据做筛选，即分类的标签由传统ATPG方法或者SAT求解器给出，若原始电路数据的故障类型为可测故障，则从生成的补充电路数据中筛选出可测故障添加到原始电路数据，完成数据增强。例如，故障1为可测故障，根据故障1生成的故障数据2为可测故障、故障数据3为可测故障、故障数据4为不可测故障。则将故障数据2和故障数据3添加到原始电路数据，完成故障数据1的增强。
在增强的数据上训练好故障类型分类器后，该故障类型分类器可以用来预测待检测的故障的类型。将待测试的故障按照241步骤构图并作为故障类型分类器的输入，可以得到故障的分类预测结果。示例性地，可以将待测试的新的故障转换成有向图并得到对应的邻 接矩阵，再将新的故障对应的邻接矩阵输入到训练好的故障类型分类器，可以得到故障的分类预测结果，即该故障为可测故障或者不可测故障。
图9是本申请实施例提供的一种故障数据增强的示例性流程图。图9对应图5的243步骤的多阶段生成模型。
410，节点分解。
根据图8所示的节点分解过程，对原始电路图数据400进行节点的分解，获得分解后的子图。示例性的，原始电路图数据400包括10000张图，对这10000张图进行分解，获得30000张子图。原始电路图数据400为241步骤根据原始电路数据构建的图数据。
420，训练合并预测模型。
可选的，可以利用图卷积网络(graph convolutional network，GCN)对410步骤中分解后的子图进行特征提取，得到各个子图的嵌入表示。然后根据子图的嵌入表示数据，利用机器学习的方法训练合并预测模型440，示例性地，该合并预测模型440可以是全连接神经网络(full connect neural network)。
根据合并预测模型440可以得到输入的电路数据能够合并得到原始电路图数据400中电路数据的概率。示例性地，原图A分解得到的子图包括A1、A2和A3，原图B分解得到的子图包括B1、B2、B3和B4，A1和A2合并得到原图的预测概率要高于A1和B3合并得到原图的预测概率。
430，生成模型生成子图。
本申请实施例通过生成模型来生成与原始电路图数据400分解后的子图类似的子图数据。示例性地，可以通过添加随机游走等随机影响，从一个二部图生成多个相似的二部图，也可以从一堆规模相差不大的数据上生成数据，即从若干二部图上生成分布相似的二部图。本申请不限制生成模型的选择，也可以选择自动编码-解码器(auto-encoder-decoder)以及自动编码-解码器的多种变种方法，训练方式按照该模型的通用训练方式即可，本申请对此不作限定。
图10是本申请实施例提供的一种生成模型的结构示意图。其中D1、D2为判别器，G为生成器，Solver为求解器，freal-1和freal-2为判断为真的生成数据，ffake-1和ffake-2为判断为假的生成数据，Xreal为原始输入的真实数据，即原始电路图数据400分解后的子图数据，Xfake为生成器G生成的子图数据。z为随机向量，pz指的是z符合的分布，例如高斯分布。生成器G根据输入的随机向量z生成子图数据Xfake，Xfake可以用矩阵来表示。应理解，freal-1和freal-2成对出现，ffake-1和ffake-2成对出现。
S1为D1综合freal-1和ffake-1结果后的输出，S2为D2综合freal-2和ffake-2结果后的输出。S1和S2为生成的子图450。示例性地，S1和S2的计算表达式可以为公式(1)所示，H为p和q的信息熵。当p代表freal-1且q代表ffake-1时，或者当p代表ffake-1且q代表freal-1时，ffake-1与freal-1的信息熵即为D1的输出。当p代表freal-2且q代表ffake-2时，或者当p代表ffake-2且q代表freal-2时，ffake-2与freal-2的信息熵即为D2的输出。
对于S1来说，p(x)为freal-1的分布且q(x)为ffake-1的分布，或者，p(x)为ffake-1的分布且q(x)为freal-1的分布。对于S2来说，p(x)为freal-2的分布且q(x)为ffake-2的分布，或者，p(x)为ffake-2的分布且q(x)为freal-2的分布。X为G生成的数据分布。
以生成模型为GAN为例，GAN的输入是二部图或者有向图的邻接矩阵，输出的终止条件由判决器的损失函数决定，该损失函数衡量了生成器的生成数据和原始数据的差距。本申请不限制损失函数的选择，示例性的，可以使用Wasserstain损失函数，wasserstain损失函数为公式(2)所示，其中，pr为真实数据的分布，pg为生成数据的分布，K是节点的个数，即变量的个数，L是每个变量的维度，为pr和pg两个分布的上确界，W代表两个分布的wasserstain距离。具体使用的损失函数不应理解为对本申请的限制。
以生成模型为GAN、损失函数为wasserstain损失函数为例，图10中的Wasserstain生成对抗网络(wasserstain generative adversarial networks，WGAN)可以包括两部分子网络：
一部分是生成器G，主要用于生成与输入向量相似的数据，基本结构可以是一个基于图结构的全连接网络，也可以采用其他结构，该结构不应理解为对本申请的限制；
另一部分是两个判别器D1和D2，D1可以采用和生成器G对偶的结构，主要用于判别生成的数据分布与输入数据的分布是否相似。应理解，原始输入的真实数据Xreal拥有天然的结构信息，判别生成的数据分布与输入数据的分布是否相似即判断Xfake与Xreal的数据结构是否相似。经D1判别与输入数据Xreal分布相似的生成数据为freal-1，判别与输入数据Xreal分布不相似的生成数据为ffake-1。D2可以采用依托图神经网络的NeuroSAT结构，学习SAT求解中的核心冲突信息，判断生成数据和真实数据的求解相似性。以Xfake作为输入，Solver可以输出判断为真的生成数据freal-2，freal-2可以是冲突向量。D2可以将生成数据与freal-2进行求解相似性判断，判别与freal-2求解相似程度小于预设阈值的为ffake-2，并综合freal-2和ffake-2后输出。
图11是本申请实施例提供的一种D2判别器的结构示意图。D2为依托图神经网络的NeuroSAT结构。示例性地，可以将输入数据510转换为图的嵌入表示520，然后将图的嵌入表示520转换为节点的向量表示530，利用深度分类器540(全连接神经网络)对转换后的向量进行分类，输出分类预测结果550(SAT或者是UNSAT)。
本申请实施例中，D1和D2在训练中不进行参数共享，D1和D2的训练顺序不做任何限定。可选的，可以优先训练D2，再完成对整体的训练。生成器G负责输出和输入数据510相似的子图数据，判别器D1和D2负责最小化生成器G生成的数据分布与输入的原始数据分布的差别。
470，节点的预测合并。
将430步骤生成的子图450输入到420步骤中训练好的合并预测模型440中进行合并预测，若输出的预测概率值大于预设阈值，则根据图8所示的节点合并过程，对子图450进行节点的合并得到补充电路图数据490；若输出的预测概率值小于等于预设阈值，则将子图450作为补充电路图数据490。可以看出，本申请实施例的数据增强是在原始电路图数据400的结构特性基础上进行的数据增强。
图12是本申请实施例提供的一种故障类型分类器的结构示意图。图12对应图5中245步骤进行故障分类预测的故障类型分类器。本申请不对故障类型分类器的具体选择做任何限制。应理解，虽然图12中故障类型分类器的结构和生成模型中的D2相似，但是二者利用完全不同的数据，也承担着完全不同的功能，因此是完全不同的两个网络。
示例性地，本申请实施例提供的故障类型分类器为GNN的变种模型，可以根据故障激发和传播的局部电路数据构造二部图610，然后将二部图610转换为图的嵌入表示620，接着将图的嵌入表示620转换为节点的向量表示630，利用深度分类器540(全连接神经网络)对转换后的向量进行分类，输出分类预测结果650(可测故障或者是不可测故障)。
图13是本申请实施例提供的一种训练故障类型分类器的示例性流程图。图13对应图5的245步骤。
710，节点的表示和更新。
利用图神经网络生成每个节点对应的向量表示，图14是本申请实施例提供的一种生成节点向量表示的示意图。黑色圆点可以代表变量节点，黑色圆点之间的连线可以代表约束。该步骤的输入是图数据结构，输出是每个变量节点的向量表示。
图15是本申请实施例提供的一种节点更新的示意图。为了更加准确的反应训练过程，本申请实施例将训练过程的节点分成约束节点和变量节点，并分别更新。其中，系数矩阵代表了变量节点和约束节点的连接关系，即哪一个变量属于哪一个约束。约束节点的更新会同步更新系数矩阵，变量节点的更新也会同步更新系数矩阵。示例性地，可以先更新约束节点，再更新变量节点。变量节点的更新包括翻转变量，即将变量x转换为变量x的否然后继续更新变量节点。
720，训练分类模型。
根据节点的向量表示来完成节点分类。应理解，本申请实施例的故障类型分类器的训练过程是监督学习，标签包括可测故障和不可测故障。针对其他的工业场景，该分类可以进一步细化，具体分成几类本申请对此不做限制。
为了能够降低二分图的稀疏对学习方法的影响，本申请增加了注意力机制。注意力机制允许处理可变大小的输入，将注意力集中在最相关的输入部分，能够将节点和节点邻居的关系反应到向量中，提升向量的准确性。
完成训练后，即可得到训练好的故障类型分类器。
730，测试新故障。
通过720步骤训练好的故障类型分类器对待测试的新的故障进行分类预测，获得该故障的故障类型和一组PI的预测值。
如果是可测故障，给定阈值，将超过阈值的PI对应的预测值转换为1，否则转换为0，初始化测试向量对该故障进行测试。
针对不可测故障，返回PI预测值的降序排序，该顺序与该逻辑门可能出现在冲突核(UNSAT core)的概率一致。该降序排序结果可以作为确定待测试新的故障的测试向量的决策顺序建议。
下面通过实验数据来具体说明本申请技术方案的有益效果。
图16是本申请实施例提供的一种数据生成的示意图。其中，-lit代表负的变量，+lit代表正的变量。本申请实施例中CNF稀疏度为0.013。图16(a)为原始SAT表达式模型 的生成结果，图16(b)为本申请的多阶段生成模型迭代训练10000次的生成结果，图16(c)为本申请的多阶段生成模型迭代训练20000次的生成结果，图16(d)为本申请的多阶段生成模型迭代训练30000次的生成结果。
本申请实施例是针对ATPG场景中的数据增强。实验所用数据是公开数据集ITC’99的数据。本申请技术方案的执行流程如下：
(1)构造训练集：先将故障列表中的故障在电路中的激发和传播逐一用SAT表达式表示出来，将子电路转换为SAT表达式的方法可以包括TG-Pro、PASSAT和TIGUAN等。随后，构建每个SAT表达式对应的二部图以及每个二部图对应的邻接矩阵，构成原始训练集。为方便评估，本申请实施例将原始训练集区分为来自可测故障和不可测故障两种。
(2)选择生成模型，完成数据生成。本方案中选择GAN，也可以选择auto-encoder或者贝叶斯网络等方式。为方便GAN的训练，本申请实施例中采用wasserstain损失函数。
(3)本申请实施例选择二部图的特征包括：邻接矩阵、不同节点的度、变量节点和约束节点的分类等。可选的，还可以将二部图按照稀疏度分组，每组分别训练，也可以放到一起完成训练。
(4)训练多阶段生成模型，利用判别器判断收敛性。
从图16可以看出，随着迭代步数的增加，多阶段生成模型可以逐渐生成与原始电路数据(真实故障数据)相似的生成数据。本申请实施例通过选择一个SAT求解器或者传统ATPG方法，任选10000个由可测故障和不可测故障生成的数据，按照门的规模分为g1到g10十个组，评估保持故障分类性质的概率，结果如表1所示，其中，k代表单位千。
应理解，模块性(modularity)是一种衡量图中节点之间连接关系的统计意义的变量，模块性是对网络或图形结构的一种度量，它度量将网络划分为模块的强度。具有高模块性的网络在模块内的节点之间具有密集的连接，而在不同模块内的节点之间具有稀疏的连接。模块性通常用于优化方法中，以检测网络中的社区结构，即高连接关系的结构。
可以看出，平均90.3％的生成数据可以保持原有分类性质，同时，在原有数据的平均模块性是0.77的情况下，生成的数据的平均模块性是0.74，因此本申请技术方案以极大的概率保证了原有的模块性。由此进一步验证了本申请实施例提供的多阶段生成模型可以完成基于原始数据特性的数据增强。
本申请实施例由多阶段生成模型生成数据，而非采用规则或者随机的方式完成生成。这种生成方式更容易保证数据集性质的一致性，从而方便实施后续的机器学习算法。
表1多阶段生成模型效果评估

下面通过另外一个实验来具体说明本申请技术方案的有益效果，本申请实施例是针对ATPG中的场景完成故障分类。本申请实施例的执行流程如下：
(1)从真实电路中提取数据：从公开数据集ITC’99和和工业电路中提取故障的激发和传播对应的逻辑锥，按照逻辑锥的规模分组。选择规模小于300的逻辑锥对应的SAT表达式作为原始训练集，而规模不超过1000的逻辑锥作为测试数据集。标记真实数据的训练集作为训练集1。
(2)构建测试集：为了构建对比实验，本申请实施例在原始电路数据中添加随机生成的数据作为补充，随机的方式是任意改变逻辑锥中的门的类型或者两个门的连接。另外，本申请实施例在训练集中添加了10000个随机生成的数据，作为随机方法的数据增强，并标记增强后的训练集为训练集2。
(3)完成训练：
a)在训练集1中训练分类器，作为没有多阶段生成模型的对比方案。
b)在训练集2中训练分类器，作为没有多阶段生成模型但有随机数据增强的对比方案。
c)在训练集1中训练多阶段生成模型，按照判别器的条件判断收敛，并在生成的数据中用SAT求解器或者传统ATPG方法筛选，选出保持原有分类性质的数据添加到训练集1中实现增强。在增强后的训练集中训练分类器，按照指定损失函数完成故障类型分类器训练。
(4)完成测试：在测试集上完成三个模型的对比测试。
表2显示的是不同的数据增强方式对预测准确率的影响，第一列代表不同电路的标识，后三列分别是：原始数据上的分类器、原始数据执行了随机数据增强的分类器、以及原始数据执行了本申请提供的多阶段生成模型进行数据增强后的分类器。从实验结果可以看出，根据多阶段生成模型进行数据增强后的故障类型分类器的准确率从60.4％提高到88.7％，而随机增强数据上的训练模型反而降低到了59.4％，说明随机数据增强得到的数据性质已经与原有数据不同，随机增强的数据不仅不可以保持原有数据的性质，也很难保持自己的性质，数据性质的保持严重受到随机方式的影响。同时，本申请实施例在随机增强后的数据上训练多阶段生成模型，继续实现依托多阶段生成模型的数据增强，分类准确性从60.4％提升至88.7％。因此，本申请实施例证明了本申请技术方案的有效性。
表2不同的数据增强方式对预测准确率的影响

表3显示的是在基于SAT的ATPG中不同的数据增强方式对故障分析时间的影响，本申请实施例将多阶段生成模型和后续的故障类型分类器融合到基于SAT的ATPG中，solving表示对SAT表达式求解时间的影响，ATPG则表示对端到端的ATPG系统求解时间的影响。第一列代表不同电路的标识，“负号”表示降低的运行时间(即提升的求解性能)的比例，而“正号”则表示增加的运行时间的比例。
从表2和表3可以看出，基于多阶段生成模型的故障类型分类器不仅可以提高故障类型预测的准确率，还可以降低平均34.79％的求解时间，对于ATPG而言则可以降低7.43％的求解时间。这两个降低求解时间的比例都远远高于没有任何数据增强的结果以及随机进行数据增强的结果。
表3不同的数据增强方式对故障分析时间的影响
表4显示的是将多阶段生成模型和后续的故障类型分类器融合到基于SAT的ATPG 中的预测模型，对回溯和决策次数的影响。可以看出，本申请实施例提供的预测模型可以平均降低20.71％的回溯次数以及48.42％的决策次数，这意味着在当前全部用有限回溯来控制的ATPG决策系统中，原有未完成检测故障(aborted faults)可以平均被多覆盖9.14％。
本申请实施例提供的故障类型分类结果不仅可以用于SAT的初始化，同时还可以作为求解方法选择的依据，根据不同的预测结果，选择合适的求解方法，进一步增强求解性能。
表4预测模型对回溯和决策次数的影响
以上描述了根据本申请实施例的芯片故障分析方法，本申请所提供的方法可以作为独立的故障分析模块，服务于测试设计(design for testing，DFT)工程师，在故障检测之前完成故障分析，辅助电路检查和设计。可选的，本申请所提供的方法嵌入到现有EDA流程的ATPG模块，例如图2所示。在ATPG流程执行前进行故障初筛和分类，并针对不同类型的故障解码预测结果：针对可测故障，返回预测的不同PI的赋值，降低搜索空间；针对不可测故障，返回不同逻辑门的预测排序结果。
可选的，本申请提供的多阶段生成模型可以作为独立方案服务于ATPG场景，用于数据增强。本申请提供的故障类型分类器也可以作为独立方案，嵌入其他数据驱动的分析场景，为ATPG场景提供故障分类的初筛。
下面分别结合图17和图18描述根据本申请实施例的装置和设备。
本申请实施例还提供了一种计算机存储介质，该计算机存储介质中存储有程序指令，所述程序执行时可包括如图2、图3、图5、图8-15对应实施例中的芯片故障分析方法的部分或全部步骤。
图17为本申请实施例提供的一种计算机装置1000的结构示例图。该计算机装置1000包括获取模块1010和处理模块1020。
其中，获取模块1010，用于原始电路数据，执行图2方法中的110。
处理模块1020，用于对原始电路数据进行数据增强，得到补充电路数据，然后根据原始电路数据和补充电路数据训练故障类型分类器，通过该故障类型分类器确定待检测的新的故障的故障类型，并根据新的故障的故障类型来指导分析芯片故障，执行图2的方法、图3的方法、图5的方法、图8-15的方法中的部分或全部步骤。
图18为本申请实施例提供的另一种计算机装置1300的结构示例图。计算机装置1300包括处理器1302、通信接口1303和存储器1304。计算机装置1300的一种示例为芯片。计算机装置1300的另一种示例为计算设备。
上述本申请实施例揭示的方法可以应用于处理器1302中，或者由处理器1302实现。处理器1302可以是中央处理器(central processing unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。在实现过程中，上述方法的各步骤可以通过处理器1302中的硬件的集成逻辑电路或者软件形式的指令完成。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。
存储器1304可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
处理器1302、存储器1304和通信接口1303之间可以通过总线通信。存储器1304中存储有可执行代码，处理器1302读取存储器1304中的可执行代码以执行对应的方法。存储器1304中还可以包括操作系统等其他运行进程所需的软件模块。操作系统可以为LINUXTM，UNIXTM，WINDOWSTM等。
例如，存储器1304中的可执行代码用于实现图2、图3、图5、图8-15所示的方法，处理器1302读取存储器1304中的该可执行代码以执行图2、图3、图5、图8-15所示的方法。
在本申请的一些实施例中，所公开的方法可以实施为以机器可读格式被编码在计算机可读存储介质上的或者被编码在其它非瞬时性介质或者制品上的计算机程序指令。图19 示意性地示出根据这里展示的至少一些实施例而布置的示例计算机程序产品的概念性局部视图，所述示例计算机程序产品包括用于在计算设备上执行计算机进程的计算机程序。在一个实施例中，示例计算机程序产品1400是使用信号承载介质1401来提供的。所述信号承载介质1401可以包括一个或多个程序指令1402，其当被一个或多个处理器运行时可以提供以上针对图2、图3、图5、图8-15所示的方法中描述的功能或者部分功能。因此，例如，参考图2、图3、图5、图8-15中所示的实施例，其中的一个或多个特征可以由与信号承载介质1401相关联的一个或多个指令来承担。
在一些示例中，信号承载介质1401可以包含计算机可读介质1403，诸如但不限于，硬盘驱动器、紧密盘(CD)、数字视频光盘(DVD)、数字磁带、存储器、只读存储记忆体(read-only memory，ROM)或随机存储记忆体(random access memory，RAM)等等。在一些实施方式中，信号承载介质1401可以包含计算机可记录介质1404，诸如但不限于，存储器、读/写(R/W)CD、R/W DVD、等等。在一些实施方式中，信号承载介质1401可以包含通信介质1405，诸如但不限于，数字和/或模拟通信介质(例如，光纤电缆、波导、有线通信链路、无线通信链路、等等)。因此，例如，信号承载介质1401可以由无线形式的通信介质1405(例如，遵守IEEE 802.11标准或者其它传输协议的无线通信介质)来传达。一个或多个程序指令1402可以是，例如，计算机可执行指令或者逻辑实施指令。在一些示例中，前述的计算设备可以被配置为，响应于通过计算机可读介质1403、计算机可记录介质1404、和/或通信介质1405中的一个或多个传达到计算设备的程序指令1402，提供各种操作、功能、或者动作。应该理解，这里描述的布置仅仅是用于示例的目的。因而，本领域技术人员将理解，其它布置和其它元素(例如，机器、接口、功能、顺序、和功能组等等)能够被取而代之地使用，并且一些元素可以根据所期望的结果而一并省略。另外，所描述的元素中的许多是可以被实现为离散的或者分布式的组件的、或者以任何适当的组合和位置来结合其它组件实施的功能实体。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种芯片故障分析方法，其特征在于，包括：
    获取第一电路数据，所述第一电路数据包括多个电路节点及所述多个电路节点之间的关系，所述多个电路节点包括被电路中的故障影响的电路节点；
    根据所述第一电路数据，生成第二电路数据，所述第二电路数据与所述第一电路数据的相似度大于第一预设阈值；
    根据所述第一电路数据和所述第二电路数据训练故障类型分类器；
    根据所述故障类型分类器和待检测的第一故障，确定所述第一故障的测试向量。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述第一电路数据，生成第二电路数据，包括：
    将所述第一电路数据进行分解，得到多个第一子电路数据；
    根据所述多个第一子电路数据，生成多个第二子电路数据，所述多个第一子电路数据与所述多个第二子电路数据一一对应，每个第二子电路数据是根据所对应的第一子电路数据生成的，彼此对应的第二子电路数据与第一子电路数据之间的相似度大于第二预设阈值；
    根据合并预测模型和所述多个第二子电路数据，确定所述第二电路数据，所述合并预测模型用于预测输入的电路数据能够合并得到所述第一电路数据中的电路数据的概率，所述合并预测模型是根据所述第一电路数据和所述多个第一子电路数据训练得到的。
  3. 根据权利要求2所述的方法，其特征在于，所述将所述第一电路数据进行分解，得到多个第一子电路数据，包括：
    根据所述多个电路节点之间的关系对所述第一电路数据进行分解，得到所述多个第一子电路数据。
  4. 根据权利要求2或3所述的方法，其特征在于，所述根据合并预测模型和所述多个第二子电路数据，确定所述第二电路数据，包括：
    根据所述合并预测模型和所述多个第二子电路数据，确定第一预测概率值，所述第一预测概率值为预测所述第二子电路数据能够合并得到所述第一电路数据中的电路数据的概率值；
    若所述第一预测概率值大于第三预设阈值，则根据所述多个第二子电路数据中电路节点之间的关系对所述多个第二子电路数据进行合并，得到所述第二电路数据；
    若所述第一预测概率值小于或者等于所述第三预设阈值，则将所述多个第二子电路数据作为所述第二电路数据。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，所述根据所述故障类型分类器和待检测的第一故障，确定所述第一故障的测试向量，包括：
    根据所述故障类型分类器和待检测的所述第一故障，确定所述第一故障的故障类型和第一序列，所述第一序列包括所述第一故障所在电路中全部或者部分输入的预测值；
    根据所述第一故障的故障类型和所述第一序列，确定所述第一故障的所述测试向量。
  6. 根据权利要求5所述的方法，其特征在于，所述根据所述第一故障的故障类型和所述第一序列，确定所述第一故障的所述测试向量，包括：
    若所述第一故障的故障类型为可测故障，将所述第一序列中的所述预测值根据第四预设阈值转换为指定赋值，根据所述转换后的所述第一序列确定所述第一故障的所述测试向量；
    若所述第一故障的故障类型为不可测故障，根据所述第一序列中所述预测值的降序排序结果确定所述第一故障的所述测试向量。
  7. 根据权利要求6所述的方法，其特征在于，所述将所述第一序列中的所述预测值根据第四预设阈值转换为指定赋值，包括：
    若所述预测值大于或者等于所述第四预设阈值，将所述预测值转换为1；
    若所述预测值小于所述第四预设阈值，将所述预测值转换为0。
  8. 根据权利要求1至7任一项所述的方法，其特征在于，根据所述第一电路数据和所述第二电路数据训练故障类型分类器，包括：
    确定第三电路数据，所述第三电路数据包括与所述第一电路数据故障类型相同的所述第二电路数据；
    根据所述第一电路数据和所述第三电路数据，训练所述故障类型分类器。
  9. 根据权利要求1至8任一项所述的方法，其特征在于，所述获取第一电路数据，包括：
    获取目标故障列表中的故障所影响的多个局部电路，所述多个局部电路包括多个逻辑门和多个电路连线；
    根据所述多个局部电路构建所述第一电路数据。
  10. 一种计算机装置，其特征在于，包括：
    获取模块，用于获取第一电路数据，所述第一电路数据包括多个电路节点及所述多个电路节点之间的关系，所述多个电路节点包括被电路中的故障影响的电路节点；
    处理模块，用于根据所述第一电路数据，生成第二电路数据，所述第二电路数据与所述第一电路数据的相似度大于第一预设阈值；
    所述处理模块，还用于根据所述第一电路数据和所述第二电路数据训练故障类型分类器；
    所述处理模块，还用于根据所述故障类型分类器和待检测的第一故障，确定所述第一故障的测试向量。
  11. 根据权利要求10所述的装置，其特征在于，所述处理模块，具体用于：
    将所述第一电路数据进行分解，得到多个第一子电路数据；
    根据所述多个第一子电路数据，生成多个第二子电路数据，所述多个第一子电路数据与所述多个第二子电路数据一一对应，每个第二子电路数据是根据所对应的第一子电路数据生成的，彼此对应的第二子电路数据与第一子电路数据之间的相似度大于第二预设阈值；
    根据合并预测模型和所述多个第二子电路数据，确定所述第二电路数据，所述合并预测模型用于预测输入的电路数据能够合并得到所述第一电路数据中的电路数据的概率，所述合并预测模型是根据所述第一电路数据和所述多个第一子电路数据训练得到的。
  12. 根据权利要求11所述的装置，其特征在于，所述处理模块，具体用于：
    根据所述多个电路节点之间的关系对所述第一电路数据进行分解，得到所述多个第一子电路数据。
  13. 根据权利要求11或12所述的装置，其特征在于，所述处理模块，具体用于：
    根据所述合并预测模型和所述多个第二子电路数据，确定第一预测概率值，所述第一预测概率值为预测所述第二子电路数据能够合并得到所述第一电路数据中的电路数据的概率值；
    若所述第一预测概率值大于第三预设阈值，则根据所述多个第二子电路数据中电路节点之间的关系对所述多个第二子电路数据进行合并，得到所述第二电路数据；
    若所述第一预测概率值小于或者等于所述第三预设阈值，则将所述多个第二子电路数据作为所述第二电路数据。
  14. 根据权利要求10至13任一项所述的装置，其特征在于，所述处理模块，具体用于：
    根据所述故障类型分类器和待检测的所述第一故障，确定所述第一故障的故障类型和第一序列，所述第一序列包括所述第一故障所在电路中全部或者部分输入的预测值；
    根据所述第一故障的故障类型和所述第一序列，确定所述第一故障的所述测试向量。
  15. 根据权利要求14所述的装置，其特征在于，所述处理模块，具体用于：
    若所述第一故障的故障类型为可测故障，将所述第一序列中的所述预测值根据第四预设阈值转换为指定赋值，根据所述转换后的所述第一序列确定所述第一故障的所述测试向量；
    若所述第一故障的故障类型为不可测故障，根据所述第一序列中所述预测值的降序排序结果确定所述第一故障的所述测试向量。
  16. 根据权利要求15所述的装置，其特征在于，所述处理模块，具体用于：
    若所述预测值大于或者等于所述第四预设阈值，将所述预测值转换为1；
    若所述预测值小于所述第四预设阈值，将所述预测值转换为0。
  17. 根据权利要求10至16任一项所述的装置，其特征在于，所述处理模块，具体用于：
    确定第三电路数据，所述第三电路数据包括与所述第一电路数据故障类型相同的所述第二电路数据；
    根据所述第一电路数据和所述第三电路数据，训练所述故障类型分类器。
  18. 根据权利要求10至17任一项所述的装置，其特征在于，所述获取模块，还用于获取目标故障列表中的故障所影响的多个局部电路，所述多个局部电路包括多个逻辑门和多个电路连线；
    所述处理模块，还用于根据所述多个局部电路构建所述第一电路数据。
  19. 一种计算机设备，其特征在于，包括：处理器，所述处理器用于与存储器耦合，读取并执行所述存储器中的指令和/或程序代码，以执行如权利要求1-9中任一项所述的方法。
  20. 一种芯片系统，其特征在于，包括：逻辑电路，所述逻辑电路用于与输入/输出接口耦合，通过所述输入/输出接口传输数据，以执行如权利要求1-9中任一项所述的方法。
  21. 一种计算机可读介质，其特征在于，所述计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行如权利要求1-9中任一项所述的方法。
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